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author | K. Richard Pixley <rich@cygnus> | 1992-02-13 08:33:54 +0000 |
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committer | K. Richard Pixley <rich@cygnus> | 1992-02-13 08:33:54 +0000 |
commit | a39116f1c91d3642c068d9df871338cca9006be2 (patch) | |
tree | dbd53d94ef859ca6425ef5370573030d4766161b /gas/config/tc-i386.h | |
parent | 77806c3e79cc6ebd5ab62ce46f7cdeecad50ca52 (diff) | |
download | fsf-binutils-gdb-a39116f1c91d3642c068d9df871338cca9006be2.zip fsf-binutils-gdb-a39116f1c91d3642c068d9df871338cca9006be2.tar.gz fsf-binutils-gdb-a39116f1c91d3642c068d9df871338cca9006be2.tar.bz2 |
White space and comments only. The devo tree prior to this delta is
tagged as "vanilla" for your convenience.
There are also some comment changes.
Diffstat (limited to 'gas/config/tc-i386.h')
-rw-r--r-- | gas/config/tc-i386.h | 201 |
1 files changed, 102 insertions, 99 deletions
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h index a2b853e..b68f956 100644 --- a/gas/config/tc-i386.h +++ b/gas/config/tc-i386.h @@ -1,71 +1,74 @@ /* i386.h -- Header file for i386.c Copyright (C) 1989, Free Software Foundation. - -This file is part of GAS, the GNU Assembler. - -GAS is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GAS is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GAS; see the file COPYING. If not, write to -the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + #define TC_I386 1 +#define AOUT_MACHTYPE 100 +#define REVERSE_SORT_RELOCS + #define tc_crawl_symbol_chain(a) ; /* not used */ #define tc_headers_hook(a) ; /* not used */ - + #define MAX_OPERANDS 3 /* max operands per insn */ #define MAX_PREFIXES 4 /* max prefixes per opcode */ #define MAX_IMMEDIATE_OPERANDS 2 /* max immediates per insn */ #define MAX_MEMORY_OPERANDS 2 /* max memory ref per insn * lcall uses 2 */ -/* we define the syntax here (modulo base,index,scale syntax) */ + /* we define the syntax here (modulo base,index,scale syntax) */ #define REGISTER_PREFIX '%' #define IMMEDIATE_PREFIX '$' #define ABSOLUTE_PREFIX '*' #define PREFIX_SEPERATOR '/' - + #define TWO_BYTE_OPCODE_ESCAPE 0x0f - -/* register numbers */ + + /* register numbers */ #define EBP_REG_NUM 5 #define ESP_REG_NUM 4 - -/* modrm_byte.regmem for twobyte escape */ + + /* modrm_byte.regmem for twobyte escape */ #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM -/* index_base_byte.index for no index register addressing */ + /* index_base_byte.index for no index register addressing */ #define NO_INDEX_REGISTER ESP_REG_NUM -/* index_base_byte.base for no base register addressing */ + /* index_base_byte.base for no base register addressing */ #define NO_BASE_REGISTER EBP_REG_NUM - -/* these are the att as opcode suffixes, making movl --> mov, for example */ + + /* these are the att as opcode suffixes, making movl --> mov, for example */ #define DWORD_OPCODE_SUFFIX 'l' #define WORD_OPCODE_SUFFIX 'w' #define BYTE_OPCODE_SUFFIX 'b' - -/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ + + /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ #define REGMEM_FIELD_HAS_REG 0x3 /* always = 0x3 */ #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) #define END_OF_INSN '\0' /* -When an operand is read in it is classified by its type. This type includes -all the possible ways an operand can be used. Thus, '%eax' is both 'register -# 0' and 'The Accumulator'. In our language this is expressed by OR'ing -'Reg32' (any 32 bit register) and 'Acc' (the accumulator). -Operands are classified so that we can match given operand types with -the opcode table in i386-opcode.h. - */ + When an operand is read in it is classified by its type. This type includes + all the possible ways an operand can be used. Thus, '%eax' is both 'register + # 0' and 'The Accumulator'. In our language this is expressed by OR'ing + 'Reg32' (any 32 bit register) and 'Acc' (the accumulator). + Operands are classified so that we can match given operand types with + the opcode table in i386-opcode.h. + */ #define Unknown 0x0 /* register */ #define Reg8 0x1 /* 8 bit reg */ @@ -113,8 +116,8 @@ the opcode table in i386-opcode.h. #define Abs (Abs8|Abs16|Abs32) #define MODE_FROM_DISP_SIZE(t) \ - ((t&(Disp8)) ? 1 : \ - ((t&(Disp32)) ? 2 : 0)) + ((t&(Disp8)) ? 1 : \ + ((t&(Disp32)) ? 2 : 0)) #define Byte (Reg8|Imm8|Imm8S) #define Word (Reg16|Imm16) @@ -122,8 +125,8 @@ the opcode table in i386-opcode.h. /* convert opcode suffix ('b' 'w' 'l' typically) into type specifyer */ #define OPCODE_SUFFIX_TO_TYPE(s) \ - (s == BYTE_OPCODE_SUFFIX ? Byte : \ - (s == WORD_OPCODE_SUFFIX ? Word : DWord)) + (s == BYTE_OPCODE_SUFFIX ? Byte : \ + (s == WORD_OPCODE_SUFFIX ? Word : DWord)) #define FITS_IN_SIGNED_BYTE(num) ((num) >= -128 && (num) <= 127) #define FITS_IN_UNSIGNED_BYTE(num) ((num) >= 0 && (num) <= 255) @@ -131,41 +134,41 @@ the opcode table in i386-opcode.h. #define FITS_IN_SIGNED_WORD(num) ((num) >= -32768 && (num) <= 32767) #define SMALLEST_DISP_TYPE(num) \ - FITS_IN_SIGNED_BYTE(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32) + FITS_IN_SIGNED_BYTE(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32) #define SMALLEST_IMM_TYPE(num) \ - (num == 1) ? (Imm1|Imm8|Imm8S|Imm16|Imm32): \ - FITS_IN_SIGNED_BYTE(num) ? (Imm8S|Imm8|Imm16|Imm32) : \ - FITS_IN_UNSIGNED_BYTE(num) ? (Imm8|Imm16|Imm32): \ - (FITS_IN_SIGNED_WORD(num)||FITS_IN_UNSIGNED_WORD(num)) ? (Imm16|Imm32) : \ - (Imm32) + (num == 1) ? (Imm1|Imm8|Imm8S|Imm16|Imm32): \ + FITS_IN_SIGNED_BYTE(num) ? (Imm8S|Imm8|Imm16|Imm32) : \ + FITS_IN_UNSIGNED_BYTE(num) ? (Imm8|Imm16|Imm32): \ + (FITS_IN_SIGNED_WORD(num)||FITS_IN_UNSIGNED_WORD(num)) ? (Imm16|Imm32) : \ + (Imm32) typedef struct { - /* instruction name sans width suffix ("mov" for movl insns) */ - char *name; - - /* how many operands */ - unsigned int operands; - - /* base_opcode is the fundamental opcode byte with a optional prefix(es). */ - unsigned int base_opcode; - - /* extension_opcode is the 3 bit extension for group <n> insns. - If this template has no extension opcode (the usual case) use None */ - unsigned char extension_opcode; + /* instruction name sans width suffix ("mov" for movl insns) */ + char *name; + + /* how many operands */ + unsigned int operands; + + /* base_opcode is the fundamental opcode byte with a optional prefix(es). */ + unsigned int base_opcode; + + /* extension_opcode is the 3 bit extension for group <n> insns. + If this template has no extension opcode (the usual case) use None */ + unsigned char extension_opcode; #define None 0xff /* If no extension_opcode is possible. */ - - /* the bits in opcode_modifier are used to generate the final opcode from - the base_opcode. These bits also are used to detect alternate forms of - the same instruction */ - unsigned int opcode_modifier; - -/* opcode_modifier bits: */ + + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ #define W 0x1 /* set if operands are words or dwords */ #define D 0x2 /* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */ -/* direction flag for floating insns: MUST BE 0x400 */ + /* direction flag for floating insns: MUST BE 0x400 */ #define FloatD 0x400 -/* shorthand */ + /* shorthand */ #define DW (D|W) #define ShortForm 0x10 /* register is in low 3 bits of opcode */ #define ShortFormW 0x20 /* ShortForm and W bit is 0x8 */ @@ -173,7 +176,7 @@ typedef struct { #define Seg3ShortForm 0x80 /* fs/gs segment register insns. */ #define Jump 0x100 /* special case for jump insns. */ #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ -/* 0x400 CANNOT BE USED since it's already used by FloatD above */ + /* 0x400 CANNOT BE USED since it's already used by FloatD above */ #define DONT_USE 0x400 #define NoModrm 0x800 #define Modrm 0x1000 @@ -181,23 +184,23 @@ typedef struct { #define JumpByte 0x4000 #define JumpDword 0x8000 #define ReverseRegRegmem 0x10000 - - /* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the - instuction comes in byte, word, and dword sizes and is encoded into - machine code in the canonical way. */ + + /* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the + instuction comes in byte, word, and dword sizes and is encoded into + machine code in the canonical way. */ #define COMES_IN_ALL_SIZES (W) - - /* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the - source and destination operands can be reversed by setting either - the D (for integer insns) or the FloatD (for floating insns) bit - in base_opcode. */ + + /* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the + source and destination operands can be reversed by setting either + the D (for integer insns) or the FloatD (for floating insns) bit + in base_opcode. */ #define COMES_IN_BOTH_DIRECTIONS (D|FloatD) - - /* operand_types[i] describes the type of operand i. This is made - by OR'ing together all of the possible type masks. (e.g. - 'operand_types[i] = Reg|Imm' specifies that operand i can be - either a register or an immediate operand */ - unsigned int operand_types[3]; + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand */ + unsigned int operand_types[3]; } template; /* @@ -206,42 +209,42 @@ typedef struct { ole hash table of insns. The templates themselves start at START and range up to (but not including) END. -*/ + */ typedef struct { - template *start; - template *end; + template *start; + template *end; } templates; /* these are for register name --> number & type hash lookup */ typedef struct { - char * reg_name; - unsigned int reg_type; - unsigned int reg_num; + char * reg_name; + unsigned int reg_type; + unsigned int reg_num; } reg_entry; typedef struct { - char * seg_name; - unsigned int seg_prefix; + char * seg_name; + unsigned int seg_prefix; } seg_entry; /* these are for prefix name --> prefix code hash lookup */ typedef struct { - char * prefix_name; - unsigned char prefix_code; + char * prefix_name; + unsigned char prefix_code; } prefix_entry; /* 386 operand encoding bytes: see 386 book for details of this. */ typedef struct { - unsigned regmem:3; /* codes register or memory operand */ - unsigned reg:3; /* codes register operand (or extended opcode) */ - unsigned mode:2; /* how to interpret regmem & reg */ + unsigned regmem:3; /* codes register or memory operand */ + unsigned reg:3; /* codes register operand (or extended opcode) */ + unsigned mode:2; /* how to interpret regmem & reg */ } modrm_byte; /* 386 opcode byte to code indirect addressing. */ typedef struct { - unsigned base:3; - unsigned index:3; - unsigned scale:2; + unsigned base:3; + unsigned index:3; + unsigned scale:2; } base_index_byte; /* end of tc-i386.h */ |