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| author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2020-06-04 16:17:07 +0200 |
|---|---|---|
| committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2020-06-04 16:17:42 +0200 |
| commit | d8740be15930b820ab51d7a76695194022a83551 (patch) | |
| tree | bc27d8c02f25e78556d67cf0f753e39d070bd47f /cpu | |
| parent | e9bffec9afc45cf7c49308f0b4b8cc6bf68f58f2 (diff) | |
| download | fsf-binutils-gdb-d8740be15930b820ab51d7a76695194022a83551.zip fsf-binutils-gdb-d8740be15930b820ab51d7a76695194022a83551.tar.gz fsf-binutils-gdb-d8740be15930b820ab51d7a76695194022a83551.tar.bz2 | |
cpu,gas,opcodes: remove no longer needed workaround from the BPF port
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
* bpf.opc (bpf_print_insn): Do not set endian_code here.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
bpf_cgen_cpu_open.
(md_assemble): Remove no longer needed hack.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* disassemble.c (disassemble_init_for_target): Set endian_code for
bpf targets.
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
* bpf-dis.c: Likewise.
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ChangeLog | 5 | ||||
| -rw-r--r-- | cpu/bpf.cpu | 10 | ||||
| -rw-r--r-- | cpu/bpf.opc | 1 |
3 files changed, 8 insertions, 8 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 41ff181..f2ac243 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,5 +1,10 @@ 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> + * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. + * bpf.opc (bpf_print_insn): Do not set endian_code here. + +2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> + * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value. diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu index 47d7cb0..dcfb0ca 100644 --- a/cpu/bpf.cpu +++ b/cpu/bpf.cpu @@ -98,13 +98,9 @@ ;; Length of an unknown instruction. Used by disassembly and by the ;; simulator's invalid insn handler. (default-insn-bitsize 64) - ;; Number of bits of insn that can be initially fetched. XXX this - ;; should be 64 (the size of the smallest insn) but until CGEN - ;; gets fixed to place constant fields in their own words, we have - ;; to use this workaround to avoid the opcode byte to be placed at - ;; the wrong side of the instruction when assembling in - ;; big-endian. - (base-insn-bitsize 8))) + ;; Number of bits of insn that can be initially fetched. This is + ;; the size of the smallest insn. + (base-insn-bitsize 64))) (define-bpf-isa le) (define-bpf-isa be) diff --git a/cpu/bpf.opc b/cpu/bpf.opc index e2acaa4..e70ee04 100644 --- a/cpu/bpf.opc +++ b/cpu/bpf.opc @@ -129,7 +129,6 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) info->bytes_per_chunk = 1; info->bytes_per_line = 8; - info->endian_code = BFD_ENDIAN_BIG; /* Attempt to read the base part of the insn. */ buflen = cd->base_insn_bitsize / 8; |