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author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
---|---|---|
committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
commit | 9204ccd4b136e01457f6dfd2d62aaa98530ce740 (patch) | |
tree | 1e0bb744bfe15b40a4fc368be826232eae55ad85 /binutils | |
parent | a3fb396f2dc57f585a49091e12ec6c588c45e681 (diff) | |
download | fsf-binutils-gdb-9204ccd4b136e01457f6dfd2d62aaa98530ce740.zip fsf-binutils-gdb-9204ccd4b136e01457f6dfd2d62aaa98530ce740.tar.gz fsf-binutils-gdb-9204ccd4b136e01457f6dfd2d62aaa98530ce740.tar.bz2 |
MIPS/opcodes: Do not use CP0 register names for control registers
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
Diffstat (limited to 'binutils')
-rw-r--r-- | binutils/ChangeLog | 6 | ||||
-rw-r--r-- | binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d | 2 | ||||
-rw-r--r-- | binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d | 2 |
3 files changed, 8 insertions, 2 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index f53d3b5..a0f77e9 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,5 +1,11 @@ 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 + operand disassembly. + * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise. + +2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000' machine for disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise. diff --git a/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d b/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d index ac6db71..1fe1c2f 100644 --- a/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d +++ b/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d @@ -7,7 +7,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 40020800 mfc0 v0,c0_random -[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,c0_random +[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,\$1 [0-9a-f]+ <[^>]*> 40620800 0x40620800 [0-9a-f]+ <[^>]*> 40620c00 0x40620c00 \.\.\. diff --git a/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d b/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d index 6aaea53..cc4b34c 100644 --- a/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d +++ b/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d @@ -7,7 +7,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 40020800 mfc0 v0,c0_random -[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,c0_random +[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,\$1 [0-9a-f]+ <[^>]*> 40620800 mfgc0 v0,c0_random [0-9a-f]+ <[^>]*> 40620c00 0x40620c00 \.\.\. |