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| author | Maciej W. Rozycki <macro@mips.com> | 2018-04-05 14:35:25 -0700 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@mips.com> | 2018-04-05 22:37:17 +0100 |
| commit | 2d8c1a2318a75f43491bdc7acbeb24590145d7a6 (patch) | |
| tree | 40b069569b8ff66ac64e0396123bc84d7bcd0b25 /binutils | |
| parent | 494e49c9855c75e5cf95a2c031401d2d4f5e21fe (diff) | |
| download | fsf-binutils-gdb-2d8c1a2318a75f43491bdc7acbeb24590145d7a6.zip fsf-binutils-gdb-2d8c1a2318a75f43491bdc7acbeb24590145d7a6.tar.gz fsf-binutils-gdb-2d8c1a2318a75f43491bdc7acbeb24590145d7a6.tar.bz2 | |
MIPS/binutils/testsuite: Fix `.dc.l' typo in `strip-13mips64.s'
Fix a typo: `.dc.w' -> `.dc.l' in `strip-13mips64.s', correcting a bug
from commit 2f8ceb38991e ("binutils/testsuite: Support REL and MIPS64
reloc formats with `strip-13'"). For relocation format correctness only
as there is no observable change in test results due to the lack of
connection between the second relocation entry affected and the examined
error message produced.
binutils/
* testsuite/binutils-all/strip-13mips64.s: Use `.dc.l' rather
than `.dc.w' in second relocation.
Diffstat (limited to 'binutils')
| -rw-r--r-- | binutils/ChangeLog | 5 | ||||
| -rw-r--r-- | binutils/testsuite/binutils-all/strip-13mips64.s | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 1a97ff3..a577978 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,5 +1,10 @@ 2018-04-05 Maciej W. Rozycki <macro@mips.com> + * testsuite/binutils-all/strip-13mips64.s: Use `.dc.l' rather + than `.dc.w' in second relocation. + +2018-04-05 Maciej W. Rozycki <macro@mips.com> + * testsuite/binutils-all/strip-13.d: Also expect `unsupported relocation type 0x8f' error message. diff --git a/binutils/testsuite/binutils-all/strip-13mips64.s b/binutils/testsuite/binutils-all/strip-13mips64.s index 36323e0..cee9c75 100644 --- a/binutils/testsuite/binutils-all/strip-13mips64.s +++ b/binutils/testsuite/binutils-all/strip-13mips64.s @@ -9,6 +9,6 @@ foo: .dc.a 0x0000008f .dc.a 0 - .dc.w 0 + .dc.l 0 .dc.b 0, 0, 0, 0 .dc.a 0 |