[ bfd/ChangeLog ]

2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
	* archures.c (bfd_mach_mipsisa32r2): New define.
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_mipsisa32r2): New enum value.
	(arch_info_struct): Add entry for I_mipsisa32r2.
	* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
	(_bfd_mips_elf_final_write_processing): Add
	bfd_mach_mipsisa32r2 case.
	(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
	binaries marked as using MIPS32 Release 2.

[ binutils/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
	changes in MIPS -M options.

[ gas/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
	CPU variants.
	* configure: Regenerate.
	* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
	(macro_build): Handle "K" operand.
	(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
	CPU_HAS_DROR and CPU_HAS_ROR are currently used.
	(mips_ip): New variable "lastpos", and implement "+A", "+B",
	and "+C" operands for MIPS32 Release 2 ins/ext instructions.
	Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
	(validate_mips_insn): Implement "+" as a way to extend the
	allowed operands, and implement "K", "+A", "+B", and "+C"
	operands.
	(OPTION_MIPS32R2): New define.
	(md_longopts): Add entry for OPTION_MIPS32R2.
	(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
	(md_parse_option): Handle OPTION_MIPS32R2.
	(s_mipsset): Reimplement handling of ".set mipsN" options
	and add support for ".set mips32r2".
	(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
	(md_show_usage): Document "-mips32r2" option.
	* doc/as.texinfo: Document "-mips32r2" option.
	* doc/c-mips.texi: Likewise.

[ gas/testsuite/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0-names-mips32r2.d: New test.
	* gas/mips/hwr-names-mips32r2.d: New test.
	* gas/mips/hwr-names-numeric.d: New test.
	* gas/mips/hwr-names.s: New test source file.
	* gas/mips/mips32r2.d: New test.
	* gas/mips/mips32r2.s: New test source file.
	* gas/mips/mips32r2-ill.l: New test.
	* gas/mips/mips32r2-ill.s: New test source file.
	* gas/mips/mips.exp: Add mips32r2 architecture data array
	entry.  Run new tests mentioned above.

[ include/elf/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h (E_MIPS_ARCH_32R2): New define.

[ include/opcode/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Document "+" as the start of two-character operand
	type names, and add new "K", "+A", "+B", and "+C" operand types.
	(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
	(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
	defines.

[ opcodes/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
	(mips_hwr_names_mips3264r2): New arrays.
	(mips_arch_choice): New "hwr_names" member.
	(mips_arch_choices): Adjust for structure change, and add a new
	entry for "mips32r2" ISA.
	(mips_hwr_names): New variable.
	(set_default_mips_dis_options): Set mips_hwr_names.
	(parse_mips_dis_option): New "hwr-names" option which sets
	mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
	(print_insn_arg): Change return type to "int"
	and use that to indicate number of characters consumed.
	Add support for "+" operand extension character, "+A", "+B",
	"+C", and "K" operands.
	(print_insn_mips): Adjust for changes to print_insn_arg.
	(print_mips_disassembler_options): Adjust for "hwr-names"
	addition and "reg-names" change.
	* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
	(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
	forms of "sll".  Add new MIPS32 Release 2 instructions: ehb,
	di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
	rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
	Note that hardware rotate instructions (ror, rorv) can be
	used on MIPS32 Release 2, and add the official mnemonics
	for them (rotr, rotrv) and the similar "rotl" mnemonic for
	left-rotate.

6 files changed, 36 insertions, 2 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index b2a283a..b58e0d5 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,17 @@
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
+	* archures.c (bfd_mach_mipsisa32r2): New define.
+	* bfd-in2.h: Regenerate.
+	* cpu-mips.c (I_mipsisa32r2): New enum value.
+	(arch_info_struct): Add entry for I_mipsisa32r2.
+	* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
+	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
+	(_bfd_mips_elf_final_write_processing): Add
+	bfd_mach_mipsisa32r2 case.
+	(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
+	binaries marked as using MIPS32 Release 2.
+
 2002-12-30    Dmitry Diky <diwil@mail.ru>
 
 	* Makefile.am: Add msp430 target.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index d8b465c..998bca7 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -800,6 +800,7 @@ NAME(aout,machine_type) (arch, machine, unknown)
 	case bfd_mach_mips12000:
 	case bfd_mach_mips16:
 	case bfd_mach_mipsisa32:
+	case bfd_mach_mipsisa32r2:
 	case bfd_mach_mips5:
 	case bfd_mach_mipsisa64:
 	case bfd_mach_mips_sb1:
diff --git a/bfd/archures.c b/bfd/archures.c
index 2ad7267..4c93cda 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -145,6 +145,7 @@ DESCRIPTION
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
 .#define bfd_mach_mipsisa32             32
+.#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa64             64
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_i386 1
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c727679..cdcf7ae 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1572,6 +1572,7 @@ enum bfd_architecture
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
 #define bfd_mach_mipsisa32             32
+#define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa64             64
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_i386 1
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index e587535..13355c5 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -82,6 +82,7 @@ enum
   I_mips16,
   I_mips5,
   I_mipsisa32,
+  I_mipsisa32r2,
   I_mipsisa64,
   I_sb1,
 };
@@ -111,6 +112,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips16,   "mips:16",        FALSE, NN(I_mips16)),
   N (64, 64, bfd_mach_mips5,    "mips:mips5",     FALSE, NN(I_mips5)),
   N (32, 32, bfd_mach_mipsisa32,  "mips:isa32",   FALSE, NN(I_mipsisa32)),
+  N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, 0),
 };
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 80a583b..ca79c64 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -3102,6 +3102,8 @@ elf_mips_isa (flags)
       return 32;
     case E_MIPS_ARCH_64:
       return 64;
+    case E_MIPS_ARCH_32R2:
+      return 33;
     }
   return 4;
 }
@@ -3172,6 +3174,10 @@ _bfd_elf_mips_mach (flags)
 	case E_MIPS_ARCH_64:
 	  return bfd_mach_mipsisa64;
 	  break;
+
+	case E_MIPS_ARCH_32R2:
+	  return bfd_mach_mipsisa32r2;
+	  break;
 	}
     }
 
@@ -6047,6 +6053,11 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
 
     case bfd_mach_mipsisa64:
       val = E_MIPS_ARCH_64;
+      break;
+
+    case bfd_mach_mipsisa32r2:
+      val = E_MIPS_ARCH_32R2;
+      break;
     }
 
   elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);
@@ -7854,8 +7865,10 @@ _bfd_mips_elf_merge_private_bfd_data (ibfd, obfd)
 	     using 64-bit ISAs.  They will normally use the same data sizes
 	     and calling conventions.  */
 
-	  if ((  (new_isa == 1 || new_isa == 2 || new_isa == 32)
-	       ^ (old_isa == 1 || old_isa == 2 || old_isa == 32)) != 0)
+	  if ((  (new_isa == 1 || new_isa == 2 || new_isa == 32
+		  || new_isa == 33)
+	       ^ (old_isa == 1 || old_isa == 2 || old_isa == 32
+		  || old_isa == 33)) != 0)
 	    {
 	      (*_bfd_error_handler)
 	       (_("%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"),
@@ -8005,6 +8018,8 @@ _bfd_mips_elf_print_private_bfd_data (abfd, ptr)
     fprintf (file, _(" [mips32]"));
   else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
     fprintf (file, _(" [mips64]"));
+  else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2)
+    fprintf (file, _(" [mips32r2]"));
   else
     fprintf (file, _(" [unknown ISA]"));