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author | Maciej W. Rozycki <macro@linux-mips.org> | 2011-07-29 22:46:29 +0000 |
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committer | Maciej W. Rozycki <macro@linux-mips.org> | 2011-07-29 22:46:29 +0000 |
commit | 2309ddf22209e1d2ab769dc778d9f764463b8509 (patch) | |
tree | 521ed9469046338465628aa4dba2cdc408e89242 /bfd/elfxx-mips.c | |
parent | a50242fb51ba8a75bb60f15a958dde817e2c6a88 (diff) | |
download | fsf-binutils-gdb-2309ddf22209e1d2ab769dc778d9f764463b8509.zip fsf-binutils-gdb-2309ddf22209e1d2ab769dc778d9f764463b8509.tar.gz fsf-binutils-gdb-2309ddf22209e1d2ab769dc778d9f764463b8509.tar.bz2 |
bfd/
* elfxx-mips.c: Adjust comments throughout.
(mips_elf_relax_delete_bytes): Reshape code.
(_bfd_mips_elf_relax_section): Remove check for
R_MICROMIPS_GPREL16 relocations. Reshape code.
gas/
* config/tc-mips.c: Adjust comments throughout.
(reglist_lookup): Reshape code.
(jmp_reloc_p, jalr_reloc_p): Reformat.
(got16_reloc_p, hi16_reloc_p, lo16_reloc_p): Handle microMIPS
relocations.
(gpr_mod_mask): Remove unused variable.
(gpr_read_mask, gpr_write_mask): Reshape code.
(fpr_read_mask, fpr_write_mask): Likewise.
(nops_for_vr4130): Ensure non-microMIPS mode.
(can_swap_branch_p): Correct pinfo2 reference. Reshape code.
(append_insn): Skip Loongson 2F workaround in MIPS16 mode. Use
the outermost operator of a compound relocation to determines
the relocated field. Fix formatting.
(md_convert_frag): Reshape code.
include/opcode/
* mips.h: Clarify the description of microMIPS instruction
manipulation macros.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
Diffstat (limited to 'bfd/elfxx-mips.c')
-rw-r--r-- | bfd/elfxx-mips.c | 49 |
1 files changed, 22 insertions, 27 deletions
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index 53a9477..36b881e 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -11910,8 +11910,7 @@ mips_elf_relax_delete_bytes (bfd *abfd, symtab_hdr = &elf_tdata (abfd)->symtab_hdr; isym = (Elf_Internal_Sym *) symtab_hdr->contents; for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) - if (isym->st_shndx == sec_shndx - && isym->st_value > addr) + if (isym->st_shndx == sec_shndx && isym->st_value > addr) isym->st_value -= count; /* Now adjust the global symbols defined in this section. */ @@ -11928,9 +11927,8 @@ mips_elf_relax_delete_bytes (bfd *abfd, || sym_hash->root.type == bfd_link_hash_defweak) && sym_hash->root.u.def.section == sec) { - bfd_vma value; + bfd_vma value = sym_hash->root.u.def.value; - value = sym_hash->root.u.def.value; if (ELF_ST_IS_MICROMIPS (sym_hash->other)) value &= MINUS_TWO; if (value > addr) @@ -12336,6 +12334,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, unsigned long opcode; bfd_vma symval; bfd_vma pcrval; + bfd_byte *ptr; int fndopc; /* The number of bytes to delete for relaxation and from where @@ -12347,8 +12346,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, this reloc. */ if (r_type != R_MICROMIPS_HI16 && r_type != R_MICROMIPS_PC16_S1 - && r_type != R_MICROMIPS_26_S1 - && r_type != R_MICROMIPS_GPREL16) + && r_type != R_MICROMIPS_26_S1) continue; /* Get the section contents if we haven't done so already. */ @@ -12361,6 +12359,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, else if (!bfd_malloc_and_get_section (abfd, sec, &contents)) goto error_return; } + ptr = contents + irel->r_offset; /* Read this BFD's local symbols if we haven't done so already. */ if (isymbuf == NULL && symtab_hdr->sh_info != 0) @@ -12432,8 +12431,8 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, if (irel->r_offset + 4 > sec->size) continue; - opcode = bfd_get_16 (abfd, contents + irel->r_offset ) << 16; - opcode |= bfd_get_16 (abfd, contents + irel->r_offset + 2); + opcode = bfd_get_16 (abfd, ptr ) << 16; + opcode |= bfd_get_16 (abfd, ptr + 2); /* This is the pc-relative distance from the instruction the relocation is applied to, to the symbol referred. */ @@ -12477,7 +12476,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, /* See if the LUI instruction *might* be in a branch delay slot. */ if (irel->r_offset >= 2 - && check_br16_dslot (abfd, contents + irel->r_offset - 2) > 0 + && check_br16_dslot (abfd, ptr - 2) && !(irel->r_offset >= 4 /* If the instruction is actually a 4-byte branch, the value of check_br16_dslot doesn't matter. @@ -12487,7 +12486,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, irel->r_offset - 4))) continue; if (irel->r_offset >= 4 - && check_br32_dslot (abfd, contents + irel->r_offset - 4) > 0) + && check_br32_dslot (abfd, ptr - 4)) continue; reg = OP32_SREG (opcode); @@ -12502,11 +12501,11 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, case 0: break; case 2: - if (check_br16 (abfd, contents + irel->r_offset + 4, reg)) + if (check_br16 (abfd, ptr + 4, reg)) break; continue; case 4: - if (check_br32 (abfd, contents + irel->r_offset + 4, reg)) + if (check_br32 (abfd, ptr + 4, reg)) break; continue; default: @@ -12581,8 +12580,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, && irel->r_offset + 5 < sec->size && ((fndopc = find_match (opcode, bz_rs_insns_32)) >= 0 || (fndopc = find_match (opcode, bz_rt_insns_32)) >= 0) - && MATCH (bfd_get_16 (abfd, contents + irel->r_offset + 4), - nop_insn_16)) + && MATCH (bfd_get_16 (abfd, ptr + 4), nop_insn_16)) { unsigned long reg; @@ -12593,10 +12591,8 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, | BZC32_REG_FIELD (reg) | (opcode & 0xffff)); /* Addend value. */ - bfd_put_16 (abfd, (opcode >> 16) & 0xffff, - contents + irel->r_offset); - bfd_put_16 (abfd, opcode & 0xffff, - contents + irel->r_offset + 2); + bfd_put_16 (abfd, (opcode >> 16) & 0xffff, ptr); + bfd_put_16 (abfd, opcode & 0xffff, ptr + 2); /* Delete the 16-bit delay slot NOP: two bytes from irel->offset + 4. */ @@ -12617,7 +12613,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, bfd_put_16 (abfd, (b_insn_16.match | (opcode & 0x3ff)), /* Addend value. */ - contents + irel->r_offset); + ptr); /* Delete 2 bytes from irel->r_offset + 2. */ delcnt = 2; @@ -12645,7 +12641,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, (bz_insns_16[fndopc].match | BZ16_REG_FIELD (reg) | (opcode & 0x7f)), /* Addend value. */ - contents + irel->r_offset); + ptr); /* Delete 2 bytes from irel->r_offset + 2. */ delcnt = 2; @@ -12661,14 +12657,13 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, unsigned long n32opc; bfd_boolean relaxed = FALSE; - n32opc = bfd_get_16 (abfd, contents + irel->r_offset + 4) << 16; - n32opc |= bfd_get_16 (abfd, contents + irel->r_offset + 6); + n32opc = bfd_get_16 (abfd, ptr + 4) << 16; + n32opc |= bfd_get_16 (abfd, ptr + 6); if (MATCH (n32opc, nop_insn_32)) { /* Replace delay slot 32-bit NOP with a 16-bit NOP. */ - bfd_put_16 (abfd, nop_insn_16.match, - contents + irel->r_offset + 4); + bfd_put_16 (abfd, nop_insn_16.match, ptr + 4); relaxed = TRUE; } @@ -12679,7 +12674,7 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, (move_insn_16.match | MOVE16_RD_FIELD (MOVE32_RD (n32opc)) | MOVE16_RS_FIELD (MOVE32_RS (n32opc))), - contents + irel->r_offset + 4); + ptr + 4); relaxed = TRUE; } @@ -12691,9 +12686,9 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec, /* JAL with 32-bit delay slot that is changed to a JALS with 16-bit delay slot. */ bfd_put_16 (abfd, (jal_insn_32_bd16.match >> 16) & 0xffff, - contents + irel->r_offset); + ptr); bfd_put_16 (abfd, jal_insn_32_bd16.match & 0xffff, - contents + irel->r_offset + 2); + ptr + 2); /* Delete 2 bytes from irel->r_offset + 6. */ delcnt = 2; |