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authorJoseph Myers <joseph@codesourcery.com>2009-02-03 18:16:04 +0000
committerJoseph Myers <joseph@codesourcery.com>2009-02-03 18:16:04 +0000
commit52b6b6b972d426d44aa9ada61cf7f052d350a3cc (patch)
treec4dbf41fdece504534dfb283a5f7a7036e4c4af7 /bfd/cpu-mips.c
parenta53fddce83af312fd3aa023c66b007b9e3937805 (diff)
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bfd:
2009-02-03 Sandip Matte <sandip@rmicorp.com> * aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr. * archures.c (bfd_mach_mips_xlr): Define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_xlr): Define. (arch_info_struct): Add XLR entry. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR. (mips_set_isa_flags): Handle bfd_mach_mips_xlr (mips_mach_extensions): Add XLR entry. binutils: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR. gas: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT and M_MSGWAIT_T. (mips_cpu_info_table): Add XLR entry. * doc/c-mips.texi (-march): Document xlr. gas/testsuite: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * gas/mips/mips.exp (xlr): New architecture. (xlr-ext): Run test. * gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New. include/elf: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (E_MIPS_MACH_XLR): Define. include/opcode: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (INSN_XLR): Define. (INSN_CHIP_MASK): Update. (CPU_XLR): Define. (OPCODE_IS_MEMBER): Update. (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. opcodes: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define. (mips_arch_choices): Add XLR entry. * mips-opc.c (XLR): Define. (mips_builtin_opcodes): Add XLR instructions.
Diffstat (limited to 'bfd/cpu-mips.c')
-rw-r--r--bfd/cpu-mips.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 1102467..4c98821 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -91,7 +91,8 @@ enum
I_sb1,
I_loongson_2e,
I_loongson_2f,
- I_mipsocteon
+ I_mipsocteon,
+ I_xlr
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -129,7 +130,8 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
- N (64, 64, bfd_mach_mips_octeon, "mips:octeon", FALSE, 0)
+ N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
+ N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0)
};
/* The default architecture is mips:3000, but with a machine number of