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authorEric B. Weddington <eric.weddington@atmel.com>2011-03-22 18:10:48 +0000
committerEric B. Weddington <eric.weddington@atmel.com>2011-03-22 18:10:48 +0000
commit8cc66334fa03f92b70da1a17685a093b6b0850ba (patch)
tree3c347ee26f7d734336dbf0c44bbffdc0af9ccd7a /bfd/cpu-avr.c
parent3167638f1e8e74e15650adda08449c2e32572552 (diff)
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/bfd:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * archures.c: Add AVR XMEGA architecture information. * cpu-avr.c (arch_info_struct): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. (elf32_avr_object_p): Likewise. /gas: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (struct avr_opcodes_s): Add opcode field. (AVR_INSN): Change definition to match. (avr_opcodes): Likewise, change to match. (mcu_types): Add XMEGA architecture names and new XMEGA device names. (md_show_usage): Add XMEGA architecture names. (avr_operand): Add 'E' constraint for DES instruction of XMEGA devices. Add support for SPM Z+ instruction. * doc/c-avr.texi: Add documentation for XMEGA architectures and devices. /include/opcode: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): New instruction set flags. (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. /ld: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures. (eavrxmega?.c): Likewise. * configure.tgt (targ_extra_emuls): Likewise. * emulparams/avrxmega1.sh: New file. * emulparams/avrxmega2.sh: Likewise. * emulparams/avrxmega3.sh: Likewise. * emulparams/avrxmega4.sh: Likewise. * emulparams/avrxmega5.sh: Likewise. * emulparams/avrxmega6.sh: Likewise. * emulparams/avrxmega7.sh: Likewise. * emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation): Add avrxmega6, avrxmega7 to list of architectures for no stubs. /opcodes: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr-dis.c (avr_operand): Add opcode_str parameter. Check for post-increment to support LPM Z+ instruction. Add support for 'E' constraint for DES instruction. (print_insn_avr): Adjust calls to avr_operand. Rename variable.
Diffstat (limited to 'bfd/cpu-avr.c')
-rw-r--r--bfd/cpu-avr.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/bfd/cpu-avr.c b/bfd/cpu-avr.c
index 9e62ab4..07ba6dc 100644
--- a/bfd/cpu-avr.c
+++ b/bfd/cpu-avr.c
@@ -133,7 +133,29 @@ static const bfd_arch_info_type arch_info_struct[] =
N (22, bfd_mach_avr51, "avr:51", FALSE, & arch_info_struct[9]),
/* 3-Byte PC. */
- N (22, bfd_mach_avr6, "avr:6", FALSE, NULL)
+ N (22, bfd_mach_avr6, "avr:6", FALSE, & arch_info_struct[10]),
+
+ /* Xmega 1 */
+ N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[11]),
+
+ /* Xmega 2 */
+ N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[12]),
+
+ /* Xmega 3 */
+ N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[13]),
+
+ /* Xmega 4 */
+ N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[14]),
+
+ /* Xmega 5 */
+ N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[15]),
+
+ /* Xmega 6 */
+ N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[16]),
+
+ /* Xmega 7 */
+ N (24, bfd_mach_avrxmega7, "avr:107", FALSE, NULL)
+
};
const bfd_arch_info_type bfd_avr_arch =