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authorChris Demetriou <cgd@google.com>2002-02-11 06:13:49 +0000
committerChris Demetriou <cgd@google.com>2002-02-11 06:13:49 +0000
commitf701dad2bae25125b3f23d12f843aba5417b771c (patch)
treeecb41ddabc913851220029fd10ed3c128b3d1081 /README
parent06880219d1bcf36a737d27d1761c8a56cb8eda3a (diff)
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2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode fields (i.e., add and move commas) so that they more closely match the MIPS ISA documentation opcode partitioning.
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