aboutsummaryrefslogtreecommitdiff
path: root/COPYING.LIB
diff options
context:
space:
mode:
authorIgor Tsimbalist <igor.v.tsimbalist@intel.com>2018-01-17 19:45:52 +0300
committerH.J. Lu <hjl.tools@gmail.com>2018-06-14 15:40:49 -0700
commit43a3f9926388842c1e1316b378da6e75914ffb70 (patch)
tree50da321c6b4f77e7d5790f29fd80b4c1688b5b47 /COPYING.LIB
parent7b90f188b2ccb45cf9650de69c2c61a9712dc21d (diff)
downloadfsf-binutils-gdb-43a3f9926388842c1e1316b378da6e75914ffb70.zip
fsf-binutils-gdb-43a3f9926388842c1e1316b378da6e75914ffb70.tar.gz
fsf-binutils-gdb-43a3f9926388842c1e1316b378da6e75914ffb70.tar.bz2
Replace CET bit with IBT and SHSTK bits.
The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. (cherry picked from commit d777820bf5abea433c36e956b53b299502e0f708)
Diffstat (limited to 'COPYING.LIB')
0 files changed, 0 insertions, 0 deletions