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| author | YunQiang Su <yunqiang.su@cipunited.com> | 2024-07-19 19:01:52 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 19:01:52 +0100 |
| commit | 73a833412e2d613be460a0daa3fc33568bec6c13 (patch) | |
| tree | 5cd4f5fbf6dd2c148b4b8d3127d5d76664181a1c | |
| parent | 31bd9f4682d611387993a8127a25ab42252b59c9 (diff) | |
| download | fsf-binutils-gdb-73a833412e2d613be460a0daa3fc33568bec6c13.zip fsf-binutils-gdb-73a833412e2d613be460a0daa3fc33568bec6c13.tar.gz fsf-binutils-gdb-73a833412e2d613be460a0daa3fc33568bec6c13.tar.bz2 | |
MIPS/opcodes: Remove the regular MIPS "+t" operand code
The semantics of the regular MIPS "+t" operand code is exactly the same
as that of the "E" operand code, so replace the former with the latter
in the single MFTC0 instruction with implicit 'sel' == 0 encoding where
it's used, matching the encoding with explicit 'sel' as well as other
instructions.
| -rw-r--r-- | include/opcode/mips.h | 3 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f80110f..1e4b3e2 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -653,7 +653,6 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "y" 5 bit control target register (OP_*_RT) - "+t" 5 bit coprocessor 0 destination register (OP_*_RT) MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) @@ -760,7 +759,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "1234567890" "~!@#$%^&*|:'";\" "ABCEFGHIJKLMNOPQRSTUVWXZ" - "abcdefghijklmnopqrstuvwxyz" + "abcdefghijklmnopqrs uvwxyz" Extension character sequences used so far ("-" followed by the following), for quick reference when adding more: diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 6389301..734a027 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -117,7 +117,6 @@ decode_mips_operand (const char *p) case 'q': REG (0, 0, R5900_Q); case 'r': REG (0, 0, R5900_R); case 's': MSB (5, 11, 0, false, 31); /* (0 .. 31) */ - case 't': REG (5, 16, COPRO); case 'u': SPECIAL (3, 16, IMM_INDEX); case 'v': SPECIAL (2, 16, IMM_INDEX); case 'w': SPECIAL (1, 16, IMM_INDEX); @@ -1406,7 +1405,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 }, {"mftacx", "d", 0x41020021, 0xffff07ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, {"mftacx", "d,*", 0x41020021, 0xfff307ff, WR_1|RD_a|TRAP, 0, 0, MT32, 0 }, -{"mftc0", "d,+t", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, +{"mftc0", "d,E", 0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC, 0, 0, MT32, 0 }, {"mftc1", "d,T", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, {"mftc1", "d,E", 0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0, 0, MT32, 0 }, |