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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-04-19 14:54:46 +0100 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-04-19 14:56:34 +0100 |
| commit | cd6608e49d884f01536b5948ed3a64241dbb4a1f (patch) | |
| tree | 94520d967448ea6a7e515a48a338072087c32250 | |
| parent | fe1640ff8ecc95beeab88f9aa6141bbeec149485 (diff) | |
| download | fsf-binutils-gdb-cd6608e49d884f01536b5948ed3a64241dbb4a1f.zip fsf-binutils-gdb-cd6608e49d884f01536b5948ed3a64241dbb4a1f.tar.gz fsf-binutils-gdb-cd6608e49d884f01536b5948ed3a64241dbb4a1f.tar.bz2 | |
aarch64: Add new data cache maintenance operations
This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in
conjunction with DC instruction. This change is part of RME (Realm Management
Extension).
gas/ChangeLog:
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/rme.d: Update test.
* testsuite/gas/aarch64/rme.s: Update test.
opcodes/ChangeLog:
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
DC instruction.
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/rme.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/rme.s | 4 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 |
5 files changed, 18 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 2c498a6..da2f91f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * testsuite/gas/aarch64/rme.d: Update test. + * testsuite/gas/aarch64/rme.s: Update test. + 2021-04-19 Jan Beulich <jbeulich@suse.com> * as.h (sprint_value): Delete. diff --git a/gas/testsuite/gas/aarch64/rme.d b/gas/testsuite/gas/aarch64/rme.d index 3667e87..89bedb8 100644 --- a/gas/testsuite/gas/aarch64/rme.d +++ b/gas/testsuite/gas/aarch64/rme.d @@ -12,3 +12,5 @@ Disassembly of section \.text: 8: d53e2180 mrs x0, gptbr_el3 c: d51e21c0 msr gpccr_el3, x0 10: d51e2180 msr gptbr_el3, x0 + 14: d50e7e20 dc cipapa, x0 + 18: d50e7ea0 dc cigdpapa, x0 diff --git a/gas/testsuite/gas/aarch64/rme.s b/gas/testsuite/gas/aarch64/rme.s index 89ee3a8..b9a915d 100644 --- a/gas/testsuite/gas/aarch64/rme.s +++ b/gas/testsuite/gas/aarch64/rme.s @@ -8,3 +8,7 @@ mrs x0, gptbr_el3 /* Write to RME system registers. */ msr gpccr_el3, x0 msr gptbr_el3, x0 + +/* RME data cache maintenance operations. */ +dc cipapa, x0 +dc cigdpapa, x0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5dc51cd..5bae9d0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + + * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for + DC instruction. + 2021-04-19 Jan Beulich <jbeulich@suse.com> * aarch64-asm.c (encode_asimd_fcvt): Add initializer for diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 8727def..b315a82 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4763,6 +4763,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] = { "cisw", CPENS (0, C7, C14, 2), F_HASXT }, { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT }, { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT }, + { "cipapa", CPENS (6, C7, C14, 1), F_HASXT }, + { "cigdpapa", CPENS (6, C7, C14, 5), F_HASXT }, { 0, CPENS(0,0,0,0), 0 } }; |