diff options
| author | Peter Bergner <bergner@vnet.ibm.com> | 2007-10-16 02:26:30 +0000 |
|---|---|---|
| committer | Peter Bergner <bergner@vnet.ibm.com> | 2007-10-16 02:26:30 +0000 |
| commit | 8dbcd839b1bbad39586246ca2d444822b5f91ad7 (patch) | |
| tree | dd111c6f35b5d11ca6ae324f4e894c6d6ff566fb | |
| parent | 1b64748beda63e896f48cb4c9409d8629db10747 (diff) | |
| download | fsf-binutils-gdb-8dbcd839b1bbad39586246ca2d444822b5f91ad7.zip fsf-binutils-gdb-8dbcd839b1bbad39586246ca2d444822b5f91ad7.tar.gz fsf-binutils-gdb-8dbcd839b1bbad39586246ca2d444822b5f91ad7.tar.bz2 | |
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Verify instructions are sorted
according to major opcode number.
opcodes/
* ppc-opc.c (TE): Correct signedness.
(powerpc_opcodes): Sort psq_st and psq_stu according to major
opcode number.
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-ppc.c | 12 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 12 |
4 files changed, 29 insertions, 6 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 407db44..8cf8f04 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2007-10-15 Peter Bergner <bergner@vnet.ibm.com> + + * config/tc-ppc.c (ppc_setup_opcodes): Verify instructions are sorted + according to major opcode number. + 2007-10-15 Alan Modra <amodra@bigpond.net.au> * read.c (do_s_func): Check asprintf return status. diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 868258f..fc8b9a07 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1249,6 +1249,7 @@ ppc_setup_opcodes (void) const struct powerpc_macro *macro; const struct powerpc_macro *macro_end; bfd_boolean bad_insn = FALSE; + unsigned long prev_opcode = 0; if (ppc_hash != NULL) hash_die (ppc_hash); @@ -1296,6 +1297,17 @@ ppc_setup_opcodes (void) { const unsigned char *o; unsigned long omask = op->mask; + unsigned long major_opcode = PPC_OP (op->opcode); + + /* The major opcodes had better be sorted. Code in the disassembler + assumes the insns are sorted according to major opcode. */ + if (major_opcode < prev_opcode) + { + as_bad (_("major opcode is not sorted for %s"), + op->name); + bad_insn = TRUE; + } + prev_opcode = major_opcode; /* The mask had better not trim off opcode bits. */ if ((op->opcode & omask) != op->opcode) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a611ea0..a73c99b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2007-10-15 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-opc.c (TE): Correct signedness. + (powerpc_opcodes): Sort psq_st and psq_stu according to major + opcode number. + 2007-10-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Reformat. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 8dbfad3..ad30fc5 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -492,13 +492,13 @@ const struct powerpc_operand powerpc_operands[] = #define VS VD { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, - /* The SIMM field in a VX form instruction. */ + /* The SIMM field in a VX form instruction, and TE in Z form. */ #define SIMM VD + 1 +#define TE SIMM { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, - /* The UIMM field in a VX form instruction, and TE in Z form. */ + /* The UIMM field in a VX form instruction. */ #define UIMM SIMM + 1 -#define TE UIMM { 0x1f, 16, NULL, NULL, 0 }, /* The SHB field in a VA form instruction. */ @@ -4495,9 +4495,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } }, -{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } }, - { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, @@ -4561,6 +4558,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, +{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } }, +{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } }, + { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, |