[ARM] Add ARMv8.3 VJCVT instruction

Add support for VJCVT javascript conversion instruction.

gas/
	* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
	(insns): Add vjcvt.
	* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
	* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
	* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add vjcvt.

9 files changed, 76 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3f3a10e..a721bb2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,15 @@
 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
+	* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
+	(insns): Add vjcvt.
+	* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
+	* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
+	* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
+	* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
+	* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.
+
+2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
 	* config/tc-arm.c (arm_archs): Add "armv8.3-a".
 	* doc/c-arm.texi (-march): Add "armv8.3-a".
 
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b139b5e..3515fc6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -234,6 +234,8 @@ static const arm_feature_set arm_ext_ras =
 /* FP16 instructions.  */
 static const arm_feature_set arm_ext_fp16 =
   ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
+static const arm_feature_set arm_ext_v8_3 =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
 
 static const arm_feature_set arm_arch_any = ARM_ANY;
 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
@@ -17440,6 +17442,16 @@ do_crc32cw (void)
   do_crc32_1 (1, 2);
 }
 
+static void
+do_vjcvt (void)
+{
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+	      _(BAD_FPU));
+  neon_check_type (2, NS_FD, N_S32, N_F64);
+  do_vfp_sp_dp_cvt ();
+  do_vfp_cond_or_thumb ();
+}
+
 
 /* Overall per-instruction processing.	*/
 
@@ -19783,6 +19795,12 @@ static const struct asm_opcode insns[] =
  TUE ("esb", 320f010, f3af8010, 0, (), noargs,  noargs),
 
 #undef  ARM_VARIANT
+#define ARM_VARIANT   & arm_ext_v8_3
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8_3
+ NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
+
+#undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT NULL
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d
new file mode 100644
index 0000000..a38f6e6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a+fp
+#error-output: armv8_3-a-fp-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l
new file mode 100644
index 0000000..755b6f7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l
@@ -0,0 +1,7 @@
+[^:]+: Assembler messages:
+[^:]+:3: Error: operand types can't be inferred -- `vjcvt s0,d1'
+[^:]+:4: Error: VFP single precision register expected -- `vjcvt\.s32\.f64 r0,d1'
+[^:]+:5: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f64 s0,s1'
+[^:]+:6: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f32 s0,s1'
+[^:]+:7: Error: bad type in Neon instruction -- `vjcvt\.s32\.f32 s0,d1'
+[^:]+:8: Error: bad type in Neon instruction -- `vjcvt\.f32\.f64 s0,d1'
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s
new file mode 100644
index 0000000..dffb726
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s
@@ -0,0 +1,8 @@
+	.text
+	.arm
+	vjcvt s0, d1
+	vjcvt.s32.f64 r0, d1
+	vjcvt.s32.f64 s0, s1
+	vjcvt.s32.f32 s0, s1
+	vjcvt.s32.f32 s0, d1
+	vjcvt.f32.f64 s0, d1
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp.d b/gas/testsuite/gas/arm/armv8_3-a-fp.d
new file mode 100644
index 0000000..7f60754
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp.d
@@ -0,0 +1,15 @@
+#as: -march=armv8.3-a+fp
+#objdump: -dr
+#skip: *-*-pe *-wince-* *-*-coff
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+   [0-9a-f]+:	eef90bc7 	vjcvt.s32.f64	s1, d7
+   [0-9a-f]+:	eef90bc7 	vjcvt.s32.f64	s1, d7
+
+[0-9a-f]+ <.*>:
+   [0-9a-f]+:	eef9 0bc7 	vjcvt.s32.f64	s1, d7
+
diff --git a/gas/testsuite/gas/arm/armv8_3-a-fp.s b/gas/testsuite/gas/arm/armv8_3-a-fp.s
new file mode 100644
index 0000000..f02510e
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_3-a-fp.s
@@ -0,0 +1,8 @@
+	.text
+A1:
+	.arm
+	vjcvt.s32.f64 s1, d7
+	vjcvtal.s32.f64 s1, d7
+T1:
+	.thumb
+	vjcvt.s32.f64 s1, d7
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 783ffa2..e288096 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	* arm-dis.c (coprocessor_opcodes): Add vjcvt.
+
 2016-12-01  Nick Clifton  <nickc@redhat.com>
 
 	PR binutils/20893
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 87d4930..0380d37 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -971,6 +971,10 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
 
+  /* ARMv8.3 javascript conversion instruction.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+    0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
+
   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
 };