/bfd:

2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* archures.c: Add AVR XMEGA architecture information.
	* cpu-avr.c (arch_info_struct): Likewise.
	* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
	(elf32_avr_object_p): Likewise.

/gas:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
	(AVR_INSN): Change definition to match.
	(avr_opcodes): Likewise, change to match.
	(mcu_types): Add XMEGA architecture names and new XMEGA device names.
	(md_show_usage): Add XMEGA architecture names.
	(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
	Add support for SPM Z+ instruction.
	* doc/c-avr.texi: Add documentation for XMEGA architectures and
	devices.

/include/opcode:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
	New instruction set flags.
	(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.

/ld:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
	(eavrxmega?.c): Likewise.
	* configure.tgt (targ_extra_emuls): Likewise.
	* emulparams/avrxmega1.sh: New file.
	* emulparams/avrxmega2.sh: Likewise.
	* emulparams/avrxmega3.sh: Likewise.
	* emulparams/avrxmega4.sh: Likewise.
	* emulparams/avrxmega5.sh: Likewise.
	* emulparams/avrxmega6.sh: Likewise.
	* emulparams/avrxmega7.sh: Likewise.
	* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
	Add avrxmega6, avrxmega7 to list of architectures for no stubs.

/opcodes:
2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	post-increment to support LPM Z+ instruction. Add support for 'E'
	constraint for DES instruction.
	(print_insn_avr): Adjust calls to avr_operand. Rename variable.

23 files changed, 364 insertions, 16 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index a1131c8..c9e1fc3 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* archures.c: Add AVR XMEGA architecture information.
+	* cpu-avr.c (arch_info_struct): Likewise.
+	* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
+	(elf32_avr_object_p): Likewise.
+
 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 
 	* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
diff --git a/bfd/archures.c b/bfd/archures.c
index 0efc658..cd8500f 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -376,6 +376,13 @@ DESCRIPTION
 .#define bfd_mach_avr5		5
 .#define bfd_mach_avr51		51
 .#define bfd_mach_avr6		6
+.#define bfd_mach_avrxmega1 101
+.#define bfd_mach_avrxmega2 102
+.#define bfd_mach_avrxmega3 103
+.#define bfd_mach_avrxmega4 104
+.#define bfd_mach_avrxmega5 105
+.#define bfd_mach_avrxmega6 106
+.#define bfd_mach_avrxmega7 107
 .  bfd_arch_bfin,        {* ADI Blackfin *}
 .#define bfd_mach_bfin          1
 .  bfd_arch_cr16,       {* National Semiconductor CompactRISC (ie CR16). *}
diff --git a/bfd/cpu-avr.c b/bfd/cpu-avr.c
index 9e62ab4..07ba6dc 100644
--- a/bfd/cpu-avr.c
+++ b/bfd/cpu-avr.c
@@ -133,7 +133,29 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (22, bfd_mach_avr51, "avr:51", FALSE, & arch_info_struct[9]),
 
   /* 3-Byte PC.  */
-  N (22, bfd_mach_avr6, "avr:6", FALSE, NULL)
+  N (22, bfd_mach_avr6, "avr:6", FALSE, & arch_info_struct[10]),
+  
+  /* Xmega 1 */
+  N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[11]),
+
+  /* Xmega 2 */
+  N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[12]),
+  
+  /* Xmega 3 */
+  N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[13]),
+  
+  /* Xmega 4 */
+  N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[14]),
+  
+  /* Xmega 5 */
+  N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[15]),
+  
+  /* Xmega 6 */
+  N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[16]),
+  
+  /* Xmega 7 */
+  N (24, bfd_mach_avrxmega7, "avr:107", FALSE, NULL)
+  
 };
 
 const bfd_arch_info_type bfd_avr_arch =
diff --git a/bfd/elf32-avr.c b/bfd/elf32-avr.c
index ecc60de..1bc40c4 100644
--- a/bfd/elf32-avr.c
+++ b/bfd/elf32-avr.c
@@ -1298,6 +1298,34 @@ bfd_elf_avr_final_write_processing (bfd *abfd,
     case bfd_mach_avr6:
       val = E_AVR_MACH_AVR6;
       break;
+
+    case bfd_mach_avrxmega1:
+      val = E_AVR_MACH_XMEGA1;
+      break;
+
+    case bfd_mach_avrxmega2:
+      val = E_AVR_MACH_XMEGA2;
+      break;
+
+    case bfd_mach_avrxmega3:
+      val = E_AVR_MACH_XMEGA3;
+      break;
+
+    case bfd_mach_avrxmega4:
+      val = E_AVR_MACH_XMEGA4;
+      break;
+
+    case bfd_mach_avrxmega5:
+      val = E_AVR_MACH_XMEGA5;
+      break;
+
+    case bfd_mach_avrxmega6:
+      val = E_AVR_MACH_XMEGA6;
+      break;
+
+    case bfd_mach_avrxmega7:
+      val = E_AVR_MACH_XMEGA7;
+      break;
     }
 
   elf_elfheader (abfd)->e_machine = EM_AVR;
@@ -1360,6 +1388,34 @@ elf32_avr_object_p (bfd *abfd)
 	case E_AVR_MACH_AVR6:
 	  e_set = bfd_mach_avr6;
 	  break;
+
+	case E_AVR_MACH_XMEGA1:
+	  e_set = bfd_mach_avrxmega1;
+	  break;
+
+	case E_AVR_MACH_XMEGA2:
+	  e_set = bfd_mach_avrxmega2;
+	  break;
+
+	case E_AVR_MACH_XMEGA3:
+	  e_set = bfd_mach_avrxmega3;
+	  break;
+
+	case E_AVR_MACH_XMEGA4:
+	  e_set = bfd_mach_avrxmega4;
+	  break;
+
+	case E_AVR_MACH_XMEGA5:
+	  e_set = bfd_mach_avrxmega5;
+	  break;
+
+	case E_AVR_MACH_XMEGA6:
+	  e_set = bfd_mach_avrxmega6;
+	  break;
+
+	case E_AVR_MACH_XMEGA7:
+	  e_set = bfd_mach_avrxmega7;
+	  break;
 	}
     }
   return bfd_default_set_arch_mach (abfd, bfd_arch_avr,
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1155aa2..7bfd52c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
+	(AVR_INSN): Change definition to match.
+	(avr_opcodes): Likewise, change to match.
+	(mcu_types): Add XMEGA architecture names and new XMEGA device names.
+	(md_show_usage): Add XMEGA architecture names.
+	(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
+	Add support for SPM Z+ instruction.
+	* doc/c-avr.texi: Add documentation for XMEGA architectures and
+	devices.
+
 2011-03-21  Eric B. Weddington  <eric.weddington@atmel.com>
 
 	* config/tc-avr.c (md_show_usage): Add "Assembler" text to output.
diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c
index 4214d61..e924939 100644
--- a/gas/config/tc-avr.c
+++ b/gas/config/tc-avr.c
@@ -29,18 +29,19 @@ struct avr_opcodes_s
 {
   char *        name;
   char *        constraints;
+  char *        opcode;
   int           insn_size;		/* In words.  */
   int           isa;
   unsigned int  bin_opcode;
 };
 
 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
-{#NAME, CONSTR, SIZE, ISA, BIN},
+{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
 
 struct avr_opcodes_s avr_opcodes[] =
 {
   #include "opcode/avr.h"
-  {NULL, NULL, 0, 0, 0}
+  {NULL, NULL, NULL, 0, 0, 0}
 };
 
 const char comment_chars[] = ";";
@@ -79,6 +80,13 @@ static struct mcu_type_s mcu_types[] =
   {"avr5",       AVR_ISA_AVR51,   bfd_mach_avr5},
   {"avr51",      AVR_ISA_AVR51,   bfd_mach_avr51},
   {"avr6",       AVR_ISA_AVR6,    bfd_mach_avr6},
+  {"avrxmega1",  AVR_ISA_XMEGA,   bfd_mach_avrxmega1},
+  {"avrxmega2",  AVR_ISA_XMEGA,   bfd_mach_avrxmega2},
+  {"avrxmega3",  AVR_ISA_XMEGA,   bfd_mach_avrxmega3},
+  {"avrxmega4",  AVR_ISA_XMEGA,   bfd_mach_avrxmega4},
+  {"avrxmega5",  AVR_ISA_XMEGA,   bfd_mach_avrxmega5},
+  {"avrxmega6",  AVR_ISA_XMEGA,   bfd_mach_avrxmega6},
+  {"avrxmega7",  AVR_ISA_XMEGA,   bfd_mach_avrxmega7},
   {"at90s1200",  AVR_ISA_1200,    bfd_mach_avr1},
   {"attiny11",   AVR_ISA_AVR1,    bfd_mach_avr1},
   {"attiny12",   AVR_ISA_AVR1,    bfd_mach_avr1},
@@ -237,6 +245,21 @@ static struct mcu_type_s mcu_types[] =
   {"at90usb1287",AVR_ISA_AVR51,   bfd_mach_avr51},
   {"atmega2560", AVR_ISA_AVR6,    bfd_mach_avr6},
   {"atmega2561", AVR_ISA_AVR6,    bfd_mach_avr6},
+  {"atxmega16a4", AVR_ISA_XMEGA,  bfd_mach_avrxmega2},
+  {"atxmega16d4", AVR_ISA_XMEGA,  bfd_mach_avrxmega2},
+  {"atxmega32a4", AVR_ISA_XMEGA,  bfd_mach_avrxmega2},
+  {"atxmega32d4", AVR_ISA_XMEGA,  bfd_mach_avrxmega2},
+  {"atxmega64a3", AVR_ISA_XMEGA,  bfd_mach_avrxmega4},
+  {"atxmega64d3", AVR_ISA_XMEGA,  bfd_mach_avrxmega4},
+  {"atxmega64a1", AVR_ISA_XMEGA,  bfd_mach_avrxmega5},
+  {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
+  {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
   {NULL, 0, 0}
 };
 
@@ -413,6 +436,11 @@ md_show_usage (FILE *stream)
 	"                   avr5  - enhanced AVR core with up to 64K program memory\n"
 	"                   avr51 - enhanced AVR core with up to 128K program memory\n"
 	"                   avr6  - enhanced AVR core with up to 256K program memory\n"
+	"                   avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
+	"                   avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
+	"                   avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
+	"                   avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
+	"                   avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
 	"                   or immediate microcontroller name.\n"));
   fprintf (stream,
       _("  -mall-opcodes    accept all AVR opcodes, even if not supported by MCU\n"
@@ -840,7 +868,12 @@ avr_operand (struct avr_opcodes_s *opcode,
       if (*str == '+')
 	{
 	  ++str;
-	  op_mask |= 1;
+          char *s;
+          for (s = opcode->opcode; *s; ++s)
+            {
+              if (*s == '+')
+                op_mask |= (1 << (15 - (s - opcode->opcode)));
+            }
 	}
 
       /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+".  */
@@ -957,6 +990,16 @@ avr_operand (struct avr_opcodes_s *opcode,
       }
       break;
 
+    case 'E':
+      {
+	unsigned int x;
+
+	x = avr_get_constant (str, 15);
+	str = input_line_pointer;
+	op_mask |= (x << 4);
+      }
+      break;
+    
     case '?':
       break;
 
diff --git a/gas/doc/c-avr.texi b/gas/doc/c-avr.texi
index 14f8979..347dfa5b 100644
--- a/gas/doc/c-avr.texi
+++ b/gas/doc/c-avr.texi
@@ -85,6 +85,27 @@ atmega128rfa1, at90can128, at90usb1286, at90usb1287, m3000).
 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types:
 atmega2560, atmega2561).
 
+Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program
+memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4,
+atxmega32d4).
+
+Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program
+memory space and greater than 64K data space (MCU types: atxmega32a4).
+
+Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
+memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).
+
+Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program 
+memory space and greater than 64K data space (MCU types: atxmega64a1).
+
+Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
+memory space and less than 64K data space (MCU types: atxmega128a3,
+atxmega128d3, atxmega192a3, atxmega192d3, atxmega256a3, atxmega256a3b,
+atxmega192d3).
+
+Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
+memory space and greater than 64K data space (MCU types: atxmega128a1).
+
 @cindex @code{-mall-opcodes} command line option, AVR
 @item -mall-opcodes
 Accept all AVR opcodes, even if not supported by @code{-mmcu}.
diff --git a/include/elf/avr.h b/include/elf/avr.h
index b80728c..11d43f9 100644
--- a/include/elf/avr.h
+++ b/include/elf/avr.h
@@ -40,6 +40,13 @@
 #define E_AVR_MACH_AVR5 5
 #define E_AVR_MACH_AVR51 51
 #define E_AVR_MACH_AVR6 6 
+#define E_AVR_MACH_XMEGA1 101
+#define E_AVR_MACH_XMEGA2 102
+#define E_AVR_MACH_XMEGA3 103
+#define E_AVR_MACH_XMEGA4 104
+#define E_AVR_MACH_XMEGA5 105
+#define E_AVR_MACH_XMEGA6 106
+#define E_AVR_MACH_XMEGA7 107
 
 /* Relocations.  */
 START_RELOC_NUMBERS (elf_avr_reloc_type)
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 60c9bb7..fe85069 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
+	New instruction set flags.
+	(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
+
 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h (M_PREF_AB): New enum value.
diff --git a/include/opcode/avr.h b/include/opcode/avr.h
index bdf9823..c754234 100644
--- a/include/opcode/avr.h
+++ b/include/opcode/avr.h
@@ -31,6 +31,8 @@
 #define AVR_ISA_BRK   0x0400 /* device has BREAK (on-chip debug) */
 #define AVR_ISA_EIND  0x0800 /* device has >128K program memory (none yet) */
 #define AVR_ISA_MOVW  0x1000 /* device has MOVW */
+#define AVR_ISA_SPMX  0x2000 /* device has SPM Z[+] */
+#define AVR_ISA_DES   0x4000 /* device has DES */
 
 #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
 #define AVR_ISA_2xxx  (AVR_ISA_TINY1 | AVR_ISA_SRAM)
@@ -49,6 +51,8 @@
 #define AVR_ISA_94K   (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
 #define AVR_ISA_M323  (AVR_ISA_M161 | AVR_ISA_BRK)
 #define AVR_ISA_M128  (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
+#define AVR_ISA_M256  (AVR_ISA_M128 | AVR_ISA_EIND)
+#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
 
 #define AVR_ISA_AVR1   AVR_ISA_TINY1
 #define AVR_ISA_AVR2   AVR_ISA_2xxx
@@ -109,6 +113,7 @@
    L - signed pc relative offset from -2048 to 2047
    h - absolute code address (call, jmp)
    S - immediate value from 0 to 7 (S = s << 4)
+   E - immediate value from 0 to 15, shifted left by 4 (des)
    ? - use this opcode entry if no parameters, else use next opcode entry
 
    Order is important - some binary opcodes have more than one name,
@@ -169,7 +174,8 @@ AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
 AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
 AVR_INSN (break,"",    "1001010110011000", 1, AVR_ISA_BRK,  0x9598)
 AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
-AVR_INSN (spm,  "",    "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
+AVR_INSN (spm,  "?",   "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
+AVR_INSN (spm,  "z",   "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8)
 
 AVR_INSN (adc,  "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
 AVR_INSN (add,  "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
@@ -283,3 +289,6 @@ AVR_INSN (st,   "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
 AVR_INSN (eicall, "",  "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
 AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
 
+/* DES instruction for encryption and decryption */
+AVR_INSN (des,  "E",   "10010100EEEE1011", 1, AVR_ISA_DES,  0x940B)
+
diff --git a/ld/ChangeLog b/ld/ChangeLog
index e91439b..23c6f17 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,18 @@
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
+	(eavrxmega?.c): Likewise.
+	* configure.tgt (targ_extra_emuls): Likewise.
+	* emulparams/avrxmega1.sh: New file.
+	* emulparams/avrxmega2.sh: Likewise.
+	* emulparams/avrxmega3.sh: Likewise.
+	* emulparams/avrxmega4.sh: Likewise.
+	* emulparams/avrxmega5.sh: Likewise.
+	* emulparams/avrxmega6.sh: Likewise.
+	* emulparams/avrxmega7.sh: Likewise.
+	* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
+	Add avrxmega6, avrxmega7 to list of architectures for no stubs.
+
 2011-03-21  Eric B. Weddington  <eric.weddington@atmel.com>
 
 	* scripttempl/avr.sc: Add fuse, lock, and signature memory regions.
diff --git a/ld/Makefile.am b/ld/Makefile.am
index 75f13a4..a9e76f8 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -163,6 +163,13 @@ ALL_EMULATION_SOURCES = \
 	eavr5.c \
 	eavr51.c \
 	eavr6.c \
+	eavrxmega1.o \
+	eavrxmega2.o \
+	eavrxmega3.o \
+	eavrxmega4.o \
+	eavrxmega5.o \
+	eavrxmega6.o \
+	eavrxmega7.o \
 	ecoff_i860.c \
 	ecoff_sparc.c \
 	ecrisaout.c \
@@ -773,6 +780,34 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(srcdir)/emultempl/avrelf.em \
   $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
   ${GEN_DEPENDS}
 	${GENSCRIPTS} avr6 "$(tdir_avr2)"
+eavrxmega1.c: $(srcdir)/emulparams/avrxmega1.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega1 "$(tdir_avr2)"
+eavrxmega2.c: $(srcdir)/emulparams/avrxmega2.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega2 "$(tdir_avr2)"
+eavrxmega3.c: $(srcdir)/emulparams/avrxmega3.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega3 "$(tdir_avr2)"
+eavrxmega4.c: $(srcdir)/emulparams/avrxmega4.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega4 "$(tdir_avr2)"
+eavrxmega5.c: $(srcdir)/emulparams/avrxmega5.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega5 "$(tdir_avr2)"
+eavrxmega6.c: $(srcdir)/emulparams/avrxmega6.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega6 "$(tdir_avr2)"
+eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \
+  $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+  ${GEN_DEPENDS}
+	${GENSCRIPTS} avrxmega7 "$(tdir_avr2)"
 ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
   $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 4025837..88ebee3 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -111,7 +111,7 @@ xscale-*-coff)		targ_emul=armcoff ;;
 xscale-*-elf)		targ_emul=armelf
 			;;
 avr-*-*)		targ_emul=avr2
-			targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
+			targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7"
 			;;
 bfin-*-elf)		targ_emul=elf32bfin;
 			targ_extra_emuls="elf32bfinfd"
diff --git a/ld/emulparams/avrxmega1.sh b/ld/emulparams/avrxmega1.sh
new file mode 100644
index 0000000..95e8aac
--- /dev/null
+++ b/ld/emulparams/avrxmega1.sh
@@ -0,0 +1,12 @@
+ARCH=avr:101
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emulparams/avrxmega2.sh b/ld/emulparams/avrxmega2.sh
new file mode 100644
index 0000000..f282a69
--- /dev/null
+++ b/ld/emulparams/avrxmega2.sh
@@ -0,0 +1,12 @@
+ARCH=avr:102
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emulparams/avrxmega3.sh b/ld/emulparams/avrxmega3.sh
new file mode 100644
index 0000000..abaa5b3
--- /dev/null
+++ b/ld/emulparams/avrxmega3.sh
@@ -0,0 +1,12 @@
+ARCH=avr:103
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emulparams/avrxmega4.sh b/ld/emulparams/avrxmega4.sh
new file mode 100644
index 0000000..829c8b7
--- /dev/null
+++ b/ld/emulparams/avrxmega4.sh
@@ -0,0 +1,12 @@
+ARCH=avr:104
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emulparams/avrxmega5.sh b/ld/emulparams/avrxmega5.sh
new file mode 100644
index 0000000..0a09aee
--- /dev/null
+++ b/ld/emulparams/avrxmega5.sh
@@ -0,0 +1,12 @@
+ARCH=avr:105
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emulparams/avrxmega6.sh b/ld/emulparams/avrxmega6.sh
new file mode 100644
index 0000000..3c3a468
--- /dev/null
+++ b/ld/emulparams/avrxmega6.sh
@@ -0,0 +1,12 @@
+ARCH=avr:106
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emulparams/avrxmega7.sh b/ld/emulparams/avrxmega7.sh
new file mode 100644
index 0000000..b84a0ba
--- /dev/null
+++ b/ld/emulparams/avrxmega7.sh
@@ -0,0 +1,12 @@
+ARCH=avr:107
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=1024K
+DATA_ORIGIN=0x802000
+DATA_LENGTH=0xffa0
+EXTRA_EM_FILE=avrelf
diff --git a/ld/emultempl/avrelf.em b/ld/emultempl/avrelf.em
index 84f1633..7f8c05e 100644
--- a/ld/emultempl/avrelf.em
+++ b/ld/emultempl/avrelf.em
@@ -71,8 +71,10 @@ avr_elf_${EMULATION_NAME}_before_allocation (void)
 
   gld${EMULATION_NAME}_before_allocation ();
 
-  /* We only need stubs for the avr6 family.  */
-  if (strcmp ("${EMULATION_NAME}","avr6"))
+  /* We only need stubs for avr6, avrxmega6, and avrxmega7. */
+  if (strcmp ("${EMULATION_NAME}","avr6") 
+      && strcmp ("${EMULATION_NAME}","avrxmega6")
+      && strcmp ("${EMULATION_NAME}","avrxmega7") )
     avr_no_stubs = TRUE;
 
   avr_elf_set_global_bfd_parameters ();
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0300c26..6ef4525 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
+	post-increment to support LPM Z+ instruction. Add support for 'E'
+	constraint for DES instruction.
+	(print_insn_avr): Adjust calls to avr_operand. Rename variable.
+
 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 
 	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
diff --git a/opcodes/avr-dis.c b/opcodes/avr-dis.c
index 976c371..85d7ab3 100644
--- a/opcodes/avr-dis.c
+++ b/opcodes/avr-dis.c
@@ -50,7 +50,7 @@ static const char * comment_start = "0x";
 
 static int
 avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
-             char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
+             char *opcode_str, char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
 {
   int ok = 1;
   *sym = 0;
@@ -118,8 +118,18 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
 
     case 'z':
       *buf++ = 'Z';
-      if (insn & 0x1)
+
+      /* Check for post-increment. */
+      char *s;
+      for (s = opcode_str; *s; ++s)
+        {
+          if (*s == '+')
+            {
 	*buf++ = '+';
+              break;
+            }
+        }
+
       *buf = '\0';
       if (AVR_UNDEF_P (insn))
 	sprintf (comment, _("undefined"));
@@ -227,6 +237,10 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
       }
       break;
       
+    case 'E':
+      sprintf (buf, "%d", (insn >> 4) & 15);
+      break;
+      
     case '?':
       *buf = '\0';
       break;
@@ -331,7 +345,8 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
 
   if (opcode->name)
     {
-      char *op = opcode->constraints;
+      char *constraints = opcode->constraints;
+      char *opcode_str = opcode->opcode;
 
       insn2 = 0;
       ok = 1;
@@ -342,14 +357,14 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
 	  cmd_len = 4;
 	}
 
-      if (*op && *op != '?')
+      if (*constraints && *constraints != '?')
 	{
-	  int regs = REGISTER_P (*op);
+	  int regs = REGISTER_P (*constraints);
 
-	  ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0, &sym_op1, &sym_addr1);
+	  ok = avr_operand (insn, insn2, addr, *constraints, opcode_str, op1, comment1, 0, &sym_op1, &sym_addr1);
 
-	  if (ok && *(++op) == ',')
-	    ok = avr_operand (insn, insn2, addr, *(++op), op2,
+	  if (ok && *(++constraints) == ',')
+	    ok = avr_operand (insn, insn2, addr, *(++constraints), opcode_str, op2,
 			      *comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2);
 	}
     }