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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2019-01-14 10:35:50 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2019-01-14 10:35:50 +0000 |
| commit | 55e8aae79a341ce777565dade196e47773b53274 (patch) | |
| tree | a612486a502e2eb83198668e24c7d4f6223418b4 | |
| parent | 4ea904edb7b04ad526bd8a5401729a6c1f5a982f (diff) | |
| download | fsf-binutils-gdb-55e8aae79a341ce777565dade196e47773b53274.zip fsf-binutils-gdb-55e8aae79a341ce777565dade196e47773b53274.tar.gz fsf-binutils-gdb-55e8aae79a341ce777565dade196e47773b53274.tar.bz2 | |
Implement the assembly instructions yield, wfe, wfi and sev for ARMv6T2 in both ARM mode and Thumb mode.
* config/tc-arm.c (arm_ext_v6k_v6t2): Define.
(insns) [ARM_VARIANT]: Modified.
(insns) [THUMB_VARIANT]: To implement few ARMv6K instructions
in ARMv6T2 as well.
* testsuite/gas/arm/archv6t2-1.d: New test.
* testsuite/gas/arm/archv6t2-1.s: Likewise.
* testsuite/gas/arm/archv6t2-2.d: Likewise.
| -rw-r--r-- | gas/ChangeLog | 10 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/archv6t2-1.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/archv6t2-1.s | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/archv6t2-2.d | 12 |
5 files changed, 44 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 7d47d93..abc0923 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2019-01-14 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * config/tc-arm.c (arm_ext_v6k_v6t2): Define. + (insns) [ARM_VARIANT]: Modified. + (insns) [THUMB_VARIANT]: To implement few ARMv6K instructions + in ARMv6T2 as well. + * testsuite/gas/arm/archv6t2-1.d: New test. + * testsuite/gas/arm/archv6t2-1.s: Likewise. + * testsuite/gas/arm/archv6t2-2.d: Likewise. + 2019-01-11 Alan Modra <amodra@gmail.com> PR 23963 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 7900c1b..da5dd25 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -204,6 +204,9 @@ static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J); static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6); static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K); static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2); +/* Only for compatability of hint instructions. */ +static const arm_feature_set arm_ext_v6k_v6t2 = + ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2); static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM); static const arm_feature_set arm_ext_v6_dsp = @@ -19994,9 +19997,9 @@ static const struct asm_opcode insns[] = TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), #undef ARM_VARIANT -#define ARM_VARIANT & arm_ext_v6k +#define ARM_VARIANT & arm_ext_v6k_v6t2 #undef THUMB_VARIANT -#define THUMB_VARIANT & arm_ext_v6k +#define THUMB_VARIANT & arm_ext_v6k_v6t2 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), diff --git a/gas/testsuite/gas/arm/archv6t2-1.d b/gas/testsuite/gas/arm/archv6t2-1.d new file mode 100644 index 0000000..a4b4c34 --- /dev/null +++ b/gas/testsuite/gas/arm/archv6t2-1.d @@ -0,0 +1,12 @@ +# name: ARMv6T2 THUMB mode +# as: -march=armv6t2 -mthumb +# source: archv6t2-1.s +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> bf10 yield +0[0-9a-f]+ <[^>]+> bf20 wfe +0[0-9a-f]+ <[^>]+> bf30 wfi +0[0-9a-f]+ <[^>]+> bf40 sev diff --git a/gas/testsuite/gas/arm/archv6t2-1.s b/gas/testsuite/gas/arm/archv6t2-1.s new file mode 100644 index 0000000..b621bbe --- /dev/null +++ b/gas/testsuite/gas/arm/archv6t2-1.s @@ -0,0 +1,5 @@ + .text + yield + wfe + wfi + sev diff --git a/gas/testsuite/gas/arm/archv6t2-2.d b/gas/testsuite/gas/arm/archv6t2-2.d new file mode 100644 index 0000000..0617bfc --- /dev/null +++ b/gas/testsuite/gas/arm/archv6t2-2.d @@ -0,0 +1,12 @@ +# name: ARMv6T2 ARM mode +# as: -march=armv6t2 +# source: archv6t2-1.s +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e320f001 yield +0[0-9a-f]+ <[^>]+> e320f002 wfe +0[0-9a-f]+ <[^>]+> e320f003 wfi +0[0-9a-f]+ <[^>]+> e320f004 sev |