diff options
| author | Svein Seldal <svein@dev.seldal.com> | 2002-11-18 08:28:44 +0000 |
|---|---|---|
| committer | Svein Seldal <svein@dev.seldal.com> | 2002-11-18 08:28:44 +0000 |
| commit | 48c5eb8a707f4a6daf9c3f1da5691a0f3f678884 (patch) | |
| tree | f8bff8fc06a93750ff72a9c8da4f3eba071390b9 | |
| parent | 23ce3b1cd03d01e68979f3a4a66fd16aba993fe0 (diff) | |
| download | fsf-binutils-gdb-48c5eb8a707f4a6daf9c3f1da5691a0f3f678884.zip fsf-binutils-gdb-48c5eb8a707f4a6daf9c3f1da5691a0f3f678884.tar.gz fsf-binutils-gdb-48c5eb8a707f4a6daf9c3f1da5691a0f3f678884.tar.bz2 | |
TIC4X testcase commit
* binutils/testsuite/binutils-all/objcopy.exp: Disable tic4x
from test
* binutils/testsuite/binutils-all/objdump.exp: Setup proper
values for tic4x testcase
* gas/testsuite/gas/all/gas.exp: Setup for tic4x testcase
* gas/testsuite/gas/macros/macros.exp: Ditto
* gas/testsuite/gas/all/gas.exp: Setup for tic4x testcase
* gas/testsuite/gas/macros/macros.exp: Ditto
* gas/testsuite/gas/tic4x: New tic4x gas testsuite directory
* ld/testsuite/ld-scripts/script.exp: Setup for tic4x testcase
27 files changed, 6354 insertions, 8 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index bbf1d61..8a58087 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,9 @@ +2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> + + * testsuite/binutils-all/objcopy.exp: Disable tic4x from test + * testsuite/binutils-all/objdump.exp: Setup proper values for tic4x + testcase + 2002-11-14 Nick Clifton <nickc@redhat.com> * readelf.c (process_program_headers): Add comment about return diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsuite/binutils-all/objcopy.exp index e36f14e..5d4a1bb 100644 --- a/binutils/testsuite/binutils-all/objcopy.exp +++ b/binutils/testsuite/binutils-all/objcopy.exp @@ -80,7 +80,7 @@ if ![string match "" $got] then { setup_xfail "m8*-*" setup_xfail "or32-*-rtems*" "or32-*-coff" setup_xfail "sh-*-coff*" "sh-*-rtems*" - setup_xfail "tic80-*-*" "w65-*" "z8*-*" + setup_xfail "tic4x-*-*" "tic80-*-*" "w65-*" "z8*-*" clear_xfail "hppa*64*-*-hpux*" "hppa*-*-linux*" "hppa*-*-lites*" clear_xfail "hppa*-*-*n*bsd*" "hppa*-*-rtems*" "*-*-*elf*" "m68*-*-sysv4*" diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp index 53168d4..bdfc4b1 100644 --- a/binutils/testsuite/binutils-all/objdump.exp +++ b/binutils/testsuite/binutils-all/objdump.exp @@ -96,6 +96,11 @@ if ![regexp $want $got all text_name text_size data_name data_size] then { verbose "data name is $data_name size is $data_size" set ets 8 set eds 4 + # The [ti]c4x target has the property sizeof(char)=sizeof(long)=1 + if [istarget *c4x*-*-*] then { + set ets 2 + set eds 1 + } # c54x section sizes are in bytes, not octets; adjust accordingly if [istarget *c54x*-*-*] then { set ets 4 diff --git a/gas/ChangeLog b/gas/ChangeLog index 7c3c96d..338b873 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,28 @@ +2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> + + * testsuite/gas/all/gas.exp: Setup for tic4x testcase + * testsuite/gas/macros/macros.exp: Ditto + * testsuite/gas/tic4x: New tic4x gas testsuite directory + * testsuite/gas/tic4x/addressing.s: Create + * testsuite/gas/tic4x/addressing_c3x.d: Create + * testsuite/gas/tic4x/addressing_c4x.d: Create + * testsuite/gas/tic4x/allopcodes.S: Create + * testsuite/gas/tic4x/data.d: Create + * testsuite/gas/tic4x/data.s: Create + * testsuite/gas/tic4x/float.d: Create + * testsuite/gas/tic4x/float.s: Create + * testsuite/gas/tic4x/opclasses.h: Create + * testsuite/gas/tic4x/opcodes.s: Create + * testsuite/gas/tic4x/opcodes_c3x.d: Create + * testsuite/gas/tic4x/opcodes_c4x.d: Create + * testsuite/gas/tic4x/rebuild.sh: Create + * testsuite/gas/tic4x/registers.s: Create + * testsuite/gas/tic4x/registers_c3x.d: Create + * testsuite/gas/tic4x/registers_c4x.d: Create + * testsuite/gas/tic4x/tic4x.exp: Create + * testsuite/gas/tic4x/zeros.d: Create + * testsuite/gas/tic4x/zeros.s: Create + 2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> * config/tc-tic4x.c: Remove c4x_pseudo_ignore function. diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index ddbc76d..31cfa4e 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -90,8 +90,10 @@ proc do_930509a {} { # C54x assembler (for compatibility) does not allow differences between # forward references # C30 counts a four byte offset as a difference of one. -if { ![istarget hppa*-*-*] - && ![istarget *c30*-*-*] && ![istarget *c54x*-*-*] } then { +if { ![istarget hppa*-*-*] && + ![istarget *c30*-*-*] && + ![istarget *c4x*-*-*] && + ![istarget *c54x*-*-*] } then { # the vax fails because VMS can apparently actually handle this # case in relocs, so gas doesn't handle it itself. setup_xfail "h8300*-*-elf*" "mn10200*-*-*" "mn10300*-*-*" "vax*-*-vms*" @@ -102,6 +104,7 @@ if { ![istarget hppa*-*-*] # These directives are done in the c54x-specific tests instead case $target_triplet in { { hppa*-*-* } { } + { *c4x*-*-* } { } { *c54x*-*-* } { } default { run_dump_test struct @@ -115,7 +118,7 @@ case $target_triplet in { # We omit the ARM toolchains because they define locals to # start with '.', which eliminates .eos, .text etc from the output. # Omit c54x, since .tag and .def mean something different on that target -if { ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c54x*-*-coff]) \ +if { ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \ ||([istarget *-*-pe*] && ![istarget arm*-*-pe*] && ![istarget thumb*-*-pe*]) \ || [istarget a29k-*-udi*] \ || [istarget a29k-*-ebmon*] \ @@ -158,6 +161,7 @@ proc test_cond {} { # again, p2align doesn't work on c54x target case $target_triplet in { { hppa*-*-* } { } + { *c4x*-*-* } { } { *c54x*-*-* } { } default { test_cond diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp index b90cd96..313f612 100644 --- a/gas/testsuite/gas/macros/macros.exp +++ b/gas/testsuite/gas/macros/macros.exp @@ -4,13 +4,13 @@ if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } { run_dump_test test1 } -if ![istarget *c54x*-*-*] { +if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } { run_dump_test test2 } run_dump_test test3 -if ![istarget *c54x*-*-*] { +if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } { run_dump_test irp run_dump_test rept } @@ -20,13 +20,14 @@ gas_test_error "err.s" "" "macro infinite recursion" case $target_triplet in { { hppa*-*-* } { if [istarget *-*-linux*] { run_dump_test semi } } + { *c4x*-*-* } { } { *c54x*-*-* } { } default { run_dump_test semi } } -if { ![istarget hppa*-*-*] || [istarget *-*-linux*]} { +if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } { # FIXME: Due to macro mishandling of ONLY_STANDARD_ESCAPES. setup_xfail "avr-*" "cris-*" @@ -36,6 +37,6 @@ if { ![istarget hppa*-*-*] || [istarget *-*-linux*]} { setup_xfail "rs6000-*-*" # FIXME: Due to difference in what "consecutive octets" means. - setup_xfail "*c54x*-*" + setup_xfail "*c4x*-*-*" "*c54x*-*" run_dump_test strings } diff --git a/gas/testsuite/gas/tic4x/addressing.s b/gas/testsuite/gas/tic4x/addressing.s new file mode 100644 index 0000000..fa09513 --- /dev/null +++ b/gas/testsuite/gas/tic4x/addressing.s @@ -0,0 +1,371 @@ + ;; + ;; test all addressing modes and register constraints + ;; (types/classes is read from include/opcodes/tic4x.h) + ;; + .text +start: + + ;; + ;; Type B - infix condition branch + ;; +Type_BI:bu Type_BI ; Unconditional branch (00000) + bc Type_BI ; Carry branch (00001) + blo Type_BI ; Lower than branch (00001) + bls Type_BI ; Lower than or same branch (00010) + bhi Type_BI ; Higher than branch (00011) + bhs Type_BI ; Higher than or same branch (00100) + bnc Type_BI ; No carry branch (00100) + beq Type_BI ; Equal to branch (00101) + bz Type_BI ; Zero branch (00101) + bne Type_BI ; Not equal to branch (00110) + bnz Type_BI ; Not zero branch (00110) + blt Type_BI ; Less than branch (00111) + bn Type_BI ; Negative branch (00111) + ble Type_BI ; Less than or equal to branch (01000) + bgt Type_BI ; Greater than branch (01001) + bp Type_BI ; Positive branch (01001) + bge Type_BI ; Greater than or equal branch (01010) + bnn Type_BI ; Nonnegative branch (01010) + bnv Type_BI ; No overflow branch (01000) + bv Type_BI ; Overflow branch (01101) + bnuf Type_BI ; No underflow branch (01110) + buf Type_BI ; Underflow branch (01111) + bnlv Type_BI ; No latched overflow branch (10000) + blv Type_BI ; Latched overflow branch (10001) + bnluf Type_BI ; No latched FP underflow branch (10010) + bluf Type_BI ; Latched FP underflow branch (10011) + bzuf Type_BI ; Zero or FP underflow branch (10100) + b Type_BI ; Unconditional branch (00000) + + ;; + ;; Type C - infix condition load + ;; +Type_CI:ldiu R0,R0 ; Unconditional load (00000) + ldic R0,R0 ; Carry load (00001) + ldilo R0,R0 ; Lower than load (00001) + ldils R0,R0 ; Lower than or same load (00010) + ldihi R0,R0 ; Higher than load (00011) + ldihs R0,R0 ; Higher than or same load (00100) + ldinc R0,R0 ; No carry load (00100) + ldieq R0,R0 ; Equal to load (00101) + ldiz R0,R0 ; Zero load (00101) + ldine R0,R0 ; Not equal to load (00110) + ldinz R0,R0 ; Not zero load (00110) + ldil R0,R0 ; Less than load (00111) + ldin R0,R0 ; Negative load (00111) + ldile R0,R0 ; Less than or equal to load (01000) + ldigt R0,R0 ; Greater than load (01001) + ldip R0,R0 ; Positive load (01001) + ldige R0,R0 ; Greater than or equal load (01010) + ldinn R0,R0 ; Nonnegative load (01010) + ldinv R0,R0 ; No overflow load (01000) + ldiv R0,R0 ; Overflow load (01101) + ldinuf R0,R0 ; No underflow load (01110) + ldiuf R0,R0 ; Underflow load (01111) + ldinlv R0,R0 ; No latched overflow load (10000) + ldilv R0,R0 ; Latched overflow load (10001) + ldinluf R0,R0 ; No latched FP underflow load (10010) + ldiluf R0,R0 ; Latched FP underflow load (10011) + ldizuf R0,R0 ; Zero or FP underflow load (10100) + + ;; + ;; Type * - Indirect (full) + ;; +Type_ind: + ldi *AR0,R0 ; Indirect addressing (G=10) + ldi *+AR0(5),R0 ; with predisplacement add + ldi *-AR0(5),R0 ; with predisplacement subtract + ldi *++AR0(5),R0 ; with predisplacement add and modify + ldi *--AR0(5),R0 ; with predisplacement subtract and modify + ldi *AR0++(5),R0 ; with postdisplacement add and modify + ldi *AR0--(5),R0 ; with postdisplacement subtract and modify + ldi *AR0++(5)%,R0 ; with postdisplacement add and circular modify + ldi *AR0--(5)%,R0 ; with postdisplacement subtract and circular modify + ldi *+AR0(IR0),R0 ; with predisplacement add + ldi *-AR0(IR0),R0 ; with predisplacement subtract + ldi *++AR0(IR0),R0 ; with predisplacement add and modify + ldi *--AR0(IR0),R0 ; with predisplacement subtract and modify + ldi *AR0++(IR0),R0 ; with postdisplacement add and modify + ldi *AR0--(IR0),R0 ; with postdisplacement subtract and modify + ldi *AR0++(IR0)%,R0 ; with postdisplacement add and circular modify + ldi *AR0--(IR0)%,R0 ; with postdisplacement subtract and circular modify + ldi *AR0++(IR0)B,R0 ; with postincrement add and bit-reversed modify + ldi *AR0++,R0 ; Same as *AR0++(1) + + ;; + ;; Type # - Direct for ldp + ;; +Type_ldp: + ldp 12 + ldp @start + ldp start + + ;; + ;; Type @ - Direct + ;; +Type_dir: + ldi @start,R0 + ldi start,R0 + ldi @16,R0 + ldi @65535,R0 + + ;; + ;; Type A - Address register + ;; +Type_A: dbc AR0,R0 + dbc AR2,R0 + dbc AR7,R0 + + ;; + ;; Type B - Unsigned integer (PC) + ;; +Type_B: br start + br 0x809800 + + ;; + ;; Type C - Indirect + ;; + .ifdef TEST_C4X +Type_C: addc3 *+AR0(5),R0,R0 + .endif + + ;; + ;; Type E - Register (all) + ;; +Type_E: andn3 R0,R0,R0 + andn3 AR0,R0,R0 + addc3 DP,R0,R0 + andn3 R7,R0,R0 + + ;; + ;; Type e - Register (0-11) + ;; +Type_ee:subf3 R7,R0,R0 + addf3 R0,R0,R0 + addf3 R7,R0,R0 + cmpf3 R7,R0 + .ifdef TEST_C4X + addf3 R11,R0,R0 + .endif + + ;; + ;; Type F - Short float immediate + ;; +Type_F: ldf 0,R0 + ldf 3.5,R0 + ldf -3.5,R0 + ldf 0e-3.5e-1,R0 + + ;; + ;; Type G - Register (all) + ;; +Type_G: andn3 R0,AR0,R0 + addc3 R0,DP,R0 + addc3 R0,R0,R0 + andn3 R0,R7,R0 + + ;; + ;; Type g - Register (0-11) + ;; +Type_gg:subf3 R0,R7,R0 + addf3 R0,R0,R0 + addf3 R0,R7,R0 + cmpf3 R0,R7 + .ifdef TEST_C4X + addf3 R0,R11,R0 + .endif + + ;; + ;; Type H - Register (0-7) + ;; +Type_H: stf R0,*AR0 &|| stf R0,*AR0 + stf R0,*AR0 &|| stf R2,*AR0 + stf R0,*AR0 &|| stf R7,*AR0 + + ;; + ;; Type I - Indirect + ;; +Type_I: addf3 *AR0,R0,R0 ; Indirect addressing (G=10) + addf3 *+AR0(1),R0,R0 ; with predisplacement add + addf3 *-AR0(1),R0,R0 ; with predisplacement subtract + addf3 *++AR0(1),R0,R0 ; with predisplacement add and modify + addf3 *--AR0(1),R0,R0 ; with predisplacement subtract and modify + addf3 *AR0++(1),R0,R0 ; with postdisplacement add and modify + addf3 *AR0--(1),R0,R0 ; with postdisplacement subtract and modify + addf3 *AR0++(1)%,R0,R0; with postdisplacement add and circular modify + addf3 *AR0--(1)%,R0,R0; with postdisplacement subtract and circular modify + addf3 *+AR0(IR0),R0,R0; with predisplacement add + addf3 *-AR0(IR0),R0,R0; with predisplacement subtract + addf3 *++AR0(IR0),R0,R0; with predisplacement add and modify + addf3 *--AR0(IR0),R0,R0; with predisplacement subtract and modify + addf3 *AR0++(IR0),R0,R0; with postdisplacement add and modify + addf3 *AR0--(IR0),R0,R0; with postdisplacement subtract and modify + addf3 *AR0++(IR0)%,R0,R0; with postdisplacement add and circular modify + addf3 *AR0--(IR0)%,R0,R0; with postdisplacement subtract and circular modify + addf3 *AR0++(IR0)B,R0,R0; with postincrement add and bit-reversed modify + addf3 *AR0++,R0,R0 ; Same as *AR0++(1) + + ;; + ;; Type J - Indirect + ;; +Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10) + addf3 R0,*+AR0(1),R0 ; with predisplacement add + addf3 R0,*-AR0(1),R0 ; with predisplacement subtract + addf3 R0,*++AR0(1),R0 ; with predisplacement add and modify + addf3 R0,*--AR0(1),R0 ; with predisplacement subtract and modify + addf3 R0,*AR0++(1),R0 ; with postdisplacement add and modify + addf3 R0,*AR0--(1),R0 ; with postdisplacement subtract and modify + addf3 R0,*AR0++(1)%,R0; with postdisplacement add and circular modify + addf3 R0,*AR0--(1)%,R0; with postdisplacement subtract and circular modify + addf3 R0,*+AR0(IR0),R0; with predisplacement add + addf3 R0,*-AR0(IR0),R0; with predisplacement subtract + addf3 R0,*++AR0(IR0),R0; with predisplacement add and modify + addf3 R0,*--AR0(IR0),R0; with predisplacement subtract and modify + addf3 R0,*AR0++(IR0),R0; with postdisplacement add and modify + addf3 R0,*AR0--(IR0),R0; with postdisplacement subtract and modify + addf3 R0,*AR0++(IR0)%,R0; with postdisplacement add and circular modify + addf3 R0,*AR0--(IR0)%,R0; with postdisplacement subtract and circular modify + addf3 R0,*AR0++(IR0)B,R0; with postincrement add and bit-reversed modify + addf3 R0,*AR0++,R0 ; Same as *AR0++(1) + + ;; + ;; Type K - Register (0-7) + ;; +Type_K: ldf *AR0,R0 &|| ldf *AR0,R0 + ldf *AR0,R0 &|| ldf *AR0,R2 + ldf *AR0,R0 &|| ldf *AR0,R7 + + ;; + ;; Type L - Register (0-7) + ;; +Type_L: stf R0,*AR0 &|| stf R0,*AR0 + stf R2,*AR0 &|| stf R0,*AR0 + stf R7,*AR0 &|| stf R0,*AR0 + + ;; + ;; Type M - Register (2-3) + ;; +Type_M: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2 + mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R3 + + ;; + ;; Type N - Register (0-1) + ;; +Type_N: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2 + mpyf3 *AR0,*AR0,R1 &|| addf3 R0,R0,R2 + + ;; + ;; Type O - Indirect + ;; + .ifdef TEST_C4X +Type_O: addc3 *+AR0(5),*+AR0(5),R0 + .endif + + ;; + ;; Type P - Displacement (PC rel) + ;; +Type_P: callc start + callc 1 + + ;; + ;; Type Q - Register (all) + ;; +Type_Q: ldi R0,R0 + ldi AR0,R0 + ldi DP,R0 + ldi SP,R0 + + ;; + ;; Type q - Register (0-11) + ;; +Type_qq:fix R0,R0 + fix R7,R0 + .ifdef TEST_C4X + fix R11,R0 + absf R11,R0 + .endif + + ;; + ;; Type R - Register (all) + ;; +Type_R: ldi R0,R0 + ldi R0,AR0 + ldi R0,DP + ldi R0,SP + + ;; + ;; Type r - Register (0-11) + ;; +Type_rr:ldf R0,R0 + ldf R0,R7 + .ifdef TEST_C4X + ldf R0,R11 + .endif + + ;; + ;; Type S - Signed immediate + ;; +Type_S: ldi 0,R0 + ldi -123,R0 + ldi 6543,R0 + ldi -32768, R0 + + ;; + ;; Type T - Integer + ;; + .ifdef TEST_C4X +Type_T: stik 0,*AR0 + stik 12,*AR0 + stik -5,*AR0 + .endif + + ;; + ;; Type U - Unsigned integer + ;; +Type_U: and 0,R0 + and 256,R0 + and 65535,R0 + + ;; + ;; Type V - Vector + ;; +Type_V: trapu 12 + trapu 0 + trapu 31 + .ifdef TEST_C4X + trapu 511 + .endif + + ;; + ;; Type W - Short int + ;; + .ifdef TEST_C4X +Type_W: addc3 -3,R0,R0 + addc3 5,R0,R0 + .endif + + ;; + ;; Type X - Expansion register + ;; + .ifdef TEST_C4X +Type_X: ldep IVTP,R0 + ldep TVTP,R0 + .endif + + ;; + ;; Type Y - Address register + ;; + .ifdef TEST_C4X +Type_Y: lda R0,AR0 + lda R0,DP + lda R0,SP + lda R0,IR0 + .endif + + ;; + ;; Type Z - Expansion register + ;; + .ifdef TEST_C4X +Type_Z: ldpe R0,IVTP + ldpe R0,TVTP + .endif diff --git a/gas/testsuite/gas/tic4x/addressing_c3x.d b/gas/testsuite/gas/tic4x/addressing_c3x.d new file mode 100644 index 0000000..cd1c3ea --- /dev/null +++ b/gas/testsuite/gas/tic4x/addressing_c3x.d @@ -0,0 +1,243 @@ +#as: -m30 --defsym TEST_C3X=1 +#objdump: -d -z +#name: c3x addressing modes +#source: addressing.s + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <Type_BI>: + 0: 6a00ffff.* + 1: 6a01fffe.* + 2: 6a01fffd.* + 3: 6a02fffc.* + 4: 6a03fffb.* + 5: 6a04fffa.* + 6: 6a04fff9.* + 7: 6a05fff8.* + 8: 6a05fff7.* + 9: 6a06fff6.* + a: 6a06fff5.* + b: 6a07fff4.* + c: 6a07fff3.* + d: 6a08fff2.* + e: 6a09fff1.* + f: 6a09fff0.* + 10: 6a0affef.* + 11: 6a0affee.* + 12: 6a0cffed.* + 13: 6a0dffec.* + 14: 6a0effeb.* + 15: 6a0fffea.* + 16: 6a10ffe9.* + 17: 6a11ffe8.* + 18: 6a12ffe7.* + 19: 6a13ffe6.* + 1a: 6a14ffe5.* + 1b: 6a00ffe4.* + +0000001c <Type_CI>: + 1c: 50000000.* + 1d: 50800000.* + 1e: 50800000.* + 1f: 51000000.* + 20: 51800000.* + 21: 52000000.* + 22: 52000000.* + 23: 52800000.* + 24: 52800000.* + 25: 53000000.* + 26: 53000000.* + 27: 53800000.* + 28: 53800000.* + 29: 54000000.* + 2a: 54800000.* + 2b: 54800000.* + 2c: 55000000.* + 2d: 55000000.* + 2e: 56000000.* + 2f: 56800000.* + 30: 57000000.* + 31: 57800000.* + 32: 58000000.* + 33: 58800000.* + 34: 59000000.* + 35: 59800000.* + 36: 5a000000.* + +00000037 <Type_ind>: + 37: 0840c000.* + 38: 08400005.* + 39: 08400805.* + 3a: 08401005.* + 3b: 08401805.* + 3c: 08402005.* + 3d: 08402805.* + 3e: 08403005.* + 3f: 08403805.* + 40: 08404000.* + 41: 08404800.* + 42: 08405000.* + 43: 08405800.* + 44: 08406000.* + 45: 08406800.* + 46: 08407000.* + 47: 08407800.* + 48: 0840c800.* + 49: 08402001.* + +0000004a <Type_ldp>: + 4a: 5070000c.* + 4b: 50700000.* + 4c: 50700000.* + +0000004d <Type_dir>: + 4d: 08200000.* + 4e: 08200000.* + 4f: 08200010.* + 50: 0820ffff.* + +00000051 <Type_A>: + 51: 6c010000.* + 52: 6c810000.* + 53: 6dc10000.* + +00000054 <Type_B>: + 54: 60000000.* + 55: 60809800.* + +00000056 <Type_E>: + 56: 22000000.* + 57: 22000008.* + 58: 20000010.* + 59: 22000007.* + +0000005a <Type_ee>: + 5a: 26800007.* + 5b: 20800000.* + 5c: 20800007.* + 5d: 23000007.* + +0000005e <Type_F>: + 5e: 07608000.* + 5f: 07601600.* + 60: 07601a00.* + 61: 0760eccd.* + +00000062 <Type_G>: + 62: 22000800.* + 63: 20001000.* + 64: 20000000.* + 65: 22000700.* + +00000066 <Type_gg>: + 66: 26800700.* + 67: 20800000.* + 68: 20800700.* + 69: 23000700.* + +0000006a <Type_H>: + 6a: c000c0c0.* + 6b: c002c0c0.* + 6c: c007c0c0.* + +0000006d <Type_I>: + 6d: 20c000c0.* + 6e: 20c00000.* + 6f: 20c00008.* + 70: 20c00010.* + 71: 20c00018.* + 72: 20c00020.* + 73: 20c00028.* + 74: 20c00030.* + 75: 20c00038.* + 76: 20c00040.* + 77: 20c00048.* + 78: 20c00050.* + 79: 20c00058.* + 7a: 20c00060.* + 7b: 20c00068.* + 7c: 20c00070.* + 7d: 20c00078.* + 7e: 20c000c8.* + 7f: 20c00020.* + +00000080 <Type_J>: + 80: 20a0c000.* + 81: 20a00000.* + 82: 20a00800.* + 83: 20a01000.* + 84: 20a01800.* + 85: 20a02000.* + 86: 20a02800.* + 87: 20a03000.* + 88: 20a03800.* + 89: 20a04000.* + 8a: 20a04800.* + 8b: 20a05000.* + 8c: 20a05800.* + 8d: 20a06000.* + 8e: 20a06800.* + 8f: 20a07000.* + 90: 20a07800.* + 91: 20a0c800.* + 92: 20a02000.* + +00000093 <Type_K>: + 93: c400c0c0.* + 94: c410c0c0.* + 95: c438c0c0.* + +00000096 <Type_L>: + 96: c000c0c0.* + 97: c080c0c0.* + 98: c1c0c0c0.* + +00000099 <Type_M>: + 99: 8000c0c0.* + 9a: 8040c0c0.* + +0000009b <Type_N>: + 9b: 8000c0c0.* + 9c: 8080c0c0.* + +0000009d <Type_P>: + 9d: 7201ff62.* + 9e: 72010001.* + +0000009f <Type_Q>: + 9f: 08000000.* + a0: 08000008.* + a1: 08000010.* + a2: 08000014.* + +000000a3 <Type_qq>: + a3: 05000000.* + a4: 05000007.* + +000000a5 <Type_R>: + a5: 08000000.* + a6: 08080000.* + a7: 08100000.* + a8: 08140000.* + +000000a9 <Type_rr>: + a9: 07000000.* + aa: 07070000.* + +000000ab <Type_S>: + ab: 08600000.* + ac: 0860ff85.* + ad: 0860198f.* + ae: 08608000.* + +000000af <Type_U>: + af: 02e00000.* + b0: 02e00100.* + b1: 02e0ffff.* + +000000b2 <Type_V>: + b2: 7400002c.* + b3: 74000020.* + b4: 7400003f.* diff --git a/gas/testsuite/gas/tic4x/addressing_c4x.d b/gas/testsuite/gas/tic4x/addressing_c4x.d new file mode 100644 index 0000000..0f1aff7 --- /dev/null +++ b/gas/testsuite/gas/tic4x/addressing_c4x.d @@ -0,0 +1,278 @@ +#as: -m40 --defsym TEST_C4X=1 +#objdump: -d -z +#name: c4x addressing modes +#source: addressing.s + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <Type_BI>: + 0: 6a00ffff.* + 1: 6a01fffe.* + 2: 6a01fffd.* + 3: 6a02fffc.* + 4: 6a03fffb.* + 5: 6a04fffa.* + 6: 6a04fff9.* + 7: 6a05fff8.* + 8: 6a05fff7.* + 9: 6a06fff6.* + a: 6a06fff5.* + b: 6a07fff4.* + c: 6a07fff3.* + d: 6a08fff2.* + e: 6a09fff1.* + f: 6a09fff0.* + 10: 6a0affef.* + 11: 6a0affee.* + 12: 6a0cffed.* + 13: 6a0dffec.* + 14: 6a0effeb.* + 15: 6a0fffea.* + 16: 6a10ffe9.* + 17: 6a11ffe8.* + 18: 6a12ffe7.* + 19: 6a13ffe6.* + 1a: 6a14ffe5.* + 1b: 6a00ffe4.* + +0000001c <Type_CI>: + 1c: 50000000.* + 1d: 50800000.* + 1e: 50800000.* + 1f: 51000000.* + 20: 51800000.* + 21: 52000000.* + 22: 52000000.* + 23: 52800000.* + 24: 52800000.* + 25: 53000000.* + 26: 53000000.* + 27: 53800000.* + 28: 53800000.* + 29: 54000000.* + 2a: 54800000.* + 2b: 54800000.* + 2c: 55000000.* + 2d: 55000000.* + 2e: 56000000.* + 2f: 56800000.* + 30: 57000000.* + 31: 57800000.* + 32: 58000000.* + 33: 58800000.* + 34: 59000000.* + 35: 59800000.* + 36: 5a000000.* + +00000037 <Type_ind>: + 37: 0840c000.* + 38: 08400005.* + 39: 08400805.* + 3a: 08401005.* + 3b: 08401805.* + 3c: 08402005.* + 3d: 08402805.* + 3e: 08403005.* + 3f: 08403805.* + 40: 08404000.* + 41: 08404800.* + 42: 08405000.* + 43: 08405800.* + 44: 08406000.* + 45: 08406800.* + 46: 08407000.* + 47: 08407800.* + 48: 0840c800.* + 49: 08402001.* + +0000004a <Type_ldp>: + 4a: 5070000c.* + 4b: 50700000.* + 4c: 50700000.* + +0000004d <Type_dir>: + 4d: 08200000.* + 4e: 08200000.* + 4f: 08200010.* + 50: 0820ffff.* + +00000051 <Type_A>: + 51: 6c010000.* + 52: 6c810000.* + 53: 6dc10000.* + +00000054 <Type_B>: + 54: 60ffffab.* + 55: 60809800.* + +00000056 <Type_C>: + 56: 30200028.* + +00000057 <Type_E>: + 57: 22000000.* + 58: 22000008.* + 59: 20000010.* + 5a: 22000007.* + +0000005b <Type_ee>: + 5b: 26800007.* + 5c: 20800000.* + 5d: 20800007.* + 5e: 23000007.* + 5f: 2080001f.* + +00000060 <Type_F>: + 60: 07608000.* + 61: 07601600.* + 62: 07601a00.* + 63: 0760eccd.* + +00000064 <Type_G>: + 64: 22000800.* + 65: 20001000.* + 66: 20000000.* + 67: 22000700.* + +00000068 <Type_gg>: + 68: 26800700.* + 69: 20800000.* + 6a: 20800700.* + 6b: 23000700.* + 6c: 20801f00.* + +0000006d <Type_H>: + 6d: c000c0c0.* + 6e: c002c0c0.* + 6f: c007c0c0.* + +00000070 <Type_I>: + 70: 20c000c0.* + 71: 20c00000.* + 72: 20c00008.* + 73: 20c00010.* + 74: 20c00018.* + 75: 20c00020.* + 76: 20c00028.* + 77: 20c00030.* + 78: 20c00038.* + 79: 20c00040.* + 7a: 20c00048.* + 7b: 20c00050.* + 7c: 20c00058.* + 7d: 20c00060.* + 7e: 20c00068.* + 7f: 20c00070.* + 80: 20c00078.* + 81: 20c000c8.* + 82: 20c00020.* + +00000083 <Type_J>: + 83: 20a0c000.* + 84: 20a00000.* + 85: 20a00800.* + 86: 20a01000.* + 87: 20a01800.* + 88: 20a02000.* + 89: 20a02800.* + 8a: 20a03000.* + 8b: 20a03800.* + 8c: 20a04000.* + 8d: 20a04800.* + 8e: 20a05000.* + 8f: 20a05800.* + 90: 20a06000.* + 91: 20a06800.* + 92: 20a07000.* + 93: 20a07800.* + 94: 20a0c800.* + 95: 20a02000.* + +00000096 <Type_K>: + 96: c400c0c0.* + 97: c410c0c0.* + 98: c438c0c0.* + +00000099 <Type_L>: + 99: c000c0c0.* + 9a: c080c0c0.* + 9b: c1c0c0c0.* + +0000009c <Type_M>: + 9c: 8000c0c0.* + 9d: 8040c0c0.* + +0000009e <Type_N>: + 9e: 8000c0c0.* + 9f: 8080c0c0.* + +000000a0 <Type_O>: + a0: 30602828.* + +000000a1 <Type_P>: + a1: 7201ff5e.* + a2: 72010001.* + +000000a3 <Type_Q>: + a3: 08000000.* + a4: 08000008.* + a5: 08000010.* + a6: 08000014.* + +000000a7 <Type_qq>: + a7: 05000000.* + a8: 05000007.* + a9: 0500001f.* + aa: 0000001f.* + +000000ab <Type_R>: + ab: 08000000.* + ac: 08080000.* + ad: 08100000.* + ae: 08140000.* + +000000af <Type_rr>: + af: 07000000.* + b0: 07070000.* + b1: 071f0000.* + +000000b2 <Type_S>: + b2: 08600000.* + b3: 0860ff85.* + b4: 0860198f.* + b5: 08608000.* + +000000b6 <Type_T>: + b6: 1560c000.* + b7: 156cc000.* + b8: 157bc000.* + +000000b9 <Type_U>: + b9: 02e00000.* + ba: 02e00100.* + bb: 02e0ffff.* + +000000bc <Type_V>: + bc: 7400000c.* + bd: 74000000.* + be: 7400001f.* + bf: 740001ff.* + +000000c0 <Type_W>: + c0: 300000fd.* + c1: 30000005.* + +000000c2 <Type_X>: + c2: 76000000.* + c3: 76000001.* + +000000c4 <Type_Y>: + c4: 1e880000.* + c5: 1e900000.* + c6: 1e940000.* + c7: 1e910000.* + +000000c8 <Type_Z>: + c8: 76800000.* + c9: 76810000.* diff --git a/gas/testsuite/gas/tic4x/allopcodes.S b/gas/testsuite/gas/tic4x/allopcodes.S new file mode 100644 index 0000000..ec5746f --- /dev/null +++ b/gas/testsuite/gas/tic4x/allopcodes.S @@ -0,0 +1,206 @@ +;;; +;;; Test all opcodes and argument permuation +;;; To make our job a lot simpler, we define a couple of +;;; insn classes, that we use to generate the proper +;;; test output. +;;; +;;; To rebuild this file you must use +;;; ./rebuild.sh +;;; +#include "opclasses.h" + + .text +start: B_CLASS( absf ) + P_CLASS( absf, stf ) + A_CLASS( absi ) + P_CLASS( absi, sti ) + A_CLASS( addc ) + TC_CLASS( addc ) + B_CLASS( addf ) + SC_CLASS( addf ) + QC_CLASS( addf, stf ) + A_CLASS( addi ) + TC_CLASS( addi ) + QC_CLASS( addi, sti ) + AU_CLASS( and ) + TC_CLASS( and ) + QC_CLASS( and, sti ) + AU_CLASS( andn ) + T_CLASS( andn ) + A_CLASS( ash ) + T_CLASS( ash ) + Q_CLASS( ash, sti ) + J_CLASS( bC, b ) + J_CLASS( bCd, bd ) +br_I: br start +brd_I: brd start +call_I: call start +call_JS: callc R0 + callc start + B_CLASS( cmpf ) + S2_CLASS( cmpf ) + A_CLASS( cmpi ) + T2_CLASS( cmpi ) + D_CLASS( dbC, db ) + D_CLASS( dbCd, dbd ) + AF_CLASS( fix ) + P_CLASS( fix, sti ) + BI_CLASS( float ) + P_CLASS( float, stf ) +iack_Z: iack @start + iack *+AR0(1) +idle_Z: idle + .ifdef TEST_IDLE2 +idle2_Z: idle2 + .endif + B_CLASS( lde ) + B_CLASS( ldf ) + LL_CLASS( ldf ) + P_CLASS( ldf, stf ) + BB_CLASS( ldfC ) + B6_CLASS( ldfi ) + A_CLASS( ldi ) + LL_CLASS( ldi ) + P_CLASS( ldi, sti ) + AB_CLASS( ldiC ) + A6_CLASS( ldii ) +ldp_Z: ldp start + B_CLASS( ldm ) + .ifdef TEST_LPWR +lopower_Z: lopower + .endif + A_CLASS( lsh ) + T_CLASS( lsh ) + Q_CLASS( lsh, sti ) + .ifdef TEST_LPWR +maxspeed_Z: maxspeed + .endif + B_CLASS( mpyf ) + SC_CLASS( mpyf ) + M_CLASS( mpyf, addf ) + QC_CLASS( mpyf, stf ) + M_CLASS( mpyf, subf ) + A_CLASS( mpyi ) + TC_CLASS( mpyi ) + M_CLASS( mpyi, addi ) + QC_CLASS( mpyi, sti ) + M_CLASS( mpyi, subi ) + A_CLASS( negb ) + B_CLASS( negf ) + P_CLASS( negf, stf ) + A_CLASS( negi ) + P_CLASS( negi, sti ) + A2_CLASS( nop ) + B_CLASS( norm ) + AU_CLASS( not ) + P_CLASS( not, sti ) + AU_CLASS( or ) + TC_CLASS( or ) + QC_CLASS( or, sti ) + R_CLASS( pop ) + RF_CLASS( popf ) + R_CLASS( push ) + RF_CLASS( pushf ) +reti_Z: retiC + reti +rets_Z: retsC + rets + B_CLASS( rnd ) + R_CLASS( rol ) + R_CLASS( rolc ) + R_CLASS( ror ) + R_CLASS( rorc ) +rptb_I2: rptb start + A3_CLASS( rpts ) +sigi_Z: sigi + B7_CLASS( stf ) + LS_CLASS( stf ) + B7_CLASS( stfi ) + A7_CLASS( sti ) + LS_CLASS( sti ) + A7_CLASS( stii ) + A_CLASS( subb ) + T_CLASS( subb ) + A_CLASS( subc ) + B_CLASS( subf ) + S_CLASS( subf ) + Q_CLASS( subf, stf ) + A_CLASS( subi ) + T_CLASS( subi ) + Q_CLASS( subi, sti ) + A_CLASS( subrb ) + B_CLASS( subrf ) + A_CLASS( subri ) +swi_Z: swi +trap_Z: trapC 10 + trap 10 + AU_CLASS( tstb ) + T2C_CLASS( tstb ) + AU_CLASS( xor ) + TC_CLASS( xor ) + QC_CLASS( xor, sti ) + + .ifdef TEST_C4X + J_CLASS( bCaf, baf ) + J_CLASS( bCat, bat ) + B6_CLASS( frieee ) + P_CLASS( frieee, stf ) +laj_I: laj start +laj_JS: lajc R0 + lajc start +lat_Z: latC 10 + A_CLASS( lb0 ) + A_CLASS( lb1 ) + A_CLASS( lb2 ) + A_CLASS( lb3 ) + AU_CLASS( lbu0 ) + AU_CLASS( lbu1 ) + AU_CLASS( lbu2 ) + AU_CLASS( lbu3 ) + AY_CLASS( lda ) +ldep_Z: ldep IVTP, AR0 +ldhi_Z: ldhi 35, R0 + ldhi start, R0 +ldpe_Z: ldpe AR0, IVTP +ldpk_Z: ldpk start + A_CLASS( lh0 ) + A_CLASS( lh1 ) + AU_CLASS( lhu0 ) + AU_CLASS( lhu1 ) + A_CLASS( lwl0 ) + A_CLASS( lwl1 ) + A_CLASS( lwl2 ) + A_CLASS( lwl3 ) + A_CLASS( lwr0 ) + A_CLASS( lwr1 ) + A_CLASS( lwr2 ) + A_CLASS( lwr3 ) + A_CLASS( mb0 ) + A_CLASS( mb1 ) + A_CLASS( mb2 ) + A_CLASS( mb3 ) + A_CLASS( mh0 ) + A_CLASS( mh1 ) + A_CLASS( mh2 ) + A_CLASS( mh3 ) + A_CLASS( mpyshi ) + TC_CLASS( mpyshi ) + A_CLASS( mpyuhi ) + TC_CLASS( mpyuhi ) + BA_CLASS( rcpf ) +retid_Z: retiCd + retid +rptb2_I2: rptb AR0 +rptbd_I2: rptbd start + rptbd AR0 + B_CLASS( rsqrf ) + A6_CLASS( sigi ) +sti2_A7: sti -5, @start + sti -5, *+AR0(5) +stik_Z: stik -5, @start + stik -5, *+AR0(5) + B_CLASS( toieee ) + P_CLASS( toieee, stf ) + .endif + .end + diff --git a/gas/testsuite/gas/tic4x/data.d b/gas/testsuite/gas/tic4x/data.d new file mode 100644 index 0000000..75f8e7b --- /dev/null +++ b/gas/testsuite/gas/tic4x/data.d @@ -0,0 +1,93 @@ +#objdump: -dz +#name: data tests + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <BYTE>: + 0: 0000000a.* + 1: 000000ff.* + 2: 00000061.* + 3: 00000062.* + 4: 00000063.* + 5: 00000061.* + +00000006 <HWORD>: + 6: 0000000a.* + 7: 0000ffff.* + 8: 00000061.* + 9: 00000062.* + a: 00000063.* + b: 00000061.* + +0000000c <INT>: + c: 0000000a.* + d: 00000000.* + e: ffffffff.* + f: 00000061.* + 10: 00000062.* + 11: 00000063.* + 12: 00000061.* + +00000013 <LONG>: + 13: ffffabcd.* + 14: 00000141.* + +00000015 <WORD>: + 15: 00000c80.* + 16: 00000042.* + 17: ffffffbf.* + 18: 0000f410.* + 19: 00000041.* + +0000001a <STRING>: + 1a: 44434241.* + 1b: 54535251.* + 1c: 73756f48.* + 1d: 306e6f74.* + +0000001e <ASCII>: + 1e: 73696854.* + 1f: 20736920.* + 20: 65762061.* + 21: 6c207972.* + 22: 20676e6f.* + 23: 74786574.* + 24: 69685400.* + 25: 73692073.* + 26: 6f6e6120.* + 27: 72656874.* + 28: 00000000.* + +00000029 <ASCIZ>: + 29: 73696854.* + 2a: 20736920.* + 2b: 65762061.* + 2c: 6c207972.* + 2d: 20676e6f.* + 2e: 74786574.* + 2f: 73696854.* + 30: 20736920.* + 31: 746f6e61.* + 32: 00726568.* + +00000033 <BLOCK>: + 33: 00000000.* + 34: 00000000.* + 35: 00000000.* + 36: 00000000.* + +00000037 <SPACE>: + 37: 00000000.* + 38: 00000000.* + 39: 00000000.* + 3a: 00000000.* + +0000003b <ALIGN>: + 3b: 08000000.* + 3c: 0c800000.* + 3d: 0c800000.* + 3e: 0c800000.* + 3f: 0c800000.* + 40: 08000000.* diff --git a/gas/testsuite/gas/tic4x/data.s b/gas/testsuite/gas/tic4x/data.s new file mode 100644 index 0000000..e77835c --- /dev/null +++ b/gas/testsuite/gas/tic4x/data.s @@ -0,0 +1,14 @@ + .text +BYTE: .byte 10,-1,"abc",'a' +HWORD: .hword 10,-1,"abc",'a' +INT: .int 10,IEEE,-1,"abc",'a' +LONG: .long 0FFFFABCDH,'A'+100h +WORD: .word 3200,1+'A',-'A',0F410h,'A' +STRING: .string "ABCD", 51h, 52h, 53h, 54h, "Houston", 36+12 +ASCII: .ascii "This is a very long text","This is another" +ASCIZ: .asciz "This is a very long text","This is another" +BLOCK: .block 4 +SPACE: .space 4 +ALIGN: ldi r0,r0 + .align + ldi r0,r0 diff --git a/gas/testsuite/gas/tic4x/float.d b/gas/testsuite/gas/tic4x/float.d new file mode 100644 index 0000000..50545bf --- /dev/null +++ b/gas/testsuite/gas/tic4x/float.d @@ -0,0 +1,82 @@ +#objdump: -d -z +#name: flonum constants + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <start>: + 0: 07608000.* + 1: 076012cd.* + 2: 07604580.* + 3: 0760e0a4.* + 4: 07604a80.* + 5: 0760ef5c.* + 6: 0760f800.* + 7: 07608000.* + 8: 07608000.* + 9: 0760f000.* + a: 0760e800.* + b: 076012cd.* + c: 0760e0a4.* + d: 07604a80.* + e: 0760ef5c.* + +0000000f <FLOAT>: + f: 80000000.* + 10: 00000000.* + 11: ff000000.* + 12: ff800000.* + 13: 53fba6af.* + 14: 01400000.* + 15: 06760000.* + 16: 01490fdb.* + +00000017 <SINGLE>: + 17: 80000000.* + 18: 00000000.* + 19: ff000000.* + 1a: ff800000.* + 1b: 53fba6af.* + 1c: 01400000.* + 1d: 06760000.* + 1e: 01490fdb.* + +0000001f <DOUBLE>: + 1f: 80000000.* + 20: 00000000.* + 21: ff000000.* + 22: ff800000.* + 23: 53fba6af.* + 24: 01400000.* + 25: 06760000.* + 26: 01490fdb.* + +00000027 <LDOUBLE>: + 27: 80000000.* + 28: 00000000.* + 29: 00000000.* + 2a: 00000000.* + 2b: ff000000.* + 2c: 00000000.* + 2d: ff800000.* + 2e: 80000000.* + 2f: 53fba6ae.* + 30: fba6ae9f.* + 31: 01400000.* + 32: 40000000.* + 33: 06760000.* + 34: 76000000.* + 35: 01490fda.* + 36: 490fdaa3.* + +00000037 <IEEE>: + 37: 00000000.* + 38: 3f800000.* + 39: 3f000000.* + 3a: bf800000.* + 3b: 00000000.* + 3c: e9045951.* + 3d: 40400000.* + 3e: 42f60000.* + 3f: 40490fdb.* diff --git a/gas/testsuite/gas/tic4x/float.s b/gas/testsuite/gas/tic4x/float.s new file mode 100644 index 0000000..af8d820 --- /dev/null +++ b/gas/testsuite/gas/tic4x/float.s @@ -0,0 +1,28 @@ + ;; test float numbers and constants + .text + ;; Standard GAS syntax +start: ldf 0e0, f0 + ldf 0e2.7, f0 + ldf 0e2.7e1, f0 + ldf 0e2.7e-1, f0 + ldf 0e-2.7e1, f0 + ldf 0e-2.7e-1, f0 + ldf -0e1.0, f0 + + ;; Standard TI syntax + ldf 0, f0 + ldf 0.0, f0 + ldf 0.5, f0 + ldf -0.5, f0 + ldf 2.7, f0 + ldf 2.7e-1, f0 + ldf -2.7e1, f0 + ldf -2.7e-1, f0 + +FLOAT: .float 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654 +SINGLE: .single 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654 +DOUBLE: .double 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654 +LDOUBLE: .ldouble 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654 +IEEE: .ieee 0f0, 0f1.0, 0f0.5, 0f-1,0, 0e-1.0e25, 3, 123, 0f3.141592654 + + .end diff --git a/gas/testsuite/gas/tic4x/opclasses.h b/gas/testsuite/gas/tic4x/opclasses.h new file mode 100644 index 0000000..c77c41d --- /dev/null +++ b/gas/testsuite/gas/tic4x/opclasses.h @@ -0,0 +1,804 @@ +/* Opcode infix + B condition 16--20 U,C,Z,LO,HI, etc. + C condition 23--27 U,C,Z,LO,HI, etc. + + Arguments + , required arg follows + ; optional arg follows + + General addressing modes + * indirect 0--15 *+AR0(5), *++AR0(IR0) + # direct (for ldp only) 0--15 @start, start + @ direct 0--15 @start, start + F short float immediate 0--15 3.5, 0e-3.5e-1 + Q register 0--15 R0, AR0, DP, SP + R register 16--20 R0, AR0, DP, SP + S short int immediate 0--15 -5, 5 + D src and dst same reg + + Three operand addressing modes + E register 0--7 R0, R7, R11 + G register 8--15 R0, R7, R11 + I indirect(short) 0--7 *+AR0(1), *+AR0(IR0) + J indirect(short) 8--15 *+AR0(1), *+AR0(IR0) + R register 16--20 R0, R7, R11 + W short int (C4x) 0--7 -3, 5 + C indirect(short) (C4x) 0--7 *+AR0(5) + O indirect(short) (C4x) 8--15 *+AR0(5) + + Parallel instruction addressing modes + E register 0--7 R0, R7, R11 + G register 8--15 R0, R7, R11 + H register 18--16 R0, R7 + I indirect(short) 0--7 *+AR0(1), *+AR0(IR0) + J indirect(short) 8--15 *+AR0(1), *+AR0(IR0) + K register 19--21 R0, R7 + L register 22--24 R0, R7 + M register (R2,R3) 22--22 R2, R3 + N register (R0,R1) 23--23 R0, R1 + + Misc. addressing modes + A address register 22--24 AR0, AR7 + B unsigned integer 0--23 @start, start (absolute on C3x, relative on C4x) + P displacement (PC Rel) 0--15 @start, start + U unsigned integer 0--15 0, 65535 + V vector (C4x: 0--8) 0--4 25, 7 + T integer (C4x) 16--20 -5, 12 + Y address reg (C4x) 16--20 AR0, DP, SP, IR0 + X expansion reg (C4x) 0--4 IVTP, TVTP + Z expansion reg (C4x) 16--20 IVTP, TVTP +*/ + +/* A: General 2-operand integer operations + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI, + SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn, + MBn, MHn, MPYSHI, MPYUHI +*/ +#define A_CLASS(name) \ +name##_A: &\ + name AR1, AR0 /* Q;R */ &\ + name AR0 /* Q;R */ &\ + name @start, AR0 /* @,R */ &\ + name *+AR0(5), AR0 /* *,R */ &\ + name -5, AR0 /* S,R */ + + +/* AB: General 2-operand integer operation with condition + Syntax: <i>c src, dst + c = Condition + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 1/0 - LDIc +*/ +#define AB_CLASS(name) \ +name##_AB: &\ + name AR1, AR0 /* Q;R */ &\ + name AR0 /* Q;R */ &\ + name @start, AR0 /* @,R */ &\ + name *+AR0(5), AR0 /* *,R */ &\ + name -5, AR0 /* S,R */ + + +/* AU: General 2-operand unsigned integer operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + dst = Register (R) + Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn +*/ +#define AU_CLASS(name) \ +name##_AU: &\ + name AR1, AR0 /* Q;R */ &\ + name AR0 /* Q;R */ &\ + name @start, AR0 /* @,R */ &\ + name *+AR0(5), AR0 /* *,R */ &\ + name 5, AR0 /* U,R */ + + +/* AF: General 2-operand float to integer operation + Syntax: <i> src, dst + src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register (R) + Instr: 1/0 - FIX +*/ +#define AF_CLASS(name) \ +name##_AF: &\ + name R1, R0 /* Q;R */ &\ + name R0 /* Q;R */ &\ + name @start, AR0 /* @,R */ &\ + name *+AR0(5), AR0 /* *,R */ &\ + name 3.5, AR0 /* F,R */ + + +/* A2: Limited 1-operand (integer) operation + Syntax: <i> src + src = Register (Q), Indirect (*), None + Instr: 1/0 - NOP +*/ +#define A2_CLASS(name) \ +name##_A2: &\ + name AR0 /* Q */ &\ + name *+AR0(5) /* * */ &\ + name /* */ + + +/* A3: General 1-operand unsigned integer operation + Syntax: <i> src + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + Instr: 1/0 - RPTS +*/ +#define A3_CLASS(name) \ +name##_A3: &\ + name AR1 /* Q */ &\ + name @start /* @ */ &\ + name *+AR0(5) /* * */ &\ + name 5 /* U */ + + +/* A6: Limited 2-operand integer operation + Syntax: <i> src, dst + src = Direct (@), Indirect (*) + dst = Register (R) + Instr: 1/1 - LDII, C4x: SIGI +*/ +#define A6_CLASS(name) \ +name##_A6: &\ + name @start, AR0 /* @,R */ &\ + name *+AR0(5), AR0 /* *,R */ + + +/* A7: Limited 2-operand integer store operation + Syntax: <i> src, dst + src = Register (R) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STI, STII +*/ +#define A7_CLASS(name) \ +name##_A7: &\ + name AR0, @start /* R,@ */ &\ + name AR0, *+AR0(5) /* R,* */ + + +/* AY: General 2-operand signed address load operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Address register - ARx, IRx, DP, BK, SP (Y) + Instr: 0/1 - C4x: LDA + Note: Q and Y should *never* be the same register +*/ +#define AY_CLASS(name) \ +name##_AY: &\ + name AR1, AR0 /* Q,Y */ &\ + name @start, AR0 /* @,Y */ &\ + name *+AR0(5), AR0 /* *,Y */ &\ + name -5, AR0 /* S,Y */ + + +/* B: General 2-operand float operation + Syntax: <i> src, dst + src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (R) + Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND, + SUBF, SUBRF, C4x: RSQRF, TOIEEE +*/ +#define B_CLASS(name) \ +name##_B: &\ + name R1, R0 /* Q;R */ &\ + name R0 /* Q;R */ &\ + name @start, R0 /* @,R */ &\ + name *+AR0(5), R0 /* *,R */ &\ + name 3.5, R0 /* F,R */ + + +/* BA: General 2-operand integer to float operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (R) + Instr: 0/1 - C4x: CRCPF +*/ +#define BA_CLASS(name) \ +name##_BA: &\ + name AR1, R0 /* Q;R */ &\ + name R0 /* Q;R */ &\ + name @start, R0 /* @,R */ &\ + name *+AR0(5), R0 /* *,R */ &\ + name 3.5, R0 /* F,R */ + + +/* BB: General 2-operand conditional float operation + Syntax: <i>c src, dst + c = Condition + src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (R) + Instr: 1/0 - LDFc +*/ +#define BB_CLASS(name) \ +name##_BB: &\ + name R1, R0 /* Q;R */ &\ + name R0 /* Q;R */ &\ + name @start, R0 /* @,R */ &\ + name *+AR0(5), R0 /* *,R */ &\ + name 3.5, R0 /* F,R */ + + +/* BI: General 2-operand integer to float operation (yet different to BA) + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register 0-11 (R) + Instr: 1/0 - FLOAT +*/ +#define BI_CLASS(name) \ +name##_BI: &\ + name AR1, R0 /* Q;R */ &\ + name R0 /* Q;R */ &\ + name @start, R0 /* @,R */ &\ + name *+AR0(5), R0 /* *,R */ &\ + name -5, R0 /* S,R */ + + +/* B6: Limited 2-operand float operation + Syntax: <i> src, dst + src = Direct (@), Indirect (*) + dst = Register 0-11 (R) + Instr: 1/1 - LDFI, C4x: FRIEEE +*/ +#define B6_CLASS(name) \ +name##_B6: &\ + name @start, R0 /* @,R */ &\ + name *+AR0(5), R0 /* *,R */ + + +/* B7: Limited 2-operand float store operation + Syntax: <i> src, dst + src = Register 0-11 (R) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STF, STFI +*/ +#define B7_CLASS(name) \ +name##_B7: &\ + name R0, @start /* R,@ */ &\ + name R0, *+AR0(5) /* R,* */ + + +/* D: Decrement and brach operations + Syntax: <i>c ARn, dst + c = condition + ARn = AR register 0-11 (A) + dst = Register (Q), PC-relative (P) + Instr: 2/0 - DBc, DBcD + Alias: <name1> <name2> +*/ +#define D_CLASS(name1, name2) \ +name1##_D: &\ + name1 AR0, R0 /* A,Q */ &\ + name1 AR0, start /* A,P */ &\ +name2##_D: &\ + name2 AR0, R0 /* A,Q */ &\ + name2 AR0, start /* A,P */ + + +/* J: General conditional branch operations + Syntax: <i>c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc + Alias: <name1> <name2> +*/ +#define J_CLASS(name1, name2) \ +name1##_J: &\ + name1 R0 /* Q */ &\ + name1 start /* P */ &\ +name2##_J: &\ + name2 R0 /* Q */ &\ + name2 start /* P */ + + +/* LL: Load-load parallell operation + Syntax: <i> src2, dst2 || <i> src1, dst1 + src1 = Indirect 0,1,IR0,IR1 (J) + dst1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1 (I) + dst2 = Register 0-7 (L) + Instr: 2/0 - LDF||LDF, LDI||LDI + Alias: i||i, i1||i2, i2||i1 +*/ +#define LL_CLASS(name) \ +name##_LL: &\ + name *+AR0(1), R0 &|| name *+AR1(1), R1 /* I,L|J,K */ &\ + name##2 *+AR0(1), R0 &|| name##1 *+AR1(1), R1 /* I,L|J,K */ &\ + name##1 *+AR1(1), R1 &|| name##2 *+AR0(1), R0 /* J,K|I,L */ + + +/* LS: Store-store parallell operation + Syntax: <i> src2, dst2 || <i> src1, dst1 + src1 = Register 0-7 (H) + dst1 = Indirect 0,1,IR0,IR1 (J) + src2 = Register 0-7 (L) + dst2 = Indirect 0,1,IR0,IR1 (I) + Instr: 2/0 - STF||STF, STI||STI + Alias: i||i, i1||i2, i2||i1. +*/ +#define LS_CLASS(name) \ +name##_LS: &\ + name R0, *+AR0(1) &|| name R1, *+AR1(1) /* L,I|H,J */ &\ + name##2 R0, *+AR0(1) &|| name##1 R1, *+AR1(1) /* L,I|H,J */ &\ + name##1 R1, *+AR1(1) &|| name##2 R0, *+AR0(1) /* H,J|L,I */ + + +/* M: General multiply and add/sub operations + Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual + <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual + <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01] + <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual + <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual + <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03] + src1 = Register 0-7 (K) + src2 = Register 0-7 (H) + src3 = Indirect 0,1,IR0,IR1 (J) + src4 = Indirect 0,1,IR0,IR1 (I) + dst1 = Register 0-1 (N) + dst2 = Register 2-3 (M) + Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3 + Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3 +*/ +#define M_CLASS(namea, nameb) \ +namea##_##nameb##_M: &\ + namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\ + namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\ + namea *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\ + namea R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\ + namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\ +namea##3_##nameb##_M: &\ + namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\ + namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\ + namea##3 *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea##3 *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\ + namea##3 R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea##3 R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\ +namea##_##nameb##3_M: &\ + namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\ + namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\ + namea *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\ + namea R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\ + namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\ +namea##3_##nameb##3_M: &\ + namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\ + namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\ + namea##3 *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea##3 *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\ + namea##3 R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea##3 R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\ + namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\ + namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\ +nameb##_##namea##_M: &\ + nameb R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\ + nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\ + nameb R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\ + nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\ + nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\ + nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ + nameb *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ +nameb##3_##namea##3_M: &\ + nameb##3 R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb##3 R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\ + nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\ + nameb##3 R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\ + nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\ + nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\ + nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ + nameb##3 *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ +nameb##_##namea##3_M: &\ + nameb R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\ + nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\ + nameb R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\ + nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\ + nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\ + nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ + nameb *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ +nameb##3_##namea##_M: &\ + nameb##3 R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb##3 R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\ + nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\ + nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\ + nameb##3 R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\ + nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\ + nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\ + nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\ + nameb##3 *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ + nameb##3 *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\ + + +/* P: General 2-operand operation with parallell store + Syntax: <ia> src2, dst1 || <ib> src3, dst2 + src2 = Indirect 0,1,IR0,IR1 (I) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF, + LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF, + TOIEEE||STF + Alias: a||b, b||a +*/ +#define P_CLASS(namea, nameb) \ +namea##_##nameb##_P: &\ + namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,L|H,J */ &\ + nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,L */ + + +/* Q: General 3-operand operation with parallell store + Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2 + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1 (I) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define Q_CLASS(namea, nameb) \ +namea##_##nameb##_Q: &\ + namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\ + nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\ +namea##3_##nameb##_Q: &\ + namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\ + nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */ + + +/* QC: General commutative 3-operand operation with parallell store + Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2 + <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1 (I) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI, + OR3||STI, XOR3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define QC_CLASS(namea, nameb) \ +namea##_##nameb##_QC: &\ + namea *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\ + namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\ + namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\ + nameb R1, *+AR1(1) &|| namea *+AR0(1), R1, R0 /* H,J|I,K;L */ &\ + nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,K;L */ &\ + nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\ +namea##3_##nameb##_QC: &\ + namea##3 *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\ + namea##3 *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\ + namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\ + nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R1, R0 /* H,J|I,K;L */ &\ + nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R0 /* H,J|I,K;L */ &\ + nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */ + + +/* R: General register integer operation + Syntax: <i> dst + dst = Register (R) + Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC +*/ +#define R_CLASS(name) \ +name##_R: &\ + name AR0 /* R */ + + +/* RF: General register float operation + Syntax: <i> dst + dst = Register 0-11 (R) + Instr: 2/0 - POPF, PUSHF +*/ +#define RF_CLASS(name) \ +name##_RF: &\ + name F0 /* R */ + + +/* S: General 3-operand float operation + Syntax: <i> src2, src1, dst + src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (R) + Instr: 1/0 - SUBF3 + Alias: i, i3 +*/ +#define S_CLASS(name) \ +name##_S: &\ + name R2, R1, R0 /* E,G;R */ &\ + name R1, R0 /* E,G;R */ &\ + name R1, *+AR0(1), R0 /* E,J,R */ &\ + name *+AR0(1), R1, R0 /* I,G;R */ &\ + name *+AR0(1), R0 /* I,G;R */ &\ + name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name *+AR0(5), R1, R0 /* C,G;R */ &\ + name *+AR0(5), R0 /* C,G;R */ &\ + name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\ + .endif &\ +name##3_S: &\ + name##3 R2, R1, R0 /* E,G;R */ &\ + name##3 R1, R0 /* E,G;R */ &\ + name##3 R1, *+AR0(1), R0 /* E,J,R */ &\ + name##3 *+AR0(1), R1, R0 /* I,G;R */ &\ + name##3 *+AR0(1), R0 /* I,G;R */ &\ + name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name##3 *+AR0(5), R1, R0 /* C,G;R */ &\ + name##3 *+AR0(5), R0 /* C,G;R */ &\ + name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\ + .endif + + +/* SC: General commutative 3-operand float operation + Syntax: <i> src2, src1, dst - Manual + <i> src1, src2, dst + src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (R) + Instr: 2/0 - ADDF3, MPYF3 + Alias: i, i3 +*/ +#define SC_CLASS(name) \ +name##_SC: &\ + name R2, R1, R0 /* E,G;R */ &\ + name R1, R0 /* E,G;R */ &\ + name R1, *+AR0(1), R0 /* E,J,R */ &\ + name *+AR0(1), R1, R0 /* I,G;R */ &\ + name *+AR0(1), R0 /* I,G;R */ &\ + name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name *+AR0(5), R1, R0 /* C,G;R */ &\ + name *+AR0(5), R0 /* C,G;R */ &\ + name R1, *+AR0(5), R0 /* G,C,R */ &\ + name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\ + .endif &\ +name##3_SC: &\ + name##3 R2, R1, R0 /* E,G;R */ &\ + name##3 R1, R0 /* E,G;R */ &\ + name##3 R1, *+AR0(1), R0 /* E,J,R */ &\ + name##3 *+AR0(1), R1, R0 /* I,G;R */ &\ + name##3 *+AR0(1), R0 /* I,G;R */ &\ + name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name##3 *+AR0(5), R1, R0 /* C,G;R */ &\ + name##3 *+AR0(5), R0 /* C,G;R */ &\ + name##3 R1, *+AR0(5), R0 /* G,C,R */ &\ + name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\ + .endif + + +/* S2: General 3-operand float operation with 2 args + Syntax: <i> src2, src1 + src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPF3 + Alias: i, i3 +*/ +#define S2_CLASS(name) \ +name##_S2: &\ + name R2, R1 /* E,G */ &\ + name R1, *+AR0(1) /* E,J */ &\ + name *+AR0(1), R1 /* I,G */ &\ + name *+AR0(1), *+AR1(1) /* I,J */ &\ + .ifdef TEST_C4X &\ + name *+AR0(5), R1 /* C,G */ &\ + name *+AR0(5), *+AR1(5) /* C,O */ &\ + .endif &\ +name##3_S2: &\ + name##3 R2, R1 /* E,G */ &\ + name##3 R1, *+AR0(1) /* E,J */ &\ + name##3 *+AR0(1), R1 /* I,G */ &\ + name##3 *+AR0(1), *+AR1(1) /* I,J */ &\ + .ifdef TEST_C4X &\ + name##3 *+AR0(5), R1 /* C,G */ &\ + name##3 *+AR0(5), *+AR1(5) /* C,O */ &\ + .endif + + +/* T: General 3-operand integer operand + Syntax: <i> src2, src1, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3 + Alias: i, i3 +*/ +#define T_CLASS(name) \ +name##_T: &\ + name AR2, AR1, AR0 /* E,G;R */ &\ + name AR1, AR0 /* E,G;R */ &\ + name AR1, *+AR0(1), AR0 /* E,J,R */ &\ + name *+AR0(1), AR1, AR0 /* I,G;R */ &\ + name *+AR0(1), AR0 /* I,G;R */ &\ + name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name 5, AR1, AR0 /* W,G;R */ &\ + name 5, AR0 /* W,G;R */ &\ + name *+AR0(5), AR1, AR0 /* C,G;R */ &\ + name *+AR0(5), AR0 /* C,G;R */ &\ + name 5, *+AR0(5), AR0 /* W,O,R */ &\ + name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\ + .endif &\ +name##3_T: &\ + name##3 AR2, AR1, AR0 /* E,G;R */ &\ + name##3 AR1, AR0 /* E,G;R */ &\ + name##3 AR1, *+AR0(1), AR0 /* E,J,R */ &\ + name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\ + name##3 *+AR0(1), AR0 /* I,G;R */ &\ + name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name##3 -5, AR1, AR0 /* W,G;R */ &\ + name##3 -5, AR0 /* W,G;R */ &\ + name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\ + name##3 *+AR0(5), AR0 /* C,G;R */ &\ + name##3 -5, *+AR0(5), AR0 /* W,O,R */ &\ + name##3 *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\ + .endif + + +/* TC: General commutative 3-operand integer operation + Syntax: <i> src2, src1, dst + <i> src1, src2, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI + Alias: i, i3 +*/ +#define TC_CLASS(name) \ +name##_TC: &\ + name AR2, AR1, AR0 /* E,G;R */ &\ + name AR1, AR0 /* E,G;R */ &\ + name AR1, *+AR0(1), AR0 /* E,J,R */ &\ + name *+AR0(1), AR1, AR0 /* I,G;R */ &\ + name *+AR0(1), AR0 /* I,G;R */ &\ + name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name 5, AR1, AR0 /* W,G;R */ &\ + name 5, AR0 /* W,G;R */ &\ + name AR1, -5, AR0 /* G,W,R */ &\ + name *+AR0(5), AR1, AR0 /* C,G;R */ &\ + name *+AR0(5), AR0 /* C,G;R */ &\ + name AR1, *+AR0(5), AR0 /* G,C,R */ &\ + name 5, *+AR0(5), AR0 /* W,O,R */ &\ + name *+AR0(5), -5, AR0 /* O,W,R */ &\ + name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\ + .endif &\ +name##3_TC: &\ + name##3 AR2, AR1, AR0 /* E,G;R */ &\ + name##3 AR1, AR0 /* E,G;R */ &\ + name##3 AR1, *+AR0(1), AR0 /* E,J,R */ &\ + name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\ + name##3 *+AR0(1), AR0 /* I,G;R */ &\ + name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\ + .ifdef TEST_C4X &\ + name##3 -5, AR1, AR0 /* W,G;R */ &\ + name##3 -5, AR0 /* W,G;R */ &\ + name##3 AR1, -5, AR0 /* G,W,R */ &\ + name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\ + name##3 *+AR0(5), AR0 /* C,G;R */ &\ + name##3 AR1, *+AR0(5), AR0 /* G,C,R */ &\ + name##3 -5, *+AR0(5), AR0 /* W,O,R */ &\ + name##3 *+AR0(5), -5, AR0 /* O,W,R */ &\ + name##3 *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\ + .endif + + +/* T2: General 3-operand integer operation with 2 args + Syntax: <i> src2, src1 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPI3 + Alias: i, i3 +*/ +#define T2_CLASS(name) \ +name##_T2: &\ + name AR2, AR1 /* E,G */ &\ + name AR1, *+AR0(1) /* E,J */ &\ + name *+AR0(1), AR1 /* I,G */ &\ + name *+AR1(1), *+AR0(1) /* I,J */ &\ + .ifdef TEST_C4X &\ + name -5, AR1 /* W,G */ &\ + name *+AR0(5), AR1 /* C,G */ &\ + name -5, *+AR0(5) /* W,O */ &\ + name *+AR0(5), *+AR1(5) /* C,O */ &\ + .endif &\ +name##3_T2: &\ + name##3 AR2, AR1 /* E,G */ &\ + name##3 AR1, *+AR0(1) /* E,J */ &\ + name##3 *+AR0(1), AR1 /* I,G */ &\ + name##3 *+AR1(1), *+AR0(1) /* I,J */ &\ + .ifdef TEST_C4X &\ + name##3 -5, AR1 /* W,G */ &\ + name##3 *+AR0(5), AR1 /* C,G */ &\ + name##3 -5, *+AR0(5) /* W,O */ &\ + name##3 *+AR0(5), *+AR1(5) /* C,O */ &\ + .endif + + +/* T2C: General commutative 3-operand integer operation with 2 args + Syntax: <i> src2, src1 - Manual + <i> src1, src2 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0) + Instr: 1/0 - TSTB3 + Alias: i, i3 +*/ +#define T2C_CLASS(name) \ +name##_T2C: &\ + name AR2, AR1 /* E,G */ &\ + name AR1, *+AR0(1) /* E,J */ &\ + name *+AR0(1), AR1 /* I,G */ &\ + name *+AR1(1), *+AR0(1) /* I,J */ &\ + .ifdef TEST_C4X &\ + name 5, AR1 /* W,G */ &\ + name AR1, -5 /* G,W */ &\ + name *+AR0(5), AR1 /* C,G */ &\ + name AR1, *+AR0(5) /* G,C */ &\ + name 5, *+AR0(5) /* W,O */ &\ + name *+AR0(5), -5 /* O,W */ &\ + name *+AR0(5), *+AR1(5) /* C,O */ &\ + .endif &\ +name##3_T2C: &\ + name##3 AR2, AR1 /* E,G */ &\ + name##3 AR1, *+AR0(1) /* E,J */ &\ + name##3 *+AR0(1), AR1 /* I,G */ &\ + name##3 *+AR1(1), *+AR0(1) /* I,J */ &\ + .ifdef TEST_C4X &\ + name##3 -5, AR1 /* W,G */ &\ + name##3 AR1, -5 /* G,W */ &\ + name##3 *+AR0(5), AR1 /* C,G */ &\ + name##3 AR1, *+AR0(5) /* G,C */ &\ + name##3 -5, *+AR0(5) /* W,O */ &\ + name##3 *+AR0(5), -5 /* O,W */ &\ + name##3 *+AR0(5), *+AR1(5) /* C,O */ &\ + .endif diff --git a/gas/testsuite/gas/tic4x/opcodes.s b/gas/testsuite/gas/tic4x/opcodes.s new file mode 100644 index 0000000..bf2c9b6 --- /dev/null +++ b/gas/testsuite/gas/tic4x/opcodes.s @@ -0,0 +1,595 @@ +; File is autogenerated from allopcodes.S - do not edit +; Please use ./rebuild.sh to rebuild this file + +;;; +;;; Test all opcodes and argument permuation +;;; To make our job a lot simpler, we define a couple of +;;; insn classes, that we use to generate the proper +;;; test output. +;;; +;;; To rebuild this file you must use +;;; ./rebuild.sh +;;; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .text +start: absf_B: & absf R1, R0 & absf R0 & absf @start, R0 & absf *+AR0(5), R0 & absf 3.5, R0 + absf_stf_P: & absf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0 + absi_A: & absi AR1, AR0 & absi AR0 & absi @start, AR0 & absi *+AR0(5), AR0 & absi -5, AR0 + absi_sti_P: & absi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0 + addc_A: & addc AR1, AR0 & addc AR0 & addc @start, AR0 & addc *+AR0(5), AR0 & addc -5, AR0 + addc_TC: & addc AR2, AR1, AR0 & addc AR1, AR0 & addc AR1, *+AR0(1), AR0 & addc *+AR0(1), AR1, AR0 & addc *+AR0(1), AR0 & addc *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addc 5, AR1, AR0 & addc 5, AR0 & addc AR1, -5, AR0 & addc *+AR0(5), AR1, AR0 & addc *+AR0(5), AR0 & addc AR1, *+AR0(5), AR0 & addc 5, *+AR0(5), AR0 & addc *+AR0(5), -5, AR0 & addc *+AR0(5), *+AR1(5), AR0 & .endif & addc3_TC: & addc3 AR2, AR1, AR0 & addc3 AR1, AR0 & addc3 AR1, *+AR0(1), AR0 & addc3 *+AR0(1), AR1, AR0 & addc3 *+AR0(1), AR0 & addc3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addc3 -5, AR1, AR0 & addc3 -5, AR0 & addc3 AR1, -5, AR0 & addc3 *+AR0(5), AR1, AR0 & addc3 *+AR0(5), AR0 & addc3 AR1, *+AR0(5), AR0 & addc3 -5, *+AR0(5), AR0 & addc3 *+AR0(5), -5, AR0 & addc3 *+AR0(5), *+AR1(5), AR0 & .endif + addf_B: & addf R1, R0 & addf R0 & addf @start, R0 & addf *+AR0(5), R0 & addf 3.5, R0 + addf_SC: & addf R2, R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 & addf *+AR0(1), R1, R0 & addf *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & addf *+AR0(5), R1, R0 & addf *+AR0(5), R0 & addf R1, *+AR0(5), R0 & addf *+AR0(5), *+AR1(5), R0 & .endif & addf3_SC: & addf3 R2, R1, R0 & addf3 R1, R0 & addf3 R1, *+AR0(1), R0 & addf3 *+AR0(1), R1, R0 & addf3 *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & addf3 *+AR0(5), R1, R0 & addf3 *+AR0(5), R0 & addf3 R1, *+AR0(5), R0 & addf3 *+AR0(5), *+AR1(5), R0 & .endif + addf_stf_QC: & addf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf R0, *+AR0(1), R0 & addf3_stf_QC: & addf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf3 R0, *+AR0(1), R0 + addi_A: & addi AR1, AR0 & addi AR0 & addi @start, AR0 & addi *+AR0(5), AR0 & addi -5, AR0 + addi_TC: & addi AR2, AR1, AR0 & addi AR1, AR0 & addi AR1, *+AR0(1), AR0 & addi *+AR0(1), AR1, AR0 & addi *+AR0(1), AR0 & addi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addi 5, AR1, AR0 & addi 5, AR0 & addi AR1, -5, AR0 & addi *+AR0(5), AR1, AR0 & addi *+AR0(5), AR0 & addi AR1, *+AR0(5), AR0 & addi 5, *+AR0(5), AR0 & addi *+AR0(5), -5, AR0 & addi *+AR0(5), *+AR1(5), AR0 & .endif & addi3_TC: & addi3 AR2, AR1, AR0 & addi3 AR1, AR0 & addi3 AR1, *+AR0(1), AR0 & addi3 *+AR0(1), AR1, AR0 & addi3 *+AR0(1), AR0 & addi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addi3 -5, AR1, AR0 & addi3 -5, AR0 & addi3 AR1, -5, AR0 & addi3 *+AR0(5), AR1, AR0 & addi3 *+AR0(5), AR0 & addi3 AR1, *+AR0(5), AR0 & addi3 -5, *+AR0(5), AR0 & addi3 *+AR0(5), -5, AR0 & addi3 *+AR0(5), *+AR1(5), AR0 & .endif + addi_sti_QC: & addi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi R0, *+AR0(1), R0 & addi3_sti_QC: & addi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi3 R0, *+AR0(1), R0 + and_AU: & and AR1, AR0 & and AR0 & and @start, AR0 & and *+AR0(5), AR0 & and 5, AR0 + and_TC: & and AR2, AR1, AR0 & and AR1, AR0 & and AR1, *+AR0(1), AR0 & and *+AR0(1), AR1, AR0 & and *+AR0(1), AR0 & and *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & and 5, AR1, AR0 & and 5, AR0 & and AR1, -5, AR0 & and *+AR0(5), AR1, AR0 & and *+AR0(5), AR0 & and AR1, *+AR0(5), AR0 & and 5, *+AR0(5), AR0 & and *+AR0(5), -5, AR0 & and *+AR0(5), *+AR1(5), AR0 & .endif & and3_TC: & and3 AR2, AR1, AR0 & and3 AR1, AR0 & and3 AR1, *+AR0(1), AR0 & and3 *+AR0(1), AR1, AR0 & and3 *+AR0(1), AR0 & and3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & and3 -5, AR1, AR0 & and3 -5, AR0 & and3 AR1, -5, AR0 & and3 *+AR0(5), AR1, AR0 & and3 *+AR0(5), AR0 & and3 AR1, *+AR0(5), AR0 & and3 -5, *+AR0(5), AR0 & and3 *+AR0(5), -5, AR0 & and3 *+AR0(5), *+AR1(5), AR0 & .endif + and_sti_QC: & and *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1(1) & and R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and *+AR0(1), R0 & sti R1, *+AR1(1) &|| and R0, *+AR0(1), R0 & and3_sti_QC: & and3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & and3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| and3 R0, *+AR0(1), R0 + andn_AU: & andn AR1, AR0 & andn AR0 & andn @start, AR0 & andn *+AR0(5), AR0 & andn 5, AR0 + andn_T: & andn AR2, AR1, AR0 & andn AR1, AR0 & andn AR1, *+AR0(1), AR0 & andn *+AR0(1), AR1, AR0 & andn *+AR0(1), AR0 & andn *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & andn 5, AR1, AR0 & andn 5, AR0 & andn *+AR0(5), AR1, AR0 & andn *+AR0(5), AR0 & andn 5, *+AR0(5), AR0 & andn *+AR0(5), *+AR1(5), AR0 & .endif & andn3_T: & andn3 AR2, AR1, AR0 & andn3 AR1, AR0 & andn3 AR1, *+AR0(1), AR0 & andn3 *+AR0(1), AR1, AR0 & andn3 *+AR0(1), AR0 & andn3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & andn3 -5, AR1, AR0 & andn3 -5, AR0 & andn3 *+AR0(5), AR1, AR0 & andn3 *+AR0(5), AR0 & andn3 -5, *+AR0(5), AR0 & andn3 *+AR0(5), *+AR1(5), AR0 & .endif + ash_A: & ash AR1, AR0 & ash AR0 & ash @start, AR0 & ash *+AR0(5), AR0 & ash -5, AR0 + ash_T: & ash AR2, AR1, AR0 & ash AR1, AR0 & ash AR1, *+AR0(1), AR0 & ash *+AR0(1), AR1, AR0 & ash *+AR0(1), AR0 & ash *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & ash 5, AR1, AR0 & ash 5, AR0 & ash *+AR0(5), AR1, AR0 & ash *+AR0(5), AR0 & ash 5, *+AR0(5), AR0 & ash *+AR0(5), *+AR1(5), AR0 & .endif & ash3_T: & ash3 AR2, AR1, AR0 & ash3 AR1, AR0 & ash3 AR1, *+AR0(1), AR0 & ash3 *+AR0(1), AR1, AR0 & ash3 *+AR0(1), AR0 & ash3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & ash3 -5, AR1, AR0 & ash3 -5, AR0 & ash3 *+AR0(5), AR1, AR0 & ash3 *+AR0(5), AR0 & ash3 -5, *+AR0(5), AR0 & ash3 *+AR0(5), *+AR1(5), AR0 & .endif + ash_sti_Q: & ash R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & ash3_sti_Q: & ash3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, *+AR0(1), R0 + bC_J: & bC R0 & bC start & b_J: & b R0 & b start + bCd_J: & bCd R0 & bCd start & bd_J: & bd R0 & bd start +br_I: br start +brd_I: brd start +call_I: call start +call_JS: callc R0 + callc start + cmpf_B: & cmpf R1, R0 & cmpf R0 & cmpf @start, R0 & cmpf *+AR0(5), R0 & cmpf 3.5, R0 + cmpf_S2: & cmpf R2, R1 & cmpf R1, *+AR0(1) & cmpf *+AR0(1), R1 & cmpf *+AR0(1), *+AR1(1) & .ifdef TEST_C4X & cmpf *+AR0(5), R1 & cmpf *+AR0(5), *+AR1(5) & .endif & cmpf3_S2: & cmpf3 R2, R1 & cmpf3 R1, *+AR0(1) & cmpf3 *+AR0(1), R1 & cmpf3 *+AR0(1), *+AR1(1) & .ifdef TEST_C4X & cmpf3 *+AR0(5), R1 & cmpf3 *+AR0(5), *+AR1(5) & .endif + cmpi_A: & cmpi AR1, AR0 & cmpi AR0 & cmpi @start, AR0 & cmpi *+AR0(5), AR0 & cmpi -5, AR0 + cmpi_T2: & cmpi AR2, AR1 & cmpi AR1, *+AR0(1) & cmpi *+AR0(1), AR1 & cmpi *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & cmpi -5, AR1 & cmpi *+AR0(5), AR1 & cmpi -5, *+AR0(5) & cmpi *+AR0(5), *+AR1(5) & .endif & cmpi3_T2: & cmpi3 AR2, AR1 & cmpi3 AR1, *+AR0(1) & cmpi3 *+AR0(1), AR1 & cmpi3 *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & cmpi3 -5, AR1 & cmpi3 *+AR0(5), AR1 & cmpi3 -5, *+AR0(5) & cmpi3 *+AR0(5), *+AR1(5) & .endif + dbC_D: & dbC AR0, R0 & dbC AR0, start & db_D: & db AR0, R0 & db AR0, start + dbCd_D: & dbCd AR0, R0 & dbCd AR0, start & dbd_D: & dbd AR0, R0 & dbd AR0, start + fix_AF: & fix R1, R0 & fix R0 & fix @start, AR0 & fix *+AR0(5), AR0 & fix 3.5, AR0 + fix_sti_P: & fix *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix *+AR0(1), R0 + float_BI: & float AR1, R0 & float R0 & float @start, R0 & float *+AR0(5), R0 & float -5, R0 + float_stf_P: & float *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float *+AR0(1), R0 +iack_Z: iack @start + iack *+AR0(1) +idle_Z: idle + .ifdef TEST_IDLE2 +idle2_Z: idle2 + .endif + lde_B: & lde R1, R0 & lde R0 & lde @start, R0 & lde *+AR0(5), R0 & lde 3.5, R0 + ldf_B: & ldf R1, R0 & ldf R0 & ldf @start, R0 & ldf *+AR0(5), R0 & ldf 3.5, R0 + ldf_LL: & ldf *+AR0(1), R0 &|| ldf *+AR1(1), R1 & ldf2 *+AR0(1), R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 *+AR0(1), R0 + ldf_stf_P: & ldf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf *+AR0(1), R0 + ldfC_BB: & ldfC R1, R0 & ldfC R0 & ldfC @start, R0 & ldfC *+AR0(5), R0 & ldfC 3.5, R0 + ldfi_B6: & ldfi @start, R0 & ldfi *+AR0(5), R0 + ldi_A: & ldi AR1, AR0 & ldi AR0 & ldi @start, AR0 & ldi *+AR0(5), AR0 & ldi -5, AR0 + ldi_LL: & ldi *+AR0(1), R0 &|| ldi *+AR1(1), R1 & ldi2 *+AR0(1), R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 *+AR0(1), R0 + ldi_sti_P: & ldi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi *+AR0(1), R0 + ldiC_AB: & ldiC AR1, AR0 & ldiC AR0 & ldiC @start, AR0 & ldiC *+AR0(5), AR0 & ldiC -5, AR0 + ldii_A6: & ldii @start, AR0 & ldii *+AR0(5), AR0 +ldp_Z: ldp start + ldm_B: & ldm R1, R0 & ldm R0 & ldm @start, R0 & ldm *+AR0(5), R0 & ldm 3.5, R0 + .ifdef TEST_LPWR +lopower_Z: lopower + .endif + lsh_A: & lsh AR1, AR0 & lsh AR0 & lsh @start, AR0 & lsh *+AR0(5), AR0 & lsh -5, AR0 + lsh_T: & lsh AR2, AR1, AR0 & lsh AR1, AR0 & lsh AR1, *+AR0(1), AR0 & lsh *+AR0(1), AR1, AR0 & lsh *+AR0(1), AR0 & lsh *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & lsh 5, AR1, AR0 & lsh 5, AR0 & lsh *+AR0(5), AR1, AR0 & lsh *+AR0(5), AR0 & lsh 5, *+AR0(5), AR0 & lsh *+AR0(5), *+AR1(5), AR0 & .endif & lsh3_T: & lsh3 AR2, AR1, AR0 & lsh3 AR1, AR0 & lsh3 AR1, *+AR0(1), AR0 & lsh3 *+AR0(1), AR1, AR0 & lsh3 *+AR0(1), AR0 & lsh3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & lsh3 -5, AR1, AR0 & lsh3 -5, AR0 & lsh3 *+AR0(5), AR1, AR0 & lsh3 *+AR0(5), AR0 & lsh3 -5, *+AR0(5), AR0 & lsh3 *+AR0(5), *+AR1(5), AR0 & .endif + lsh_sti_Q: & lsh R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, *+AR0(1), R0 & lsh3_sti_Q: & lsh3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, *+AR0(1), R0 + .ifdef TEST_LPWR +maxspeed_Z: maxspeed + .endif + mpyf_B: & mpyf R1, R0 & mpyf R0 & mpyf @start, R0 & mpyf *+AR0(5), R0 & mpyf 3.5, R0 + mpyf_SC: & mpyf R2, R1, R0 & mpyf R1, R0 & mpyf R1, *+AR0(1), R0 & mpyf *+AR0(1), R1, R0 & mpyf *+AR0(1), R0 & mpyf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & mpyf *+AR0(5), R1, R0 & mpyf *+AR0(5), R0 & mpyf R1, *+AR0(5), R0 & mpyf *+AR0(5), *+AR1(5), R0 & .endif & mpyf3_SC: & mpyf3 R2, R1, R0 & mpyf3 R1, R0 & mpyf3 R1, *+AR0(1), R0 & mpyf3 *+AR0(1), R1, R0 & mpyf3 *+AR0(1), R0 & mpyf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & mpyf3 *+AR0(5), R1, R0 & mpyf3 *+AR0(5), R0 & mpyf3 R1, *+AR0(5), R0 & mpyf3 *+AR0(5), *+AR1(5), R0 & .endif + mpyf_addf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3_addf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf_addf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3_addf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & addf_mpyf_M: & addf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3_mpyf3_M: & addf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf_mpyf3_M: & addf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3_mpyf_M: & addf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & + mpyf_stf_QC: & mpyf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf R0, *+AR0(1), R0 & mpyf3_stf_QC: & mpyf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf3 R0, *+AR0(1), R0 + mpyf_subf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3_subf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf_subf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3_subf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & subf_mpyf_M: & subf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3_mpyf3_M: & subf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf_mpyf3_M: & subf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3_mpyf_M: & subf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & + mpyi_A: & mpyi AR1, AR0 & mpyi AR0 & mpyi @start, AR0 & mpyi *+AR0(5), AR0 & mpyi -5, AR0 + mpyi_TC: & mpyi AR2, AR1, AR0 & mpyi AR1, AR0 & mpyi AR1, *+AR0(1), AR0 & mpyi *+AR0(1), AR1, AR0 & mpyi *+AR0(1), AR0 & mpyi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyi 5, AR1, AR0 & mpyi 5, AR0 & mpyi AR1, -5, AR0 & mpyi *+AR0(5), AR1, AR0 & mpyi *+AR0(5), AR0 & mpyi AR1, *+AR0(5), AR0 & mpyi 5, *+AR0(5), AR0 & mpyi *+AR0(5), -5, AR0 & mpyi *+AR0(5), *+AR1(5), AR0 & .endif & mpyi3_TC: & mpyi3 AR2, AR1, AR0 & mpyi3 AR1, AR0 & mpyi3 AR1, *+AR0(1), AR0 & mpyi3 *+AR0(1), AR1, AR0 & mpyi3 *+AR0(1), AR0 & mpyi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyi3 -5, AR1, AR0 & mpyi3 -5, AR0 & mpyi3 AR1, -5, AR0 & mpyi3 *+AR0(5), AR1, AR0 & mpyi3 *+AR0(5), AR0 & mpyi3 AR1, *+AR0(5), AR0 & mpyi3 -5, *+AR0(5), AR0 & mpyi3 *+AR0(5), -5, AR0 & mpyi3 *+AR0(5), *+AR1(5), AR0 & .endif + mpyi_addi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3_addi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi_addi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3_addi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & addi_mpyi_M: & addi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3_mpyi3_M: & addi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi_mpyi3_M: & addi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3_mpyi_M: & addi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & + mpyi_sti_QC: & mpyi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi R0, *+AR0(1), R0 & mpyi3_sti_QC: & mpyi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi3 R0, *+AR0(1), R0 + mpyi_subi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3_subi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi_subi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3_subi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & subi_mpyi_M: & subi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3_mpyi3_M: & subi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi_mpyi3_M: & subi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3_mpyi_M: & subi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & + negb_A: & negb AR1, AR0 & negb AR0 & negb @start, AR0 & negb *+AR0(5), AR0 & negb -5, AR0 + negf_B: & negf R1, R0 & negf R0 & negf @start, R0 & negf *+AR0(5), R0 & negf 3.5, R0 + negf_stf_P: & negf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf *+AR0(1), R0 + negi_A: & negi AR1, AR0 & negi AR0 & negi @start, AR0 & negi *+AR0(5), AR0 & negi -5, AR0 + negi_sti_P: & negi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi *+AR0(1), R0 + nop_A2: & nop AR0 & nop *+AR0(5) & nop + norm_B: & norm R1, R0 & norm R0 & norm @start, R0 & norm *+AR0(5), R0 & norm 3.5, R0 + not_AU: & not AR1, AR0 & not AR0 & not @start, AR0 & not *+AR0(5), AR0 & not 5, AR0 + not_sti_P: & not *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not *+AR0(1), R0 + or_AU: & or AR1, AR0 & or AR0 & or @start, AR0 & or *+AR0(5), AR0 & or 5, AR0 + or_TC: & or AR2, AR1, AR0 & or AR1, AR0 & or AR1, *+AR0(1), AR0 & or *+AR0(1), AR1, AR0 & or *+AR0(1), AR0 & or *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & or 5, AR1, AR0 & or 5, AR0 & or AR1, -5, AR0 & or *+AR0(5), AR1, AR0 & or *+AR0(5), AR0 & or AR1, *+AR0(5), AR0 & or 5, *+AR0(5), AR0 & or *+AR0(5), -5, AR0 & or *+AR0(5), *+AR1(5), AR0 & .endif & or3_TC: & or3 AR2, AR1, AR0 & or3 AR1, AR0 & or3 AR1, *+AR0(1), AR0 & or3 *+AR0(1), AR1, AR0 & or3 *+AR0(1), AR0 & or3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & or3 -5, AR1, AR0 & or3 -5, AR0 & or3 AR1, -5, AR0 & or3 *+AR0(5), AR1, AR0 & or3 *+AR0(5), AR0 & or3 AR1, *+AR0(5), AR0 & or3 -5, *+AR0(5), AR0 & or3 *+AR0(5), -5, AR0 & or3 *+AR0(5), *+AR1(5), AR0 & .endif + or_sti_QC: & or *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or *+AR0(1), R0 &|| sti R1, *+AR1(1) & or R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or *+AR0(1), R0 & sti R1, *+AR1(1) &|| or R0, *+AR0(1), R0 & or3_sti_QC: & or3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & or3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| or3 R0, *+AR0(1), R0 + pop_R: & pop AR0 + popf_RF: & popf F0 + push_R: & push AR0 + pushf_RF: & pushf F0 +reti_Z: retiC + reti +rets_Z: retsC + rets + rnd_B: & rnd R1, R0 & rnd R0 & rnd @start, R0 & rnd *+AR0(5), R0 & rnd 3.5, R0 + rol_R: & rol AR0 + rolc_R: & rolc AR0 + ror_R: & ror AR0 + rorc_R: & rorc AR0 +rptb_I2: rptb start + rpts_A3: & rpts AR1 & rpts @start & rpts *+AR0(5) & rpts 5 +sigi_Z: sigi + stf_B7: & stf R0, @start & stf R0, *+AR0(5) + stf_LS: & stf R0, *+AR0(1) &|| stf R1, *+AR1(1) & stf2 R0, *+AR0(1) &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, *+AR0(1) + stfi_B7: & stfi R0, @start & stfi R0, *+AR0(5) + sti_A7: & sti AR0, @start & sti AR0, *+AR0(5) + sti_LS: & sti R0, *+AR0(1) &|| sti R1, *+AR1(1) & sti2 R0, *+AR0(1) &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, *+AR0(1) + stii_A7: & stii AR0, @start & stii AR0, *+AR0(5) + subb_A: & subb AR1, AR0 & subb AR0 & subb @start, AR0 & subb *+AR0(5), AR0 & subb -5, AR0 + subb_T: & subb AR2, AR1, AR0 & subb AR1, AR0 & subb AR1, *+AR0(1), AR0 & subb *+AR0(1), AR1, AR0 & subb *+AR0(1), AR0 & subb *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subb 5, AR1, AR0 & subb 5, AR0 & subb *+AR0(5), AR1, AR0 & subb *+AR0(5), AR0 & subb 5, *+AR0(5), AR0 & subb *+AR0(5), *+AR1(5), AR0 & .endif & subb3_T: & subb3 AR2, AR1, AR0 & subb3 AR1, AR0 & subb3 AR1, *+AR0(1), AR0 & subb3 *+AR0(1), AR1, AR0 & subb3 *+AR0(1), AR0 & subb3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subb3 -5, AR1, AR0 & subb3 -5, AR0 & subb3 *+AR0(5), AR1, AR0 & subb3 *+AR0(5), AR0 & subb3 -5, *+AR0(5), AR0 & subb3 *+AR0(5), *+AR1(5), AR0 & .endif + subc_A: & subc AR1, AR0 & subc AR0 & subc @start, AR0 & subc *+AR0(5), AR0 & subc -5, AR0 + subf_B: & subf R1, R0 & subf R0 & subf @start, R0 & subf *+AR0(5), R0 & subf 3.5, R0 + subf_S: & subf R2, R1, R0 & subf R1, R0 & subf R1, *+AR0(1), R0 & subf *+AR0(1), R1, R0 & subf *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & subf *+AR0(5), R1, R0 & subf *+AR0(5), R0 & subf *+AR0(5), *+AR1(5), R0 & .endif & subf3_S: & subf3 R2, R1, R0 & subf3 R1, R0 & subf3 R1, *+AR0(1), R0 & subf3 *+AR0(1), R1, R0 & subf3 *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & subf3 *+AR0(5), R1, R0 & subf3 *+AR0(5), R0 & subf3 *+AR0(5), *+AR1(5), R0 & .endif + subf_stf_Q: & subf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, *+AR0(1), R0 & subf3_stf_Q: & subf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, *+AR0(1), R0 + subi_A: & subi AR1, AR0 & subi AR0 & subi @start, AR0 & subi *+AR0(5), AR0 & subi -5, AR0 + subi_T: & subi AR2, AR1, AR0 & subi AR1, AR0 & subi AR1, *+AR0(1), AR0 & subi *+AR0(1), AR1, AR0 & subi *+AR0(1), AR0 & subi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subi 5, AR1, AR0 & subi 5, AR0 & subi *+AR0(5), AR1, AR0 & subi *+AR0(5), AR0 & subi 5, *+AR0(5), AR0 & subi *+AR0(5), *+AR1(5), AR0 & .endif & subi3_T: & subi3 AR2, AR1, AR0 & subi3 AR1, AR0 & subi3 AR1, *+AR0(1), AR0 & subi3 *+AR0(1), AR1, AR0 & subi3 *+AR0(1), AR0 & subi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subi3 -5, AR1, AR0 & subi3 -5, AR0 & subi3 *+AR0(5), AR1, AR0 & subi3 *+AR0(5), AR0 & subi3 -5, *+AR0(5), AR0 & subi3 *+AR0(5), *+AR1(5), AR0 & .endif + subi_sti_Q: & subi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, *+AR0(1), R0 & subi3_sti_Q: & subi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, *+AR0(1), R0 + subrb_A: & subrb AR1, AR0 & subrb AR0 & subrb @start, AR0 & subrb *+AR0(5), AR0 & subrb -5, AR0 + subrf_B: & subrf R1, R0 & subrf R0 & subrf @start, R0 & subrf *+AR0(5), R0 & subrf 3.5, R0 + subri_A: & subri AR1, AR0 & subri AR0 & subri @start, AR0 & subri *+AR0(5), AR0 & subri -5, AR0 +swi_Z: swi +trap_Z: trapC 10 + trap 10 + tstb_AU: & tstb AR1, AR0 & tstb AR0 & tstb @start, AR0 & tstb *+AR0(5), AR0 & tstb 5, AR0 + tstb_T2C: & tstb AR2, AR1 & tstb AR1, *+AR0(1) & tstb *+AR0(1), AR1 & tstb *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & tstb 5, AR1 & tstb AR1, -5 & tstb *+AR0(5), AR1 & tstb AR1, *+AR0(5) & tstb 5, *+AR0(5) & tstb *+AR0(5), -5 & tstb *+AR0(5), *+AR1(5) & .endif & tstb3_T2C: & tstb3 AR2, AR1 & tstb3 AR1, *+AR0(1) & tstb3 *+AR0(1), AR1 & tstb3 *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & tstb3 -5, AR1 & tstb3 AR1, -5 & tstb3 *+AR0(5), AR1 & tstb3 AR1, *+AR0(5) & tstb3 -5, *+AR0(5) & tstb3 *+AR0(5), -5 & tstb3 *+AR0(5), *+AR1(5) & .endif + xor_AU: & xor AR1, AR0 & xor AR0 & xor @start, AR0 & xor *+AR0(5), AR0 & xor 5, AR0 + xor_TC: & xor AR2, AR1, AR0 & xor AR1, AR0 & xor AR1, *+AR0(1), AR0 & xor *+AR0(1), AR1, AR0 & xor *+AR0(1), AR0 & xor *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & xor 5, AR1, AR0 & xor 5, AR0 & xor AR1, -5, AR0 & xor *+AR0(5), AR1, AR0 & xor *+AR0(5), AR0 & xor AR1, *+AR0(5), AR0 & xor 5, *+AR0(5), AR0 & xor *+AR0(5), -5, AR0 & xor *+AR0(5), *+AR1(5), AR0 & .endif & xor3_TC: & xor3 AR2, AR1, AR0 & xor3 AR1, AR0 & xor3 AR1, *+AR0(1), AR0 & xor3 *+AR0(1), AR1, AR0 & xor3 *+AR0(1), AR0 & xor3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & xor3 -5, AR1, AR0 & xor3 -5, AR0 & xor3 AR1, -5, AR0 & xor3 *+AR0(5), AR1, AR0 & xor3 *+AR0(5), AR0 & xor3 AR1, *+AR0(5), AR0 & xor3 -5, *+AR0(5), AR0 & xor3 *+AR0(5), -5, AR0 & xor3 *+AR0(5), *+AR1(5), AR0 & .endif + xor_sti_QC: & xor *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor R0, *+AR0(1), R0 & xor3_sti_QC: & xor3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor3 R0, *+AR0(1), R0 + + .ifdef TEST_C4X + bCaf_J: & bCaf R0 & bCaf start & baf_J: & baf R0 & baf start + bCat_J: & bCat R0 & bCat start & bat_J: & bat R0 & bat start + frieee_B6: & frieee @start, R0 & frieee *+AR0(5), R0 + frieee_stf_P: & frieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee *+AR0(1), R0 +laj_I: laj start +laj_JS: lajc R0 + lajc start +lat_Z: latC 10 + lb0_A: & lb0 AR1, AR0 & lb0 AR0 & lb0 @start, AR0 & lb0 *+AR0(5), AR0 & lb0 -5, AR0 + lb1_A: & lb1 AR1, AR0 & lb1 AR0 & lb1 @start, AR0 & lb1 *+AR0(5), AR0 & lb1 -5, AR0 + lb2_A: & lb2 AR1, AR0 & lb2 AR0 & lb2 @start, AR0 & lb2 *+AR0(5), AR0 & lb2 -5, AR0 + lb3_A: & lb3 AR1, AR0 & lb3 AR0 & lb3 @start, AR0 & lb3 *+AR0(5), AR0 & lb3 -5, AR0 + lbu0_AU: & lbu0 AR1, AR0 & lbu0 AR0 & lbu0 @start, AR0 & lbu0 *+AR0(5), AR0 & lbu0 5, AR0 + lbu1_AU: & lbu1 AR1, AR0 & lbu1 AR0 & lbu1 @start, AR0 & lbu1 *+AR0(5), AR0 & lbu1 5, AR0 + lbu2_AU: & lbu2 AR1, AR0 & lbu2 AR0 & lbu2 @start, AR0 & lbu2 *+AR0(5), AR0 & lbu2 5, AR0 + lbu3_AU: & lbu3 AR1, AR0 & lbu3 AR0 & lbu3 @start, AR0 & lbu3 *+AR0(5), AR0 & lbu3 5, AR0 + lda_AY: & lda AR1, AR0 & lda @start, AR0 & lda *+AR0(5), AR0 & lda -5, AR0 +ldep_Z: ldep IVTP, AR0 +ldhi_Z: ldhi 35, R0 + ldhi start, R0 +ldpe_Z: ldpe AR0, IVTP +ldpk_Z: ldpk start + lh0_A: & lh0 AR1, AR0 & lh0 AR0 & lh0 @start, AR0 & lh0 *+AR0(5), AR0 & lh0 -5, AR0 + lh1_A: & lh1 AR1, AR0 & lh1 AR0 & lh1 @start, AR0 & lh1 *+AR0(5), AR0 & lh1 -5, AR0 + lhu0_AU: & lhu0 AR1, AR0 & lhu0 AR0 & lhu0 @start, AR0 & lhu0 *+AR0(5), AR0 & lhu0 5, AR0 + lhu1_AU: & lhu1 AR1, AR0 & lhu1 AR0 & lhu1 @start, AR0 & lhu1 *+AR0(5), AR0 & lhu1 5, AR0 + lwl0_A: & lwl0 AR1, AR0 & lwl0 AR0 & lwl0 @start, AR0 & lwl0 *+AR0(5), AR0 & lwl0 -5, AR0 + lwl1_A: & lwl1 AR1, AR0 & lwl1 AR0 & lwl1 @start, AR0 & lwl1 *+AR0(5), AR0 & lwl1 -5, AR0 + lwl2_A: & lwl2 AR1, AR0 & lwl2 AR0 & lwl2 @start, AR0 & lwl2 *+AR0(5), AR0 & lwl2 -5, AR0 + lwl3_A: & lwl3 AR1, AR0 & lwl3 AR0 & lwl3 @start, AR0 & lwl3 *+AR0(5), AR0 & lwl3 -5, AR0 + lwr0_A: & lwr0 AR1, AR0 & lwr0 AR0 & lwr0 @start, AR0 & lwr0 *+AR0(5), AR0 & lwr0 -5, AR0 + lwr1_A: & lwr1 AR1, AR0 & lwr1 AR0 & lwr1 @start, AR0 & lwr1 *+AR0(5), AR0 & lwr1 -5, AR0 + lwr2_A: & lwr2 AR1, AR0 & lwr2 AR0 & lwr2 @start, AR0 & lwr2 *+AR0(5), AR0 & lwr2 -5, AR0 + lwr3_A: & lwr3 AR1, AR0 & lwr3 AR0 & lwr3 @start, AR0 & lwr3 *+AR0(5), AR0 & lwr3 -5, AR0 + mb0_A: & mb0 AR1, AR0 & mb0 AR0 & mb0 @start, AR0 & mb0 *+AR0(5), AR0 & mb0 -5, AR0 + mb1_A: & mb1 AR1, AR0 & mb1 AR0 & mb1 @start, AR0 & mb1 *+AR0(5), AR0 & mb1 -5, AR0 + mb2_A: & mb2 AR1, AR0 & mb2 AR0 & mb2 @start, AR0 & mb2 *+AR0(5), AR0 & mb2 -5, AR0 + mb3_A: & mb3 AR1, AR0 & mb3 AR0 & mb3 @start, AR0 & mb3 *+AR0(5), AR0 & mb3 -5, AR0 + mh0_A: & mh0 AR1, AR0 & mh0 AR0 & mh0 @start, AR0 & mh0 *+AR0(5), AR0 & mh0 -5, AR0 + mh1_A: & mh1 AR1, AR0 & mh1 AR0 & mh1 @start, AR0 & mh1 *+AR0(5), AR0 & mh1 -5, AR0 + mh2_A: & mh2 AR1, AR0 & mh2 AR0 & mh2 @start, AR0 & mh2 *+AR0(5), AR0 & mh2 -5, AR0 + mh3_A: & mh3 AR1, AR0 & mh3 AR0 & mh3 @start, AR0 & mh3 *+AR0(5), AR0 & mh3 -5, AR0 + mpyshi_A: & mpyshi AR1, AR0 & mpyshi AR0 & mpyshi @start, AR0 & mpyshi *+AR0(5), AR0 & mpyshi -5, AR0 + mpyshi_TC: & mpyshi AR2, AR1, AR0 & mpyshi AR1, AR0 & mpyshi AR1, *+AR0(1), AR0 & mpyshi *+AR0(1), AR1, AR0 & mpyshi *+AR0(1), AR0 & mpyshi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyshi 5, AR1, AR0 & mpyshi 5, AR0 & mpyshi AR1, -5, AR0 & mpyshi *+AR0(5), AR1, AR0 & mpyshi *+AR0(5), AR0 & mpyshi AR1, *+AR0(5), AR0 & mpyshi 5, *+AR0(5), AR0 & mpyshi *+AR0(5), -5, AR0 & mpyshi *+AR0(5), *+AR1(5), AR0 & .endif & mpyshi3_TC: & mpyshi3 AR2, AR1, AR0 & mpyshi3 AR1, AR0 & mpyshi3 AR1, *+AR0(1), AR0 & mpyshi3 *+AR0(1), AR1, AR0 & mpyshi3 *+AR0(1), AR0 & mpyshi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyshi3 -5, AR1, AR0 & mpyshi3 -5, AR0 & mpyshi3 AR1, -5, AR0 & mpyshi3 *+AR0(5), AR1, AR0 & mpyshi3 *+AR0(5), AR0 & mpyshi3 AR1, *+AR0(5), AR0 & mpyshi3 -5, *+AR0(5), AR0 & mpyshi3 *+AR0(5), -5, AR0 & mpyshi3 *+AR0(5), *+AR1(5), AR0 & .endif + mpyuhi_A: & mpyuhi AR1, AR0 & mpyuhi AR0 & mpyuhi @start, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi -5, AR0 + mpyuhi_TC: & mpyuhi AR2, AR1, AR0 & mpyuhi AR1, AR0 & mpyuhi AR1, *+AR0(1), AR0 & mpyuhi *+AR0(1), AR1, AR0 & mpyuhi *+AR0(1), AR0 & mpyuhi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyuhi 5, AR1, AR0 & mpyuhi 5, AR0 & mpyuhi AR1, -5, AR0 & mpyuhi *+AR0(5), AR1, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi AR1, *+AR0(5), AR0 & mpyuhi 5, *+AR0(5), AR0 & mpyuhi *+AR0(5), -5, AR0 & mpyuhi *+AR0(5), *+AR1(5), AR0 & .endif & mpyuhi3_TC: & mpyuhi3 AR2, AR1, AR0 & mpyuhi3 AR1, AR0 & mpyuhi3 AR1, *+AR0(1), AR0 & mpyuhi3 *+AR0(1), AR1, AR0 & mpyuhi3 *+AR0(1), AR0 & mpyuhi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyuhi3 -5, AR1, AR0 & mpyuhi3 -5, AR0 & mpyuhi3 AR1, -5, AR0 & mpyuhi3 *+AR0(5), AR1, AR0 & mpyuhi3 *+AR0(5), AR0 & mpyuhi3 AR1, *+AR0(5), AR0 & mpyuhi3 -5, *+AR0(5), AR0 & mpyuhi3 *+AR0(5), -5, AR0 & mpyuhi3 *+AR0(5), *+AR1(5), AR0 & .endif + rcpf_BA: & rcpf AR1, R0 & rcpf R0 & rcpf @start, R0 & rcpf *+AR0(5), R0 & rcpf 3.5, R0 +retid_Z: retiCd + retid +rptb2_I2: rptb AR0 +rptbd_I2: rptbd start + rptbd AR0 + rsqrf_B: & rsqrf R1, R0 & rsqrf R0 & rsqrf @start, R0 & rsqrf *+AR0(5), R0 & rsqrf 3.5, R0 + sigi_A6: & sigi @start, AR0 & sigi *+AR0(5), AR0 +sti2_A7: sti -5, @start + sti -5, *+AR0(5) +stik_Z: stik -5, @start + stik -5, *+AR0(5) + toieee_B: & toieee R1, R0 & toieee R0 & toieee @start, R0 & toieee *+AR0(5), R0 & toieee 3.5, R0 + toieee_stf_P: & toieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee *+AR0(1), R0 + .endif + .end + diff --git a/gas/testsuite/gas/tic4x/opcodes_c3x.d b/gas/testsuite/gas/tic4x/opcodes_c3x.d new file mode 100644 index 0000000..ae92bfa --- /dev/null +++ b/gas/testsuite/gas/tic4x/opcodes_c3x.d @@ -0,0 +1,1342 @@ +#as: -m30 --defsym TEST_C3X=1 +#objdump: -d -z +#name: c3x opcodes +#source: opcodes.s + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <absf_B>: + 0: 00000001.* + 1: 00000000.* + 2: 00200000.* + 3: 00400005.* + 4: 00601600.* + +00000005 <absf_stf_P>: + 5: c8010100.* + 6: c8010100.* + +00000007 <absi_A>: + 7: 00880009.* + 8: 00880008.* + 9: 00a80000.* + a: 00c80005.* + b: 00e8fffb.* + +0000000c <absi_sti_P>: + c: ca010100.* + d: ca010100.* + +0000000e <addc_A>: + e: 01080009.* + f: 01080008.* + 10: 01280000.* + 11: 01480005.* + 12: 0168fffb.* + +00000013 <addc_TC>: + 13: 2008090a.* + 14: 01080009.* + 15: 20280009.* + 16: 20480900.* + 17: 01480001.* + 18: 20680001.* + +00000019 <addc3_TC>: + 19: 2008090a.* + 1a: 20080809.* + 1b: 20280009.* + 1c: 20480900.* + 1d: 20480800.* + 1e: 20680001.* + +0000001f <addf_B>: + 1f: 01800001.* + 20: 01800000.* + 21: 01a00000.* + 22: 01c00005.* + 23: 01e01600.* + +00000024 <addf_SC>: + 24: 20800102.* + 25: 01800001.* + 26: 20a00001.* + 27: 20c00100.* + 28: 01c00001.* + 29: 20e00100.* + +0000002a <addf3_SC>: + 2a: 20800102.* + 2b: 20800001.* + 2c: 20a00001.* + 2d: 20c00100.* + 2e: 20c00000.* + 2f: 20e00100.* + +00000030 <addf_stf_QC>: + 30: cc090100.* + 31: cc010100.* + 32: cc010100.* + 33: cc090100.* + 34: cc010100.* + 35: cc010100.* + +00000036 <addf3_stf_QC>: + 36: cc090100.* + 37: cc010100.* + 38: cc010100.* + 39: cc090100.* + 3a: cc010100.* + 3b: cc010100.* + +0000003c <addi_A>: + 3c: 02080009.* + 3d: 02080008.* + 3e: 02280000.* + 3f: 02480005.* + 40: 0268fffb.* + +00000041 <addi_TC>: + 41: 2108090a.* + 42: 02080009.* + 43: 21280009.* + 44: 21480900.* + 45: 02480001.* + 46: 21680001.* + +00000047 <addi3_TC>: + 47: 2108090a.* + 48: 21080809.* + 49: 21280009.* + 4a: 21480900.* + 4b: 21480800.* + 4c: 21680001.* + +0000004d <addi_sti_QC>: + 4d: ce090100.* + 4e: ce010100.* + 4f: ce010100.* + 50: ce090100.* + 51: ce010100.* + 52: ce010100.* + +00000053 <addi3_sti_QC>: + 53: ce090100.* + 54: ce010100.* + 55: ce010100.* + 56: ce090100.* + 57: ce010100.* + 58: ce010100.* + +00000059 <and_AU>: + 59: 02880009.* + 5a: 02880008.* + 5b: 02a80000.* + 5c: 02c80005.* + 5d: 02e80005.* + +0000005e <and_TC>: + 5e: 2188090a.* + 5f: 02880009.* + 60: 21a80009.* + 61: 21c80900.* + 62: 02c80001.* + 63: 21e80001.* + +00000064 <and3_TC>: + 64: 2188090a.* + 65: 21880809.* + 66: 21a80009.* + 67: 21c80900.* + 68: 21c80800.* + 69: 21e80001.* + +0000006a <and_sti_QC>: + 6a: d0090100.* + 6b: d0010100.* + 6c: d0010100.* + 6d: d0090100.* + 6e: d0010100.* + 6f: d0010100.* + +00000070 <and3_sti_QC>: + 70: d0090100.* + 71: d0010100.* + 72: d0010100.* + 73: d0090100.* + 74: d0010100.* + 75: d0010100.* + +00000076 <andn_AU>: + 76: 03080009.* + 77: 03080008.* + 78: 03280000.* + 79: 03480005.* + 7a: 03680005.* + +0000007b <andn_T>: + 7b: 2208090a.* + 7c: 03080009.* + 7d: 22280009.* + 7e: 22480900.* + 7f: 03480001.* + 80: 22680001.* + +00000081 <andn3_T>: + 81: 2208090a.* + 82: 22080809.* + 83: 22280009.* + 84: 22480900.* + 85: 22480800.* + 86: 22680001.* + +00000087 <ash_A>: + 87: 03880009.* + 88: 03880008.* + 89: 03a80000.* + 8a: 03c80005.* + 8b: 03e8fffb.* + +0000008c <ash_T>: + 8c: 2288090a.* + 8d: 03880009.* + 8e: 22a80009.* + 8f: 22c80900.* + 90: 03c80001.* + 91: 22e80001.* + +00000092 <ash3_T>: + 92: 2288090a.* + 93: 22880809.* + 94: 22a80009.* + 95: 22c80900.* + 96: 22c80800.* + 97: 22e80001.* + +00000098 <ash_sti_Q>: + 98: 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+000005a5 <rsqrf_B>: + 5a5: 1c800001.* + 5a6: 1c800000.* + 5a7: 1ca00000.* + 5a8: 1cc00005.* + 5a9: 1ce01600.* + +000005aa <sigi_A6>: + 5aa: 16280000.* + 5ab: 16480005.* + +000005ac <sti2_A7>: + 5ac: 151b0000.* + 5ad: 157b0005.* + +000005ae <stik_Z>: + 5ae: 151b0000.* + 5af: 157b0005.* + +000005b0 <toieee_B>: + 5b0: 1b800001.* + 5b1: 1b800000.* + 5b2: 1ba00000.* + 5b3: 1bc00005.* + 5b4: 1be01600.* + +000005b5 <toieee_stf_P>: + 5b5: f0010100.* + 5b6: f0010100.* diff --git a/gas/testsuite/gas/tic4x/rebuild.sh b/gas/testsuite/gas/tic4x/rebuild.sh new file mode 100755 index 0000000..3e98a32 --- /dev/null +++ b/gas/testsuite/gas/tic4x/rebuild.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +echo "Rebuilding opcodes.s from allopcodes.S" +cat <<EOF >opcodes.s +; File is autogenerated from allopcodes.S - do not edit +; Please use ./rebuild.sh to rebuild this file + +EOF + +cpp -P allopcodes.S >>opcodes.s diff --git a/gas/testsuite/gas/tic4x/registers.s b/gas/testsuite/gas/tic4x/registers.s new file mode 100644 index 0000000..b45f063 --- /dev/null +++ b/gas/testsuite/gas/tic4x/registers.s @@ -0,0 +1,69 @@ + ;; test all register names c3x + .text + ;; Test the base names + .ifdef TEST_ALL +start: ldi R0,R0 + ldi R0,R1 + ldi R0,R2 + ldi R0,R3 + ldi R0,R4 + ldi R0,R5 + ldi R0,R6 + ldi R0,R7 + ldi R0,AR0 + ldi R0,AR1 + ldi R0,AR2 + ldi R0,AR3 + ldi R0,AR4 + ldi R0,AR5 + ldi R0,AR6 + ldi R0,AR7 + ldi R0,DP + ldi R0,IR0 + ldi R0,IR1 + ldi R0,BK + ldi R0,SP + ldi R0,ST + .endif + .ifdef TEST_C3X + ldi R0,IE + ldi R0,IF + ldi R0,IOF + .endif + .ifdef TEST_C4X + ldi R0,DIE + ldi R0,IIE + ldi R0,IIF + .endif + .ifdef TEST_ALL + ldi R0,RS + ldi R0,RE + ldi R0,RC + .endif + .ifdef TEST_C4X + ldi R0,R8 + ldi R0,R9 + ldi R0,R10 + ldi R0,R11 + ldpe R0,IVTP + ldpe R0,TVTP + .endif + + ;; Test the alternative names + .ifdef TEST_ALL + ldf F0,F0 + ldf F0,F1 + ldf F0,F2 + ldf F0,F3 + ldf F0,F4 + ldf F0,F5 + ldf F0,F6 + ldf F0,F7 + .endif + .ifdef TEST_C4X + ldf F0,F8 + ldf F0,F9 + ldf F0,F10 + ldf F0,F11 + .endif + .end diff --git a/gas/testsuite/gas/tic4x/registers_c3x.d b/gas/testsuite/gas/tic4x/registers_c3x.d new file mode 100644 index 0000000..b7b3bf0 --- /dev/null +++ b/gas/testsuite/gas/tic4x/registers_c3x.d @@ -0,0 +1,46 @@ +#as: -m30 --defsym TEST_ALL=1 --defsym TEST_C3X=1 +#objdump: -d -z +#name: c3x registers +#source: registers.s + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <start>: + 0: 08000000.* + 1: 08010000.* + 2: 08020000.* + 3: 08030000.* + 4: 08040000.* + 5: 08050000.* + 6: 08060000.* + 7: 08070000.* + 8: 08080000.* + 9: 08090000.* + a: 080a0000.* + b: 080b0000.* + c: 080c0000.* + d: 080d0000.* + e: 080e0000.* + f: 080f0000.* + 10: 08100000.* + 11: 08110000.* + 12: 08120000.* + 13: 08130000.* + 14: 08140000.* + 15: 08150000.* + 16: 08160000.* + 17: 08170000.* + 18: 08180000.* + 19: 08190000.* + 1a: 081a0000.* + 1b: 081b0000.* + 1c: 07000000.* + 1d: 07010000.* + 1e: 07020000.* + 1f: 07030000.* + 20: 07040000.* + 21: 07050000.* + 22: 07060000.* + 23: 07070000.* diff --git a/gas/testsuite/gas/tic4x/registers_c4x.d b/gas/testsuite/gas/tic4x/registers_c4x.d new file mode 100644 index 0000000..cf9fa50 --- /dev/null +++ b/gas/testsuite/gas/tic4x/registers_c4x.d @@ -0,0 +1,56 @@ +#as: -m40 --defsym TEST_ALL=1 --defsym TEST_C4X=1 +#objdump: -d -z +#name: c4x registers +#source: registers.s + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <start>: + 0: 08000000.* + 1: 08010000.* + 2: 08020000.* + 3: 08030000.* + 4: 08040000.* + 5: 08050000.* + 6: 08060000.* + 7: 08070000.* + 8: 08080000.* + 9: 08090000.* + a: 080a0000.* + b: 080b0000.* + c: 080c0000.* + d: 080d0000.* + e: 080e0000.* + f: 080f0000.* + 10: 08100000.* + 11: 08110000.* + 12: 08120000.* + 13: 08130000.* + 14: 08140000.* + 15: 08150000.* + 16: 08160000.* + 17: 08170000.* + 18: 08180000.* + 19: 08190000.* + 1a: 081a0000.* + 1b: 081b0000.* + 1c: 081c0000.* + 1d: 081d0000.* + 1e: 081e0000.* + 1f: 081f0000.* + 20: 76800000.* + 21: 76810000.* + 22: 07000000.* + 23: 07010000.* + 24: 07020000.* + 25: 07030000.* + 26: 07040000.* + 27: 07050000.* + 28: 07060000.* + 29: 07070000.* + 2a: 071c0000.* + 2b: 071d0000.* + 2c: 071e0000.* + 2d: 071f0000.* diff --git a/gas/testsuite/gas/tic4x/tic4x.exp b/gas/testsuite/gas/tic4x/tic4x.exp new file mode 100644 index 0000000..100bdf9 --- /dev/null +++ b/gas/testsuite/gas/tic4x/tic4x.exp @@ -0,0 +1,64 @@ + +# +# Test x930509a -- correct assembly of differences involving forward +# references. +# +proc do_930509a_tic4x {} { + set testname "difference between forward references (tic4x version)" + set x 0 + gas_start "../all/x930509.s" "-al" + while 1 { +# We need to accomodate both byte orders here. +# If ".long" means an 8-byte value on some target someday, this test will have +# to be fixed. + expect { + -re "^ +1 .... 00 ?00 ?00 ?00" { fail $testname; set x 1 } + -re "^ +1 .... 01 ?00 ?00 ?00" { pass $testname; set x 1 } + -re "^ +1 .... 00 ?00 ?00 ?01" { pass $testname; set x 1 } + -re "\[^\n\]*\n" { } + timeout { perror "timeout\n"; break } + eof { break } + } + } + gas_finish + if !$x then { fail $testname } +} + + +# +# TI TMS320C4X tests. +# +if [istarget *c4x*-*-*] then { + do_930509a_tic4x + + # Test zero-based disassemble test + run_dump_test "zeros" + + # Test the register names on the c3x and on the c4x + run_dump_test "registers_c3x" + run_dump_test "registers_c4x" + + # Make sure the c4x registers dont work on c3x + gas_test_error "registers.s" "-m30 --defsym TEST_C4X=1" "c4x register usage in c3x" + + # Test data storage + run_dump_test "data" + + # Test flonums + run_dump_test "float" + + # Test all addressing modes + run_dump_test "addressing_c3x" + run_dump_test "addressing_c4x" + + # Make sure the c4x addressing dont work on c3x + gas_test_error "addressing.s" "-m30 --defsym TEST_C4X=1" "c4x addressing usage in c3x" + + # Test float instructions + run_dump_test "opcodes_c3x" + run_dump_test "opcodes_c4x" + + # Make sure the c4x ops dont work on c3x + #gas_test_error "opcodes.s" "-m30 --defsym TEST_C4X=1" "c4x instruction usage in c3x" + # -- for some reason this test crashes dejagnu, hence disabled! +} diff --git a/gas/testsuite/gas/tic4x/zeros.d b/gas/testsuite/gas/tic4x/zeros.d new file mode 100644 index 0000000..8e45968 --- /dev/null +++ b/gas/testsuite/gas/tic4x/zeros.d @@ -0,0 +1,24 @@ +#objdump: -d +#name: zero-value disassemble check + +.*: +file format .*c4x.* + +Disassembly of section .text: + +00000000 <start>: + 0: 00000000.* + 1: 00000000.* + 2: 00000002.* + ... + 16: 00000001.* + 17: 00000001.* + 18: 00000002.* + 19: 00000000.* + 1a: 00000001.* + 1b: 00000001.* + 1c: 00000002.* + 1d: 00000000.* + 1e: 00000000.* + 1f: 00000002.* + 20: 00000000.* + 21: 00000000.* diff --git a/gas/testsuite/gas/tic4x/zeros.s b/gas/testsuite/gas/tic4x/zeros.s new file mode 100644 index 0000000..d7295ad --- /dev/null +++ b/gas/testsuite/gas/tic4x/zeros.s @@ -0,0 +1,35 @@ + .text +start: .long 0 + .long 0 + .long 2 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 1 + .long 1 + .long 2 + .long 0 + .long 1 + .long 1 + .long 2 + .long 0 + .long 0 + .long 2 + .long 0 + .long 0 diff --git a/ld/ChangeLog b/ld/ChangeLog index 3e98cde..304973e 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,7 @@ +2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> + + * testsuite/ld-scripts/script.exp: Setup for tic4x testcase + 2002-11-14 Egor Duda <deo@logos-m.ru> * ldmain.c (main): Make runtime relocs disabled by default. Remove diff --git a/ld/testsuite/ld-scripts/script.exp b/ld/testsuite/ld-scripts/script.exp index a7f6bad..96cf04b 100644 --- a/ld/testsuite/ld-scripts/script.exp +++ b/ld/testsuite/ld-scripts/script.exp @@ -42,6 +42,10 @@ proc check_script { } { } else { set text_end 0x104 set data_end 0x1004 + if [istarget *c4x*-*-*] then { + set text_end 0x101 + set data_end 0x1001 + } if [istarget *c54x*-*-*] then { set text_end 0x102 set data_end 0x1002 |