MIPS: Add Octeon 3 support

binutils:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* readelf.c (print_mips_isa_ext): Print the value of Octeon3.

gas:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
	(mips_cpu_info_table): Octeon3 enables virt ase.
	* doc/c-mips.texi: Document octeon3 as an acceptable value for
	-march=.

gas/testsuite:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gas/mips/mips.exp: Add support for Octeon3 architecture.
	Also add in support for running Octeon3 tests.
	* gas/mips/octeon3.d: New test.
	* gas/mips/octeon3.s: New test source.

opcodes:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* mips-dis.c (mips_arch_choices): Add octeon3.
	* mips-opc.c (IOCT): Include INSN_OCTEON3.
	(IOCT2): Likewise.
	(IOCT3): New define.
	(IVIRT): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
	IVIRT instructions.
	Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
	operand for IOCT3.

bfd:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* archures.c: Add octeon3 for mips target.
	* bfd-in2.h: Regenerate.
	* bfd/cpu-mips.c: Define I_mipsocteon3.
	nfo_struct): Add octeon3 support.
	* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
	octeon3.
	(mips_set_isa_flags): Add support for octeon3.
	(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
	(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
	extension of bfd_mach_mips_octeon2.
	(print_mips_isa_ext): Print the value of Octeon3.

20 files changed, 146 insertions, 4 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index d861257..87297d0 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,18 @@
+2014-10-31  Andrew Pinski  <apinski@cavium.com>
+            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* archures.c: Add octeon3 for mips target.
+	* bfd-in2.h: Regenerate.
+	* bfd/cpu-mips.c: Define I_mipsocteon3.
+	nfo_struct): Add octeon3 support.
+	* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
+	octeon3.
+	(mips_set_isa_flags): Add support for octeon3.
+	(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3. 
+	(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
+	extension of bfd_mach_mips_octeon2.
+	(print_mips_isa_ext): Print the value of Octeon3.
+
 2014-10-31  Nick Clifton  <nickc@redhat.com>
 
 	PR binutils/17512
diff --git a/bfd/archures.c b/bfd/archures.c
index c9fd6c8..5e069b2 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -179,6 +179,7 @@ DESCRIPTION
 .#define bfd_mach_mips_octeon		6501
 .#define bfd_mach_mips_octeonp		6601
 .#define bfd_mach_mips_octeon2		6502
+.#define bfd_mach_mips_octeon3          6503
 .#define bfd_mach_mips_xlr              887682   {* decimal 'XLR'  *}
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c7a2bb5..433b171 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1966,6 +1966,7 @@ enum bfd_architecture
 #define bfd_mach_mips_octeon           6501
 #define bfd_mach_mips_octeonp          6601
 #define bfd_mach_mips_octeon2          6502
+#define bfd_mach_mips_octeon3          6503
 #define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index b617aaa..a376944 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -102,6 +102,7 @@ enum
   I_mipsocteon,
   I_mipsocteonp,
   I_mipsocteon2,
+  I_mipsocteon3,
   I_xlr,
   I_micromips
 };
@@ -152,6 +153,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
   N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
+  N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3",  FALSE, NN(I_mipsocteon3)),
   N (64, 64, bfd_mach_mips_xlr, "mips:xlr",       FALSE, NN(I_xlr)),
   N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
 };
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 61c363a..f82102a 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6588,6 +6588,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_LS3A:
       return bfd_mach_mips_loongson_3a;
 
+    case E_MIPS_MACH_OCTEON3:
+      return bfd_mach_mips_octeon3;
+
     case E_MIPS_MACH_OCTEON2:
       return bfd_mach_mips_octeon2;
 
@@ -11859,6 +11862,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
       break;
 
+    case bfd_mach_mips_octeon3:
+      val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON3;
+      break;
+
     case bfd_mach_mips_xlr:
       val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
       break;
@@ -13905,6 +13912,8 @@ bfd_mips_isa_ext (bfd *abfd)
       return AFL_EXT_OCTEON;
     case bfd_mach_mips_octeonp:
       return AFL_EXT_OCTEONP;
+    case bfd_mach_mips_octeon3:
+      return AFL_EXT_OCTEON3;
     case bfd_mach_mips_octeon2:
       return AFL_EXT_OCTEON2;
     case bfd_mach_mips_xlr:
@@ -14730,6 +14739,7 @@ struct mips_mach_extension
 static const struct mips_mach_extension mips_mach_extensions[] =
 {
   /* MIPS64r2 extensions.  */
+  { bfd_mach_mips_octeon3, bfd_mach_mips_octeon2 },
   { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
   { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
   { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
@@ -15522,6 +15532,9 @@ print_mips_isa_ext (FILE *file, unsigned int isa_ext)
     case AFL_EXT_XLR:
       fputs ("RMI XLR", file);
       break;
+    case AFL_EXT_OCTEON3:
+      fputs ("Cavium Networks Octeon3", file);
+      break;
     case AFL_EXT_OCTEON2:
       fputs ("Cavium Networks Octeon2", file);
       break;
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index a6ddebe..1db5338 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2014-10-31  Andrew Pinski  <apinski@cavium.com>
+            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
+
 2014-10-31  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	* cxxfilt.c (main): Add case for dlang_demangling style.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 6ddc078..f5aa28d 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -12767,6 +12767,9 @@ print_mips_isa_ext (unsigned int isa_ext)
     case AFL_EXT_XLR:
       fputs ("RMI XLR", stdout);
       break;
+    case AFL_EXT_OCTEON3:
+      fputs ("Cavium Networks Octeon3", stdout);
+      break;
     case AFL_EXT_OCTEON2:
       fputs ("Cavium Networks Octeon2", stdout);
       break;
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 183232f..a1a4224 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2014-10-31  Andrew Pinski  <apinski@cavium.com>
+            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
+	(mips_cpu_info_table): Octeon3 enables virt ase.
+	* doc/c-mips.texi: Document octeon3 as an acceptable value for
+	-march=.
+
 2014-10-30  Dr Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 
 	* config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 54442f4..355a566 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -510,7 +510,8 @@ static int mips_32bitmode = 0;
 #define CPU_HAS_ROR(CPU)	CPU_HAS_DROR (CPU)
 
 /* True if CPU is in the Octeon family */
-#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
+			    || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
 
 /* True if CPU has seq/sne and seqi/snei instructions.  */
 #define CPU_HAS_SEQ(CPU)	(CPU_IS_OCTEON (CPU))
@@ -18663,6 +18664,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "octeon",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON },
   { "octeon+",	      0, 0,			ISA_MIPS64R2, CPU_OCTEONP },
   { "octeon2",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON2 },
+  { "octeon3",	      0, ASE_VIRT | ASE_VIRT64,	ISA_MIPS64R5, CPU_OCTEON3 },
 
   /* RMI Xlr */
   { "xlr",	      0, 0,			ISA_MIPS64,   CPU_XLR },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index d960022..899e6e2 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -382,6 +382,7 @@ loongson3a,
 octeon,
 octeon+,
 octeon2,
+octeon3,
 xlr,
 xlp
 @end quotation
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 4988b00..1b41cc4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2014-10-31  Andrew Pinski  <apinski@cavium.com>
+            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* gas/mips/mips.exp: Add support for Octeon3 architecture.
+	Also add in support for running Octeon3 tests.
+	* gas/mips/octeon3.d: New test.
+	* gas/mips/octeon3.s: New test source.
+
 2014-10-21  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* gas/mips/insn-opts.d: New test.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 5750b75..855e2cd 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -495,6 +495,9 @@ mips_arch_create octeonp 64	octeon { oddspreg } \
 mips_arch_create octeon2 64	octeonp { oddspreg } \
 			{ -march=octeon2 -mtune=octeon2 } { -mmips:octeon2 } \
 			{ }
+mips_arch_create octeon3 64	octeon2 { oddspreg } \
+			{ -march=octeon3 -mtune=octeon3 } { -mmips:octeon3 } \
+			{ }
 mips_arch_create xlr 	64	mips64	{ oddspreg } \
 			{ -march=xlr -mtune=xlr } { -mmips:xlr }
 mips_arch_create r5900 	64	mips3	{ gpr_ilocks singlefloat nollsc } \
@@ -1100,6 +1103,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_list_test_arches "octeon-ill"	[mips_arch_list_matching octeon]
     run_dump_test_arches "octeon-pref"	[mips_arch_list_matching octeon]
     run_dump_test_arches "octeon2"	[mips_arch_list_matching octeon2]
+    run_dump_test_arches "octeon3"	[mips_arch_list_matching octeon3]
 
     run_dump_test "smartmips"
     run_dump_test_arches "mips32-dsp"	[mips_arch_list_matching mips32r2 \
diff --git a/gas/testsuite/gas/mips/octeon3.d b/gas/testsuite/gas/mips/octeon3.d
new file mode 100644
index 0000000..0e0b508
--- /dev/null
+++ b/gas/testsuite/gas/mips/octeon3.d
@@ -0,0 +1,20 @@
+#objdump: -d -r --show-raw-insn
+#name: MIPS octeon3 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*:	71ec0008 	mtm0	t3,t0
+.*:	71a40008 	mtm0	t1,a0
+.*:	7083000c 	mtm1	a0,v1
+.*:	70e1000c 	mtm1	a3,at
+.*:	7022000d 	mtm2	at,v0
+.*:	7083000c 	mtm1	a0,v1
+.*:	70a20009 	mtp0	a1,v0
+.*:	70c40009 	mtp0	a2,a0
+.*:	7083000a 	mtp1	a0,v1
+.*:	70e1000a 	mtp1	a3,at
+.*:	7022000b 	mtp2	at,v0
+.*:	7083000a 	mtp1	a0,v1
diff --git a/gas/testsuite/gas/mips/octeon3.s b/gas/testsuite/gas/mips/octeon3.s
new file mode 100644
index 0000000..f28425c
--- /dev/null
+++ b/gas/testsuite/gas/mips/octeon3.s
@@ -0,0 +1,22 @@
+	.text
+	.set noreorder
+	.set noat
+
+foo:
+	mtm0 $15,$12
+	mtm0 $13,$4
+
+	mtm1 $4,$3
+	mtm1 $7,$1
+
+	mtm2 $1,$2
+	mtm1 $4,$3
+
+	mtp0 $5,$2
+	mtp0 $6,$4
+
+	mtp1 $4,$3
+	mtp1 $7,$1
+
+	mtp2 $1,$2
+	mtp1 $4,$3
diff --git a/include/ChangeLog b/include/ChangeLog
index 1eec0a4..0204432 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2014-10-30  Andrew Pinski  <apinski@cavium.com>
+
+	* elf/mips.h (AFL_EXT_OCTEON3): Define.
+	INSN_OCTEON3, CPU_OCTEON3): Define.
+
 2014-10-22  Matthew Fortune  <matthew.fortune@imgtec.com>
 
 	* elf/mips.h (AFL_ASE_MASK): Define.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 2ed6acd..8b885bc 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1246,6 +1246,7 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
 #define AFL_EXT_5500         16  /* NEC VR5500 instruction.  */
 #define AFL_EXT_LOONGSON_2E  17  /* ST Microelectronics Loongson 2E.  */
 #define AFL_EXT_LOONGSON_2F  18  /* ST Microelectronics Loongson 2F.  */
+#define AFL_EXT_OCTEON3      19  /* Cavium Networks Octeon3.  */
 
 /* Masks for the flags1 word of an ABI flags structure.  */
 #define AFL_FLAGS1_ODDSPREG   1	 /* Uses odd single-precision registers.  */
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index ef26167..ab40c60 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1196,6 +1196,7 @@ static const unsigned int mips_isa_table[] = {
 #define INSN_OCTEON		  0x00000800
 #define INSN_OCTEONP		  0x00000200
 #define INSN_OCTEON2		  0x00000100
+#define INSN_OCTEON3		  0x00000040
 
 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
@@ -1323,6 +1324,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
+#define CPU_OCTEON3	6503
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
 
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
@@ -1388,6 +1390,9 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_OCTEON2:
       return (mask & INSN_OCTEON2) != 0;
 
+    case CPU_OCTEON3:
+      return (mask & INSN_OCTEON3) != 0;
+
     case CPU_XLR:
       return (mask & INSN_XLR) != 0;
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6175d24..6b7edd6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2014-10-31  Andrew Pinski  <apinski@cavium.com>
+            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
+
+	* mips-dis.c (mips_arch_choices): Add octeon3.
+	* mips-opc.c (IOCT): Include INSN_OCTEON3.
+	(IOCT2): Likewise.
+	(IOCT3): New define.
+	(IVIRT): New define.
+	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+	tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
+	IVIRT instructions.
+	Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
+	operand for IOCT3.
+
 2014-10-29  Nick Clifton  <nickc@redhat.com>
 
 	* po/de.po: Updated German translation.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1eb1d45..e710d04 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -649,6 +649,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
     NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
 
+  { "octeon3",   1, bfd_mach_mips_octeon3, CPU_OCTEON3,
+    ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
+    mips_cp0_names_numeric,
+    NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
   { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
     ISA_MIPS64 | INSN_XLR, 0,
     mips_cp0_names_xlr,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0e9f716..6e0299e 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -316,9 +316,10 @@ decode_mips_operand (const char *p)
 #define N5	(INSN_5400 | INSN_5500)
 #define N54	INSN_5400
 #define N55	INSN_5500
-#define IOCT	(INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
-#define IOCTP	(INSN_OCTEONP | INSN_OCTEON2)
-#define IOCT2	INSN_OCTEON2
+#define IOCT	(INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCTP	(INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT2	(INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT3	INSN_OCTEON3
 #define XLR     INSN_XLR
 #define IVIRT	ASE_VIRT
 #define IVIRT64	ASE_VIRT64
@@ -1496,11 +1497,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtlhx",		"s",		0x00000053, 0xfc1fffff,	RD_1|MOD_HILO,		0,		0,		SMT,	0 },
 {"mtcr",		"t,s",		0x70000019, 0xfc00ffff, RD_1|RD_2,		0,		XLR,		0,	0 },
 {"mtm0",		"s",		0x70000008, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
+{"mtm0",    		"s,t",		0x70000008, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtm1",		"s",		0x7000000c, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
+{"mtm1",    		"s,t",		0x7000000c, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtm2",		"s",		0x7000000d, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
+{"mtm2",    		"s,t",		0x7000000d, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtp0",		"s",		0x70000009, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
+{"mtp0",    		"s,t",		0x70000009, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtp1",		"s",		0x7000000a, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
+{"mtp1",    		"s,t",		0x7000000a, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtp2",		"s",		0x7000000b, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
+{"mtp2",    		"s,t",		0x7000000b, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtsa",		"s",		0x00000029, 0xfc1fffff,	RD_1,			0,		EE,		0,	0 },
 {"mtsab",		"s,j",		0x04180000, 0xfc1f0000,	RD_1,			0,		EE,		0,	0 },
 {"mtsah",		"s,j",		0x04190000, 0xfc1f0000,	RD_1,			0,		EE,		0,	0 },