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| author | Matthieu Longo <matthieu.longo@arm.com> | 2024-05-17 12:04:25 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-05-22 12:02:09 +0100 |
| commit | ef2d28fd02c37d5ab4c3a6a2e9e8844d9ff96a4c (patch) | |
| tree | 49c8af0e36a254e424289d993cd294f9849e14e0 | |
| parent | bbe8d019ed362251ce429585c091a97e19cd0db7 (diff) | |
| download | fsf-binutils-gdb-ef2d28fd02c37d5ab4c3a6a2e9e8844d9ff96a4c.zip fsf-binutils-gdb-ef2d28fd02c37d5ab4c3a6a2e9e8844d9ff96a4c.tar.gz fsf-binutils-gdb-ef2d28fd02c37d5ab4c3a6a2e9e8844d9ff96a4c.tar.bz2 | |
aarch64: fix incorrect encoding for system register pmsdsfr_el1
This patch fixes a mistake in the encoding of the system register
pmsdsfr_el1.
Reference:
https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/PMSDSFR-EL1--Sampling-Data-Source-Filter-Register?lang=en
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-sys-regs.def | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d index e420f70..4c19a50 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d @@ -7,8 +7,8 @@ Disassembly of section \.text: 0+ <.*>: -.*: d51c9a83 msr pmsdsfr_el1, x3 -.*: d53c9a83 mrs x3, pmsdsfr_el1 +.*: d5189a83 msr pmsdsfr_el1, x3 +.*: d5389a83 mrs x3, pmsdsfr_el1 .*: d5385340 mrs x0, erxgsr_el1 .*: d5181063 msr sctlr2_el1, x3 .*: d5381063 mrs x3, sctlr2_el1 diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index c47563c..10b57c1 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -741,7 +741,7 @@ SYSREG ("pmscr_el1", CPENC (3,0,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE)) SYSREG ("pmscr_el12", CPENC (3,5,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE)) SYSREG ("pmscr_el2", CPENC (3,4,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE)) - SYSREG ("pmsdsfr_el1", CPENC (3,4,9,10,4), F_ARCHEXT, AARCH64_FEATURE (SPE_FDS)) + SYSREG ("pmsdsfr_el1", CPENC (3,0,9,10,4), F_ARCHEXT, AARCH64_FEATURE (SPE_FDS)) SYSREG ("pmselr_el0", CPENC (3,3,9,12,5), 0, AARCH64_NO_FEATURES) SYSREG ("pmsevfr_el1", CPENC (3,0,9,9,5), F_ARCHEXT, AARCH64_FEATURE (PROFILE)) SYSREG ("pmsfcr_el1", CPENC (3,0,9,9,4), F_ARCHEXT, AARCH64_FEATURE (PROFILE)) |