diff options
| author | Doug Evans <dje@google.com> | 1998-02-20 00:45:47 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 1998-02-20 00:45:47 +0000 |
| commit | cab581557e08db9079cff43cda6f312ea404fc0c (patch) | |
| tree | ebe678cf7a0db147378806e36284602de85229b6 | |
| parent | a94cefa164a3f0984fd9991e94e0815bfb954eb9 (diff) | |
| download | fsf-binutils-gdb-cab581557e08db9079cff43cda6f312ea404fc0c.zip fsf-binutils-gdb-cab581557e08db9079cff43cda6f312ea404fc0c.tar.gz fsf-binutils-gdb-cab581557e08db9079cff43cda6f312ea404fc0c.tar.bz2 | |
* m32r.c (do_lock,do_unlock): Delete.
* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
* sem.c,sem-switch.c: Regenerate.
* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
| -rw-r--r-- | sim/m32r/ChangeLog | 38 | ||||
| -rw-r--r-- | sim/m32r/cpu.h | 568 | ||||
| -rw-r--r-- | sim/m32r/cpux.h | 780 | ||||
| -rw-r--r-- | sim/m32r/decode.c | 245 | ||||
| -rw-r--r-- | sim/m32r/decode.h | 295 | ||||
| -rw-r--r-- | sim/m32r/decodex.c | 306 | ||||
| -rw-r--r-- | sim/m32r/decodex.h | 357 | ||||
| -rw-r--r-- | sim/m32r/extract.c | 3 | ||||
| -rw-r--r-- | sim/m32r/m32r.c | 258 | ||||
| -rw-r--r-- | sim/m32r/model.c | 12 | ||||
| -rw-r--r-- | sim/m32r/readx.c | 261 | ||||
| -rw-r--r-- | sim/m32r/sem-switch.c | 228 | ||||
| -rw-r--r-- | sim/m32r/sem.c | 241 | ||||
| -rw-r--r-- | sim/m32r/semx.c | 348 |
14 files changed, 2284 insertions, 1656 deletions
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index 50df1e1..a0383df 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,41 @@ +Thu Feb 19 16:39:35 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r.c (do_lock,do_unlock): Delete. + * cpu.[ch],decode.[ch],extract.c,model.c: Regenerate. + * sem.c,sem-switch.c: Regenerate. +start-sanitize-m32rx + * cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate. +end-sanitize-m32rx + +Tue Feb 17 18:18:10 1998 Doug Evans <devans@seba.cygnus.com> + + * Makefile.in (M32R_OBJS): Add cpu.o. + (cpu.o): Add rule for. + (NL_TARGET): Define. + * configure.in: Add AC_CHECK_PROG(SCHEME). + * cpu.c: New file. + * cpuall.h,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate. + * sem-switch.c,sem.c: Regenerate. + * mloop.in (execute): Update call to semantic fn. +start-sanitize-m32rx + (M32RX_OBJS): Add cpux.o. + (cpux.o): Add rule for. + cpux.c: New file. + * cpux.h,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate. + * m32rx.c (m32rx_h_accums_{get,set}): Rewrite. + (m32rx_h_cr_{get,set}): New functions. + (m32rx_h_accums_{get,set}): New functions. + * mloopx.in: Rewrite main loop. +end-sanitize-m32rx + + * m32r.c (do_trap): Move from here. + * sim-if.c (do_trap): To here, and rewrite to use CB_SYSCALL support. + (sim_create_inferior): Use h_pc_set. + (h_pc_{get,set}): New functions. + (h_gr_{get,set}): New functions. + (syscall_{read,write}_mem): New functions. + * sim-main.h (h_{gr,pc}_{get,set}): Declare. + Tue Feb 17 12:44:38 1998 Andrew Cagney <cagney@b1.cygnus.com> * sim-if.c (sim_store_register, sim_fetch_register): Pass in diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 3e4abb7..c48cee2 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -1,5 +1,7 @@ /* CPU family header for m32r. +This file is machine generated with CGEN. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of the GNU Simulators. @@ -43,13 +45,25 @@ typedef struct { #define GET_H_GR(a1) CPU (h_gr)[a1] #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) /* control registers */ - SI h_cr[7]; + USI h_cr[7]; #define GET_H_CR(a1) CPU (h_cr)[a1] #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) /* accumulator */ DI h_accum; #define GET_H_ACCUM() CPU (h_accum) #define SET_H_ACCUM(x) (CPU (h_accum) = (x)) +/* start-sanitize-m32rx */ + /* accumulators */ + DI h_accums[2]; +/* end-sanitize-m32rx */ +#define GET_H_ACCUMS(a1) CPU (h_accums)[a1] +#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x)) +/* start-sanitize-m32rx */ + /* abort flag */ + UBI h_abort; +/* end-sanitize-m32rx */ +#define GET_H_ABORT() CPU (h_abort) +#define SET_H_ABORT(x) (CPU (h_abort) = (x)) /* condition bit */ UBI h_cond; #define GET_H_COND() CPU (h_cond) @@ -78,6 +92,10 @@ typedef struct { SI h_bpc; #define GET_H_BPC() CPU (h_bpc) #define SET_H_BPC(x) (CPU (h_bpc) = (x)) + /* lock */ + UBI h_lock; +#define GET_H_LOCK() CPU (h_lock) +#define SET_H_LOCK(x) (CPU (h_lock) = (x)) } hardware; #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) /* CPU profiling state information. */ @@ -88,8 +106,35 @@ typedef struct { #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile) } M32R_CPU_DATA; -/* FIXME: length parm to decode() is currently unneeded. */ -extern DECODE *m32r_decode (SIM_CPU *, insn_t /*, int*/); +USI m32r_h_pc_get (SIM_CPU *); +void m32r_h_pc_set (SIM_CPU *, USI); +SI m32r_h_gr_get (SIM_CPU *, UINT); +void m32r_h_gr_set (SIM_CPU *, UINT, SI); +USI m32r_h_cr_get (SIM_CPU *, UINT); +void m32r_h_cr_set (SIM_CPU *, UINT, USI); +DI m32r_h_accum_get (SIM_CPU *); +void m32r_h_accum_set (SIM_CPU *, DI); +DI m32r_h_accums_get (SIM_CPU *, UINT); +void m32r_h_accums_set (SIM_CPU *, UINT, DI); +UBI m32r_h_abort_get (SIM_CPU *); +void m32r_h_abort_set (SIM_CPU *, UBI); +UBI m32r_h_cond_get (SIM_CPU *); +void m32r_h_cond_set (SIM_CPU *, UBI); +UBI m32r_h_sm_get (SIM_CPU *); +void m32r_h_sm_set (SIM_CPU *, UBI); +UBI m32r_h_bsm_get (SIM_CPU *); +void m32r_h_bsm_set (SIM_CPU *, UBI); +UBI m32r_h_ie_get (SIM_CPU *); +void m32r_h_ie_set (SIM_CPU *, UBI); +UBI m32r_h_bie_get (SIM_CPU *); +void m32r_h_bie_set (SIM_CPU *, UBI); +UBI m32r_h_bcond_get (SIM_CPU *); +void m32r_h_bcond_set (SIM_CPU *, UBI); +SI m32r_h_bpc_get (SIM_CPU *); +void m32r_h_bpc_set (SIM_CPU *, SI); +UBI m32r_h_lock_get (SIM_CPU *); +void m32r_h_lock_set (SIM_CPU *, UBI); +extern DECODE *m32r_decode (SIM_CPU *, PCADDR, insn_t); /* The ARGBUF struct. */ struct argbuf { @@ -97,173 +142,229 @@ struct argbuf { unsigned int length; PCADDR addr; const struct cgen_insn *opcode; - /* unsigned long insn; - no longer needed */ +#if ! defined (SCACHE_P) + insn_t insn; +#endif /* cpu specific data follows */ union { struct { /* e.g. add $dr,$sr */ SI * f_r1; SI * f_r2; } fmt_0_add; - struct { /* e.g. add3 $dr,$sr,$slo16 */ + struct { /* e.g. add3 $dr,$sr,#$slo16 */ SI * f_r1; SI * f_r2; HI f_simm16; } fmt_1_add3; - struct { /* e.g. and3 $dr,$sr,$uimm16 */ + struct { /* e.g. and3 $dr,$sr,#$uimm16 */ SI * f_r1; SI * f_r2; USI f_uimm16; } fmt_2_and3; - struct { /* e.g. or3 $dr,$sr,$ulo16 */ + struct { /* e.g. or3 $dr,$sr,#$ulo16 */ SI * f_r1; SI * f_r2; UHI f_uimm16; } fmt_3_or3; - struct { /* e.g. addi $dr,$simm8 */ + struct { /* e.g. addi $dr,#$simm8 */ SI * f_r1; SI f_simm8; } fmt_4_addi; - struct { /* e.g. addv3 $dr,$sr,$simm16 */ + struct { /* e.g. addv $dr,$sr */ + SI * f_r1; + SI * f_r2; + } fmt_5_addv; + struct { /* e.g. addv3 $dr,$sr,#$simm16 */ SI * f_r1; SI * f_r2; SI f_simm16; - } fmt_5_addv3; + } fmt_6_addv3; struct { /* e.g. addx $dr,$sr */ SI * f_r1; SI * f_r2; - } fmt_6_addx; + } fmt_7_addx; struct { /* e.g. bc $disp8 */ IADDR f_disp8; - } fmt_7_bc8; + } fmt_8_bc8; struct { /* e.g. bc $disp24 */ IADDR f_disp24; - } fmt_8_bc24; + } fmt_9_bc24; struct { /* e.g. beq $src1,$src2,$disp16 */ SI * f_r1; SI * f_r2; IADDR f_disp16; - } fmt_9_beq; + } fmt_10_beq; struct { /* e.g. beqz $src2,$disp16 */ SI * f_r2; IADDR f_disp16; - } fmt_10_beqz; + } fmt_11_beqz; struct { /* e.g. bl $disp8 */ IADDR f_disp8; - } fmt_11_bl8; + } fmt_12_bl8; struct { /* e.g. bl $disp24 */ IADDR f_disp24; - } fmt_12_bl24; + } fmt_13_bl24; struct { /* e.g. bra $disp8 */ IADDR f_disp8; - } fmt_13_bra8; + } fmt_14_bra8; struct { /* e.g. bra $disp24 */ IADDR f_disp24; - } fmt_14_bra24; + } fmt_15_bra24; struct { /* e.g. cmp $src1,$src2 */ SI * f_r1; SI * f_r2; - } fmt_15_cmp; - struct { /* e.g. cmpi $src2,$simm16 */ + } fmt_16_cmp; + struct { /* e.g. cmpi $src2,#$simm16 */ SI * f_r2; SI f_simm16; - } fmt_16_cmpi; - struct { /* e.g. cmpui $src2,$uimm16 */ + } fmt_17_cmpi; + struct { /* e.g. cmpui $src2,#$uimm16 */ SI * f_r2; USI f_uimm16; - } fmt_17_cmpui; + } fmt_18_cmpui; struct { /* e.g. div $dr,$sr */ SI * f_r1; SI * f_r2; - } fmt_18_div; + } fmt_19_div; struct { /* e.g. jl $sr */ SI * f_r2; - } fmt_19_jl; + } fmt_20_jl; struct { /* e.g. jmp $sr */ SI * f_r2; - } fmt_20_jmp; + } fmt_21_jmp; struct { /* e.g. ld $dr,@$sr */ SI * f_r1; SI * f_r2; - } fmt_21_ld; + } fmt_22_ld; struct { /* e.g. ld $dr,@($slo16,$sr) */ SI * f_r1; SI * f_r2; HI f_simm16; - } fmt_22_ld_d; + } fmt_23_ld_d; struct { /* e.g. ldb $dr,@$sr */ SI * f_r1; SI * f_r2; - } fmt_23_ldb; + } fmt_24_ldb; struct { /* e.g. ldb $dr,@($slo16,$sr) */ SI * f_r1; SI * f_r2; HI f_simm16; - } fmt_24_ldb_d; + } fmt_25_ldb_d; struct { /* e.g. ldh $dr,@$sr */ SI * f_r1; SI * f_r2; - } fmt_25_ldh; + } fmt_26_ldh; struct { /* e.g. ldh $dr,@($slo16,$sr) */ SI * f_r1; SI * f_r2; HI f_simm16; - } fmt_26_ldh_d; - struct { /* e.g. ld24 $dr,$uimm24 */ + } fmt_27_ldh_d; + struct { /* e.g. ld $dr,@$sr+ */ + SI * f_r1; + SI * f_r2; + } fmt_28_ld_plus; + struct { /* e.g. ld24 $dr,#$uimm24 */ SI * f_r1; ADDR f_uimm24; - } fmt_27_ld24; - struct { /* e.g. ldi $dr,$simm8 */ + } fmt_29_ld24; + struct { /* e.g. ldi $dr,#$simm8 */ SI * f_r1; SI f_simm8; - } fmt_28_ldi8; + } fmt_30_ldi8; struct { /* e.g. ldi $dr,$slo16 */ SI * f_r1; HI f_simm16; - } fmt_29_ldi16; + } fmt_31_ldi16; + struct { /* e.g. lock $dr,@$sr */ + SI * f_r1; + SI * f_r2; + } fmt_32_lock; struct { /* e.g. machi $src1,$src2 */ SI * f_r1; SI * f_r2; - } fmt_30_machi; + } fmt_33_machi; + struct { /* e.g. mulhi $src1,$src2 */ + SI * f_r1; + SI * f_r2; + } fmt_34_mulhi; struct { /* e.g. mv $dr,$sr */ SI * f_r1; SI * f_r2; - } fmt_31_mv; + } fmt_35_mv; struct { /* e.g. mvfachi $dr */ SI * f_r1; - } fmt_32_mvfachi; + } fmt_36_mvfachi; struct { /* e.g. mvfc $dr,$scr */ SI * f_r1; UINT f_r2; - } fmt_33_mvfc; + } fmt_37_mvfc; struct { /* e.g. mvtachi $src1 */ SI * f_r1; - } fmt_34_mvtachi; + } fmt_38_mvtachi; struct { /* e.g. mvtc $sr,$dcr */ UINT f_r1; SI * f_r2; - } fmt_35_mvtc; + } fmt_39_mvtc; struct { /* e.g. nop */ int empty; - } fmt_36_nop; + } fmt_40_nop; struct { /* e.g. rac */ int empty; - } fmt_37_rac; - struct { /* e.g. seth $dr,$hi16 */ + } fmt_41_rac; + struct { /* e.g. rte */ + int empty; + } fmt_42_rte; + struct { /* e.g. seth $dr,#$hi16 */ SI * f_r1; UHI f_hi16; - } fmt_38_seth; - struct { /* e.g. slli $dr,$uimm5 */ + } fmt_43_seth; + struct { /* e.g. sll3 $dr,$sr,#$simm16 */ + SI * f_r1; + SI * f_r2; + SI f_simm16; + } fmt_44_sll3; + struct { /* e.g. slli $dr,#$uimm5 */ SI * f_r1; USI f_uimm5; - } fmt_39_slli; + } fmt_45_slli; + struct { /* e.g. st $src1,@$src2 */ + SI * f_r1; + SI * f_r2; + } fmt_46_st; struct { /* e.g. st $src1,@($slo16,$src2) */ SI * f_r1; SI * f_r2; HI f_simm16; - } fmt_40_st_d; - struct { /* e.g. trap $uimm4 */ + } fmt_47_st_d; + struct { /* e.g. stb $src1,@$src2 */ + SI * f_r1; + SI * f_r2; + } fmt_48_stb; + struct { /* e.g. stb $src1,@($slo16,$src2) */ + SI * f_r1; + SI * f_r2; + HI f_simm16; + } fmt_49_stb_d; + struct { /* e.g. sth $src1,@$src2 */ + SI * f_r1; + SI * f_r2; + } fmt_50_sth; + struct { /* e.g. sth $src1,@($slo16,$src2) */ + SI * f_r1; + SI * f_r2; + HI f_simm16; + } fmt_51_sth_d; + struct { /* e.g. st $src1,@+$src2 */ + SI * f_r1; + SI * f_r2; + } fmt_52_st_plus; + struct { /* e.g. trap #$uimm4 */ USI f_uimm4; - } fmt_41_trap; + } fmt_53_trap; + struct { /* e.g. unlock $src1,@$src2 */ + SI * f_r1; + SI * f_r2; + } fmt_54_unlock; } fields; #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/ unsigned long h_gr_get; @@ -272,8 +373,9 @@ struct argbuf { }; /* A cached insn. - This is also used in the non-scache case. In this situation we assume - the cache size is 1, and do a few things a little differently. */ + This is currently also used in the non-scache case. In this situation we + assume the cache size is 1, and do a few things a little differently. */ +/* FIXME: non-scache version to be redone. */ struct scache { IADDR next; @@ -282,12 +384,8 @@ struct scache { SEMANTIC_FN *sem_fn; #endif #if ! WITH_SEM_SWITCH_FAST -#if WITH_SCACHE - SEMANTIC_CACHE_FN *sem_fast_fn; -#else SEMANTIC_FN *sem_fast_fn; #endif -#endif #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST #ifdef __GNUC__ void *sem_case; @@ -376,7 +474,21 @@ struct scache { f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \ -#define EXTRACT_FMT_5_ADDV3_VARS \ +#define EXTRACT_FMT_5_ADDV_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_5_ADDV_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_6_ADDV3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -384,7 +496,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_5_ADDV3_CODE \ +#define EXTRACT_FMT_6_ADDV3_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -392,45 +504,45 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_6_ADDX_VARS \ +#define EXTRACT_FMT_7_ADDX_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_6_ADDX_CODE \ +#define EXTRACT_FMT_7_ADDX_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_7_BC8_VARS \ +#define EXTRACT_FMT_8_BC8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_7_BC8_CODE \ +#define EXTRACT_FMT_8_BC8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_8_BC24_VARS \ +#define EXTRACT_FMT_9_BC24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_8_BC24_CODE \ +#define EXTRACT_FMT_9_BC24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_9_BEQ_VARS \ +#define EXTRACT_FMT_10_BEQ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -438,15 +550,15 @@ struct scache { UINT f_r2; \ int f_disp16; \ unsigned int length; -#define EXTRACT_FMT_9_BEQ_CODE \ +#define EXTRACT_FMT_10_BEQ_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ - f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \ + f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \ -#define EXTRACT_FMT_10_BEQZ_VARS \ +#define EXTRACT_FMT_11_BEQZ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -454,77 +566,77 @@ struct scache { UINT f_r2; \ int f_disp16; \ unsigned int length; -#define EXTRACT_FMT_10_BEQZ_CODE \ +#define EXTRACT_FMT_11_BEQZ_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ - f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \ + f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \ -#define EXTRACT_FMT_11_BL8_VARS \ +#define EXTRACT_FMT_12_BL8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_11_BL8_CODE \ +#define EXTRACT_FMT_12_BL8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_12_BL24_VARS \ +#define EXTRACT_FMT_13_BL24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_12_BL24_CODE \ +#define EXTRACT_FMT_13_BL24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_13_BRA8_VARS \ +#define EXTRACT_FMT_14_BRA8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_13_BRA8_CODE \ +#define EXTRACT_FMT_14_BRA8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_14_BRA24_VARS \ +#define EXTRACT_FMT_15_BRA24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_14_BRA24_CODE \ +#define EXTRACT_FMT_15_BRA24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_15_CMP_VARS \ +#define EXTRACT_FMT_16_CMP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_15_CMP_CODE \ +#define EXTRACT_FMT_16_CMP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_16_CMPI_VARS \ +#define EXTRACT_FMT_17_CMPI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -532,7 +644,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_16_CMPI_CODE \ +#define EXTRACT_FMT_17_CMPI_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -540,7 +652,7 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_17_CMPUI_VARS \ +#define EXTRACT_FMT_18_CMPUI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -548,7 +660,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_17_CMPUI_CODE \ +#define EXTRACT_FMT_18_CMPUI_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -556,7 +668,7 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_18_DIV_VARS \ +#define EXTRACT_FMT_19_DIV_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -564,7 +676,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_18_DIV_CODE \ +#define EXTRACT_FMT_19_DIV_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -572,49 +684,49 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_19_JL_VARS \ +#define EXTRACT_FMT_20_JL_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_19_JL_CODE \ +#define EXTRACT_FMT_20_JL_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_20_JMP_VARS \ +#define EXTRACT_FMT_21_JMP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_20_JMP_CODE \ +#define EXTRACT_FMT_21_JMP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_21_LD_VARS \ +#define EXTRACT_FMT_22_LD_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_21_LD_CODE \ +#define EXTRACT_FMT_22_LD_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_22_LD_D_VARS \ +#define EXTRACT_FMT_23_LD_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -622,7 +734,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_22_LD_D_CODE \ +#define EXTRACT_FMT_23_LD_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -630,21 +742,21 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_23_LDB_VARS \ +#define EXTRACT_FMT_24_LDB_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_23_LDB_CODE \ +#define EXTRACT_FMT_24_LDB_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_24_LDB_D_VARS \ +#define EXTRACT_FMT_25_LDB_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -652,7 +764,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_24_LDB_D_CODE \ +#define EXTRACT_FMT_25_LDB_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -660,21 +772,21 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_25_LDH_VARS \ +#define EXTRACT_FMT_26_LDH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_25_LDH_CODE \ +#define EXTRACT_FMT_26_LDH_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_26_LDH_D_VARS \ +#define EXTRACT_FMT_27_LDH_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -682,7 +794,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_26_LDH_D_CODE \ +#define EXTRACT_FMT_27_LDH_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -690,31 +802,45 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_27_LD24_VARS \ +#define EXTRACT_FMT_28_LD_PLUS_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_28_LD_PLUS_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_29_LD24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_uimm24; \ unsigned int length; -#define EXTRACT_FMT_27_LD24_CODE \ +#define EXTRACT_FMT_29_LD24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \ -#define EXTRACT_FMT_28_LDI8_VARS \ +#define EXTRACT_FMT_30_LDI8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_simm8; \ unsigned int length; -#define EXTRACT_FMT_28_LDI8_CODE \ +#define EXTRACT_FMT_30_LDI8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \ -#define EXTRACT_FMT_29_LDI16_VARS \ +#define EXTRACT_FMT_31_LDI16_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -722,7 +848,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_29_LDI16_CODE \ +#define EXTRACT_FMT_31_LDI16_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -730,119 +856,161 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_30_MACHI_VARS \ +#define EXTRACT_FMT_32_LOCK_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_32_LOCK_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_33_MACHI_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_33_MACHI_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_34_MULHI_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_34_MULHI_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_35_MV_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_30_MACHI_CODE \ +#define EXTRACT_FMT_35_MV_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_31_MV_VARS \ +#define EXTRACT_FMT_36_MVFACHI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_31_MV_CODE \ +#define EXTRACT_FMT_36_MVFACHI_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_32_MVFACHI_VARS \ +#define EXTRACT_FMT_37_MVFC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_32_MVFACHI_CODE \ +#define EXTRACT_FMT_37_MVFC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_33_MVFC_VARS \ +#define EXTRACT_FMT_38_MVTACHI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_33_MVFC_CODE \ +#define EXTRACT_FMT_38_MVTACHI_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_34_MVTACHI_VARS \ +#define EXTRACT_FMT_39_MVTC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_34_MVTACHI_CODE \ +#define EXTRACT_FMT_39_MVTC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_35_MVTC_VARS \ +#define EXTRACT_FMT_40_NOP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_35_MVTC_CODE \ +#define EXTRACT_FMT_40_NOP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_36_NOP_VARS \ +#define EXTRACT_FMT_41_RAC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_36_NOP_CODE \ +#define EXTRACT_FMT_41_RAC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_37_RAC_VARS \ +#define EXTRACT_FMT_42_RTE_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_37_RAC_CODE \ +#define EXTRACT_FMT_42_RTE_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_38_SETH_VARS \ +#define EXTRACT_FMT_43_SETH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -850,7 +1018,7 @@ struct scache { UINT f_r2; \ UINT f_hi16; \ unsigned int length; -#define EXTRACT_FMT_38_SETH_CODE \ +#define EXTRACT_FMT_43_SETH_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -858,21 +1026,51 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_39_SLLI_VARS \ +#define EXTRACT_FMT_44_SLL3_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + int f_simm16; \ + unsigned int length; +#define EXTRACT_FMT_44_SLL3_CODE \ + length = 4; \ + f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ + +#define EXTRACT_FMT_45_SLLI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_shift_op2; \ UINT f_uimm5; \ unsigned int length; -#define EXTRACT_FMT_39_SLLI_CODE \ +#define EXTRACT_FMT_45_SLLI_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \ f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \ -#define EXTRACT_FMT_40_ST_D_VARS \ +#define EXTRACT_FMT_46_ST_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_46_ST_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_47_ST_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -880,7 +1078,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_40_ST_D_CODE \ +#define EXTRACT_FMT_47_ST_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -888,18 +1086,106 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_41_TRAP_VARS \ +#define EXTRACT_FMT_48_STB_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_48_STB_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_49_STB_D_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + int f_simm16; \ + unsigned int length; +#define EXTRACT_FMT_49_STB_D_CODE \ + length = 4; \ + f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ + +#define EXTRACT_FMT_50_STH_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_50_STH_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_51_STH_D_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + int f_simm16; \ + unsigned int length; +#define EXTRACT_FMT_51_STH_D_CODE \ + length = 4; \ + f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ + +#define EXTRACT_FMT_52_ST_PLUS_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_52_ST_PLUS_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_53_TRAP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_uimm4; \ unsigned int length; -#define EXTRACT_FMT_41_TRAP_CODE \ +#define EXTRACT_FMT_53_TRAP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ +#define EXTRACT_FMT_54_UNLOCK_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_54_UNLOCK_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + #endif /* CPU_M32R_H */ diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h index 49e887d..366eec5 100644 --- a/sim/m32r/cpux.h +++ b/sim/m32r/cpux.h @@ -45,7 +45,7 @@ typedef struct { #define GET_H_GR(a1) CPU (h_gr)[a1] #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) /* control registers */ - SI h_cr[7]; + USI h_cr[7]; #define GET_H_CR(a1) CPU (h_cr)[a1] #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) /* accumulator */ @@ -92,6 +92,10 @@ typedef struct { SI h_bpc; #define GET_H_BPC() CPU (h_bpc) #define SET_H_BPC(x) (CPU (h_bpc) = (x)) + /* lock */ + UBI h_lock; +#define GET_H_LOCK() CPU (h_lock) +#define SET_H_LOCK(x) (CPU (h_lock) = (x)) } hardware; #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) /* CPU profiling state information. */ @@ -102,6 +106,34 @@ typedef struct { #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile) } M32RX_CPU_DATA; +USI m32rx_h_pc_get (SIM_CPU *); +void m32rx_h_pc_set (SIM_CPU *, USI); +SI m32rx_h_gr_get (SIM_CPU *, UINT); +void m32rx_h_gr_set (SIM_CPU *, UINT, SI); +USI m32rx_h_cr_get (SIM_CPU *, UINT); +void m32rx_h_cr_set (SIM_CPU *, UINT, USI); +DI m32rx_h_accum_get (SIM_CPU *); +void m32rx_h_accum_set (SIM_CPU *, DI); +DI m32rx_h_accums_get (SIM_CPU *, UINT); +void m32rx_h_accums_set (SIM_CPU *, UINT, DI); +UBI m32rx_h_abort_get (SIM_CPU *); +void m32rx_h_abort_set (SIM_CPU *, UBI); +UBI m32rx_h_cond_get (SIM_CPU *); +void m32rx_h_cond_set (SIM_CPU *, UBI); +UBI m32rx_h_sm_get (SIM_CPU *); +void m32rx_h_sm_set (SIM_CPU *, UBI); +UBI m32rx_h_bsm_get (SIM_CPU *); +void m32rx_h_bsm_set (SIM_CPU *, UBI); +UBI m32rx_h_ie_get (SIM_CPU *); +void m32rx_h_ie_set (SIM_CPU *, UBI); +UBI m32rx_h_bie_get (SIM_CPU *); +void m32rx_h_bie_set (SIM_CPU *, UBI); +UBI m32rx_h_bcond_get (SIM_CPU *); +void m32rx_h_bcond_set (SIM_CPU *, UBI); +SI m32rx_h_bpc_get (SIM_CPU *); +void m32rx_h_bpc_set (SIM_CPU *, SI); +UBI m32rx_h_lock_get (SIM_CPU *); +void m32rx_h_lock_set (SIM_CPU *, UBI); extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t); /* The ARGBUF struct. */ @@ -138,201 +170,245 @@ struct argbuf { UINT f_r1; SI f_simm8; } fmt_4_addi; + struct { /* e.g. addv $dr,$sr */ + UINT f_r1; + UINT f_r2; + } fmt_5_addv; struct { /* e.g. addv3 $dr,$sr,#$simm16 */ UINT f_r1; UINT f_r2; SI f_simm16; - } fmt_5_addv3; + } fmt_6_addv3; struct { /* e.g. addx $dr,$sr */ UINT f_r1; UINT f_r2; - } fmt_6_addx; + } fmt_7_addx; struct { /* e.g. bc $disp8 */ IADDR f_disp8; - } fmt_7_bc8; + } fmt_8_bc8; struct { /* e.g. bc $disp24 */ IADDR f_disp24; - } fmt_8_bc24; + } fmt_9_bc24; struct { /* e.g. beq $src1,$src2,$disp16 */ UINT f_r1; UINT f_r2; IADDR f_disp16; - } fmt_9_beq; + } fmt_10_beq; struct { /* e.g. beqz $src2,$disp16 */ UINT f_r2; IADDR f_disp16; - } fmt_10_beqz; + } fmt_11_beqz; struct { /* e.g. bl $disp8 */ IADDR f_disp8; - } fmt_11_bl8; + } fmt_12_bl8; struct { /* e.g. bl $disp24 */ IADDR f_disp24; - } fmt_12_bl24; + } fmt_13_bl24; struct { /* e.g. bcl $disp8 */ IADDR f_disp8; - } fmt_13_bcl8; + } fmt_14_bcl8; struct { /* e.g. bcl $disp24 */ IADDR f_disp24; - } fmt_14_bcl24; + } fmt_15_bcl24; struct { /* e.g. bra $disp8 */ IADDR f_disp8; - } fmt_15_bra8; + } fmt_16_bra8; struct { /* e.g. bra $disp24 */ IADDR f_disp24; - } fmt_16_bra24; + } fmt_17_bra24; struct { /* e.g. cmp $src1,$src2 */ UINT f_r1; UINT f_r2; - } fmt_17_cmp; + } fmt_18_cmp; struct { /* e.g. cmpi $src2,#$simm16 */ UINT f_r2; SI f_simm16; - } fmt_18_cmpi; + } fmt_19_cmpi; struct { /* e.g. cmpui $src2,#$uimm16 */ UINT f_r2; USI f_uimm16; - } fmt_19_cmpui; + } fmt_20_cmpui; struct { /* e.g. cmpz $src2 */ UINT f_r2; - } fmt_20_cmpz; + } fmt_21_cmpz; struct { /* e.g. div $dr,$sr */ UINT f_r1; UINT f_r2; - } fmt_21_div; + } fmt_22_div; struct { /* e.g. jc $sr */ UINT f_r2; - } fmt_22_jc; + } fmt_23_jc; struct { /* e.g. jl $sr */ UINT f_r2; - } fmt_23_jl; + } fmt_24_jl; struct { /* e.g. jmp $sr */ UINT f_r2; - } fmt_24_jmp; + } fmt_25_jmp; struct { /* e.g. ld $dr,@$sr */ UINT f_r1; UINT f_r2; - } fmt_25_ld; + } fmt_26_ld; struct { /* e.g. ld $dr,@($slo16,$sr) */ UINT f_r1; UINT f_r2; HI f_simm16; - } fmt_26_ld_d; + } fmt_27_ld_d; struct { /* e.g. ldb $dr,@$sr */ UINT f_r1; UINT f_r2; - } fmt_27_ldb; + } fmt_28_ldb; struct { /* e.g. ldb $dr,@($slo16,$sr) */ UINT f_r1; UINT f_r2; HI f_simm16; - } fmt_28_ldb_d; + } fmt_29_ldb_d; struct { /* e.g. ldh $dr,@$sr */ UINT f_r1; UINT f_r2; - } fmt_29_ldh; + } fmt_30_ldh; struct { /* e.g. ldh $dr,@($slo16,$sr) */ UINT f_r1; UINT f_r2; HI f_simm16; - } fmt_30_ldh_d; + } fmt_31_ldh_d; + struct { /* e.g. ld $dr,@$sr+ */ + UINT f_r1; + UINT f_r2; + } fmt_32_ld_plus; struct { /* e.g. ld24 $dr,#$uimm24 */ UINT f_r1; ADDR f_uimm24; - } fmt_31_ld24; + } fmt_33_ld24; struct { /* e.g. ldi $dr,#$simm8 */ UINT f_r1; SI f_simm8; - } fmt_32_ldi8; + } fmt_34_ldi8; struct { /* e.g. ldi $dr,$slo16 */ UINT f_r1; HI f_simm16; - } fmt_33_ldi16; + } fmt_35_ldi16; + struct { /* e.g. lock $dr,@$sr */ + UINT f_r1; + UINT f_r2; + } fmt_36_lock; struct { /* e.g. machi $src1,$src2,$acc */ UINT f_r1; UINT f_acc; UINT f_r2; - } fmt_34_machi_a; + } fmt_37_machi_a; struct { /* e.g. mulhi $src1,$src2,$acc */ UINT f_r1; UINT f_acc; UINT f_r2; - } fmt_35_mulhi_a; + } fmt_38_mulhi_a; struct { /* e.g. mv $dr,$sr */ UINT f_r1; UINT f_r2; - } fmt_36_mv; + } fmt_39_mv; struct { /* e.g. mvfachi $dr,$accs */ UINT f_r1; UINT f_accs; - } fmt_37_mvfachi_a; + } fmt_40_mvfachi_a; struct { /* e.g. mvfc $dr,$scr */ UINT f_r1; UINT f_r2; - } fmt_38_mvfc; + } fmt_41_mvfc; struct { /* e.g. mvtachi $src1,$accs */ UINT f_r1; UINT f_accs; - } fmt_39_mvtachi_a; + } fmt_42_mvtachi_a; struct { /* e.g. mvtc $sr,$dcr */ UINT f_r1; UINT f_r2; - } fmt_40_mvtc; + } fmt_43_mvtc; struct { /* e.g. nop */ int empty; - } fmt_41_nop; - struct { /* e.g. rac $accd */ - UINT f_accd; - } fmt_42_rac_d; - struct { /* e.g. rac $accd,$accs */ - UINT f_accd; - UINT f_accs; - } fmt_43_rac_ds; + } fmt_44_nop; struct { /* e.g. rac $accd,$accs,#$imm1 */ UINT f_accd; UINT f_accs; USI f_imm1; - } fmt_44_rac_dsi; + } fmt_45_rac_dsi; struct { /* e.g. rte */ int empty; - } fmt_45_rte; + } fmt_46_rte; struct { /* e.g. seth $dr,#$hi16 */ UINT f_r1; UHI f_hi16; - } fmt_46_seth; + } fmt_47_seth; + struct { /* e.g. sll3 $dr,$sr,#$simm16 */ + UINT f_r1; + UINT f_r2; + SI f_simm16; + } fmt_48_sll3; struct { /* e.g. slli $dr,#$uimm5 */ UINT f_r1; USI f_uimm5; - } fmt_47_slli; + } fmt_49_slli; + struct { /* e.g. st $src1,@$src2 */ + UINT f_r1; + UINT f_r2; + } fmt_50_st; struct { /* e.g. st $src1,@($slo16,$src2) */ UINT f_r1; UINT f_r2; HI f_simm16; - } fmt_48_st_d; + } fmt_51_st_d; + struct { /* e.g. stb $src1,@$src2 */ + UINT f_r1; + UINT f_r2; + } fmt_52_stb; + struct { /* e.g. stb $src1,@($slo16,$src2) */ + UINT f_r1; + UINT f_r2; + HI f_simm16; + } fmt_53_stb_d; + struct { /* e.g. sth $src1,@$src2 */ + UINT f_r1; + UINT f_r2; + } fmt_54_sth; + struct { /* e.g. sth $src1,@($slo16,$src2) */ + UINT f_r1; + UINT f_r2; + HI f_simm16; + } fmt_55_sth_d; + struct { /* e.g. st $src1,@+$src2 */ + UINT f_r1; + UINT f_r2; + } fmt_56_st_plus; struct { /* e.g. trap #$uimm4 */ USI f_uimm4; - } fmt_49_trap; - struct { /* e.g. satb $dr,$src2 */ + } fmt_57_trap; + struct { /* e.g. unlock $src1,@$src2 */ UINT f_r1; UINT f_r2; - } fmt_50_satb; - struct { /* e.g. sat $dr,$src2 */ + } fmt_58_unlock; + struct { /* e.g. satb $dr,$sr */ UINT f_r1; UINT f_r2; - } fmt_51_sat; + } fmt_59_satb; + struct { /* e.g. sat $dr,$sr */ + UINT f_r1; + UINT f_r2; + } fmt_60_sat; struct { /* e.g. sadd */ int empty; - } fmt_52_sadd; + } fmt_61_sadd; struct { /* e.g. macwu1 $src1,$src2 */ UINT f_r1; UINT f_r2; - } fmt_53_macwu1; + } fmt_62_macwu1; struct { /* e.g. msblo $src1,$src2 */ UINT f_r1; UINT f_r2; - } fmt_54_msblo; + } fmt_63_msblo; + struct { /* e.g. mulwu1 $src1,$src2 */ + UINT f_r1; + UINT f_r2; + } fmt_64_mulwu1; struct { /* e.g. sc */ int empty; - } fmt_55_sc; + } fmt_65_sc; } fields; #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/ unsigned long h_gr_get; @@ -341,8 +417,9 @@ struct argbuf { }; /* A cached insn. - This is also used in the non-scache case. In this situation we assume - the cache size is 1, and do a few things a little differently. */ + This is currently also used in the non-scache case. In this situation we + assume the cache size is 1, and do a few things a little differently. */ +/* FIXME: non-scache version to be redone. */ struct scache { IADDR next; @@ -351,12 +428,8 @@ struct scache { SEMANTIC_FN *sem_fn; #endif #if ! WITH_SEM_SWITCH_FAST -#if WITH_SCACHE - SEMANTIC_CACHE_FN *sem_fast_fn; -#else SEMANTIC_FN *sem_fast_fn; #endif -#endif #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST #ifdef __GNUC__ void *sem_case; @@ -445,7 +518,21 @@ struct scache { f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \ -#define EXTRACT_FMT_5_ADDV3_VARS \ +#define EXTRACT_FMT_5_ADDV_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_5_ADDV_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_6_ADDV3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -453,7 +540,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_5_ADDV3_CODE \ +#define EXTRACT_FMT_6_ADDV3_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -461,45 +548,45 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_6_ADDX_VARS \ +#define EXTRACT_FMT_7_ADDX_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_6_ADDX_CODE \ +#define EXTRACT_FMT_7_ADDX_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_7_BC8_VARS \ +#define EXTRACT_FMT_8_BC8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_7_BC8_CODE \ +#define EXTRACT_FMT_8_BC8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_8_BC24_VARS \ +#define EXTRACT_FMT_9_BC24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_8_BC24_CODE \ +#define EXTRACT_FMT_9_BC24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_9_BEQ_VARS \ +#define EXTRACT_FMT_10_BEQ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -507,15 +594,15 @@ struct scache { UINT f_r2; \ int f_disp16; \ unsigned int length; -#define EXTRACT_FMT_9_BEQ_CODE \ +#define EXTRACT_FMT_10_BEQ_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ - f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \ + f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \ -#define EXTRACT_FMT_10_BEQZ_VARS \ +#define EXTRACT_FMT_11_BEQZ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -523,101 +610,101 @@ struct scache { UINT f_r2; \ int f_disp16; \ unsigned int length; -#define EXTRACT_FMT_10_BEQZ_CODE \ +#define EXTRACT_FMT_11_BEQZ_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ - f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \ + f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \ -#define EXTRACT_FMT_11_BL8_VARS \ +#define EXTRACT_FMT_12_BL8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_11_BL8_CODE \ +#define EXTRACT_FMT_12_BL8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_12_BL24_VARS \ +#define EXTRACT_FMT_13_BL24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_12_BL24_CODE \ +#define EXTRACT_FMT_13_BL24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_13_BCL8_VARS \ +#define EXTRACT_FMT_14_BCL8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_13_BCL8_CODE \ +#define EXTRACT_FMT_14_BCL8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_14_BCL24_VARS \ +#define EXTRACT_FMT_15_BCL24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_14_BCL24_CODE \ +#define EXTRACT_FMT_15_BCL24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_15_BRA8_VARS \ +#define EXTRACT_FMT_16_BRA8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp8; \ unsigned int length; -#define EXTRACT_FMT_15_BRA8_CODE \ +#define EXTRACT_FMT_16_BRA8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \ + f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \ -#define EXTRACT_FMT_16_BRA24_VARS \ +#define EXTRACT_FMT_17_BRA24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_disp24; \ unsigned int length; -#define EXTRACT_FMT_16_BRA24_CODE \ +#define EXTRACT_FMT_17_BRA24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ - f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \ + f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \ -#define EXTRACT_FMT_17_CMP_VARS \ +#define EXTRACT_FMT_18_CMP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_17_CMP_CODE \ +#define EXTRACT_FMT_18_CMP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_18_CMPI_VARS \ +#define EXTRACT_FMT_19_CMPI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -625,7 +712,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_18_CMPI_CODE \ +#define EXTRACT_FMT_19_CMPI_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -633,7 +720,7 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_19_CMPUI_VARS \ +#define EXTRACT_FMT_20_CMPUI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -641,7 +728,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_19_CMPUI_CODE \ +#define EXTRACT_FMT_20_CMPUI_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -649,21 +736,21 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_20_CMPZ_VARS \ +#define EXTRACT_FMT_21_CMPZ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_20_CMPZ_CODE \ +#define EXTRACT_FMT_21_CMPZ_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_21_DIV_VARS \ +#define EXTRACT_FMT_22_DIV_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -671,7 +758,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_21_DIV_CODE \ +#define EXTRACT_FMT_22_DIV_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -679,63 +766,63 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_22_JC_VARS \ +#define EXTRACT_FMT_23_JC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_22_JC_CODE \ +#define EXTRACT_FMT_23_JC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_23_JL_VARS \ +#define EXTRACT_FMT_24_JL_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_23_JL_CODE \ +#define EXTRACT_FMT_24_JL_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_24_JMP_VARS \ +#define EXTRACT_FMT_25_JMP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_24_JMP_CODE \ +#define EXTRACT_FMT_25_JMP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_25_LD_VARS \ +#define EXTRACT_FMT_26_LD_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_25_LD_CODE \ +#define EXTRACT_FMT_26_LD_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_26_LD_D_VARS \ +#define EXTRACT_FMT_27_LD_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -743,7 +830,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_26_LD_D_CODE \ +#define EXTRACT_FMT_27_LD_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -751,21 +838,21 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_27_LDB_VARS \ +#define EXTRACT_FMT_28_LDB_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_27_LDB_CODE \ +#define EXTRACT_FMT_28_LDB_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_28_LDB_D_VARS \ +#define EXTRACT_FMT_29_LDB_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -773,7 +860,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_28_LDB_D_CODE \ +#define EXTRACT_FMT_29_LDB_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -781,21 +868,21 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_29_LDH_VARS \ +#define EXTRACT_FMT_30_LDH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_29_LDH_CODE \ +#define EXTRACT_FMT_30_LDH_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_30_LDH_D_VARS \ +#define EXTRACT_FMT_31_LDH_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -803,7 +890,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_30_LDH_D_CODE \ +#define EXTRACT_FMT_31_LDH_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -811,31 +898,45 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_31_LD24_VARS \ +#define EXTRACT_FMT_32_LD_PLUS_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_32_LD_PLUS_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_33_LD24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_uimm24; \ unsigned int length; -#define EXTRACT_FMT_31_LD24_CODE \ +#define EXTRACT_FMT_33_LD24_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \ -#define EXTRACT_FMT_32_LDI8_VARS \ +#define EXTRACT_FMT_34_LDI8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ int f_simm8; \ unsigned int length; -#define EXTRACT_FMT_32_LDI8_CODE \ +#define EXTRACT_FMT_34_LDI8_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \ -#define EXTRACT_FMT_33_LDI16_VARS \ +#define EXTRACT_FMT_35_LDI16_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -843,7 +944,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_33_LDI16_CODE \ +#define EXTRACT_FMT_35_LDI16_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -851,7 +952,21 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_34_MACHI_A_VARS \ +#define EXTRACT_FMT_36_LOCK_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_36_LOCK_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_37_MACHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -859,7 +974,7 @@ struct scache { UINT f_op23; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_34_MACHI_A_CODE \ +#define EXTRACT_FMT_37_MACHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ @@ -867,7 +982,7 @@ struct scache { f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_35_MULHI_A_VARS \ +#define EXTRACT_FMT_38_MULHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -875,7 +990,7 @@ struct scache { UINT f_op23; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_35_MULHI_A_CODE \ +#define EXTRACT_FMT_38_MULHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ @@ -883,21 +998,21 @@ struct scache { f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_36_MV_VARS \ +#define EXTRACT_FMT_39_MV_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_36_MV_CODE \ +#define EXTRACT_FMT_39_MV_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_37_MVFACHI_A_VARS \ +#define EXTRACT_FMT_40_MVFACHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -905,7 +1020,7 @@ struct scache { UINT f_accs; \ UINT f_op3; \ unsigned int length; -#define EXTRACT_FMT_37_MVFACHI_A_CODE \ +#define EXTRACT_FMT_40_MVFACHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ @@ -913,21 +1028,21 @@ struct scache { f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \ f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \ -#define EXTRACT_FMT_38_MVFC_VARS \ +#define EXTRACT_FMT_41_MVFC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_38_MVFC_CODE \ +#define EXTRACT_FMT_41_MVFC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_39_MVTACHI_A_VARS \ +#define EXTRACT_FMT_42_MVTACHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -935,7 +1050,7 @@ struct scache { UINT f_accs; \ UINT f_op3; \ unsigned int length; -#define EXTRACT_FMT_39_MVTACHI_A_CODE \ +#define EXTRACT_FMT_42_MVTACHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ @@ -943,35 +1058,35 @@ struct scache { f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \ f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \ -#define EXTRACT_FMT_40_MVTC_VARS \ +#define EXTRACT_FMT_43_MVTC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_40_MVTC_CODE \ +#define EXTRACT_FMT_43_MVTC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_41_NOP_VARS \ +#define EXTRACT_FMT_44_NOP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_41_NOP_CODE \ +#define EXTRACT_FMT_44_NOP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_42_RAC_D_VARS \ +#define EXTRACT_FMT_45_RAC_DSI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_accd; \ @@ -981,7 +1096,7 @@ struct scache { UINT f_bit14; \ UINT f_imm1; \ unsigned int length; -#define EXTRACT_FMT_42_RAC_D_CODE \ +#define EXTRACT_FMT_45_RAC_DSI_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \ @@ -989,93 +1104,143 @@ struct scache { f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \ f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \ - f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \ + f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \ -#define EXTRACT_FMT_43_RAC_DS_VARS \ +#define EXTRACT_FMT_46_RTE_VARS \ /* Instruction fields. */ \ UINT f_op1; \ - UINT f_accd; \ - UINT f_bits67; \ + UINT f_r1; \ UINT f_op2; \ - UINT f_accs; \ - UINT f_bit14; \ - UINT f_imm1; \ + UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_43_RAC_DS_CODE \ +#define EXTRACT_FMT_46_RTE_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ - f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \ - f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ - f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \ - f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \ - f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_44_RAC_DSI_VARS \ +#define EXTRACT_FMT_47_SETH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ - UINT f_accd; \ - UINT f_bits67; \ + UINT f_r1; \ UINT f_op2; \ - UINT f_accs; \ - UINT f_bit14; \ - UINT f_imm1; \ + UINT f_r2; \ + UINT f_hi16; \ + unsigned int length; +#define EXTRACT_FMT_47_SETH_CODE \ + length = 4; \ + f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ + f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ + +#define EXTRACT_FMT_48_SLL3_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_44_RAC_DSI_CODE \ +#define EXTRACT_FMT_48_SLL3_CODE \ + length = 4; \ + f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ + +#define EXTRACT_FMT_49_SLLI_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_shift_op2; \ + UINT f_uimm5; \ + unsigned int length; +#define EXTRACT_FMT_49_SLLI_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ - f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \ - f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \ + f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \ + +#define EXTRACT_FMT_50_ST_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_50_ST_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ - f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \ - f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \ - f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_45_RTE_VARS \ +#define EXTRACT_FMT_51_ST_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ + int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_45_RTE_CODE \ +#define EXTRACT_FMT_51_ST_D_CODE \ + length = 4; \ + f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ + +#define EXTRACT_FMT_52_STB_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_52_STB_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_46_SETH_VARS \ +#define EXTRACT_FMT_53_STB_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ - UINT f_hi16; \ + int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_46_SETH_CODE \ +#define EXTRACT_FMT_53_STB_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ - f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ + f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_47_SLLI_VARS \ +#define EXTRACT_FMT_54_STH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - UINT f_shift_op2; \ - UINT f_uimm5; \ + UINT f_op2; \ + UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_47_SLLI_CODE \ +#define EXTRACT_FMT_54_STH_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ - f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \ - f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_48_ST_D_VARS \ +#define EXTRACT_FMT_55_STH_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1083,7 +1248,7 @@ struct scache { UINT f_r2; \ int f_simm16; \ unsigned int length; -#define EXTRACT_FMT_48_ST_D_CODE \ +#define EXTRACT_FMT_55_STH_D_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -1091,21 +1256,49 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_49_TRAP_VARS \ +#define EXTRACT_FMT_56_ST_PLUS_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_56_ST_PLUS_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_57_TRAP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_uimm4; \ unsigned int length; -#define EXTRACT_FMT_49_TRAP_CODE \ +#define EXTRACT_FMT_57_TRAP_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_50_SATB_VARS \ +#define EXTRACT_FMT_58_UNLOCK_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_58_UNLOCK_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_59_SATB_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1113,7 +1306,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_50_SATB_CODE \ +#define EXTRACT_FMT_59_SATB_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -1121,7 +1314,7 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_51_SAT_VARS \ +#define EXTRACT_FMT_60_SAT_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1129,7 +1322,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_51_SAT_CODE \ +#define EXTRACT_FMT_60_SAT_CODE \ length = 4; \ f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \ @@ -1137,56 +1330,70 @@ struct scache { f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \ -#define EXTRACT_FMT_52_SADD_VARS \ +#define EXTRACT_FMT_61_SADD_VARS \ + /* Instruction fields. */ \ + UINT f_op1; \ + UINT f_r1; \ + UINT f_op2; \ + UINT f_r2; \ + unsigned int length; +#define EXTRACT_FMT_61_SADD_CODE \ + length = 2; \ + f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ + f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ + f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ + f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ + +#define EXTRACT_FMT_62_MACWU1_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_52_SADD_CODE \ +#define EXTRACT_FMT_62_MACWU1_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_53_MACWU1_VARS \ +#define EXTRACT_FMT_63_MSBLO_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_53_MACWU1_CODE \ +#define EXTRACT_FMT_63_MSBLO_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_54_MSBLO_VARS \ +#define EXTRACT_FMT_64_MULWU1_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_54_MSBLO_CODE \ +#define EXTRACT_FMT_64_MULWU1_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \ f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \ -#define EXTRACT_FMT_55_SC_VARS \ +#define EXTRACT_FMT_65_SC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_55_SC_CODE \ +#define EXTRACT_FMT_65_SC_CODE \ length = 2; \ f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \ f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \ @@ -1217,205 +1424,252 @@ struct parexec { SI dr; SI simm8; } fmt_4_addi; + struct { /* e.g. addv $dr,$sr */ + SI dr; + SI sr; + } fmt_5_addv; struct { /* e.g. addv3 $dr,$sr,#$simm16 */ SI simm16; SI sr; - } fmt_5_addv3; + } fmt_6_addv3; struct { /* e.g. addx $dr,$sr */ UBI condbit; SI dr; SI sr; - } fmt_6_addx; + } fmt_7_addx; struct { /* e.g. bc $disp8 */ UBI condbit; IADDR disp8; - } fmt_7_bc8; + } fmt_8_bc8; struct { /* e.g. bc $disp24 */ UBI condbit; IADDR disp24; - } fmt_8_bc24; + } fmt_9_bc24; struct { /* e.g. beq $src1,$src2,$disp16 */ IADDR disp16; SI src1; SI src2; - } fmt_9_beq; + } fmt_10_beq; struct { /* e.g. beqz $src2,$disp16 */ IADDR disp16; SI src2; - } fmt_10_beqz; + } fmt_11_beqz; struct { /* e.g. bl $disp8 */ IADDR disp8; USI pc; - } fmt_11_bl8; + } fmt_12_bl8; struct { /* e.g. bl $disp24 */ IADDR disp24; USI pc; - } fmt_12_bl24; + } fmt_13_bl24; struct { /* e.g. bcl $disp8 */ UBI condbit; IADDR disp8; USI pc; - } fmt_13_bcl8; + } fmt_14_bcl8; struct { /* e.g. bcl $disp24 */ UBI condbit; IADDR disp24; USI pc; - } fmt_14_bcl24; + } fmt_15_bcl24; struct { /* e.g. bra $disp8 */ IADDR disp8; - } fmt_15_bra8; + } fmt_16_bra8; struct { /* e.g. bra $disp24 */ IADDR disp24; - } fmt_16_bra24; + } fmt_17_bra24; struct { /* e.g. cmp $src1,$src2 */ SI src1; SI src2; - } fmt_17_cmp; + } fmt_18_cmp; struct { /* e.g. cmpi $src2,#$simm16 */ SI simm16; SI src2; - } fmt_18_cmpi; + } fmt_19_cmpi; struct { /* e.g. cmpui $src2,#$uimm16 */ SI src2; USI uimm16; - } fmt_19_cmpui; + } fmt_20_cmpui; struct { /* e.g. cmpz $src2 */ SI src2; - } fmt_20_cmpz; + } fmt_21_cmpz; struct { /* e.g. div $dr,$sr */ SI dr; SI sr; - } fmt_21_div; + } fmt_22_div; struct { /* e.g. jc $sr */ UBI condbit; SI sr; - } fmt_22_jc; + } fmt_23_jc; struct { /* e.g. jl $sr */ USI pc; SI sr; - } fmt_23_jl; + } fmt_24_jl; struct { /* e.g. jmp $sr */ SI sr; - } fmt_24_jmp; + } fmt_25_jmp; struct { /* e.g. ld $dr,@$sr */ UQI h_memory_sr; SI sr; - } fmt_25_ld; + } fmt_26_ld; struct { /* e.g. ld $dr,@($slo16,$sr) */ UQI h_memory_add_WI_sr_slo16; HI slo16; SI sr; - } fmt_26_ld_d; + } fmt_27_ld_d; struct { /* e.g. ldb $dr,@$sr */ UQI h_memory_sr; SI sr; - } fmt_27_ldb; + } fmt_28_ldb; struct { /* e.g. ldb $dr,@($slo16,$sr) */ UQI h_memory_add_WI_sr_slo16; HI slo16; SI sr; - } fmt_28_ldb_d; + } fmt_29_ldb_d; struct { /* e.g. ldh $dr,@$sr */ UQI h_memory_sr; SI sr; - } fmt_29_ldh; + } fmt_30_ldh; struct { /* e.g. ldh $dr,@($slo16,$sr) */ UQI h_memory_add_WI_sr_slo16; HI slo16; SI sr; - } fmt_30_ldh_d; + } fmt_31_ldh_d; + struct { /* e.g. ld $dr,@$sr+ */ + UQI h_memory_sr; + SI sr; + } fmt_32_ld_plus; struct { /* e.g. ld24 $dr,#$uimm24 */ ADDR uimm24; - } fmt_31_ld24; + } fmt_33_ld24; struct { /* e.g. ldi $dr,#$simm8 */ SI simm8; - } fmt_32_ldi8; + } fmt_34_ldi8; struct { /* e.g. ldi $dr,$slo16 */ HI slo16; - } fmt_33_ldi16; + } fmt_35_ldi16; + struct { /* e.g. lock $dr,@$sr */ + UQI h_memory_sr; + SI sr; + } fmt_36_lock; struct { /* e.g. machi $src1,$src2,$acc */ DI acc; SI src1; SI src2; - } fmt_34_machi_a; + } fmt_37_machi_a; struct { /* e.g. mulhi $src1,$src2,$acc */ SI src1; SI src2; - } fmt_35_mulhi_a; + } fmt_38_mulhi_a; struct { /* e.g. mv $dr,$sr */ SI sr; - } fmt_36_mv; + } fmt_39_mv; struct { /* e.g. mvfachi $dr,$accs */ DI accs; - } fmt_37_mvfachi_a; + } fmt_40_mvfachi_a; struct { /* e.g. mvfc $dr,$scr */ - SI scr; - } fmt_38_mvfc; + USI scr; + } fmt_41_mvfc; struct { /* e.g. mvtachi $src1,$accs */ DI accs; SI src1; - } fmt_39_mvtachi_a; + } fmt_42_mvtachi_a; struct { /* e.g. mvtc $sr,$dcr */ SI sr; - } fmt_40_mvtc; + } fmt_43_mvtc; struct { /* e.g. nop */ int empty; - } fmt_41_nop; - struct { /* e.g. rac $accd */ - DI accum; - } fmt_42_rac_d; - struct { /* e.g. rac $accd,$accs */ - DI accs; - } fmt_43_rac_ds; + } fmt_44_nop; struct { /* e.g. rac $accd,$accs,#$imm1 */ DI accs; USI imm1; - } fmt_44_rac_dsi; + } fmt_45_rac_dsi; struct { /* e.g. rte */ UBI h_bcond_0; UBI h_bie_0; SI h_bpc_0; UBI h_bsm_0; - } fmt_45_rte; + } fmt_46_rte; struct { /* e.g. seth $dr,#$hi16 */ UHI hi16; - } fmt_46_seth; + } fmt_47_seth; + struct { /* e.g. sll3 $dr,$sr,#$simm16 */ + SI simm16; + SI sr; + } fmt_48_sll3; struct { /* e.g. slli $dr,#$uimm5 */ SI dr; USI uimm5; - } fmt_47_slli; + } fmt_49_slli; + struct { /* e.g. st $src1,@$src2 */ + SI src1; + SI src2; + } fmt_50_st; struct { /* e.g. st $src1,@($slo16,$src2) */ HI slo16; SI src1; SI src2; - } fmt_48_st_d; + } fmt_51_st_d; + struct { /* e.g. stb $src1,@$src2 */ + SI src1; + SI src2; + } fmt_52_stb; + struct { /* e.g. stb $src1,@($slo16,$src2) */ + HI slo16; + SI src1; + SI src2; + } fmt_53_stb_d; + struct { /* e.g. sth $src1,@$src2 */ + SI src1; + SI src2; + } fmt_54_sth; + struct { /* e.g. sth $src1,@($slo16,$src2) */ + HI slo16; + SI src1; + SI src2; + } fmt_55_sth_d; + struct { /* e.g. st $src1,@+$src2 */ + SI src1; + SI src2; + } fmt_56_st_plus; struct { /* e.g. trap #$uimm4 */ + USI pc; + USI h_cr_0; USI uimm4; - } fmt_49_trap; - struct { /* e.g. satb $dr,$src2 */ + } fmt_57_trap; + struct { /* e.g. unlock $src1,@$src2 */ + UBI h_lock_0; + SI src1; SI src2; - } fmt_50_satb; - struct { /* e.g. sat $dr,$src2 */ + } fmt_58_unlock; + struct { /* e.g. satb $dr,$sr */ + SI sr; + } fmt_59_satb; + struct { /* e.g. sat $dr,$sr */ UBI condbit; - SI src2; - } fmt_51_sat; + SI sr; + } fmt_60_sat; struct { /* e.g. sadd */ DI h_accums_0; DI h_accums_1; - } fmt_52_sadd; + } fmt_61_sadd; struct { /* e.g. macwu1 $src1,$src2 */ DI h_accums_1; SI src1; SI src2; - } fmt_53_macwu1; + } fmt_62_macwu1; struct { /* e.g. msblo $src1,$src2 */ DI accum; SI src1; SI src2; - } fmt_54_msblo; + } fmt_63_msblo; + struct { /* e.g. mulwu1 $src1,$src2 */ + SI src1; + SI src2; + } fmt_64_mulwu1; struct { /* e.g. sc */ UBI condbit; - } fmt_55_sc; + } fmt_65_sc; } operands; }; diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index a474d0a..6f94926 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -48,21 +48,23 @@ with this program; if not, write to the Free Software Foundation, Inc., #endif #endif +/* FIXME: Need to review choices for the following. */ + #if WITH_SEM_SWITCH_FULL #define FULL(fn) 0 #else #define FULL(fn) XCONCAT3 (m32r,_sem_,fn) #endif +#if WITH_FAST #if WITH_SEM_SWITCH_FAST #define FAST(fn) 0 #else -#if WITH_SCACHE -#define FAST(fn) XCONCAT3 (m32r,_semc_,fn) +#define FAST(fn) XCONCAT3 (m32r,_semf_,fn) /* f for fast */ +#endif #else #define FAST(fn) 0 #endif -#endif /*#define DECODE M32R_DECODE*/ @@ -81,97 +83,96 @@ static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), FULL (xor), FAST (xor) }; static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), FULL (xor3), FAST (xor3) }; static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), FULL (addi), FAST (addi) }; -static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_0_add), FULL (addv), FAST (addv) }; -static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_5_addv3), FULL (addv3), FAST (addv3) }; -static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_6_addx), FULL (addx), FAST (addx) }; -static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_7_bc8), FULL (bc8), FAST (bc8) }; -static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_8_bc24), FULL (bc24), FAST (bc24) }; -static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_9_beq), FULL (beq), FAST (beq) }; -static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_10_beqz), FULL (beqz), FAST (beqz) }; -static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_10_beqz), FULL (bgez), FAST (bgez) }; -static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) }; -static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_10_beqz), FULL (blez), FAST (blez) }; -static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_10_beqz), FULL (bltz), FAST (bltz) }; -static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_10_beqz), FULL (bnez), FAST (bnez) }; -static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_11_bl8), FULL (bl8), FAST (bl8) }; -static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_12_bl24), FULL (bl24), FAST (bl24) }; -static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) }; -static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) }; -static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_9_beq), FULL (bne), FAST (bne) }; -static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_13_bra8), FULL (bra8), FAST (bra8) }; -static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_14_bra24), FULL (bra24), FAST (bra24) }; -static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_15_cmp), FULL (cmp), FAST (cmp) }; -static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_16_cmpi), FULL (cmpi), FAST (cmpi) }; -static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_15_cmp), FULL (cmpu), FAST (cmpu) }; -static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_17_cmpui), FULL (cmpui), FAST (cmpui) }; -static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_18_div), FULL (div), FAST (div) }; -static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_18_div), FULL (divu), FAST (divu) }; -static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_18_div), FULL (rem), FAST (rem) }; -static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_18_div), FULL (remu), FAST (remu) }; -static DECODE decode_divh = { M32R_INSN_DIVH, & ITAB (M32R_INSN_DIVH), EX (fmt_18_div), FULL (divh), FAST (divh) }; -static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_19_jl), FULL (jl), FAST (jl) }; -static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_20_jmp), FULL (jmp), FAST (jmp) }; -static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_21_ld), FULL (ld), FAST (ld) }; -static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_22_ld_d), FULL (ld_d), FAST (ld_d) }; -static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_23_ldb), FULL (ldb), FAST (ldb) }; -static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_24_ldb_d), FULL (ldb_d), FAST (ldb_d) }; -static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_25_ldh), FULL (ldh), FAST (ldh) }; -static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_26_ldh_d), FULL (ldh_d), FAST (ldh_d) }; -static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_23_ldb), FULL (ldub), FAST (ldub) }; -static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_24_ldb_d), FULL (ldub_d), FAST (ldub_d) }; -static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_25_ldh), FULL (lduh), FAST (lduh) }; -static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_26_ldh_d), FULL (lduh_d), FAST (lduh_d) }; -static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_21_ld), FULL (ld_plus), FAST (ld_plus) }; -static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_27_ld24), FULL (ld24), FAST (ld24) }; -static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_28_ldi8), FULL (ldi8), FAST (ldi8) }; -static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_29_ldi16), FULL (ldi16), FAST (ldi16) }; -static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_0_add), FULL (lock), FAST (lock) }; -static DECODE decode_machi = { M32R_INSN_MACHI, & ITAB (M32R_INSN_MACHI), EX (fmt_30_machi), FULL (machi), FAST (machi) }; -static DECODE decode_maclo = { M32R_INSN_MACLO, & ITAB (M32R_INSN_MACLO), EX (fmt_30_machi), FULL (maclo), FAST (maclo) }; -static DECODE decode_macwhi = { M32R_INSN_MACWHI, & ITAB (M32R_INSN_MACWHI), EX (fmt_30_machi), FULL (macwhi), FAST (macwhi) }; -static DECODE decode_macwlo = { M32R_INSN_MACWLO, & ITAB (M32R_INSN_MACWLO), EX (fmt_30_machi), FULL (macwlo), FAST (macwlo) }; +static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_5_addv), FULL (addv), FAST (addv) }; +static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_6_addv3), FULL (addv3), FAST (addv3) }; +static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_7_addx), FULL (addx), FAST (addx) }; +static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_8_bc8), FULL (bc8), FAST (bc8) }; +static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_9_bc24), FULL (bc24), FAST (bc24) }; +static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_10_beq), FULL (beq), FAST (beq) }; +static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_11_beqz), FULL (beqz), FAST (beqz) }; +static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_11_beqz), FULL (bgez), FAST (bgez) }; +static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_11_beqz), FULL (bgtz), FAST (bgtz) }; +static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_11_beqz), FULL (blez), FAST (blez) }; +static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_11_beqz), FULL (bltz), FAST (bltz) }; +static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_11_beqz), FULL (bnez), FAST (bnez) }; +static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_12_bl8), FULL (bl8), FAST (bl8) }; +static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_13_bl24), FULL (bl24), FAST (bl24) }; +static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_8_bc8), FULL (bnc8), FAST (bnc8) }; +static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_9_bc24), FULL (bnc24), FAST (bnc24) }; +static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_10_beq), FULL (bne), FAST (bne) }; +static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_14_bra8), FULL (bra8), FAST (bra8) }; +static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_15_bra24), FULL (bra24), FAST (bra24) }; +static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_16_cmp), FULL (cmp), FAST (cmp) }; +static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_17_cmpi), FULL (cmpi), FAST (cmpi) }; +static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_16_cmp), FULL (cmpu), FAST (cmpu) }; +static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_18_cmpui), FULL (cmpui), FAST (cmpui) }; +static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_19_div), FULL (div), FAST (div) }; +static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_19_div), FULL (divu), FAST (divu) }; +static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_19_div), FULL (rem), FAST (rem) }; +static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_19_div), FULL (remu), FAST (remu) }; +static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_20_jl), FULL (jl), FAST (jl) }; +static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_21_jmp), FULL (jmp), FAST (jmp) }; +static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_22_ld), FULL (ld), FAST (ld) }; +static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_23_ld_d), FULL (ld_d), FAST (ld_d) }; +static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_24_ldb), FULL (ldb), FAST (ldb) }; +static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_25_ldb_d), FULL (ldb_d), FAST (ldb_d) }; +static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_26_ldh), FULL (ldh), FAST (ldh) }; +static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_27_ldh_d), FULL (ldh_d), FAST (ldh_d) }; +static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_24_ldb), FULL (ldub), FAST (ldub) }; +static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_25_ldb_d), FULL (ldub_d), FAST (ldub_d) }; +static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_26_ldh), FULL (lduh), FAST (lduh) }; +static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_27_ldh_d), FULL (lduh_d), FAST (lduh_d) }; +static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_28_ld_plus), FULL (ld_plus), FAST (ld_plus) }; +static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_29_ld24), FULL (ld24), FAST (ld24) }; +static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_30_ldi8), FULL (ldi8), FAST (ldi8) }; +static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_31_ldi16), FULL (ldi16), FAST (ldi16) }; +static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_32_lock), FULL (lock), FAST (lock) }; +static DECODE decode_machi = { M32R_INSN_MACHI, & ITAB (M32R_INSN_MACHI), EX (fmt_33_machi), FULL (machi), FAST (machi) }; +static DECODE decode_maclo = { M32R_INSN_MACLO, & ITAB (M32R_INSN_MACLO), EX (fmt_33_machi), FULL (maclo), FAST (maclo) }; +static DECODE decode_macwhi = { M32R_INSN_MACWHI, & ITAB (M32R_INSN_MACWHI), EX (fmt_33_machi), FULL (macwhi), FAST (macwhi) }; +static DECODE decode_macwlo = { M32R_INSN_MACWLO, & ITAB (M32R_INSN_MACWLO), EX (fmt_33_machi), FULL (macwlo), FAST (macwlo) }; static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), FULL (mul), FAST (mul) }; -static DECODE decode_mulhi = { M32R_INSN_MULHI, & ITAB (M32R_INSN_MULHI), EX (fmt_15_cmp), FULL (mulhi), FAST (mulhi) }; -static DECODE decode_mullo = { M32R_INSN_MULLO, & ITAB (M32R_INSN_MULLO), EX (fmt_15_cmp), FULL (mullo), FAST (mullo) }; -static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & ITAB (M32R_INSN_MULWHI), EX (fmt_15_cmp), FULL (mulwhi), FAST (mulwhi) }; -static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & ITAB (M32R_INSN_MULWLO), EX (fmt_15_cmp), FULL (mulwlo), FAST (mulwlo) }; -static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_31_mv), FULL (mv), FAST (mv) }; -static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & ITAB (M32R_INSN_MVFACHI), EX (fmt_32_mvfachi), FULL (mvfachi), FAST (mvfachi) }; -static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & ITAB (M32R_INSN_MVFACLO), EX (fmt_32_mvfachi), FULL (mvfaclo), FAST (mvfaclo) }; -static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & ITAB (M32R_INSN_MVFACMI), EX (fmt_32_mvfachi), FULL (mvfacmi), FAST (mvfacmi) }; -static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_33_mvfc), FULL (mvfc), FAST (mvfc) }; -static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & ITAB (M32R_INSN_MVTACHI), EX (fmt_34_mvtachi), FULL (mvtachi), FAST (mvtachi) }; -static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & ITAB (M32R_INSN_MVTACLO), EX (fmt_34_mvtachi), FULL (mvtaclo), FAST (mvtaclo) }; -static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_35_mvtc), FULL (mvtc), FAST (mvtc) }; -static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_31_mv), FULL (neg), FAST (neg) }; -static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_36_nop), FULL (nop), FAST (nop) }; -static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_31_mv), FULL (not), FAST (not) }; -static DECODE decode_rac = { M32R_INSN_RAC, & ITAB (M32R_INSN_RAC), EX (fmt_37_rac), FULL (rac), FAST (rac) }; -static DECODE decode_rach = { M32R_INSN_RACH, & ITAB (M32R_INSN_RACH), EX (fmt_37_rac), FULL (rach), FAST (rach) }; -static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_38_rte), FULL (rte), FAST (rte) }; -static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_39_seth), FULL (seth), FAST (seth) }; +static DECODE decode_mulhi = { M32R_INSN_MULHI, & ITAB (M32R_INSN_MULHI), EX (fmt_34_mulhi), FULL (mulhi), FAST (mulhi) }; +static DECODE decode_mullo = { M32R_INSN_MULLO, & ITAB (M32R_INSN_MULLO), EX (fmt_34_mulhi), FULL (mullo), FAST (mullo) }; +static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & ITAB (M32R_INSN_MULWHI), EX (fmt_34_mulhi), FULL (mulwhi), FAST (mulwhi) }; +static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & ITAB (M32R_INSN_MULWLO), EX (fmt_34_mulhi), FULL (mulwlo), FAST (mulwlo) }; +static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_35_mv), FULL (mv), FAST (mv) }; +static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & ITAB (M32R_INSN_MVFACHI), EX (fmt_36_mvfachi), FULL (mvfachi), FAST (mvfachi) }; +static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & ITAB (M32R_INSN_MVFACLO), EX (fmt_36_mvfachi), FULL (mvfaclo), FAST (mvfaclo) }; +static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & ITAB (M32R_INSN_MVFACMI), EX (fmt_36_mvfachi), FULL (mvfacmi), FAST (mvfacmi) }; +static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_37_mvfc), FULL (mvfc), FAST (mvfc) }; +static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & ITAB (M32R_INSN_MVTACHI), EX (fmt_38_mvtachi), FULL (mvtachi), FAST (mvtachi) }; +static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & ITAB (M32R_INSN_MVTACLO), EX (fmt_38_mvtachi), FULL (mvtaclo), FAST (mvtaclo) }; +static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_39_mvtc), FULL (mvtc), FAST (mvtc) }; +static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_35_mv), FULL (neg), FAST (neg) }; +static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_40_nop), FULL (nop), FAST (nop) }; +static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_35_mv), FULL (not), FAST (not) }; +static DECODE decode_rac = { M32R_INSN_RAC, & ITAB (M32R_INSN_RAC), EX (fmt_41_rac), FULL (rac), FAST (rac) }; +static DECODE decode_rach = { M32R_INSN_RACH, & ITAB (M32R_INSN_RACH), EX (fmt_41_rac), FULL (rach), FAST (rach) }; +static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_42_rte), FULL (rte), FAST (rte) }; +static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_43_seth), FULL (seth), FAST (seth) }; static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), FULL (sll), FAST (sll) }; -static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_5_addv3), FULL (sll3), FAST (sll3) }; -static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_40_slli), FULL (slli), FAST (slli) }; +static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_44_sll3), FULL (sll3), FAST (sll3) }; +static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_45_slli), FULL (slli), FAST (slli) }; static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), FULL (sra), FAST (sra) }; -static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_5_addv3), FULL (sra3), FAST (sra3) }; -static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_40_slli), FULL (srai), FAST (srai) }; +static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_44_sll3), FULL (sra3), FAST (sra3) }; +static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_45_slli), FULL (srai), FAST (srai) }; static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), FULL (srl), FAST (srl) }; -static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_5_addv3), FULL (srl3), FAST (srl3) }; -static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_40_slli), FULL (srli), FAST (srli) }; -static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_15_cmp), FULL (st), FAST (st) }; -static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_41_st_d), FULL (st_d), FAST (st_d) }; -static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_15_cmp), FULL (stb), FAST (stb) }; -static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_41_st_d), FULL (stb_d), FAST (stb_d) }; -static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_15_cmp), FULL (sth), FAST (sth) }; -static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_41_st_d), FULL (sth_d), FAST (sth_d) }; -static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_15_cmp), FULL (st_plus), FAST (st_plus) }; -static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_15_cmp), FULL (st_minus), FAST (st_minus) }; +static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_44_sll3), FULL (srl3), FAST (srl3) }; +static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_45_slli), FULL (srli), FAST (srli) }; +static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_46_st), FULL (st), FAST (st) }; +static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_47_st_d), FULL (st_d), FAST (st_d) }; +static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_48_stb), FULL (stb), FAST (stb) }; +static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_49_stb_d), FULL (stb_d), FAST (stb_d) }; +static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_50_sth), FULL (sth), FAST (sth) }; +static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_51_sth_d), FULL (sth_d), FAST (sth_d) }; +static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_52_st_plus), FULL (st_plus), FAST (st_plus) }; +static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_52_st_plus), FULL (st_minus), FAST (st_minus) }; static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), FULL (sub), FAST (sub) }; -static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_0_add), FULL (subv), FAST (subv) }; -static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_6_addx), FULL (subx), FAST (subx) }; -static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_42_trap), FULL (trap), FAST (trap) }; -static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_15_cmp), FULL (unlock), FAST (unlock) }; +static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_5_addv), FULL (subv), FAST (subv) }; +static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_7_addx), FULL (subx), FAST (subx) }; +static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_53_trap), FULL (trap), FAST (trap) }; +static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_54_unlock), FULL (unlock), FAST (unlock) }; DECODE m32r_decode_illegal = { M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL), @@ -218,7 +219,6 @@ DECODE *m32r_decode_vars[] = { & decode_divu, & decode_rem, & decode_remu, - & decode_divh, & decode_jl, & decode_jmp, & decode_ld, @@ -339,7 +339,7 @@ m32r_decode (current_cpu, pc, insn) && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, - && case_0_144, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, @@ -406,7 +406,7 @@ m32r_decode (current_cpu, pc, insn) &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, - 0, &decode_divu, &decode_rem, &decode_remu, + &decode_div, &decode_divu, &decode_rem, &decode_remu, &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, @@ -508,67 +508,6 @@ m32r_decode (current_cpu, pc, insn) unsigned int val = (((insn >> 8) & (15 << 0))); return insns[val]; } - CASE (0, 144) : - { -#ifdef __GNUC__ - static void *labels_0_144[16] = { - && case_0_144_0, && default_0_144, && default_0_144, && default_0_144, - && default_0_144, && default_0_144, && default_0_144, && default_0_144, - && default_0_144, && default_0_144, && default_0_144, && default_0_144, - && default_0_144, && default_0_144, && default_0_144, && default_0_144, - }; -#endif - static DECODE *insns[16] = { - 0, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val; - /* Must fetch more bits. */ - insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2); - val = (((insn >> 12) & (15 << 0))); - DECODE_SWITCH (0_144, val) - { - CASE (0_144, 0) : - { -#ifdef __GNUC__ - static void *labels_0_144_0[16] = { - && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, - && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, - && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, - && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, - }; -#endif - static DECODE *insns[16] = { - 0, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val; - val = (((insn >> 8) & (15 << 0))); - DECODE_SWITCH (0_144_0, val) - { - CASE (0_144_0, 0) : - { - static DECODE *insns[16] = { - &decode_div, &decode_divh, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - return insns[val]; - } - DEFAULT (0_144_0) : return insns[val]; - } - ENDSWITCH (0_144_0) - } - DEFAULT (0_144) : return insns[val]; - } - ENDSWITCH (0_144) - } CASE (0, 240) : /* fall through */ CASE (0, 241) : /* fall through */ CASE (0, 242) : /* fall through */ diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h index 3511e31..5bc1508 100644 --- a/sim/m32r/decode.h +++ b/sim/m32r/decode.h @@ -27,259 +27,268 @@ with this program; if not, write to the Free Software Foundation, Inc., #define EX(fn) XCONCAT3 (m32r,_ex_,fn) #define SEM(fn) XCONCAT3 (m32r,_sem_,fn) -#define SEMC(fn) XCONCAT3 (m32r,_semc_,fn) +#define SEMF(fn) XCONCAT3 (m32r,_semf_,fn) extern EXTRACT_FN EX (illegal); extern SEMANTIC_FN SEM (illegal); -extern SEMANTIC_CACHE_FN SEMC (illegal); - +extern SEMANTIC_FN SEMF (illegal); extern EXTRACT_FN EX (fmt_0_add); extern EXTRACT_FN EX (fmt_1_add3); extern EXTRACT_FN EX (fmt_2_and3); extern EXTRACT_FN EX (fmt_3_or3); extern EXTRACT_FN EX (fmt_4_addi); -extern EXTRACT_FN EX (fmt_5_addv3); -extern EXTRACT_FN EX (fmt_6_addx); -extern EXTRACT_FN EX (fmt_7_bc8); -extern EXTRACT_FN EX (fmt_8_bc24); -extern EXTRACT_FN EX (fmt_9_beq); -extern EXTRACT_FN EX (fmt_10_beqz); -extern EXTRACT_FN EX (fmt_11_bl8); -extern EXTRACT_FN EX (fmt_12_bl24); -extern EXTRACT_FN EX (fmt_13_bra8); -extern EXTRACT_FN EX (fmt_14_bra24); -extern EXTRACT_FN EX (fmt_15_cmp); -extern EXTRACT_FN EX (fmt_16_cmpi); -extern EXTRACT_FN EX (fmt_17_cmpui); -extern EXTRACT_FN EX (fmt_18_div); -extern EXTRACT_FN EX (fmt_19_jl); -extern EXTRACT_FN EX (fmt_20_jmp); -extern EXTRACT_FN EX (fmt_21_ld); -extern EXTRACT_FN EX (fmt_22_ld_d); -extern EXTRACT_FN EX (fmt_23_ldb); -extern EXTRACT_FN EX (fmt_24_ldb_d); -extern EXTRACT_FN EX (fmt_25_ldh); -extern EXTRACT_FN EX (fmt_26_ldh_d); -extern EXTRACT_FN EX (fmt_27_ld24); -extern EXTRACT_FN EX (fmt_28_ldi8); -extern EXTRACT_FN EX (fmt_29_ldi16); -extern EXTRACT_FN EX (fmt_30_machi); -extern EXTRACT_FN EX (fmt_31_mv); -extern EXTRACT_FN EX (fmt_32_mvfachi); -extern EXTRACT_FN EX (fmt_33_mvfc); -extern EXTRACT_FN EX (fmt_34_mvtachi); -extern EXTRACT_FN EX (fmt_35_mvtc); -extern EXTRACT_FN EX (fmt_36_nop); -extern EXTRACT_FN EX (fmt_37_rac); -extern EXTRACT_FN EX (fmt_38_rte); -extern EXTRACT_FN EX (fmt_39_seth); -extern EXTRACT_FN EX (fmt_40_slli); -extern EXTRACT_FN EX (fmt_41_st_d); -extern EXTRACT_FN EX (fmt_42_trap); +extern EXTRACT_FN EX (fmt_5_addv); +extern EXTRACT_FN EX (fmt_6_addv3); +extern EXTRACT_FN EX (fmt_7_addx); +extern EXTRACT_FN EX (fmt_8_bc8); +extern EXTRACT_FN EX (fmt_9_bc24); +extern EXTRACT_FN EX (fmt_10_beq); +extern EXTRACT_FN EX (fmt_11_beqz); +extern EXTRACT_FN EX (fmt_12_bl8); +extern EXTRACT_FN EX (fmt_13_bl24); +extern EXTRACT_FN EX (fmt_14_bra8); +extern EXTRACT_FN EX (fmt_15_bra24); +extern EXTRACT_FN EX (fmt_16_cmp); +extern EXTRACT_FN EX (fmt_17_cmpi); +extern EXTRACT_FN EX (fmt_18_cmpui); +extern EXTRACT_FN EX (fmt_19_div); +extern EXTRACT_FN EX (fmt_20_jl); +extern EXTRACT_FN EX (fmt_21_jmp); +extern EXTRACT_FN EX (fmt_22_ld); +extern EXTRACT_FN EX (fmt_23_ld_d); +extern EXTRACT_FN EX (fmt_24_ldb); +extern EXTRACT_FN EX (fmt_25_ldb_d); +extern EXTRACT_FN EX (fmt_26_ldh); +extern EXTRACT_FN EX (fmt_27_ldh_d); +extern EXTRACT_FN EX (fmt_28_ld_plus); +extern EXTRACT_FN EX (fmt_29_ld24); +extern EXTRACT_FN EX (fmt_30_ldi8); +extern EXTRACT_FN EX (fmt_31_ldi16); +extern EXTRACT_FN EX (fmt_32_lock); +extern EXTRACT_FN EX (fmt_33_machi); +extern EXTRACT_FN EX (fmt_34_mulhi); +extern EXTRACT_FN EX (fmt_35_mv); +extern EXTRACT_FN EX (fmt_36_mvfachi); +extern EXTRACT_FN EX (fmt_37_mvfc); +extern EXTRACT_FN EX (fmt_38_mvtachi); +extern EXTRACT_FN EX (fmt_39_mvtc); +extern EXTRACT_FN EX (fmt_40_nop); +extern EXTRACT_FN EX (fmt_41_rac); +extern EXTRACT_FN EX (fmt_42_rte); +extern EXTRACT_FN EX (fmt_43_seth); +extern EXTRACT_FN EX (fmt_44_sll3); +extern EXTRACT_FN EX (fmt_45_slli); +extern EXTRACT_FN EX (fmt_46_st); +extern EXTRACT_FN EX (fmt_47_st_d); +extern EXTRACT_FN EX (fmt_48_stb); +extern EXTRACT_FN EX (fmt_49_stb_d); +extern EXTRACT_FN EX (fmt_50_sth); +extern EXTRACT_FN EX (fmt_51_sth_d); +extern EXTRACT_FN EX (fmt_52_st_plus); +extern EXTRACT_FN EX (fmt_53_trap); +extern EXTRACT_FN EX (fmt_54_unlock); extern SEMANTIC_FN SEM (add); -extern SEMANTIC_CACHE_FN SEMC (add); +extern SEMANTIC_FN SEMF (add); extern SEMANTIC_FN SEM (add3); -extern SEMANTIC_CACHE_FN SEMC (add3); +extern SEMANTIC_FN SEMF (add3); extern SEMANTIC_FN SEM (and); -extern SEMANTIC_CACHE_FN SEMC (and); +extern SEMANTIC_FN SEMF (and); extern SEMANTIC_FN SEM (and3); -extern SEMANTIC_CACHE_FN SEMC (and3); +extern SEMANTIC_FN SEMF (and3); extern SEMANTIC_FN SEM (or); -extern SEMANTIC_CACHE_FN SEMC (or); +extern SEMANTIC_FN SEMF (or); extern SEMANTIC_FN SEM (or3); -extern SEMANTIC_CACHE_FN SEMC (or3); +extern SEMANTIC_FN SEMF (or3); extern SEMANTIC_FN SEM (xor); -extern SEMANTIC_CACHE_FN SEMC (xor); +extern SEMANTIC_FN SEMF (xor); extern SEMANTIC_FN SEM (xor3); -extern SEMANTIC_CACHE_FN SEMC (xor3); +extern SEMANTIC_FN SEMF (xor3); extern SEMANTIC_FN SEM (addi); -extern SEMANTIC_CACHE_FN SEMC (addi); +extern SEMANTIC_FN SEMF (addi); extern SEMANTIC_FN SEM (addv); -extern SEMANTIC_CACHE_FN SEMC (addv); +extern SEMANTIC_FN SEMF (addv); extern SEMANTIC_FN SEM (addv3); -extern SEMANTIC_CACHE_FN SEMC (addv3); +extern SEMANTIC_FN SEMF (addv3); extern SEMANTIC_FN SEM (addx); -extern SEMANTIC_CACHE_FN SEMC (addx); +extern SEMANTIC_FN SEMF (addx); extern SEMANTIC_FN SEM (bc8); -extern SEMANTIC_CACHE_FN SEMC (bc8); +extern SEMANTIC_FN SEMF (bc8); extern SEMANTIC_FN SEM (bc24); -extern SEMANTIC_CACHE_FN SEMC (bc24); +extern SEMANTIC_FN SEMF (bc24); extern SEMANTIC_FN SEM (beq); -extern SEMANTIC_CACHE_FN SEMC (beq); +extern SEMANTIC_FN SEMF (beq); extern SEMANTIC_FN SEM (beqz); -extern SEMANTIC_CACHE_FN SEMC (beqz); +extern SEMANTIC_FN SEMF (beqz); extern SEMANTIC_FN SEM (bgez); -extern SEMANTIC_CACHE_FN SEMC (bgez); +extern SEMANTIC_FN SEMF (bgez); extern SEMANTIC_FN SEM (bgtz); -extern SEMANTIC_CACHE_FN SEMC (bgtz); +extern SEMANTIC_FN SEMF (bgtz); extern SEMANTIC_FN SEM (blez); -extern SEMANTIC_CACHE_FN SEMC (blez); +extern SEMANTIC_FN SEMF (blez); extern SEMANTIC_FN SEM (bltz); -extern SEMANTIC_CACHE_FN SEMC (bltz); +extern SEMANTIC_FN SEMF (bltz); extern SEMANTIC_FN SEM (bnez); -extern SEMANTIC_CACHE_FN SEMC (bnez); +extern SEMANTIC_FN SEMF (bnez); extern SEMANTIC_FN SEM (bl8); -extern SEMANTIC_CACHE_FN SEMC (bl8); +extern SEMANTIC_FN SEMF (bl8); extern SEMANTIC_FN SEM (bl24); -extern SEMANTIC_CACHE_FN SEMC (bl24); +extern SEMANTIC_FN SEMF (bl24); extern SEMANTIC_FN SEM (bnc8); -extern SEMANTIC_CACHE_FN SEMC (bnc8); +extern SEMANTIC_FN SEMF (bnc8); extern SEMANTIC_FN SEM (bnc24); -extern SEMANTIC_CACHE_FN SEMC (bnc24); +extern SEMANTIC_FN SEMF (bnc24); extern SEMANTIC_FN SEM (bne); -extern SEMANTIC_CACHE_FN SEMC (bne); +extern SEMANTIC_FN SEMF (bne); extern SEMANTIC_FN SEM (bra8); -extern SEMANTIC_CACHE_FN SEMC (bra8); +extern SEMANTIC_FN SEMF (bra8); extern SEMANTIC_FN SEM (bra24); -extern SEMANTIC_CACHE_FN SEMC (bra24); +extern SEMANTIC_FN SEMF (bra24); extern SEMANTIC_FN SEM (cmp); -extern SEMANTIC_CACHE_FN SEMC (cmp); +extern SEMANTIC_FN SEMF (cmp); extern SEMANTIC_FN SEM (cmpi); -extern SEMANTIC_CACHE_FN SEMC (cmpi); +extern SEMANTIC_FN SEMF (cmpi); extern SEMANTIC_FN SEM (cmpu); -extern SEMANTIC_CACHE_FN SEMC (cmpu); +extern SEMANTIC_FN SEMF (cmpu); extern SEMANTIC_FN SEM (cmpui); -extern SEMANTIC_CACHE_FN SEMC (cmpui); +extern SEMANTIC_FN SEMF (cmpui); extern SEMANTIC_FN SEM (div); -extern SEMANTIC_CACHE_FN SEMC (div); +extern SEMANTIC_FN SEMF (div); extern SEMANTIC_FN SEM (divu); -extern SEMANTIC_CACHE_FN SEMC (divu); +extern SEMANTIC_FN SEMF (divu); extern SEMANTIC_FN SEM (rem); -extern SEMANTIC_CACHE_FN SEMC (rem); +extern SEMANTIC_FN SEMF (rem); extern SEMANTIC_FN SEM (remu); -extern SEMANTIC_CACHE_FN SEMC (remu); -extern SEMANTIC_FN SEM (divh); -extern SEMANTIC_CACHE_FN SEMC (divh); +extern SEMANTIC_FN SEMF (remu); extern SEMANTIC_FN SEM (jl); -extern SEMANTIC_CACHE_FN SEMC (jl); +extern SEMANTIC_FN SEMF (jl); extern SEMANTIC_FN SEM (jmp); -extern SEMANTIC_CACHE_FN SEMC (jmp); +extern SEMANTIC_FN SEMF (jmp); extern SEMANTIC_FN SEM (ld); -extern SEMANTIC_CACHE_FN SEMC (ld); +extern SEMANTIC_FN SEMF (ld); extern SEMANTIC_FN SEM (ld_d); -extern SEMANTIC_CACHE_FN SEMC (ld_d); +extern SEMANTIC_FN SEMF (ld_d); extern SEMANTIC_FN SEM (ldb); -extern SEMANTIC_CACHE_FN SEMC (ldb); +extern SEMANTIC_FN SEMF (ldb); extern SEMANTIC_FN SEM (ldb_d); -extern SEMANTIC_CACHE_FN SEMC (ldb_d); +extern SEMANTIC_FN SEMF (ldb_d); extern SEMANTIC_FN SEM (ldh); -extern SEMANTIC_CACHE_FN SEMC (ldh); +extern SEMANTIC_FN SEMF (ldh); extern SEMANTIC_FN SEM (ldh_d); -extern SEMANTIC_CACHE_FN SEMC (ldh_d); +extern SEMANTIC_FN SEMF (ldh_d); extern SEMANTIC_FN SEM (ldub); -extern SEMANTIC_CACHE_FN SEMC (ldub); +extern SEMANTIC_FN SEMF (ldub); extern SEMANTIC_FN SEM (ldub_d); -extern SEMANTIC_CACHE_FN SEMC (ldub_d); +extern SEMANTIC_FN SEMF (ldub_d); extern SEMANTIC_FN SEM (lduh); -extern SEMANTIC_CACHE_FN SEMC (lduh); +extern SEMANTIC_FN SEMF (lduh); extern SEMANTIC_FN SEM (lduh_d); -extern SEMANTIC_CACHE_FN SEMC (lduh_d); +extern SEMANTIC_FN SEMF (lduh_d); extern SEMANTIC_FN SEM (ld_plus); -extern SEMANTIC_CACHE_FN SEMC (ld_plus); +extern SEMANTIC_FN SEMF (ld_plus); extern SEMANTIC_FN SEM (ld24); -extern SEMANTIC_CACHE_FN SEMC (ld24); +extern SEMANTIC_FN SEMF (ld24); extern SEMANTIC_FN SEM (ldi8); -extern SEMANTIC_CACHE_FN SEMC (ldi8); +extern SEMANTIC_FN SEMF (ldi8); extern SEMANTIC_FN SEM (ldi16); -extern SEMANTIC_CACHE_FN SEMC (ldi16); +extern SEMANTIC_FN SEMF (ldi16); extern SEMANTIC_FN SEM (lock); -extern SEMANTIC_CACHE_FN SEMC (lock); +extern SEMANTIC_FN SEMF (lock); extern SEMANTIC_FN SEM (machi); -extern SEMANTIC_CACHE_FN SEMC (machi); +extern SEMANTIC_FN SEMF (machi); extern SEMANTIC_FN SEM (maclo); -extern SEMANTIC_CACHE_FN SEMC (maclo); +extern SEMANTIC_FN SEMF (maclo); extern SEMANTIC_FN SEM (macwhi); -extern SEMANTIC_CACHE_FN SEMC (macwhi); +extern SEMANTIC_FN SEMF (macwhi); extern SEMANTIC_FN SEM (macwlo); -extern SEMANTIC_CACHE_FN SEMC (macwlo); +extern SEMANTIC_FN SEMF (macwlo); extern SEMANTIC_FN SEM (mul); -extern SEMANTIC_CACHE_FN SEMC (mul); +extern SEMANTIC_FN SEMF (mul); extern SEMANTIC_FN SEM (mulhi); -extern SEMANTIC_CACHE_FN SEMC (mulhi); +extern SEMANTIC_FN SEMF (mulhi); extern SEMANTIC_FN SEM (mullo); -extern SEMANTIC_CACHE_FN SEMC (mullo); +extern SEMANTIC_FN SEMF (mullo); extern SEMANTIC_FN SEM (mulwhi); -extern SEMANTIC_CACHE_FN SEMC (mulwhi); +extern SEMANTIC_FN SEMF (mulwhi); extern SEMANTIC_FN SEM (mulwlo); -extern SEMANTIC_CACHE_FN SEMC (mulwlo); +extern SEMANTIC_FN SEMF (mulwlo); extern SEMANTIC_FN SEM (mv); -extern SEMANTIC_CACHE_FN SEMC (mv); +extern SEMANTIC_FN SEMF (mv); extern SEMANTIC_FN SEM (mvfachi); -extern SEMANTIC_CACHE_FN SEMC (mvfachi); +extern SEMANTIC_FN SEMF (mvfachi); extern SEMANTIC_FN SEM (mvfaclo); -extern SEMANTIC_CACHE_FN SEMC (mvfaclo); +extern SEMANTIC_FN SEMF (mvfaclo); extern SEMANTIC_FN SEM (mvfacmi); -extern SEMANTIC_CACHE_FN SEMC (mvfacmi); +extern SEMANTIC_FN SEMF (mvfacmi); extern SEMANTIC_FN SEM (mvfc); -extern SEMANTIC_CACHE_FN SEMC (mvfc); +extern SEMANTIC_FN SEMF (mvfc); extern SEMANTIC_FN SEM (mvtachi); -extern SEMANTIC_CACHE_FN SEMC (mvtachi); +extern SEMANTIC_FN SEMF (mvtachi); extern SEMANTIC_FN SEM (mvtaclo); -extern SEMANTIC_CACHE_FN SEMC (mvtaclo); +extern SEMANTIC_FN SEMF (mvtaclo); extern SEMANTIC_FN SEM (mvtc); -extern SEMANTIC_CACHE_FN SEMC (mvtc); +extern SEMANTIC_FN SEMF (mvtc); extern SEMANTIC_FN SEM (neg); -extern SEMANTIC_CACHE_FN SEMC (neg); +extern SEMANTIC_FN SEMF (neg); extern SEMANTIC_FN SEM (nop); -extern SEMANTIC_CACHE_FN SEMC (nop); +extern SEMANTIC_FN SEMF (nop); extern SEMANTIC_FN SEM (not); -extern SEMANTIC_CACHE_FN SEMC (not); +extern SEMANTIC_FN SEMF (not); extern SEMANTIC_FN SEM (rac); -extern SEMANTIC_CACHE_FN SEMC (rac); +extern SEMANTIC_FN SEMF (rac); extern SEMANTIC_FN SEM (rach); -extern SEMANTIC_CACHE_FN SEMC (rach); +extern SEMANTIC_FN SEMF (rach); extern SEMANTIC_FN SEM (rte); -extern SEMANTIC_CACHE_FN SEMC (rte); +extern SEMANTIC_FN SEMF (rte); extern SEMANTIC_FN SEM (seth); -extern SEMANTIC_CACHE_FN SEMC (seth); +extern SEMANTIC_FN SEMF (seth); extern SEMANTIC_FN SEM (sll); -extern SEMANTIC_CACHE_FN SEMC (sll); +extern SEMANTIC_FN SEMF (sll); extern SEMANTIC_FN SEM (sll3); -extern SEMANTIC_CACHE_FN SEMC (sll3); +extern SEMANTIC_FN SEMF (sll3); extern SEMANTIC_FN SEM (slli); -extern SEMANTIC_CACHE_FN SEMC (slli); +extern SEMANTIC_FN SEMF (slli); extern SEMANTIC_FN SEM (sra); -extern SEMANTIC_CACHE_FN SEMC (sra); +extern SEMANTIC_FN SEMF (sra); extern SEMANTIC_FN SEM (sra3); -extern SEMANTIC_CACHE_FN SEMC (sra3); +extern SEMANTIC_FN SEMF (sra3); extern SEMANTIC_FN SEM (srai); -extern SEMANTIC_CACHE_FN SEMC (srai); +extern SEMANTIC_FN SEMF (srai); extern SEMANTIC_FN SEM (srl); -extern SEMANTIC_CACHE_FN SEMC (srl); +extern SEMANTIC_FN SEMF (srl); extern SEMANTIC_FN SEM (srl3); -extern SEMANTIC_CACHE_FN SEMC (srl3); +extern SEMANTIC_FN SEMF (srl3); extern SEMANTIC_FN SEM (srli); -extern SEMANTIC_CACHE_FN SEMC (srli); +extern SEMANTIC_FN SEMF (srli); extern SEMANTIC_FN SEM (st); -extern SEMANTIC_CACHE_FN SEMC (st); +extern SEMANTIC_FN SEMF (st); extern SEMANTIC_FN SEM (st_d); -extern SEMANTIC_CACHE_FN SEMC (st_d); +extern SEMANTIC_FN SEMF (st_d); extern SEMANTIC_FN SEM (stb); -extern SEMANTIC_CACHE_FN SEMC (stb); +extern SEMANTIC_FN SEMF (stb); extern SEMANTIC_FN SEM (stb_d); -extern SEMANTIC_CACHE_FN SEMC (stb_d); +extern SEMANTIC_FN SEMF (stb_d); extern SEMANTIC_FN SEM (sth); -extern SEMANTIC_CACHE_FN SEMC (sth); +extern SEMANTIC_FN SEMF (sth); extern SEMANTIC_FN SEM (sth_d); -extern SEMANTIC_CACHE_FN SEMC (sth_d); +extern SEMANTIC_FN SEMF (sth_d); extern SEMANTIC_FN SEM (st_plus); -extern SEMANTIC_CACHE_FN SEMC (st_plus); +extern SEMANTIC_FN SEMF (st_plus); extern SEMANTIC_FN SEM (st_minus); -extern SEMANTIC_CACHE_FN SEMC (st_minus); +extern SEMANTIC_FN SEMF (st_minus); extern SEMANTIC_FN SEM (sub); -extern SEMANTIC_CACHE_FN SEMC (sub); +extern SEMANTIC_FN SEMF (sub); extern SEMANTIC_FN SEM (subv); -extern SEMANTIC_CACHE_FN SEMC (subv); +extern SEMANTIC_FN SEMF (subv); extern SEMANTIC_FN SEM (subx); -extern SEMANTIC_CACHE_FN SEMC (subx); +extern SEMANTIC_FN SEMF (subx); extern SEMANTIC_FN SEM (trap); -extern SEMANTIC_CACHE_FN SEMC (trap); +extern SEMANTIC_FN SEMF (trap); extern SEMANTIC_FN SEM (unlock); -extern SEMANTIC_CACHE_FN SEMC (unlock); +extern SEMANTIC_FN SEMF (unlock); #undef EX #undef SEM -#undef SEMC +#undef SEMF #endif /* M32R_DECODE_H */ diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c index 3ed3018..3883b28 100644 --- a/sim/m32r/decodex.c +++ b/sim/m32r/decodex.c @@ -48,21 +48,23 @@ with this program; if not, write to the Free Software Foundation, Inc., #endif #endif +/* FIXME: Need to review choices for the following. */ + #if WITH_SEM_SWITCH_FULL #define FULL(fn) 0 #else #define FULL(fn) XCONCAT3 (m32rx,_sem_,fn) #endif +#if WITH_FAST #if WITH_SEM_SWITCH_FAST #define FAST(fn) 0 #else -#if WITH_SCACHE -#define FAST(fn) XCONCAT3 (m32rx,_semc_,fn) +#define FAST(fn) XCONCAT3 (m32rx,_semf_,fn) /* f for fast */ +#endif #else #define FAST(fn) 0 #endif -#endif /*#define DECODE M32RX_DECODE*/ @@ -81,116 +83,112 @@ static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), READ (FMT_0_ADD), FULL (xor), FAST (xor) }; static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), READ (FMT_2_AND3), FULL (xor3), FAST (xor3) }; static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), READ (FMT_4_ADDI), FULL (addi), FAST (addi) }; -static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_0_add), READ (FMT_0_ADD), FULL (addv), FAST (addv) }; -static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (addv3), FAST (addv3) }; -static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_6_addx), READ (FMT_6_ADDX), FULL (addx), FAST (addx) }; -static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_7_bc8), READ (FMT_7_BC8), FULL (bc8), FAST (bc8) }; -static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_8_bc24), READ (FMT_8_BC24), FULL (bc24), FAST (bc24) }; -static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_9_beq), READ (FMT_9_BEQ), FULL (beq), FAST (beq) }; -static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (beqz), FAST (beqz) }; -static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bgez), FAST (bgez) }; -static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bgtz), FAST (bgtz) }; -static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (blez), FAST (blez) }; -static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bltz), FAST (bltz) }; -static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bnez), FAST (bnez) }; -static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_11_bl8), READ (FMT_11_BL8), FULL (bl8), FAST (bl8) }; -static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_12_bl24), READ (FMT_12_BL24), FULL (bl24), FAST (bl24) }; -static DECODE decode_bcl8 = { M32R_INSN_BCL8, & ITAB (M32R_INSN_BCL8), EX (fmt_13_bcl8), READ (FMT_13_BCL8), FULL (bcl8), FAST (bcl8) }; -static DECODE decode_bcl24 = { M32R_INSN_BCL24, & ITAB (M32R_INSN_BCL24), EX (fmt_14_bcl24), READ (FMT_14_BCL24), FULL (bcl24), FAST (bcl24) }; -static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_7_bc8), READ (FMT_7_BC8), FULL (bnc8), FAST (bnc8) }; -static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_8_bc24), READ (FMT_8_BC24), FULL (bnc24), FAST (bnc24) }; -static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_9_beq), READ (FMT_9_BEQ), FULL (bne), FAST (bne) }; -static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_15_bra8), READ (FMT_15_BRA8), FULL (bra8), FAST (bra8) }; -static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_16_bra24), READ (FMT_16_BRA24), FULL (bra24), FAST (bra24) }; -static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & ITAB (M32R_INSN_BNCL8), EX (fmt_13_bcl8), READ (FMT_13_BCL8), FULL (bncl8), FAST (bncl8) }; -static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & ITAB (M32R_INSN_BNCL24), EX (fmt_14_bcl24), READ (FMT_14_BCL24), FULL (bncl24), FAST (bncl24) }; -static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (cmp), FAST (cmp) }; -static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_18_cmpi), READ (FMT_18_CMPI), FULL (cmpi), FAST (cmpi) }; -static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (cmpu), FAST (cmpu) }; -static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_19_cmpui), READ (FMT_19_CMPUI), FULL (cmpui), FAST (cmpui) }; -static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & ITAB (M32R_INSN_CMPEQ), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (cmpeq), FAST (cmpeq) }; -static DECODE decode_cmpz = { M32R_INSN_CMPZ, & ITAB (M32R_INSN_CMPZ), EX (fmt_20_cmpz), READ (FMT_20_CMPZ), FULL (cmpz), FAST (cmpz) }; -static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_21_div), READ (FMT_21_DIV), FULL (div), FAST (div) }; -static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_21_div), READ (FMT_21_DIV), FULL (divu), FAST (divu) }; -static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_21_div), READ (FMT_21_DIV), FULL (rem), FAST (rem) }; -static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_21_div), READ (FMT_21_DIV), FULL (remu), FAST (remu) }; -static DECODE decode_divh = { M32R_INSN_DIVH, & ITAB (M32R_INSN_DIVH), EX (fmt_21_div), READ (FMT_21_DIV), FULL (divh), FAST (divh) }; -static DECODE decode_jc = { M32R_INSN_JC, & ITAB (M32R_INSN_JC), EX (fmt_22_jc), READ (FMT_22_JC), FULL (jc), FAST (jc) }; -static DECODE decode_jnc = { M32R_INSN_JNC, & ITAB (M32R_INSN_JNC), EX (fmt_22_jc), READ (FMT_22_JC), FULL (jnc), FAST (jnc) }; -static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_23_jl), READ (FMT_23_JL), FULL (jl), FAST (jl) }; -static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_24_jmp), READ (FMT_24_JMP), FULL (jmp), FAST (jmp) }; -static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_25_ld), READ (FMT_25_LD), FULL (ld), FAST (ld) }; -static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_26_ld_d), READ (FMT_26_LD_D), FULL (ld_d), FAST (ld_d) }; -static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_27_ldb), READ (FMT_27_LDB), FULL (ldb), FAST (ldb) }; -static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_28_ldb_d), READ (FMT_28_LDB_D), FULL (ldb_d), FAST (ldb_d) }; -static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_29_ldh), READ (FMT_29_LDH), FULL (ldh), FAST (ldh) }; -static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_30_ldh_d), READ (FMT_30_LDH_D), FULL (ldh_d), FAST (ldh_d) }; -static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_27_ldb), READ (FMT_27_LDB), FULL (ldub), FAST (ldub) }; -static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_28_ldb_d), READ (FMT_28_LDB_D), FULL (ldub_d), FAST (ldub_d) }; -static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_29_ldh), READ (FMT_29_LDH), FULL (lduh), FAST (lduh) }; -static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_30_ldh_d), READ (FMT_30_LDH_D), FULL (lduh_d), FAST (lduh_d) }; -static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_25_ld), READ (FMT_25_LD), FULL (ld_plus), FAST (ld_plus) }; -static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_31_ld24), READ (FMT_31_LD24), FULL (ld24), FAST (ld24) }; -static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_32_ldi8), READ (FMT_32_LDI8), FULL (ldi8), FAST (ldi8) }; -static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_33_ldi16), READ (FMT_33_LDI16), FULL (ldi16), FAST (ldi16) }; -static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_0_add), READ (FMT_0_ADD), FULL (lock), FAST (lock) }; -static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & ITAB (M32R_INSN_MACHI_A), EX (fmt_34_machi_a), READ (FMT_34_MACHI_A), FULL (machi_a), FAST (machi_a) }; -static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & ITAB (M32R_INSN_MACLO_A), EX (fmt_34_machi_a), READ (FMT_34_MACHI_A), FULL (maclo_a), FAST (maclo_a) }; +static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_5_addv), READ (FMT_5_ADDV), FULL (addv), FAST (addv) }; +static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_6_addv3), READ (FMT_6_ADDV3), FULL (addv3), FAST (addv3) }; +static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_7_addx), READ (FMT_7_ADDX), FULL (addx), FAST (addx) }; +static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_8_bc8), READ (FMT_8_BC8), FULL (bc8), FAST (bc8) }; +static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_9_bc24), READ (FMT_9_BC24), FULL (bc24), FAST (bc24) }; +static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_10_beq), READ (FMT_10_BEQ), FULL (beq), FAST (beq) }; +static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (beqz), FAST (beqz) }; +static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bgez), FAST (bgez) }; +static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bgtz), FAST (bgtz) }; +static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (blez), FAST (blez) }; +static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bltz), FAST (bltz) }; +static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_11_beqz), READ (FMT_11_BEQZ), FULL (bnez), FAST (bnez) }; +static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_12_bl8), READ (FMT_12_BL8), FULL (bl8), FAST (bl8) }; +static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_13_bl24), READ (FMT_13_BL24), FULL (bl24), FAST (bl24) }; +static DECODE decode_bcl8 = { M32R_INSN_BCL8, & ITAB (M32R_INSN_BCL8), EX (fmt_14_bcl8), READ (FMT_14_BCL8), FULL (bcl8), FAST (bcl8) }; +static DECODE decode_bcl24 = { M32R_INSN_BCL24, & ITAB (M32R_INSN_BCL24), EX (fmt_15_bcl24), READ (FMT_15_BCL24), FULL (bcl24), FAST (bcl24) }; +static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_8_bc8), READ (FMT_8_BC8), FULL (bnc8), FAST (bnc8) }; +static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_9_bc24), READ (FMT_9_BC24), FULL (bnc24), FAST (bnc24) }; +static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_10_beq), READ (FMT_10_BEQ), FULL (bne), FAST (bne) }; +static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_16_bra8), READ (FMT_16_BRA8), FULL (bra8), FAST (bra8) }; +static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_17_bra24), READ (FMT_17_BRA24), FULL (bra24), FAST (bra24) }; +static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & ITAB (M32R_INSN_BNCL8), EX (fmt_14_bcl8), READ (FMT_14_BCL8), FULL (bncl8), FAST (bncl8) }; +static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & ITAB (M32R_INSN_BNCL24), EX (fmt_15_bcl24), READ (FMT_15_BCL24), FULL (bncl24), FAST (bncl24) }; +static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_18_cmp), READ (FMT_18_CMP), FULL (cmp), FAST (cmp) }; +static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_19_cmpi), READ (FMT_19_CMPI), FULL (cmpi), FAST (cmpi) }; +static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_18_cmp), READ (FMT_18_CMP), FULL (cmpu), FAST (cmpu) }; +static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_20_cmpui), READ (FMT_20_CMPUI), FULL (cmpui), FAST (cmpui) }; +static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & ITAB (M32R_INSN_CMPEQ), EX (fmt_18_cmp), READ (FMT_18_CMP), FULL (cmpeq), FAST (cmpeq) }; +static DECODE decode_cmpz = { M32R_INSN_CMPZ, & ITAB (M32R_INSN_CMPZ), EX (fmt_21_cmpz), READ (FMT_21_CMPZ), FULL (cmpz), FAST (cmpz) }; +static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_22_div), READ (FMT_22_DIV), FULL (div), FAST (div) }; +static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_22_div), READ (FMT_22_DIV), FULL (divu), FAST (divu) }; +static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_22_div), READ (FMT_22_DIV), FULL (rem), FAST (rem) }; +static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_22_div), READ (FMT_22_DIV), FULL (remu), FAST (remu) }; +static DECODE decode_divh = { M32R_INSN_DIVH, & ITAB (M32R_INSN_DIVH), EX (fmt_22_div), READ (FMT_22_DIV), FULL (divh), FAST (divh) }; +static DECODE decode_jc = { M32R_INSN_JC, & ITAB (M32R_INSN_JC), EX (fmt_23_jc), READ (FMT_23_JC), FULL (jc), FAST (jc) }; +static DECODE decode_jnc = { M32R_INSN_JNC, & ITAB (M32R_INSN_JNC), EX (fmt_23_jc), READ (FMT_23_JC), FULL (jnc), FAST (jnc) }; +static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_24_jl), READ (FMT_24_JL), FULL (jl), FAST (jl) }; +static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_25_jmp), READ (FMT_25_JMP), FULL (jmp), FAST (jmp) }; +static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_26_ld), READ (FMT_26_LD), FULL (ld), FAST (ld) }; +static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_27_ld_d), READ (FMT_27_LD_D), FULL (ld_d), FAST (ld_d) }; +static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_28_ldb), READ (FMT_28_LDB), FULL (ldb), FAST (ldb) }; +static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_29_ldb_d), READ (FMT_29_LDB_D), FULL (ldb_d), FAST (ldb_d) }; +static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_30_ldh), READ (FMT_30_LDH), FULL (ldh), FAST (ldh) }; +static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_31_ldh_d), READ (FMT_31_LDH_D), FULL (ldh_d), FAST (ldh_d) }; +static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_28_ldb), READ (FMT_28_LDB), FULL (ldub), FAST (ldub) }; +static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_29_ldb_d), READ (FMT_29_LDB_D), FULL (ldub_d), FAST (ldub_d) }; +static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_30_ldh), READ (FMT_30_LDH), FULL (lduh), FAST (lduh) }; +static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_31_ldh_d), READ (FMT_31_LDH_D), FULL (lduh_d), FAST (lduh_d) }; +static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_32_ld_plus), READ (FMT_32_LD_PLUS), FULL (ld_plus), FAST (ld_plus) }; +static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_33_ld24), READ (FMT_33_LD24), FULL (ld24), FAST (ld24) }; +static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_34_ldi8), READ (FMT_34_LDI8), FULL (ldi8), FAST (ldi8) }; +static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_35_ldi16), READ (FMT_35_LDI16), FULL (ldi16), FAST (ldi16) }; +static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_36_lock), READ (FMT_36_LOCK), FULL (lock), FAST (lock) }; +static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & ITAB (M32R_INSN_MACHI_A), EX (fmt_37_machi_a), READ (FMT_37_MACHI_A), FULL (machi_a), FAST (machi_a) }; +static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & ITAB (M32R_INSN_MACLO_A), EX (fmt_37_machi_a), READ (FMT_37_MACHI_A), FULL (maclo_a), FAST (maclo_a) }; static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (mul), FAST (mul) }; -static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & ITAB (M32R_INSN_MULHI_A), EX (fmt_35_mulhi_a), READ (FMT_35_MULHI_A), FULL (mulhi_a), FAST (mulhi_a) }; -static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & ITAB (M32R_INSN_MULLO_A), EX (fmt_35_mulhi_a), READ (FMT_35_MULHI_A), FULL (mullo_a), FAST (mullo_a) }; -static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_36_mv), READ (FMT_36_MV), FULL (mv), FAST (mv) }; -static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & ITAB (M32R_INSN_MVFACHI_A), EX (fmt_37_mvfachi_a), READ (FMT_37_MVFACHI_A), FULL (mvfachi_a), FAST (mvfachi_a) }; -static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & ITAB (M32R_INSN_MVFACLO_A), EX (fmt_37_mvfachi_a), READ (FMT_37_MVFACHI_A), FULL (mvfaclo_a), FAST (mvfaclo_a) }; -static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & ITAB (M32R_INSN_MVFACMI_A), EX (fmt_37_mvfachi_a), READ (FMT_37_MVFACHI_A), FULL (mvfacmi_a), FAST (mvfacmi_a) }; -static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_38_mvfc), READ (FMT_38_MVFC), FULL (mvfc), FAST (mvfc) }; -static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & ITAB (M32R_INSN_MVTACHI_A), EX (fmt_39_mvtachi_a), READ (FMT_39_MVTACHI_A), FULL (mvtachi_a), FAST (mvtachi_a) }; -static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & ITAB (M32R_INSN_MVTACLO_A), EX (fmt_39_mvtachi_a), READ (FMT_39_MVTACHI_A), FULL (mvtaclo_a), FAST (mvtaclo_a) }; -static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_40_mvtc), READ (FMT_40_MVTC), FULL (mvtc), FAST (mvtc) }; -static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_36_mv), READ (FMT_36_MV), FULL (neg), FAST (neg) }; -static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_41_nop), READ (FMT_41_NOP), FULL (nop), FAST (nop) }; -static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_36_mv), READ (FMT_36_MV), FULL (not), FAST (not) }; -static DECODE decode_rac_d = { M32R_INSN_RAC_D, & ITAB (M32R_INSN_RAC_D), EX (fmt_42_rac_d), READ (FMT_42_RAC_D), FULL (rac_d), FAST (rac_d) }; -static DECODE decode_rac_ds = { M32R_INSN_RAC_DS, & ITAB (M32R_INSN_RAC_DS), EX (fmt_43_rac_ds), READ (FMT_43_RAC_DS), FULL (rac_ds), FAST (rac_ds) }; -static DECODE decode_rac_dsi = { M32R_INSN_RAC_DSI, & ITAB (M32R_INSN_RAC_DSI), EX (fmt_44_rac_dsi), READ (FMT_44_RAC_DSI), FULL (rac_dsi), FAST (rac_dsi) }; -static DECODE decode_rach_d = { M32R_INSN_RACH_D, & ITAB (M32R_INSN_RACH_D), EX (fmt_42_rac_d), READ (FMT_42_RAC_D), FULL (rach_d), FAST (rach_d) }; -static DECODE decode_rach_ds = { M32R_INSN_RACH_DS, & ITAB (M32R_INSN_RACH_DS), EX (fmt_43_rac_ds), READ (FMT_43_RAC_DS), FULL (rach_ds), FAST (rach_ds) }; -static DECODE decode_rach_dsi = { M32R_INSN_RACH_DSI, & ITAB (M32R_INSN_RACH_DSI), EX (fmt_44_rac_dsi), READ (FMT_44_RAC_DSI), FULL (rach_dsi), FAST (rach_dsi) }; -static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_45_rte), READ (FMT_45_RTE), FULL (rte), FAST (rte) }; -static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_46_seth), READ (FMT_46_SETH), FULL (seth), FAST (seth) }; +static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & ITAB (M32R_INSN_MULHI_A), EX (fmt_38_mulhi_a), READ (FMT_38_MULHI_A), FULL (mulhi_a), FAST (mulhi_a) }; +static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & ITAB (M32R_INSN_MULLO_A), EX (fmt_38_mulhi_a), READ (FMT_38_MULHI_A), FULL (mullo_a), FAST (mullo_a) }; +static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_39_mv), READ (FMT_39_MV), FULL (mv), FAST (mv) }; +static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & ITAB (M32R_INSN_MVFACHI_A), EX (fmt_40_mvfachi_a), READ (FMT_40_MVFACHI_A), FULL (mvfachi_a), FAST (mvfachi_a) }; +static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & ITAB (M32R_INSN_MVFACLO_A), EX (fmt_40_mvfachi_a), READ (FMT_40_MVFACHI_A), FULL (mvfaclo_a), FAST (mvfaclo_a) }; +static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & ITAB (M32R_INSN_MVFACMI_A), EX (fmt_40_mvfachi_a), READ (FMT_40_MVFACHI_A), FULL (mvfacmi_a), FAST (mvfacmi_a) }; +static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_41_mvfc), READ (FMT_41_MVFC), FULL (mvfc), FAST (mvfc) }; +static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & ITAB (M32R_INSN_MVTACHI_A), EX (fmt_42_mvtachi_a), READ (FMT_42_MVTACHI_A), FULL (mvtachi_a), FAST (mvtachi_a) }; +static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & ITAB (M32R_INSN_MVTACLO_A), EX (fmt_42_mvtachi_a), READ (FMT_42_MVTACHI_A), FULL (mvtaclo_a), FAST (mvtaclo_a) }; +static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_43_mvtc), READ (FMT_43_MVTC), FULL (mvtc), FAST (mvtc) }; +static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_39_mv), READ (FMT_39_MV), FULL (neg), FAST (neg) }; +static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_44_nop), READ (FMT_44_NOP), FULL (nop), FAST (nop) }; +static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_39_mv), READ (FMT_39_MV), FULL (not), FAST (not) }; +static DECODE decode_rac_dsi = { M32R_INSN_RAC_DSI, & ITAB (M32R_INSN_RAC_DSI), EX (fmt_45_rac_dsi), READ (FMT_45_RAC_DSI), FULL (rac_dsi), FAST (rac_dsi) }; +static DECODE decode_rach_dsi = { M32R_INSN_RACH_DSI, & ITAB (M32R_INSN_RACH_DSI), EX (fmt_45_rac_dsi), READ (FMT_45_RAC_DSI), FULL (rach_dsi), FAST (rach_dsi) }; +static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_46_rte), READ (FMT_46_RTE), FULL (rte), FAST (rte) }; +static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_47_seth), READ (FMT_47_SETH), FULL (seth), FAST (seth) }; static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sll), FAST (sll) }; -static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (sll3), FAST (sll3) }; -static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_47_slli), READ (FMT_47_SLLI), FULL (slli), FAST (slli) }; +static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_48_sll3), READ (FMT_48_SLL3), FULL (sll3), FAST (sll3) }; +static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_49_slli), READ (FMT_49_SLLI), FULL (slli), FAST (slli) }; static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sra), FAST (sra) }; -static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (sra3), FAST (sra3) }; -static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_47_slli), READ (FMT_47_SLLI), FULL (srai), FAST (srai) }; +static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_48_sll3), READ (FMT_48_SLL3), FULL (sra3), FAST (sra3) }; +static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_49_slli), READ (FMT_49_SLLI), FULL (srai), FAST (srai) }; static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (srl), FAST (srl) }; -static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (srl3), FAST (srl3) }; -static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_47_slli), READ (FMT_47_SLLI), FULL (srli), FAST (srli) }; -static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (st), FAST (st) }; -static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_48_st_d), READ (FMT_48_ST_D), FULL (st_d), FAST (st_d) }; -static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (stb), FAST (stb) }; -static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_48_st_d), READ (FMT_48_ST_D), FULL (stb_d), FAST (stb_d) }; -static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (sth), FAST (sth) }; -static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_48_st_d), READ (FMT_48_ST_D), FULL (sth_d), FAST (sth_d) }; -static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (st_plus), FAST (st_plus) }; -static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (st_minus), FAST (st_minus) }; +static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_48_sll3), READ (FMT_48_SLL3), FULL (srl3), FAST (srl3) }; +static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_49_slli), READ (FMT_49_SLLI), FULL (srli), FAST (srli) }; +static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_50_st), READ (FMT_50_ST), FULL (st), FAST (st) }; +static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_51_st_d), READ (FMT_51_ST_D), FULL (st_d), FAST (st_d) }; +static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_52_stb), READ (FMT_52_STB), FULL (stb), FAST (stb) }; +static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_53_stb_d), READ (FMT_53_STB_D), FULL (stb_d), FAST (stb_d) }; +static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_54_sth), READ (FMT_54_STH), FULL (sth), FAST (sth) }; +static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_55_sth_d), READ (FMT_55_STH_D), FULL (sth_d), FAST (sth_d) }; +static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_56_st_plus), READ (FMT_56_ST_PLUS), FULL (st_plus), FAST (st_plus) }; +static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_56_st_plus), READ (FMT_56_ST_PLUS), FULL (st_minus), FAST (st_minus) }; static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sub), FAST (sub) }; -static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_0_add), READ (FMT_0_ADD), FULL (subv), FAST (subv) }; -static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_6_addx), READ (FMT_6_ADDX), FULL (subx), FAST (subx) }; -static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_49_trap), READ (FMT_49_TRAP), FULL (trap), FAST (trap) }; -static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (unlock), FAST (unlock) }; -static DECODE decode_satb = { M32R_INSN_SATB, & ITAB (M32R_INSN_SATB), EX (fmt_50_satb), READ (FMT_50_SATB), FULL (satb), FAST (satb) }; -static DECODE decode_sath = { M32R_INSN_SATH, & ITAB (M32R_INSN_SATH), EX (fmt_50_satb), READ (FMT_50_SATB), FULL (sath), FAST (sath) }; -static DECODE decode_sat = { M32R_INSN_SAT, & ITAB (M32R_INSN_SAT), EX (fmt_51_sat), READ (FMT_51_SAT), FULL (sat), FAST (sat) }; -static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & ITAB (M32R_INSN_PCMPBZ), EX (fmt_20_cmpz), READ (FMT_20_CMPZ), FULL (pcmpbz), FAST (pcmpbz) }; -static DECODE decode_sadd = { M32R_INSN_SADD, & ITAB (M32R_INSN_SADD), EX (fmt_52_sadd), READ (FMT_52_SADD), FULL (sadd), FAST (sadd) }; -static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & ITAB (M32R_INSN_MACWU1), EX (fmt_53_macwu1), READ (FMT_53_MACWU1), FULL (macwu1), FAST (macwu1) }; -static DECODE decode_msblo = { M32R_INSN_MSBLO, & ITAB (M32R_INSN_MSBLO), EX (fmt_54_msblo), READ (FMT_54_MSBLO), FULL (msblo), FAST (msblo) }; -static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & ITAB (M32R_INSN_MULWU1), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (mulwu1), FAST (mulwu1) }; -static DECODE decode_maclh1 = { M32R_INSN_MACLH1, & ITAB (M32R_INSN_MACLH1), EX (fmt_53_macwu1), READ (FMT_53_MACWU1), FULL (maclh1), FAST (maclh1) }; -static DECODE decode_sc = { M32R_INSN_SC, & ITAB (M32R_INSN_SC), EX (fmt_55_sc), READ (FMT_55_SC), FULL (sc), FAST (sc) }; -static DECODE decode_snc = { M32R_INSN_SNC, & ITAB (M32R_INSN_SNC), EX (fmt_55_sc), READ (FMT_55_SC), FULL (snc), FAST (snc) }; +static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_5_addv), READ (FMT_5_ADDV), FULL (subv), FAST (subv) }; +static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_7_addx), READ (FMT_7_ADDX), FULL (subx), FAST (subx) }; +static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_57_trap), READ (FMT_57_TRAP), FULL (trap), FAST (trap) }; +static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_58_unlock), READ (FMT_58_UNLOCK), FULL (unlock), FAST (unlock) }; +static DECODE decode_satb = { M32R_INSN_SATB, & ITAB (M32R_INSN_SATB), EX (fmt_59_satb), READ (FMT_59_SATB), FULL (satb), FAST (satb) }; +static DECODE decode_sath = { M32R_INSN_SATH, & ITAB (M32R_INSN_SATH), EX (fmt_59_satb), READ (FMT_59_SATB), FULL (sath), FAST (sath) }; +static DECODE decode_sat = { M32R_INSN_SAT, & ITAB (M32R_INSN_SAT), EX (fmt_60_sat), READ (FMT_60_SAT), FULL (sat), FAST (sat) }; +static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & ITAB (M32R_INSN_PCMPBZ), EX (fmt_21_cmpz), READ (FMT_21_CMPZ), FULL (pcmpbz), FAST (pcmpbz) }; +static DECODE decode_sadd = { M32R_INSN_SADD, & ITAB (M32R_INSN_SADD), EX (fmt_61_sadd), READ (FMT_61_SADD), FULL (sadd), FAST (sadd) }; +static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & ITAB (M32R_INSN_MACWU1), EX (fmt_62_macwu1), READ (FMT_62_MACWU1), FULL (macwu1), FAST (macwu1) }; +static DECODE decode_msblo = { M32R_INSN_MSBLO, & ITAB (M32R_INSN_MSBLO), EX (fmt_63_msblo), READ (FMT_63_MSBLO), FULL (msblo), FAST (msblo) }; +static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & ITAB (M32R_INSN_MULWU1), EX (fmt_64_mulwu1), READ (FMT_64_MULWU1), FULL (mulwu1), FAST (mulwu1) }; +static DECODE decode_maclh1 = { M32R_INSN_MACLH1, & ITAB (M32R_INSN_MACLH1), EX (fmt_62_macwu1), READ (FMT_62_MACWU1), FULL (maclh1), FAST (maclh1) }; +static DECODE decode_sc = { M32R_INSN_SC, & ITAB (M32R_INSN_SC), EX (fmt_65_sc), READ (FMT_65_SC), FULL (sc), FAST (sc) }; +static DECODE decode_snc = { M32R_INSN_SNC, & ITAB (M32R_INSN_SNC), EX (fmt_65_sc), READ (FMT_65_SC), FULL (snc), FAST (snc) }; DECODE m32rx_decode_illegal = { M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL), @@ -279,11 +277,7 @@ DECODE *m32rx_decode_vars[] = { & decode_neg, & decode_nop, & decode_not, - & decode_rac_d, - & decode_rac_ds, & decode_rac_dsi, - & decode_rach_d, - & decode_rach_ds, & decode_rach_dsi, & decode_rte, & decode_seth, @@ -363,7 +357,7 @@ m32rx_decode (current_cpu, pc, insn) && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && case_0_87, - && case_0_88, && case_0_89, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && case_0_95, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, && default_0, @@ -430,7 +424,7 @@ m32rx_decode (current_cpu, pc, insn) &decode_addi, &decode_addi, &decode_addi, &decode_addi, &decode_srli, &decode_srli, &decode_srai, &decode_srai, &decode_slli, &decode_slli, &decode_illegal, 0, - 0, 0, &decode_mulwu1, &decode_macwu1, + &decode_rach_dsi, &decode_rac_dsi, &decode_mulwu1, &decode_macwu1, &decode_maclh1, &decode_msblo, &decode_sadd, 0, &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, @@ -507,90 +501,6 @@ m32rx_decode (current_cpu, pc, insn) unsigned int val = (((insn >> 0) & (3 << 0))); return insns[val]; } - CASE (0, 88) : - { -#ifdef __GNUC__ - static void *labels_0_88[16] = { - && case_0_88_0, && case_0_88_1, && case_0_88_2, && case_0_88_3, - && default_0_88, && default_0_88, && default_0_88, && default_0_88, - && default_0_88, && default_0_88, && default_0_88, && default_0_88, - && default_0_88, && default_0_88, && default_0_88, && default_0_88, - }; -#endif - static DECODE *insns[16] = { - 0, 0, 0, 0, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val; - val = (((insn >> 6) & (3 << 2)) | ((insn >> 2) & (3 << 0))); - DECODE_SWITCH (0_88, val) - { - CASE (0_88, 0) : - { - static DECODE *insns[4] = { - &decode_rach_d, &decode_rach_dsi, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 0) & (3 << 0))); - return insns[val]; - } - CASE (0_88, 1) : /* fall through */ - CASE (0_88, 2) : /* fall through */ - CASE (0_88, 3) : - { - static DECODE *insns[4] = { - &decode_rach_ds, &decode_rach_dsi, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 0) & (3 << 0))); - return insns[val]; - } - DEFAULT (0_88) : return insns[val]; - } - ENDSWITCH (0_88) - } - CASE (0, 89) : - { -#ifdef __GNUC__ - static void *labels_0_89[16] = { - && case_0_89_0, && case_0_89_1, && case_0_89_2, && case_0_89_3, - && default_0_89, && default_0_89, && default_0_89, && default_0_89, - && default_0_89, && default_0_89, && default_0_89, && default_0_89, - && default_0_89, && default_0_89, && default_0_89, && default_0_89, - }; -#endif - static DECODE *insns[16] = { - 0, 0, 0, 0, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, - }; - unsigned int val; - val = (((insn >> 6) & (3 << 2)) | ((insn >> 2) & (3 << 0))); - DECODE_SWITCH (0_89, val) - { - CASE (0_89, 0) : - { - static DECODE *insns[4] = { - &decode_rac_d, &decode_rac_dsi, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 0) & (3 << 0))); - return insns[val]; - } - CASE (0_89, 1) : /* fall through */ - CASE (0_89, 2) : /* fall through */ - CASE (0_89, 3) : - { - static DECODE *insns[4] = { - &decode_rac_ds, &decode_rac_dsi, &decode_illegal, &decode_illegal, - }; - unsigned int val = (((insn >> 0) & (3 << 0))); - return insns[val]; - } - DEFAULT (0_89) : return insns[val]; - } - ENDSWITCH (0_89) - } CASE (0, 95) : { static DECODE *insns[4] = { diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h index a8b4f41..af271df 100644 --- a/sim/m32r/decodex.h +++ b/sim/m32r/decodex.h @@ -27,310 +27,311 @@ with this program; if not, write to the Free Software Foundation, Inc., #define EX(fn) XCONCAT3 (m32rx,_ex_,fn) #define SEM(fn) XCONCAT3 (m32rx,_sem_,fn) -#define SEMC(fn) XCONCAT3 (m32rx,_semc_,fn) +#define SEMF(fn) XCONCAT3 (m32rx,_semf_,fn) extern EXTRACT_FN EX (illegal); extern SEMANTIC_FN SEM (illegal); -extern SEMANTIC_CACHE_FN SEMC (illegal); - +extern SEMANTIC_FN SEMF (illegal); extern EXTRACT_FN EX (fmt_0_add); extern EXTRACT_FN EX (fmt_1_add3); extern EXTRACT_FN EX (fmt_2_and3); extern EXTRACT_FN EX (fmt_3_or3); extern EXTRACT_FN EX (fmt_4_addi); -extern EXTRACT_FN EX (fmt_5_addv3); -extern EXTRACT_FN EX (fmt_6_addx); -extern EXTRACT_FN EX (fmt_7_bc8); -extern EXTRACT_FN EX (fmt_8_bc24); -extern EXTRACT_FN EX (fmt_9_beq); -extern EXTRACT_FN EX (fmt_10_beqz); -extern EXTRACT_FN EX (fmt_11_bl8); -extern EXTRACT_FN EX (fmt_12_bl24); -extern EXTRACT_FN EX (fmt_13_bcl8); -extern EXTRACT_FN EX (fmt_14_bcl24); -extern EXTRACT_FN EX (fmt_15_bra8); -extern EXTRACT_FN EX (fmt_16_bra24); -extern EXTRACT_FN EX (fmt_17_cmp); -extern EXTRACT_FN EX (fmt_18_cmpi); -extern EXTRACT_FN EX (fmt_19_cmpui); -extern EXTRACT_FN EX (fmt_20_cmpz); -extern EXTRACT_FN EX (fmt_21_div); -extern EXTRACT_FN EX (fmt_22_jc); -extern EXTRACT_FN EX (fmt_23_jl); -extern EXTRACT_FN EX (fmt_24_jmp); -extern EXTRACT_FN EX (fmt_25_ld); -extern EXTRACT_FN EX (fmt_26_ld_d); -extern EXTRACT_FN EX (fmt_27_ldb); -extern EXTRACT_FN EX (fmt_28_ldb_d); -extern EXTRACT_FN EX (fmt_29_ldh); -extern EXTRACT_FN EX (fmt_30_ldh_d); -extern EXTRACT_FN EX (fmt_31_ld24); -extern EXTRACT_FN EX (fmt_32_ldi8); -extern EXTRACT_FN EX (fmt_33_ldi16); -extern EXTRACT_FN EX (fmt_34_machi_a); -extern EXTRACT_FN EX (fmt_35_mulhi_a); -extern EXTRACT_FN EX (fmt_36_mv); -extern EXTRACT_FN EX (fmt_37_mvfachi_a); -extern EXTRACT_FN EX (fmt_38_mvfc); -extern EXTRACT_FN EX (fmt_39_mvtachi_a); -extern EXTRACT_FN EX (fmt_40_mvtc); -extern EXTRACT_FN EX (fmt_41_nop); -extern EXTRACT_FN EX (fmt_42_rac_d); -extern EXTRACT_FN EX (fmt_43_rac_ds); -extern EXTRACT_FN EX (fmt_44_rac_dsi); -extern EXTRACT_FN EX (fmt_45_rte); -extern EXTRACT_FN EX (fmt_46_seth); -extern EXTRACT_FN EX (fmt_47_slli); -extern EXTRACT_FN EX (fmt_48_st_d); -extern EXTRACT_FN EX (fmt_49_trap); -extern EXTRACT_FN EX (fmt_50_satb); -extern EXTRACT_FN EX (fmt_51_sat); -extern EXTRACT_FN EX (fmt_52_sadd); -extern EXTRACT_FN EX (fmt_53_macwu1); -extern EXTRACT_FN EX (fmt_54_msblo); -extern EXTRACT_FN EX (fmt_55_sc); +extern EXTRACT_FN EX (fmt_5_addv); +extern EXTRACT_FN EX (fmt_6_addv3); +extern EXTRACT_FN EX (fmt_7_addx); +extern EXTRACT_FN EX (fmt_8_bc8); +extern EXTRACT_FN EX (fmt_9_bc24); +extern EXTRACT_FN EX (fmt_10_beq); +extern EXTRACT_FN EX (fmt_11_beqz); +extern EXTRACT_FN EX (fmt_12_bl8); +extern EXTRACT_FN EX (fmt_13_bl24); +extern EXTRACT_FN EX (fmt_14_bcl8); +extern EXTRACT_FN EX (fmt_15_bcl24); +extern EXTRACT_FN EX (fmt_16_bra8); +extern EXTRACT_FN EX (fmt_17_bra24); +extern EXTRACT_FN EX (fmt_18_cmp); +extern EXTRACT_FN EX (fmt_19_cmpi); +extern EXTRACT_FN EX (fmt_20_cmpui); +extern EXTRACT_FN EX (fmt_21_cmpz); +extern EXTRACT_FN EX (fmt_22_div); +extern EXTRACT_FN EX (fmt_23_jc); +extern EXTRACT_FN EX (fmt_24_jl); +extern EXTRACT_FN EX (fmt_25_jmp); +extern EXTRACT_FN EX (fmt_26_ld); +extern EXTRACT_FN EX (fmt_27_ld_d); +extern EXTRACT_FN EX (fmt_28_ldb); +extern EXTRACT_FN EX (fmt_29_ldb_d); +extern EXTRACT_FN EX (fmt_30_ldh); +extern EXTRACT_FN EX (fmt_31_ldh_d); +extern EXTRACT_FN EX (fmt_32_ld_plus); +extern EXTRACT_FN EX (fmt_33_ld24); +extern EXTRACT_FN EX (fmt_34_ldi8); +extern EXTRACT_FN EX (fmt_35_ldi16); +extern EXTRACT_FN EX (fmt_36_lock); +extern EXTRACT_FN EX (fmt_37_machi_a); +extern EXTRACT_FN EX (fmt_38_mulhi_a); +extern EXTRACT_FN EX (fmt_39_mv); +extern EXTRACT_FN EX (fmt_40_mvfachi_a); +extern EXTRACT_FN EX (fmt_41_mvfc); +extern EXTRACT_FN EX (fmt_42_mvtachi_a); +extern EXTRACT_FN EX (fmt_43_mvtc); +extern EXTRACT_FN EX (fmt_44_nop); +extern EXTRACT_FN EX (fmt_45_rac_dsi); +extern EXTRACT_FN EX (fmt_46_rte); +extern EXTRACT_FN EX (fmt_47_seth); +extern EXTRACT_FN EX (fmt_48_sll3); +extern EXTRACT_FN EX (fmt_49_slli); +extern EXTRACT_FN EX (fmt_50_st); +extern EXTRACT_FN EX (fmt_51_st_d); +extern EXTRACT_FN EX (fmt_52_stb); +extern EXTRACT_FN EX (fmt_53_stb_d); +extern EXTRACT_FN EX (fmt_54_sth); +extern EXTRACT_FN EX (fmt_55_sth_d); +extern EXTRACT_FN EX (fmt_56_st_plus); +extern EXTRACT_FN EX (fmt_57_trap); +extern EXTRACT_FN EX (fmt_58_unlock); +extern EXTRACT_FN EX (fmt_59_satb); +extern EXTRACT_FN EX (fmt_60_sat); +extern EXTRACT_FN EX (fmt_61_sadd); +extern EXTRACT_FN EX (fmt_62_macwu1); +extern EXTRACT_FN EX (fmt_63_msblo); +extern EXTRACT_FN EX (fmt_64_mulwu1); +extern EXTRACT_FN EX (fmt_65_sc); extern SEMANTIC_FN SEM (add); -extern SEMANTIC_CACHE_FN SEMC (add); +extern SEMANTIC_FN SEMF (add); extern SEMANTIC_FN SEM (add3); -extern SEMANTIC_CACHE_FN SEMC (add3); +extern SEMANTIC_FN SEMF (add3); extern SEMANTIC_FN SEM (and); -extern SEMANTIC_CACHE_FN SEMC (and); +extern SEMANTIC_FN SEMF (and); extern SEMANTIC_FN SEM (and3); -extern SEMANTIC_CACHE_FN SEMC (and3); +extern SEMANTIC_FN SEMF (and3); extern SEMANTIC_FN SEM (or); -extern SEMANTIC_CACHE_FN SEMC (or); +extern SEMANTIC_FN SEMF (or); extern SEMANTIC_FN SEM (or3); -extern SEMANTIC_CACHE_FN SEMC (or3); +extern SEMANTIC_FN SEMF (or3); extern SEMANTIC_FN SEM (xor); -extern SEMANTIC_CACHE_FN SEMC (xor); +extern SEMANTIC_FN SEMF (xor); extern SEMANTIC_FN SEM (xor3); -extern SEMANTIC_CACHE_FN SEMC (xor3); +extern SEMANTIC_FN SEMF (xor3); extern SEMANTIC_FN SEM (addi); -extern SEMANTIC_CACHE_FN SEMC (addi); +extern SEMANTIC_FN SEMF (addi); extern SEMANTIC_FN SEM (addv); -extern SEMANTIC_CACHE_FN SEMC (addv); +extern SEMANTIC_FN SEMF (addv); extern SEMANTIC_FN SEM (addv3); -extern SEMANTIC_CACHE_FN SEMC (addv3); +extern SEMANTIC_FN SEMF (addv3); extern SEMANTIC_FN SEM (addx); -extern SEMANTIC_CACHE_FN SEMC (addx); +extern SEMANTIC_FN SEMF (addx); extern SEMANTIC_FN SEM (bc8); -extern SEMANTIC_CACHE_FN SEMC (bc8); +extern SEMANTIC_FN SEMF (bc8); extern SEMANTIC_FN SEM (bc24); -extern SEMANTIC_CACHE_FN SEMC (bc24); +extern SEMANTIC_FN SEMF (bc24); extern SEMANTIC_FN SEM (beq); -extern SEMANTIC_CACHE_FN SEMC (beq); +extern SEMANTIC_FN SEMF (beq); extern SEMANTIC_FN SEM (beqz); -extern SEMANTIC_CACHE_FN SEMC (beqz); +extern SEMANTIC_FN SEMF (beqz); extern SEMANTIC_FN SEM (bgez); -extern SEMANTIC_CACHE_FN SEMC (bgez); +extern SEMANTIC_FN SEMF (bgez); extern SEMANTIC_FN SEM (bgtz); -extern SEMANTIC_CACHE_FN SEMC (bgtz); +extern SEMANTIC_FN SEMF (bgtz); extern SEMANTIC_FN SEM (blez); -extern SEMANTIC_CACHE_FN SEMC (blez); +extern SEMANTIC_FN SEMF (blez); extern SEMANTIC_FN SEM (bltz); -extern SEMANTIC_CACHE_FN SEMC (bltz); +extern SEMANTIC_FN SEMF (bltz); extern SEMANTIC_FN SEM (bnez); -extern SEMANTIC_CACHE_FN SEMC (bnez); +extern SEMANTIC_FN SEMF (bnez); extern SEMANTIC_FN SEM (bl8); -extern SEMANTIC_CACHE_FN SEMC (bl8); +extern SEMANTIC_FN SEMF (bl8); extern SEMANTIC_FN SEM (bl24); -extern SEMANTIC_CACHE_FN SEMC (bl24); +extern SEMANTIC_FN SEMF (bl24); extern SEMANTIC_FN SEM (bcl8); -extern SEMANTIC_CACHE_FN SEMC (bcl8); +extern SEMANTIC_FN SEMF (bcl8); extern SEMANTIC_FN SEM (bcl24); -extern SEMANTIC_CACHE_FN SEMC (bcl24); +extern SEMANTIC_FN SEMF (bcl24); extern SEMANTIC_FN SEM (bnc8); -extern SEMANTIC_CACHE_FN SEMC (bnc8); +extern SEMANTIC_FN SEMF (bnc8); extern SEMANTIC_FN SEM (bnc24); -extern SEMANTIC_CACHE_FN SEMC (bnc24); +extern SEMANTIC_FN SEMF (bnc24); extern SEMANTIC_FN SEM (bne); -extern SEMANTIC_CACHE_FN SEMC (bne); +extern SEMANTIC_FN SEMF (bne); extern SEMANTIC_FN SEM (bra8); -extern SEMANTIC_CACHE_FN SEMC (bra8); +extern SEMANTIC_FN SEMF (bra8); extern SEMANTIC_FN SEM (bra24); -extern SEMANTIC_CACHE_FN SEMC (bra24); +extern SEMANTIC_FN SEMF (bra24); extern SEMANTIC_FN SEM (bncl8); -extern SEMANTIC_CACHE_FN SEMC (bncl8); +extern SEMANTIC_FN SEMF (bncl8); extern SEMANTIC_FN SEM (bncl24); -extern SEMANTIC_CACHE_FN SEMC (bncl24); +extern SEMANTIC_FN SEMF (bncl24); extern SEMANTIC_FN SEM (cmp); -extern SEMANTIC_CACHE_FN SEMC (cmp); +extern SEMANTIC_FN SEMF (cmp); extern SEMANTIC_FN SEM (cmpi); -extern SEMANTIC_CACHE_FN SEMC (cmpi); +extern SEMANTIC_FN SEMF (cmpi); extern SEMANTIC_FN SEM (cmpu); -extern SEMANTIC_CACHE_FN SEMC (cmpu); +extern SEMANTIC_FN SEMF (cmpu); extern SEMANTIC_FN SEM (cmpui); -extern SEMANTIC_CACHE_FN SEMC (cmpui); +extern SEMANTIC_FN SEMF (cmpui); extern SEMANTIC_FN SEM (cmpeq); -extern SEMANTIC_CACHE_FN SEMC (cmpeq); +extern SEMANTIC_FN SEMF (cmpeq); extern SEMANTIC_FN SEM (cmpz); -extern SEMANTIC_CACHE_FN SEMC (cmpz); +extern SEMANTIC_FN SEMF (cmpz); extern SEMANTIC_FN SEM (div); -extern SEMANTIC_CACHE_FN SEMC (div); +extern SEMANTIC_FN SEMF (div); extern SEMANTIC_FN SEM (divu); -extern SEMANTIC_CACHE_FN SEMC (divu); +extern SEMANTIC_FN SEMF (divu); extern SEMANTIC_FN SEM (rem); -extern SEMANTIC_CACHE_FN SEMC (rem); +extern SEMANTIC_FN SEMF (rem); extern SEMANTIC_FN SEM (remu); -extern SEMANTIC_CACHE_FN SEMC (remu); +extern SEMANTIC_FN SEMF (remu); extern SEMANTIC_FN SEM (divh); -extern SEMANTIC_CACHE_FN SEMC (divh); +extern SEMANTIC_FN SEMF (divh); extern SEMANTIC_FN SEM (jc); -extern SEMANTIC_CACHE_FN SEMC (jc); +extern SEMANTIC_FN SEMF (jc); extern SEMANTIC_FN SEM (jnc); -extern SEMANTIC_CACHE_FN SEMC (jnc); +extern SEMANTIC_FN SEMF (jnc); extern SEMANTIC_FN SEM (jl); -extern SEMANTIC_CACHE_FN SEMC (jl); +extern SEMANTIC_FN SEMF (jl); extern SEMANTIC_FN SEM (jmp); -extern SEMANTIC_CACHE_FN SEMC (jmp); +extern SEMANTIC_FN SEMF (jmp); extern SEMANTIC_FN SEM (ld); -extern SEMANTIC_CACHE_FN SEMC (ld); +extern SEMANTIC_FN SEMF (ld); extern SEMANTIC_FN SEM (ld_d); -extern SEMANTIC_CACHE_FN SEMC (ld_d); +extern SEMANTIC_FN SEMF (ld_d); extern SEMANTIC_FN SEM (ldb); -extern SEMANTIC_CACHE_FN SEMC (ldb); +extern SEMANTIC_FN SEMF (ldb); extern SEMANTIC_FN SEM (ldb_d); -extern SEMANTIC_CACHE_FN SEMC (ldb_d); +extern SEMANTIC_FN SEMF (ldb_d); extern SEMANTIC_FN SEM (ldh); -extern SEMANTIC_CACHE_FN SEMC (ldh); +extern SEMANTIC_FN SEMF (ldh); extern SEMANTIC_FN SEM (ldh_d); -extern SEMANTIC_CACHE_FN SEMC (ldh_d); +extern SEMANTIC_FN SEMF (ldh_d); extern SEMANTIC_FN SEM (ldub); -extern SEMANTIC_CACHE_FN SEMC (ldub); +extern SEMANTIC_FN SEMF (ldub); extern SEMANTIC_FN SEM (ldub_d); -extern SEMANTIC_CACHE_FN SEMC (ldub_d); +extern SEMANTIC_FN SEMF (ldub_d); extern SEMANTIC_FN SEM (lduh); -extern SEMANTIC_CACHE_FN SEMC (lduh); +extern SEMANTIC_FN SEMF (lduh); extern SEMANTIC_FN SEM (lduh_d); -extern SEMANTIC_CACHE_FN SEMC (lduh_d); +extern SEMANTIC_FN SEMF (lduh_d); extern SEMANTIC_FN SEM (ld_plus); -extern SEMANTIC_CACHE_FN SEMC (ld_plus); +extern SEMANTIC_FN SEMF (ld_plus); extern SEMANTIC_FN SEM (ld24); -extern SEMANTIC_CACHE_FN SEMC (ld24); +extern SEMANTIC_FN SEMF (ld24); extern SEMANTIC_FN SEM (ldi8); -extern SEMANTIC_CACHE_FN SEMC (ldi8); +extern SEMANTIC_FN SEMF (ldi8); extern SEMANTIC_FN SEM (ldi16); -extern SEMANTIC_CACHE_FN SEMC (ldi16); +extern SEMANTIC_FN SEMF (ldi16); extern SEMANTIC_FN SEM (lock); -extern SEMANTIC_CACHE_FN SEMC (lock); +extern SEMANTIC_FN SEMF (lock); extern SEMANTIC_FN SEM (machi_a); -extern SEMANTIC_CACHE_FN SEMC (machi_a); +extern SEMANTIC_FN SEMF (machi_a); extern SEMANTIC_FN SEM (maclo_a); -extern SEMANTIC_CACHE_FN SEMC (maclo_a); +extern SEMANTIC_FN SEMF (maclo_a); extern SEMANTIC_FN SEM (mul); -extern SEMANTIC_CACHE_FN SEMC (mul); +extern SEMANTIC_FN SEMF (mul); extern SEMANTIC_FN SEM (mulhi_a); -extern SEMANTIC_CACHE_FN SEMC (mulhi_a); +extern SEMANTIC_FN SEMF (mulhi_a); extern SEMANTIC_FN SEM (mullo_a); -extern SEMANTIC_CACHE_FN SEMC (mullo_a); +extern SEMANTIC_FN SEMF (mullo_a); extern SEMANTIC_FN SEM (mv); -extern SEMANTIC_CACHE_FN SEMC (mv); +extern SEMANTIC_FN SEMF (mv); extern SEMANTIC_FN SEM (mvfachi_a); -extern SEMANTIC_CACHE_FN SEMC (mvfachi_a); +extern SEMANTIC_FN SEMF (mvfachi_a); extern SEMANTIC_FN SEM (mvfaclo_a); -extern SEMANTIC_CACHE_FN SEMC (mvfaclo_a); +extern SEMANTIC_FN SEMF (mvfaclo_a); extern SEMANTIC_FN SEM (mvfacmi_a); -extern SEMANTIC_CACHE_FN SEMC (mvfacmi_a); +extern SEMANTIC_FN SEMF (mvfacmi_a); extern SEMANTIC_FN SEM (mvfc); -extern SEMANTIC_CACHE_FN SEMC (mvfc); +extern SEMANTIC_FN SEMF (mvfc); extern SEMANTIC_FN SEM (mvtachi_a); -extern SEMANTIC_CACHE_FN SEMC (mvtachi_a); +extern SEMANTIC_FN SEMF (mvtachi_a); extern SEMANTIC_FN SEM (mvtaclo_a); -extern SEMANTIC_CACHE_FN SEMC (mvtaclo_a); +extern SEMANTIC_FN SEMF (mvtaclo_a); extern SEMANTIC_FN SEM (mvtc); -extern SEMANTIC_CACHE_FN SEMC (mvtc); +extern SEMANTIC_FN SEMF (mvtc); extern SEMANTIC_FN SEM (neg); -extern SEMANTIC_CACHE_FN SEMC (neg); +extern SEMANTIC_FN SEMF (neg); extern SEMANTIC_FN SEM (nop); -extern SEMANTIC_CACHE_FN SEMC (nop); +extern SEMANTIC_FN SEMF (nop); extern SEMANTIC_FN SEM (not); -extern SEMANTIC_CACHE_FN SEMC (not); -extern SEMANTIC_FN SEM (rac_d); -extern SEMANTIC_CACHE_FN SEMC (rac_d); -extern SEMANTIC_FN SEM (rac_ds); -extern SEMANTIC_CACHE_FN SEMC (rac_ds); +extern SEMANTIC_FN SEMF (not); extern SEMANTIC_FN SEM (rac_dsi); -extern SEMANTIC_CACHE_FN SEMC (rac_dsi); -extern SEMANTIC_FN SEM (rach_d); -extern SEMANTIC_CACHE_FN SEMC (rach_d); -extern SEMANTIC_FN SEM (rach_ds); -extern SEMANTIC_CACHE_FN SEMC (rach_ds); +extern SEMANTIC_FN SEMF (rac_dsi); extern SEMANTIC_FN SEM (rach_dsi); -extern SEMANTIC_CACHE_FN SEMC (rach_dsi); +extern SEMANTIC_FN SEMF (rach_dsi); extern SEMANTIC_FN SEM (rte); -extern SEMANTIC_CACHE_FN SEMC (rte); +extern SEMANTIC_FN SEMF (rte); extern SEMANTIC_FN SEM (seth); -extern SEMANTIC_CACHE_FN SEMC (seth); +extern SEMANTIC_FN SEMF (seth); extern SEMANTIC_FN SEM (sll); -extern SEMANTIC_CACHE_FN SEMC (sll); +extern SEMANTIC_FN SEMF (sll); extern SEMANTIC_FN SEM (sll3); -extern SEMANTIC_CACHE_FN SEMC (sll3); +extern SEMANTIC_FN SEMF (sll3); extern SEMANTIC_FN SEM (slli); -extern SEMANTIC_CACHE_FN SEMC (slli); +extern SEMANTIC_FN SEMF (slli); extern SEMANTIC_FN SEM (sra); -extern SEMANTIC_CACHE_FN SEMC (sra); +extern SEMANTIC_FN SEMF (sra); extern SEMANTIC_FN SEM (sra3); -extern SEMANTIC_CACHE_FN SEMC (sra3); +extern SEMANTIC_FN SEMF (sra3); extern SEMANTIC_FN SEM (srai); -extern SEMANTIC_CACHE_FN SEMC (srai); +extern SEMANTIC_FN SEMF (srai); extern SEMANTIC_FN SEM (srl); -extern SEMANTIC_CACHE_FN SEMC (srl); +extern SEMANTIC_FN SEMF (srl); extern SEMANTIC_FN SEM (srl3); -extern SEMANTIC_CACHE_FN SEMC (srl3); +extern SEMANTIC_FN SEMF (srl3); extern SEMANTIC_FN SEM (srli); -extern SEMANTIC_CACHE_FN SEMC (srli); +extern SEMANTIC_FN SEMF (srli); extern SEMANTIC_FN SEM (st); -extern SEMANTIC_CACHE_FN SEMC (st); +extern SEMANTIC_FN SEMF (st); extern SEMANTIC_FN SEM (st_d); -extern SEMANTIC_CACHE_FN SEMC (st_d); +extern SEMANTIC_FN SEMF (st_d); extern SEMANTIC_FN SEM (stb); -extern SEMANTIC_CACHE_FN SEMC (stb); +extern SEMANTIC_FN SEMF (stb); extern SEMANTIC_FN SEM (stb_d); -extern SEMANTIC_CACHE_FN SEMC (stb_d); +extern SEMANTIC_FN SEMF (stb_d); extern SEMANTIC_FN SEM (sth); -extern SEMANTIC_CACHE_FN SEMC (sth); +extern SEMANTIC_FN SEMF (sth); extern SEMANTIC_FN SEM (sth_d); -extern SEMANTIC_CACHE_FN SEMC (sth_d); +extern SEMANTIC_FN SEMF (sth_d); extern SEMANTIC_FN SEM (st_plus); -extern SEMANTIC_CACHE_FN SEMC (st_plus); +extern SEMANTIC_FN SEMF (st_plus); extern SEMANTIC_FN SEM (st_minus); -extern SEMANTIC_CACHE_FN SEMC (st_minus); +extern SEMANTIC_FN SEMF (st_minus); extern SEMANTIC_FN SEM (sub); -extern SEMANTIC_CACHE_FN SEMC (sub); +extern SEMANTIC_FN SEMF (sub); extern SEMANTIC_FN SEM (subv); -extern SEMANTIC_CACHE_FN SEMC (subv); +extern SEMANTIC_FN SEMF (subv); extern SEMANTIC_FN SEM (subx); -extern SEMANTIC_CACHE_FN SEMC (subx); +extern SEMANTIC_FN SEMF (subx); extern SEMANTIC_FN SEM (trap); -extern SEMANTIC_CACHE_FN SEMC (trap); +extern SEMANTIC_FN SEMF (trap); extern SEMANTIC_FN SEM (unlock); -extern SEMANTIC_CACHE_FN SEMC (unlock); +extern SEMANTIC_FN SEMF (unlock); extern SEMANTIC_FN SEM (satb); -extern SEMANTIC_CACHE_FN SEMC (satb); +extern SEMANTIC_FN SEMF (satb); extern SEMANTIC_FN SEM (sath); -extern SEMANTIC_CACHE_FN SEMC (sath); +extern SEMANTIC_FN SEMF (sath); extern SEMANTIC_FN SEM (sat); -extern SEMANTIC_CACHE_FN SEMC (sat); +extern SEMANTIC_FN SEMF (sat); extern SEMANTIC_FN SEM (pcmpbz); -extern SEMANTIC_CACHE_FN SEMC (pcmpbz); +extern SEMANTIC_FN SEMF (pcmpbz); extern SEMANTIC_FN SEM (sadd); -extern SEMANTIC_CACHE_FN SEMC (sadd); +extern SEMANTIC_FN SEMF (sadd); extern SEMANTIC_FN SEM (macwu1); -extern SEMANTIC_CACHE_FN SEMC (macwu1); +extern SEMANTIC_FN SEMF (macwu1); extern SEMANTIC_FN SEM (msblo); -extern SEMANTIC_CACHE_FN SEMC (msblo); +extern SEMANTIC_FN SEMF (msblo); extern SEMANTIC_FN SEM (mulwu1); -extern SEMANTIC_CACHE_FN SEMC (mulwu1); +extern SEMANTIC_FN SEMF (mulwu1); extern SEMANTIC_FN SEM (maclh1); -extern SEMANTIC_CACHE_FN SEMC (maclh1); +extern SEMANTIC_FN SEMF (maclh1); extern SEMANTIC_FN SEM (sc); -extern SEMANTIC_CACHE_FN SEMC (sc); +extern SEMANTIC_FN SEMF (sc); extern SEMANTIC_FN SEM (snc); -extern SEMANTIC_CACHE_FN SEMC (snc); +extern SEMANTIC_FN SEMF (snc); #undef EX #undef SEM -#undef SEMC +#undef SEMF #endif /* M32RX_DECODE_H */ diff --git a/sim/m32r/extract.c b/sim/m32r/extract.c index 37207ab..2dd0b39 100644 --- a/sim/m32r/extract.c +++ b/sim/m32r/extract.c @@ -865,7 +865,8 @@ EX_FN_NAME (m32r,fmt_32_lock) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - abuf->h_gr_get = 0 | (1 << f_r1) | (1 << f_r2); + abuf->h_gr_get = 0 | (1 << f_r2); + abuf->h_gr_set = 0 | (1 << f_r1); } #endif #undef FLD diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c new file mode 100644 index 0000000..863da1e --- /dev/null +++ b/sim/m32r/m32r.c @@ -0,0 +1,258 @@ +/* m32r simulator support code + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define WANT_CPU +#define WANT_CPU_M32R + +#include "sim-main.h" +#include <signal.h> +#include "libiberty.h" +#include "bfd.h" +/* FIXME: need to provide general mechanism for accessing target files + these. For now this is a hack to avoid getting the host version. */ +#include "../../libgloss/m32r/sys/syscall.h" +#include "targ-vals.h" + +/* The contents of BUF are in target byte order. */ + +void +m32r_fetch_register (sd, rn, buf) + SIM_DESC sd; + int rn; + unsigned char *buf; +{ + SIM_CPU *current_cpu = STATE_CPU (sd, 0); + + if (rn < 16) + SETTWI (buf, GET_H_GR (rn)); + else if (rn < 21) + SETTWI (buf, GET_H_CR (rn - 16)); + else switch (rn) { + case PC_REGNUM: + SETTWI (buf, GET_H_PC ()); + break; + case ACCL_REGNUM: + SETTWI (buf, GETLODI (GET_H_ACCUM ())); + break; + case ACCH_REGNUM: + SETTWI (buf, GETHIDI (GET_H_ACCUM ())); + break; +#if 0 + case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond; break; + case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm; break; + case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm; break; + case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie; break; + case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie; break; + case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry; break; /* rename: bc */ + case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI)); break; /* duplicate */ +#endif + default: abort (); + } +} + +/* The contents of BUF are in target byte order. */ + +void +m32r_store_register (sd, rn, buf) + SIM_DESC sd; + int rn; + unsigned char *buf; +{ + SIM_CPU *current_cpu = STATE_CPU (sd, 0); + + if (rn < 16) + SET_H_GR (rn, GETTWI (buf)); + else if (rn < 21) + SET_H_CR (rn - 16, GETTWI (buf)); + else switch (rn) { + case PC_REGNUM: + SET_H_PC (GETTWI (buf)); + break; + case ACCL_REGNUM: + SETLODI (CPU (h_accum), GETTWI (buf)); + break; + case ACCH_REGNUM: + SETHIDI (CPU (h_accum), GETTWI (buf)); + break; +#if 0 + case 23: STATE_CPU_CPU (sd, 0)->h_cond = *reg; break; + case 24: STATE_CPU_CPU (sd, 0)->h_sm = *reg; break; + case 25: STATE_CPU_CPU (sd, 0)->h_bsm = *reg; break; + case 26: STATE_CPU_CPU (sd, 0)->h_ie = *reg; break; + case 27: STATE_CPU_CPU (sd, 0)->h_bie = *reg; break; + case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg; break; /* rename: bc */ + case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI)); break; /* duplicate */ +#endif + } +} + +/* Handling the MSPR register is done by creating a device in the core + mapping that winds up here. */ + +device m32r_mspr_device; + +int +device_io_read_buffer (device *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + SIM_CPU *cpu, sim_cia cia) +{ + abort (); +} + +int +device_io_write_buffer (device *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + SIM_CPU *cpu, sim_cia cia) +{ +#if WITH_SCACHE + if (addr == MSPR_ADDR + && (*(char *) source & 1) != 0) + scache_flush (CPU_STATE (cpu)); +#endif + return nr_bytes; +} + +void device_error () {} + +#if WITH_PROFILE_MODEL_P + +void +m32r_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf) +{ + if ((CPU_CGEN_PROFILE (cpu)->h_gr & abuf->h_gr_get) != 0) + { + PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2; + if (TRACE_INSN_P (cpu)) + cgen_trace_printf (cpu, " ; Load stall of 2 cycles."); + } +} + +void +m32r_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf) +{ +} + +void +m32r_model_mark_busy_reg (SIM_CPU *cpu, ARGBUF *abuf) +{ + CPU_CGEN_PROFILE (cpu)->h_gr = abuf->h_gr_set; +} + +void +m32r_model_mark_unbusy_reg (SIM_CPU *cpu, ARGBUF *abuf) +{ + CPU_CGEN_PROFILE (cpu)->h_gr = 0; +} + +#endif /* WITH_PROFILE_MODEL_P */ + +USI +m32r_h_cr_get (SIM_CPU *current_cpu, UINT cr) +{ + /* FIXME: Create enums H_CR_FOO, etc. */ + switch (cr) + { + case 0 : /* psw */ + return ((CPU (h_bsm) << 15) + | (CPU (h_bie) << 14) + | (CPU (h_bcond) << 8) + | (CPU (h_sm) << 7) + | (CPU (h_ie) << 6) + | (CPU (h_cond) << 0)); + case 1 : /* condition bit */ + return CPU (h_cond); + case 2 : /* interrupt stack pointer */ + if (! CPU (h_sm)) + return CPU (h_gr[15]); + else + return CPU (h_cr[2]); + case 3 : /* user stack pointer */ + if (CPU (h_sm)) + return CPU (h_gr[15]); + else + return CPU (h_cr[3]); + case 6 : /* backup pc */ + /* ??? We don't really support this yet. */ + case 4 : /* unused */ + case 5 : /* unused */ + return CPU (h_cr[cr]); + default : + return 0; + } +} + +void +m32r_h_cr_set (SIM_CPU *current_cpu, UINT cr, USI newval) +{ + /* FIXME: Create enums H_CR_FOO, etc. */ + switch (cr) + { + case 0 : /* psw */ + { + int old_sm = CPU (h_sm); + CPU (h_bsm) = (newval & (1 << 15)) != 0; + CPU (h_bie) = (newval & (1 << 14)) != 0; + CPU (h_bcond) = (newval & (1 << 8)) != 0; + CPU (h_sm) = (newval & (1 << 7)) != 0; + CPU (h_ie) = (newval & (1 << 6)) != 0; + CPU (h_cond) = (newval & (1 << 0)) != 0; + /* When switching stack modes, update the registers. */ + if (old_sm != CPU (h_sm)) + { + if (old_sm) + { + /* Switching user -> system. */ + CPU (h_cr[3]) = CPU (h_gr[15]); + CPU (h_gr[15]) = CPU (h_cr[2]); + } + else + { + /* Switching system -> user. */ + CPU (h_cr[2]) = CPU (h_gr[15]); + CPU (h_gr[15]) = CPU (h_cr[3]); + } + } + break; + } + case 1 : /* condition bit */ + CPU (h_cond) = (newval & 1) != 0; + break; + case 2 : /* interrupt stack pointer */ + if (! CPU (h_sm)) + CPU (h_gr[15]) = newval; + else + CPU (h_cr[2]) = newval; + break; + case 3 : /* user stack pointer */ + if (CPU (h_sm)) + CPU (h_gr[15]) = newval; + else + CPU (h_cr[3]) = newval; + break; + case 4 : /* unused */ + case 5 : /* unused */ + case 6 : /* backup pc */ + CPU (h_cr[cr]) = newval; + break; + default : + /* ignore */ + break; + } +} diff --git a/sim/m32r/model.c b/sim/m32r/model.c index 8efca7e..f6dbfc6 100644 --- a/sim/m32r/model.c +++ b/sim/m32r/model.c @@ -169,10 +169,9 @@ static const INSN_TIMING m32r_d_timing[] = { { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui.a */ { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* div */ - { { (UQI) UNIT_M32R_D_U_EXEC, 27, 27 } }, /* divu */ + { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* divu */ { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* rem */ - { { (UQI) UNIT_M32R_D_U_EXEC, 27, 27 } }, /* remu */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* divh */ + { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* remu */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jl */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jmp */ { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld */ @@ -215,9 +214,9 @@ static const INSN_TIMING m32r_d_timing[] = { { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwhi */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwlo */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mv */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfachi */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfaclo */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfacmi */ + { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfachi */ + { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfaclo */ + { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfacmi */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfc */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtachi */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtaclo */ @@ -325,7 +324,6 @@ static const INSN_TIMING test_timing[] = { { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divu */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rem */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* remu */ - { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divh */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jl */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jmp */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld */ diff --git a/sim/m32r/readx.c b/sim/m32r/readx.c index fdaa077..c18510b 100644 --- a/sim/m32r/readx.c +++ b/sim/m32r/readx.c @@ -111,47 +111,43 @@ with this program; if not, write to the Free Software Foundation, Inc., && case_read_READ_FMT_39_MV, && case_read_READ_FMT_44_NOP, && case_read_READ_FMT_39_MV, - && case_read_READ_FMT_45_RAC_D, - && case_read_READ_FMT_46_RAC_DS, - && case_read_READ_FMT_47_RAC_DSI, - && case_read_READ_FMT_45_RAC_D, - && case_read_READ_FMT_46_RAC_DS, - && case_read_READ_FMT_47_RAC_DSI, - && case_read_READ_FMT_48_RTE, - && case_read_READ_FMT_49_SETH, + && case_read_READ_FMT_45_RAC_DSI, + && case_read_READ_FMT_45_RAC_DSI, + && case_read_READ_FMT_46_RTE, + && case_read_READ_FMT_47_SETH, && case_read_READ_FMT_0_ADD, - && case_read_READ_FMT_50_SLL3, - && case_read_READ_FMT_51_SLLI, + && case_read_READ_FMT_48_SLL3, + && case_read_READ_FMT_49_SLLI, && case_read_READ_FMT_0_ADD, - && case_read_READ_FMT_50_SLL3, - && case_read_READ_FMT_51_SLLI, + && case_read_READ_FMT_48_SLL3, + && case_read_READ_FMT_49_SLLI, && case_read_READ_FMT_0_ADD, - && case_read_READ_FMT_50_SLL3, - && case_read_READ_FMT_51_SLLI, - && case_read_READ_FMT_52_ST, - && case_read_READ_FMT_53_ST_D, - && case_read_READ_FMT_54_STB, - && case_read_READ_FMT_55_STB_D, - && case_read_READ_FMT_56_STH, - && case_read_READ_FMT_57_STH_D, - && case_read_READ_FMT_58_ST_PLUS, - && case_read_READ_FMT_58_ST_PLUS, + && case_read_READ_FMT_48_SLL3, + && case_read_READ_FMT_49_SLLI, + && case_read_READ_FMT_50_ST, + && case_read_READ_FMT_51_ST_D, + && case_read_READ_FMT_52_STB, + && case_read_READ_FMT_53_STB_D, + && case_read_READ_FMT_54_STH, + && case_read_READ_FMT_55_STH_D, + && case_read_READ_FMT_56_ST_PLUS, + && case_read_READ_FMT_56_ST_PLUS, && case_read_READ_FMT_0_ADD, && case_read_READ_FMT_5_ADDV, && case_read_READ_FMT_7_ADDX, - && case_read_READ_FMT_59_TRAP, - && case_read_READ_FMT_60_UNLOCK, - && case_read_READ_FMT_61_SATB, - && case_read_READ_FMT_61_SATB, - && case_read_READ_FMT_62_SAT, + && case_read_READ_FMT_57_TRAP, + && case_read_READ_FMT_58_UNLOCK, + && case_read_READ_FMT_59_SATB, + && case_read_READ_FMT_59_SATB, + && case_read_READ_FMT_60_SAT, && case_read_READ_FMT_21_CMPZ, - && case_read_READ_FMT_63_SADD, - && case_read_READ_FMT_64_MACWU1, - && case_read_READ_FMT_65_MSBLO, - && case_read_READ_FMT_66_MULWU1, - && case_read_READ_FMT_64_MACWU1, - && case_read_READ_FMT_67_SC, - && case_read_READ_FMT_67_SC, + && case_read_READ_FMT_61_SADD, + && case_read_READ_FMT_62_MACWU1, + && case_read_READ_FMT_63_MSBLO, + && case_read_READ_FMT_64_MULWU1, + && case_read_READ_FMT_62_MACWU1, + && case_read_READ_FMT_65_SC, + && case_read_READ_FMT_65_SC, 0 }; extern DECODE *m32rx_decode_vars[]; @@ -650,7 +646,7 @@ with this program; if not, write to the Free Software Foundation, Inc., EXTRACT_FMT_36_LOCK_CODE /* Fetch the input operands for the semantic handler. */ - OPRND (dr) = CPU (h_gr[f_r1]); + OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2])); OPRND (sr) = CPU (h_gr[f_r2]); #undef OPRND } @@ -755,35 +751,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_45_RAC_D) : /* e.g. rac $accd */ - { -#define OPRND(f) par_exec->operands.fmt_45_rac_d.f - EXTRACT_FMT_45_RAC_D_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_45_RAC_D_CODE - - /* Fetch the input operands for the semantic handler. */ - OPRND (accum) = CPU (h_accum); -#undef OPRND - } - BREAK (read); - - CASE (read, READ_FMT_46_RAC_DS) : /* e.g. rac $accd,$accs */ + CASE (read, READ_FMT_45_RAC_DSI) : /* e.g. rac $accd,$accs,#$imm1 */ { -#define OPRND(f) par_exec->operands.fmt_46_rac_ds.f - EXTRACT_FMT_46_RAC_DS_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_46_RAC_DS_CODE - - /* Fetch the input operands for the semantic handler. */ - OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs); -#undef OPRND - } - BREAK (read); - - CASE (read, READ_FMT_47_RAC_DSI) : /* e.g. rac $accd,$accs,#$imm1 */ - { -#define OPRND(f) par_exec->operands.fmt_47_rac_dsi.f - EXTRACT_FMT_47_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_47_RAC_DSI_CODE +#define OPRND(f) par_exec->operands.fmt_45_rac_dsi.f + EXTRACT_FMT_45_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ + EXTRACT_FMT_45_RAC_DSI_CODE /* Fetch the input operands for the semantic handler. */ OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs); @@ -792,11 +764,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_48_RTE) : /* e.g. rte */ + CASE (read, READ_FMT_46_RTE) : /* e.g. rte */ { -#define OPRND(f) par_exec->operands.fmt_48_rte.f - EXTRACT_FMT_48_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_48_RTE_CODE +#define OPRND(f) par_exec->operands.fmt_46_rte.f + EXTRACT_FMT_46_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_46_RTE_CODE /* Fetch the input operands for the semantic handler. */ OPRND (h_bcond_0) = CPU (h_bcond); @@ -807,11 +779,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_49_SETH) : /* e.g. seth $dr,#$hi16 */ + CASE (read, READ_FMT_47_SETH) : /* e.g. seth $dr,#$hi16 */ { -#define OPRND(f) par_exec->operands.fmt_49_seth.f - EXTRACT_FMT_49_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ - EXTRACT_FMT_49_SETH_CODE +#define OPRND(f) par_exec->operands.fmt_47_seth.f + EXTRACT_FMT_47_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ + EXTRACT_FMT_47_SETH_CODE /* Fetch the input operands for the semantic handler. */ OPRND (hi16) = f_hi16; @@ -819,11 +791,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_50_SLL3) : /* e.g. sll3 $dr,$sr,#$simm16 */ + CASE (read, READ_FMT_48_SLL3) : /* e.g. sll3 $dr,$sr,#$simm16 */ { -#define OPRND(f) par_exec->operands.fmt_50_sll3.f - EXTRACT_FMT_50_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_50_SLL3_CODE +#define OPRND(f) par_exec->operands.fmt_48_sll3.f + EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_48_SLL3_CODE /* Fetch the input operands for the semantic handler. */ OPRND (simm16) = f_simm16; @@ -832,11 +804,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_51_SLLI) : /* e.g. slli $dr,#$uimm5 */ + CASE (read, READ_FMT_49_SLLI) : /* e.g. slli $dr,#$uimm5 */ { -#define OPRND(f) par_exec->operands.fmt_51_slli.f - EXTRACT_FMT_51_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ - EXTRACT_FMT_51_SLLI_CODE +#define OPRND(f) par_exec->operands.fmt_49_slli.f + EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ + EXTRACT_FMT_49_SLLI_CODE /* Fetch the input operands for the semantic handler. */ OPRND (dr) = CPU (h_gr[f_r1]); @@ -845,11 +817,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_52_ST) : /* e.g. st $src1,@$src2 */ + CASE (read, READ_FMT_50_ST) : /* e.g. st $src1,@$src2 */ { -#define OPRND(f) par_exec->operands.fmt_52_st.f - EXTRACT_FMT_52_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_52_ST_CODE +#define OPRND(f) par_exec->operands.fmt_50_st.f + EXTRACT_FMT_50_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_50_ST_CODE /* Fetch the input operands for the semantic handler. */ OPRND (src1) = CPU (h_gr[f_r1]); @@ -858,11 +830,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_53_ST_D) : /* e.g. st $src1,@($slo16,$src2) */ + CASE (read, READ_FMT_51_ST_D) : /* e.g. st $src1,@($slo16,$src2) */ { -#define OPRND(f) par_exec->operands.fmt_53_st_d.f - EXTRACT_FMT_53_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_53_ST_D_CODE +#define OPRND(f) par_exec->operands.fmt_51_st_d.f + EXTRACT_FMT_51_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_51_ST_D_CODE /* Fetch the input operands for the semantic handler. */ OPRND (slo16) = f_simm16; @@ -872,11 +844,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_54_STB) : /* e.g. stb $src1,@$src2 */ + CASE (read, READ_FMT_52_STB) : /* e.g. stb $src1,@$src2 */ { -#define OPRND(f) par_exec->operands.fmt_54_stb.f - EXTRACT_FMT_54_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_54_STB_CODE +#define OPRND(f) par_exec->operands.fmt_52_stb.f + EXTRACT_FMT_52_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_52_STB_CODE /* Fetch the input operands for the semantic handler. */ OPRND (src1) = CPU (h_gr[f_r1]); @@ -885,11 +857,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_55_STB_D) : /* e.g. stb $src1,@($slo16,$src2) */ + CASE (read, READ_FMT_53_STB_D) : /* e.g. stb $src1,@($slo16,$src2) */ { -#define OPRND(f) par_exec->operands.fmt_55_stb_d.f - EXTRACT_FMT_55_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_55_STB_D_CODE +#define OPRND(f) par_exec->operands.fmt_53_stb_d.f + EXTRACT_FMT_53_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_53_STB_D_CODE /* Fetch the input operands for the semantic handler. */ OPRND (slo16) = f_simm16; @@ -899,11 +871,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_56_STH) : /* e.g. sth $src1,@$src2 */ + CASE (read, READ_FMT_54_STH) : /* e.g. sth $src1,@$src2 */ { -#define OPRND(f) par_exec->operands.fmt_56_sth.f - EXTRACT_FMT_56_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_56_STH_CODE +#define OPRND(f) par_exec->operands.fmt_54_sth.f + EXTRACT_FMT_54_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_54_STH_CODE /* Fetch the input operands for the semantic handler. */ OPRND (src1) = CPU (h_gr[f_r1]); @@ -912,11 +884,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_57_STH_D) : /* e.g. sth $src1,@($slo16,$src2) */ + CASE (read, READ_FMT_55_STH_D) : /* e.g. sth $src1,@($slo16,$src2) */ { -#define OPRND(f) par_exec->operands.fmt_57_sth_d.f - EXTRACT_FMT_57_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_57_STH_D_CODE +#define OPRND(f) par_exec->operands.fmt_55_sth_d.f + EXTRACT_FMT_55_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_55_STH_D_CODE /* Fetch the input operands for the semantic handler. */ OPRND (slo16) = f_simm16; @@ -926,11 +898,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_58_ST_PLUS) : /* e.g. st $src1,@+$src2 */ + CASE (read, READ_FMT_56_ST_PLUS) : /* e.g. st $src1,@+$src2 */ { -#define OPRND(f) par_exec->operands.fmt_58_st_plus.f - EXTRACT_FMT_58_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_58_ST_PLUS_CODE +#define OPRND(f) par_exec->operands.fmt_56_st_plus.f + EXTRACT_FMT_56_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_56_ST_PLUS_CODE /* Fetch the input operands for the semantic handler. */ OPRND (src1) = CPU (h_gr[f_r1]); @@ -939,36 +911,39 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_59_TRAP) : /* e.g. trap #$uimm4 */ + CASE (read, READ_FMT_57_TRAP) : /* e.g. trap #$uimm4 */ { -#define OPRND(f) par_exec->operands.fmt_59_trap.f - EXTRACT_FMT_59_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ - EXTRACT_FMT_59_TRAP_CODE +#define OPRND(f) par_exec->operands.fmt_57_trap.f + EXTRACT_FMT_57_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ + EXTRACT_FMT_57_TRAP_CODE /* Fetch the input operands for the semantic handler. */ + OPRND (pc) = CPU (h_pc); + OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, 0); OPRND (uimm4) = f_uimm4; #undef OPRND } BREAK (read); - CASE (read, READ_FMT_60_UNLOCK) : /* e.g. unlock $src1,@$src2 */ + CASE (read, READ_FMT_58_UNLOCK) : /* e.g. unlock $src1,@$src2 */ { -#define OPRND(f) par_exec->operands.fmt_60_unlock.f - EXTRACT_FMT_60_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_60_UNLOCK_CODE +#define OPRND(f) par_exec->operands.fmt_58_unlock.f + EXTRACT_FMT_58_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_58_UNLOCK_CODE /* Fetch the input operands for the semantic handler. */ + OPRND (h_lock_0) = CPU (h_lock); OPRND (src1) = CPU (h_gr[f_r1]); OPRND (src2) = CPU (h_gr[f_r2]); #undef OPRND } BREAK (read); - CASE (read, READ_FMT_61_SATB) : /* e.g. satb $dr,$sr */ + CASE (read, READ_FMT_59_SATB) : /* e.g. satb $dr,$sr */ { -#define OPRND(f) par_exec->operands.fmt_61_satb.f - EXTRACT_FMT_61_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_61_SATB_CODE +#define OPRND(f) par_exec->operands.fmt_59_satb.f + EXTRACT_FMT_59_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_FMT_59_SATB_CODE /* Fetch the input operands for the semantic handler. */ OPRND (sr) = CPU (h_gr[f_r2]); @@ -976,11 +951,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_62_SAT) : /* e.g. sat $dr,$sr */ + CASE (read, READ_FMT_60_SAT) : /* e.g. sat $dr,$sr */ { -#define OPRND(f) par_exec->operands.fmt_62_sat.f - EXTRACT_FMT_62_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_62_SAT_CODE +#define OPRND(f) par_exec->operands.fmt_60_sat.f + EXTRACT_FMT_60_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_FMT_60_SAT_CODE /* Fetch the input operands for the semantic handler. */ OPRND (condbit) = CPU (h_cond); @@ -989,11 +964,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_63_SADD) : /* e.g. sadd */ + CASE (read, READ_FMT_61_SADD) : /* e.g. sadd */ { -#define OPRND(f) par_exec->operands.fmt_63_sadd.f - EXTRACT_FMT_63_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_63_SADD_CODE +#define OPRND(f) par_exec->operands.fmt_61_sadd.f + EXTRACT_FMT_61_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_61_SADD_CODE /* Fetch the input operands for the semantic handler. */ OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0); @@ -1002,11 +977,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_64_MACWU1) : /* e.g. macwu1 $src1,$src2 */ + CASE (read, READ_FMT_62_MACWU1) : /* e.g. macwu1 $src1,$src2 */ { -#define OPRND(f) par_exec->operands.fmt_64_macwu1.f - EXTRACT_FMT_64_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_64_MACWU1_CODE +#define OPRND(f) par_exec->operands.fmt_62_macwu1.f + EXTRACT_FMT_62_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_62_MACWU1_CODE /* Fetch the input operands for the semantic handler. */ OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1); @@ -1016,11 +991,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_65_MSBLO) : /* e.g. msblo $src1,$src2 */ + CASE (read, READ_FMT_63_MSBLO) : /* e.g. msblo $src1,$src2 */ { -#define OPRND(f) par_exec->operands.fmt_65_msblo.f - EXTRACT_FMT_65_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_65_MSBLO_CODE +#define OPRND(f) par_exec->operands.fmt_63_msblo.f + EXTRACT_FMT_63_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_63_MSBLO_CODE /* Fetch the input operands for the semantic handler. */ OPRND (accum) = CPU (h_accum); @@ -1030,11 +1005,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_66_MULWU1) : /* e.g. mulwu1 $src1,$src2 */ + CASE (read, READ_FMT_64_MULWU1) : /* e.g. mulwu1 $src1,$src2 */ { -#define OPRND(f) par_exec->operands.fmt_66_mulwu1.f - EXTRACT_FMT_66_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_66_MULWU1_CODE +#define OPRND(f) par_exec->operands.fmt_64_mulwu1.f + EXTRACT_FMT_64_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_64_MULWU1_CODE /* Fetch the input operands for the semantic handler. */ OPRND (src1) = CPU (h_gr[f_r1]); @@ -1043,11 +1018,11 @@ with this program; if not, write to the Free Software Foundation, Inc., } BREAK (read); - CASE (read, READ_FMT_67_SC) : /* e.g. sc */ + CASE (read, READ_FMT_65_SC) : /* e.g. sc */ { -#define OPRND(f) par_exec->operands.fmt_67_sc.f - EXTRACT_FMT_67_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_67_SC_CODE +#define OPRND(f) par_exec->operands.fmt_65_sc.f + EXTRACT_FMT_65_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_65_SC_CODE /* Fetch the input operands for the semantic handler. */ OPRND (condbit) = CPU (h_cond); diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c index d944096..1b338f9 100644 --- a/sim/m32r/sem-switch.c +++ b/sim/m32r/sem-switch.c @@ -69,7 +69,6 @@ with this program; if not, write to the Free Software Foundation, Inc., && case_sem_INSN_DIVU, && case_sem_INSN_REM, && case_sem_INSN_REMU, - && case_sem_INSN_DIVH, && case_sem_INSN_JL, && case_sem_INSN_JMP, && case_sem_INSN_LD, @@ -284,7 +283,7 @@ with this program; if not, write to the Free Software Foundation, Inc., CASE (sem, INSN_ADDV) : /* addv $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_0_add.f +#define FLD(f) abuf->fields.fmt_5_addv.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -303,7 +302,7 @@ do { CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,#$simm16 */ { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_6_addv3.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -322,7 +321,7 @@ do { CASE (sem, INSN_ADDX) : /* addx $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_6_addx.f +#define FLD(f) abuf->fields.fmt_7_addx.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -341,11 +340,12 @@ do { CASE (sem, INSN_BC8) : /* bc $disp8 */ { -#define FLD(f) abuf->fields.fmt_7_bc8.f +#define FLD(f) abuf->fields.fmt_8_bc8.f new_pc = SEM_NEXT_PC (sem_arg); if (CPU (h_cond)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -354,11 +354,12 @@ if (CPU (h_cond)) { CASE (sem, INSN_BC24) : /* bc $disp24 */ { -#define FLD(f) abuf->fields.fmt_8_bc24.f +#define FLD(f) abuf->fields.fmt_9_bc24.f new_pc = SEM_NEXT_PC (sem_arg); if (CPU (h_cond)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -367,11 +368,12 @@ if (CPU (h_cond)) { CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_9_beq.f +#define FLD(f) abuf->fields.fmt_10_beq.f new_pc = SEM_NEXT_PC (sem_arg); if (EQSI (* FLD (f_r1), * FLD (f_r2))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -380,11 +382,12 @@ if (EQSI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f new_pc = SEM_NEXT_PC (sem_arg); if (EQSI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -393,11 +396,12 @@ if (EQSI (* FLD (f_r2), 0)) { CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f new_pc = SEM_NEXT_PC (sem_arg); if (GESI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -406,11 +410,12 @@ if (GESI (* FLD (f_r2), 0)) { CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f new_pc = SEM_NEXT_PC (sem_arg); if (GTSI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -419,11 +424,12 @@ if (GTSI (* FLD (f_r2), 0)) { CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f new_pc = SEM_NEXT_PC (sem_arg); if (LESI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -432,11 +438,12 @@ if (LESI (* FLD (f_r2), 0)) { CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f new_pc = SEM_NEXT_PC (sem_arg); if (LTSI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -445,11 +452,12 @@ if (LTSI (* FLD (f_r2), 0)) { CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f new_pc = SEM_NEXT_PC (sem_arg); if (NESI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -458,13 +466,14 @@ if (NESI (* FLD (f_r2), 0)) { CASE (sem, INSN_BL8) : /* bl $disp8 */ { -#define FLD(f) abuf->fields.fmt_11_bl8.f +#define FLD(f) abuf->fields.fmt_12_bl8.f new_pc = SEM_NEXT_PC (sem_arg); do { CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #undef FLD @@ -473,13 +482,14 @@ do { CASE (sem, INSN_BL24) : /* bl $disp24 */ { -#define FLD(f) abuf->fields.fmt_12_bl24.f +#define FLD(f) abuf->fields.fmt_13_bl24.f new_pc = SEM_NEXT_PC (sem_arg); do { CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #undef FLD @@ -488,11 +498,12 @@ do { CASE (sem, INSN_BNC8) : /* bnc $disp8 */ { -#define FLD(f) abuf->fields.fmt_7_bc8.f +#define FLD(f) abuf->fields.fmt_8_bc8.f new_pc = SEM_NEXT_PC (sem_arg); if (NOTBI (CPU (h_cond))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -501,11 +512,12 @@ if (NOTBI (CPU (h_cond))) { CASE (sem, INSN_BNC24) : /* bnc $disp24 */ { -#define FLD(f) abuf->fields.fmt_8_bc24.f +#define FLD(f) abuf->fields.fmt_9_bc24.f new_pc = SEM_NEXT_PC (sem_arg); if (NOTBI (CPU (h_cond))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -514,11 +526,12 @@ if (NOTBI (CPU (h_cond))) { CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */ { -#define FLD(f) abuf->fields.fmt_9_beq.f +#define FLD(f) abuf->fields.fmt_10_beq.f new_pc = SEM_NEXT_PC (sem_arg); if (NESI (* FLD (f_r1), * FLD (f_r2))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #undef FLD @@ -527,10 +540,11 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_BRA8) : /* bra $disp8 */ { -#define FLD(f) abuf->fields.fmt_13_bra8.f +#define FLD(f) abuf->fields.fmt_14_bra8.f new_pc = SEM_NEXT_PC (sem_arg); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #undef FLD } @@ -538,10 +552,11 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_BRA24) : /* bra $disp24 */ { -#define FLD(f) abuf->fields.fmt_14_bra24.f +#define FLD(f) abuf->fields.fmt_15_bra24.f new_pc = SEM_NEXT_PC (sem_arg); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #undef FLD } @@ -549,7 +564,7 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_16_cmp.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2)); @@ -561,7 +576,7 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_CMPI) : /* cmpi $src2,#$simm16 */ { -#define FLD(f) abuf->fields.fmt_16_cmpi.f +#define FLD(f) abuf->fields.fmt_17_cmpi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16)); @@ -573,7 +588,7 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_16_cmp.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2)); @@ -585,7 +600,7 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_CMPUI) : /* cmpui $src2,#$uimm16 */ { -#define FLD(f) abuf->fields.fmt_17_cmpui.f +#define FLD(f) abuf->fields.fmt_18_cmpui.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16)); @@ -597,7 +612,7 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CASE (sem, INSN_DIV) : /* div $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f new_pc = SEM_NEXT_PC (sem_arg); if (NESI (* FLD (f_r2), 0)) { @@ -611,7 +626,7 @@ if (NESI (* FLD (f_r2), 0)) { CASE (sem, INSN_DIVU) : /* divu $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f new_pc = SEM_NEXT_PC (sem_arg); if (NESI (* FLD (f_r2), 0)) { @@ -625,7 +640,7 @@ if (NESI (* FLD (f_r2), 0)) { CASE (sem, INSN_REM) : /* rem $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f new_pc = SEM_NEXT_PC (sem_arg); if (NESI (* FLD (f_r2), 0)) { @@ -639,7 +654,7 @@ if (NESI (* FLD (f_r2), 0)) { CASE (sem, INSN_REMU) : /* remu $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f new_pc = SEM_NEXT_PC (sem_arg); if (NESI (* FLD (f_r2), 0)) { @@ -651,23 +666,9 @@ if (NESI (* FLD (f_r2), 0)) { } BREAK (sem); - CASE (sem, INSN_DIVH) : /* divh $dr,$sr */ -{ -#define FLD(f) abuf->fields.fmt_18_div.f - new_pc = SEM_NEXT_PC (sem_arg); - -if (NESI (* FLD (f_r2), 0)) { -* FLD (f_r1) = DIVSI (EXTHISI (TRUNCSIHI (* FLD (f_r1))), * FLD (f_r2)); - TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); -} - -#undef FLD -} - BREAK (sem); - CASE (sem, INSN_JL) : /* jl $sr */ { -#define FLD(f) abuf->fields.fmt_19_jl.f +#define FLD(f) abuf->fields.fmt_20_jl.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -677,6 +678,7 @@ do { CPU (h_gr[14]) = temp0; TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1)); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #undef FLD @@ -685,10 +687,11 @@ do { CASE (sem, INSN_JMP) : /* jmp $sr */ { -#define FLD(f) abuf->fields.fmt_20_jmp.f +#define FLD(f) abuf->fields.fmt_21_jmp.f new_pc = SEM_NEXT_PC (sem_arg); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #undef FLD } @@ -696,7 +699,7 @@ do { CASE (sem, INSN_LD) : /* ld $dr,@$sr */ { -#define FLD(f) abuf->fields.fmt_21_ld.f +#define FLD(f) abuf->fields.fmt_22_ld.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2)); @@ -708,7 +711,7 @@ do { CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */ { -#define FLD(f) abuf->fields.fmt_22_ld_d.f +#define FLD(f) abuf->fields.fmt_23_ld_d.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))); @@ -720,7 +723,7 @@ do { CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */ { -#define FLD(f) abuf->fields.fmt_23_ldb.f +#define FLD(f) abuf->fields.fmt_24_ldb.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2))); @@ -732,7 +735,7 @@ do { CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */ { -#define FLD(f) abuf->fields.fmt_24_ldb_d.f +#define FLD(f) abuf->fields.fmt_25_ldb_d.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); @@ -744,7 +747,7 @@ do { CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */ { -#define FLD(f) abuf->fields.fmt_25_ldh.f +#define FLD(f) abuf->fields.fmt_26_ldh.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2))); @@ -756,7 +759,7 @@ do { CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */ { -#define FLD(f) abuf->fields.fmt_26_ldh_d.f +#define FLD(f) abuf->fields.fmt_27_ldh_d.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); @@ -768,7 +771,7 @@ do { CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */ { -#define FLD(f) abuf->fields.fmt_23_ldb.f +#define FLD(f) abuf->fields.fmt_24_ldb.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2))); @@ -780,7 +783,7 @@ do { CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */ { -#define FLD(f) abuf->fields.fmt_24_ldb_d.f +#define FLD(f) abuf->fields.fmt_25_ldb_d.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); @@ -792,7 +795,7 @@ do { CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */ { -#define FLD(f) abuf->fields.fmt_25_ldh.f +#define FLD(f) abuf->fields.fmt_26_ldh.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2))); @@ -804,7 +807,7 @@ do { CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */ { -#define FLD(f) abuf->fields.fmt_26_ldh_d.f +#define FLD(f) abuf->fields.fmt_27_ldh_d.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)))); @@ -816,7 +819,7 @@ do { CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */ { -#define FLD(f) abuf->fields.fmt_21_ld.f +#define FLD(f) abuf->fields.fmt_28_ld_plus.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -835,7 +838,7 @@ do { CASE (sem, INSN_LD24) : /* ld24 $dr,#$uimm24 */ { -#define FLD(f) abuf->fields.fmt_27_ld24.f +#define FLD(f) abuf->fields.fmt_29_ld24.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = FLD (f_uimm24); @@ -847,7 +850,7 @@ do { CASE (sem, INSN_LDI8) : /* ldi $dr,#$simm8 */ { -#define FLD(f) abuf->fields.fmt_28_ldi8.f +#define FLD(f) abuf->fields.fmt_30_ldi8.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = FLD (f_simm8); @@ -859,7 +862,7 @@ do { CASE (sem, INSN_LDI16) : /* ldi $dr,$slo16 */ { -#define FLD(f) abuf->fields.fmt_29_ldi16.f +#define FLD(f) abuf->fields.fmt_31_ldi16.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = FLD (f_simm16); @@ -871,10 +874,15 @@ do { CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */ { -#define FLD(f) abuf->fields.fmt_0_add.f +#define FLD(f) abuf->fields.fmt_32_lock.f new_pc = SEM_NEXT_PC (sem_arg); -do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); +do { + CPU (h_lock) = 1; + TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock)); +* FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2)); + TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); +} while (0); #undef FLD } @@ -882,7 +890,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8); @@ -894,7 +902,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8); @@ -906,7 +914,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8); @@ -918,7 +926,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8); @@ -942,7 +950,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16); @@ -954,7 +962,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16); @@ -966,7 +974,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8); @@ -978,7 +986,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8); @@ -990,7 +998,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MV) : /* mv $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_31_mv.f +#define FLD(f) abuf->fields.fmt_35_mv.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = * FLD (f_r2); @@ -1002,7 +1010,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */ { -#define FLD(f) abuf->fields.fmt_32_mvfachi.f +#define FLD(f) abuf->fields.fmt_36_mvfachi.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32)); @@ -1014,7 +1022,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */ { -#define FLD(f) abuf->fields.fmt_32_mvfachi.f +#define FLD(f) abuf->fields.fmt_36_mvfachi.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = TRUNCDISI (CPU (h_accum)); @@ -1026,7 +1034,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */ { -#define FLD(f) abuf->fields.fmt_32_mvfachi.f +#define FLD(f) abuf->fields.fmt_36_mvfachi.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16)); @@ -1038,7 +1046,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */ { -#define FLD(f) abuf->fields.fmt_33_mvfc.f +#define FLD(f) abuf->fields.fmt_37_mvfc.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2)); @@ -1050,7 +1058,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */ { -#define FLD(f) abuf->fields.fmt_34_mvtachi.f +#define FLD(f) abuf->fields.fmt_38_mvtachi.f new_pc = SEM_NEXT_PC (sem_arg); CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32)); @@ -1062,10 +1070,10 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */ { -#define FLD(f) abuf->fields.fmt_34_mvtachi.f +#define FLD(f) abuf->fields.fmt_38_mvtachi.f new_pc = SEM_NEXT_PC (sem_arg); - CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1))); + CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (f_r1))); TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum)); #undef FLD @@ -1074,7 +1082,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */ { -#define FLD(f) abuf->fields.fmt_35_mvtc.f +#define FLD(f) abuf->fields.fmt_39_mvtc.f new_pc = SEM_NEXT_PC (sem_arg); m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2)); @@ -1086,7 +1094,7 @@ m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_NEG) : /* neg $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_31_mv.f +#define FLD(f) abuf->fields.fmt_35_mv.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = NEGSI (* FLD (f_r2)); @@ -1098,7 +1106,7 @@ m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2)); CASE (sem, INSN_NOP) : /* nop */ { -#define FLD(f) abuf->fields.fmt_36_nop.f +#define FLD(f) abuf->fields.fmt_40_nop.f new_pc = SEM_NEXT_PC (sem_arg); PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); @@ -1109,7 +1117,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); CASE (sem, INSN_NOT) : /* not $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_31_mv.f +#define FLD(f) abuf->fields.fmt_35_mv.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = INVSI (* FLD (f_r2)); @@ -1121,7 +1129,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); CASE (sem, INSN_RAC) : /* rac */ { -#define FLD(f) abuf->fields.fmt_37_rac.f +#define FLD(f) abuf->fields.fmt_41_rac.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1138,7 +1146,7 @@ do { CASE (sem, INSN_RACH) : /* rach */ { -#define FLD(f) abuf->fields.fmt_37_rac.f +#define FLD(f) abuf->fields.fmt_41_rac.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1164,7 +1172,7 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760 CASE (sem, INSN_RTE) : /* rte */ { -#define FLD(f) abuf->fields.fmt_38_rte.f +#define FLD(f) abuf->fields.fmt_42_rte.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1184,7 +1192,7 @@ do { CASE (sem, INSN_SETH) : /* seth $dr,#$hi16 */ { -#define FLD(f) abuf->fields.fmt_39_seth.f +#define FLD(f) abuf->fields.fmt_43_seth.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SLLSI (FLD (f_hi16), 16); @@ -1208,7 +1216,7 @@ do { CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,#$simm16 */ { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_44_sll3.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31)); @@ -1220,7 +1228,7 @@ do { CASE (sem, INSN_SLLI) : /* slli $dr,#$uimm5 */ { -#define FLD(f) abuf->fields.fmt_40_slli.f +#define FLD(f) abuf->fields.fmt_45_slli.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5)); @@ -1244,7 +1252,7 @@ do { CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,#$simm16 */ { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_44_sll3.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31)); @@ -1256,7 +1264,7 @@ do { CASE (sem, INSN_SRAI) : /* srai $dr,#$uimm5 */ { -#define FLD(f) abuf->fields.fmt_40_slli.f +#define FLD(f) abuf->fields.fmt_45_slli.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5)); @@ -1280,7 +1288,7 @@ do { CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,#$simm16 */ { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_44_sll3.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31)); @@ -1292,7 +1300,7 @@ do { CASE (sem, INSN_SRLI) : /* srli $dr,#$uimm5 */ { -#define FLD(f) abuf->fields.fmt_40_slli.f +#define FLD(f) abuf->fields.fmt_45_slli.f new_pc = SEM_NEXT_PC (sem_arg); * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5)); @@ -1304,7 +1312,7 @@ do { CASE (sem, INSN_ST) : /* st $src1,@$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_46_st.f new_pc = SEM_NEXT_PC (sem_arg); SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); @@ -1316,7 +1324,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */ { -#define FLD(f) abuf->fields.fmt_41_st_d.f +#define FLD(f) abuf->fields.fmt_47_st_d.f new_pc = SEM_NEXT_PC (sem_arg); SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); @@ -1328,7 +1336,7 @@ SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); CASE (sem, INSN_STB) : /* stb $src1,@$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_48_stb.f new_pc = SEM_NEXT_PC (sem_arg); SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1)); @@ -1340,7 +1348,7 @@ SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */ { -#define FLD(f) abuf->fields.fmt_41_st_d.f +#define FLD(f) abuf->fields.fmt_49_stb_d.f new_pc = SEM_NEXT_PC (sem_arg); SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); @@ -1352,7 +1360,7 @@ SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); CASE (sem, INSN_STH) : /* sth $src1,@$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_50_sth.f new_pc = SEM_NEXT_PC (sem_arg); SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1)); @@ -1364,7 +1372,7 @@ SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */ { -#define FLD(f) abuf->fields.fmt_41_st_d.f +#define FLD(f) abuf->fields.fmt_51_sth_d.f new_pc = SEM_NEXT_PC (sem_arg); SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); @@ -1376,7 +1384,7 @@ SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_52_st_plus.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1392,7 +1400,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_52_st_plus.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1420,7 +1428,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CASE (sem, INSN_SUBV) : /* subv $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_0_add.f +#define FLD(f) abuf->fields.fmt_5_addv.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1439,7 +1447,7 @@ do { CASE (sem, INSN_SUBX) : /* subx $dr,$sr */ { -#define FLD(f) abuf->fields.fmt_6_addx.f +#define FLD(f) abuf->fields.fmt_7_addx.f new_pc = SEM_NEXT_PC (sem_arg); do { @@ -1458,10 +1466,17 @@ do { CASE (sem, INSN_TRAP) : /* trap #$uimm4 */ { -#define FLD(f) abuf->fields.fmt_42_trap.f +#define FLD(f) abuf->fields.fmt_53_trap.f new_pc = SEM_NEXT_PC (sem_arg); +do { +m32r_h_cr_set (current_cpu, 6, ADDSI (CPU (h_pc), 4)); + TRACE_RESULT (current_cpu, "h-cr-6", 'x', m32r_h_cr_get (current_cpu, 6)); +m32r_h_cr_set (current_cpu, 0, ANDSI (SRLSI (m32r_h_cr_get (current_cpu, 0), 8), 33488896)); + TRACE_RESULT (current_cpu, "h-cr-0", 'x', m32r_h_cr_get (current_cpu, 0)); do_trap (current_cpu, FLD (f_uimm4)); +; /*clobber*/ +} while (0); #undef FLD } @@ -1469,10 +1484,17 @@ do_trap (current_cpu, FLD (f_uimm4)); CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */ { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_54_unlock.f new_pc = SEM_NEXT_PC (sem_arg); -do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2)); +do { +if (CPU (h_lock)) { +SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); + TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2))); +} + CPU (h_lock) = 0; + TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock)); +} while (0); #undef FLD } diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c index 7ba6f3c..8c83912 100644 --- a/sim/m32r/sem.c +++ b/sim/m32r/sem.c @@ -255,7 +255,7 @@ SEM_FN_NAME (m32r,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_0_add.f +#define FLD(f) abuf->fields.fmt_5_addv.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -286,7 +286,7 @@ do { CIA SEM_FN_NAME (m32r,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_6_addv3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -317,7 +317,7 @@ do { CIA SEM_FN_NAME (m32r,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_6_addx.f +#define FLD(f) abuf->fields.fmt_7_addx.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -348,7 +348,7 @@ do { CIA SEM_FN_NAME (m32r,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_7_bc8.f +#define FLD(f) abuf->fields.fmt_8_bc8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -356,6 +356,7 @@ SEM_FN_NAME (m32r,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_cond)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -373,7 +374,7 @@ if (CPU (h_cond)) { CIA SEM_FN_NAME (m32r,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_8_bc24.f +#define FLD(f) abuf->fields.fmt_9_bc24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -381,6 +382,7 @@ SEM_FN_NAME (m32r,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_cond)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -398,7 +400,7 @@ if (CPU (h_cond)) { CIA SEM_FN_NAME (m32r,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_9_beq.f +#define FLD(f) abuf->fields.fmt_10_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -406,6 +408,7 @@ SEM_FN_NAME (m32r,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (* FLD (f_r1), * FLD (f_r2))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -424,7 +427,7 @@ if (EQSI (* FLD (f_r1), * FLD (f_r2))) { CIA SEM_FN_NAME (m32r,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -432,6 +435,7 @@ SEM_FN_NAME (m32r,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -450,7 +454,7 @@ if (EQSI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -458,6 +462,7 @@ SEM_FN_NAME (m32r,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GESI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -476,7 +481,7 @@ if (GESI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -484,6 +489,7 @@ SEM_FN_NAME (m32r,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GTSI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -502,7 +508,7 @@ if (GTSI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -510,6 +516,7 @@ SEM_FN_NAME (m32r,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LESI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -528,7 +535,7 @@ if (LESI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -536,6 +543,7 @@ SEM_FN_NAME (m32r,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LTSI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -554,7 +562,7 @@ if (LTSI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_10_beqz.f +#define FLD(f) abuf->fields.fmt_11_beqz.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -562,6 +570,7 @@ SEM_FN_NAME (m32r,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (* FLD (f_r2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -580,7 +589,7 @@ if (NESI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_11_bl8.f +#define FLD(f) abuf->fields.fmt_12_bl8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -590,6 +599,7 @@ do { TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #if WITH_PROFILE_MODEL_P @@ -608,7 +618,7 @@ do { CIA SEM_FN_NAME (m32r,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_12_bl24.f +#define FLD(f) abuf->fields.fmt_13_bl24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -618,6 +628,7 @@ do { TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #if WITH_PROFILE_MODEL_P @@ -636,7 +647,7 @@ do { CIA SEM_FN_NAME (m32r,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_7_bc8.f +#define FLD(f) abuf->fields.fmt_8_bc8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -644,6 +655,7 @@ SEM_FN_NAME (m32r,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_cond))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -661,7 +673,7 @@ if (NOTBI (CPU (h_cond))) { CIA SEM_FN_NAME (m32r,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_8_bc24.f +#define FLD(f) abuf->fields.fmt_9_bc24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -669,6 +681,7 @@ SEM_FN_NAME (m32r,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_cond))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -686,7 +699,7 @@ if (NOTBI (CPU (h_cond))) { CIA SEM_FN_NAME (m32r,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_9_beq.f +#define FLD(f) abuf->fields.fmt_10_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -694,6 +707,7 @@ SEM_FN_NAME (m32r,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (* FLD (f_r1), * FLD (f_r2))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -712,13 +726,14 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) { CIA SEM_FN_NAME (m32r,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_13_bra8.f +#define FLD(f) abuf->fields.fmt_14_bra8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -735,13 +750,14 @@ SEM_FN_NAME (m32r,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_14_bra24.f +#define FLD(f) abuf->fields.fmt_15_bra24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -758,7 +774,7 @@ SEM_FN_NAME (m32r,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_16_cmp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -781,7 +797,7 @@ SEM_FN_NAME (m32r,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_16_cmpi.f +#define FLD(f) abuf->fields.fmt_17_cmpi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -804,7 +820,7 @@ SEM_FN_NAME (m32r,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_16_cmp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -827,7 +843,7 @@ SEM_FN_NAME (m32r,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_17_cmpui.f +#define FLD(f) abuf->fields.fmt_18_cmpui.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -850,7 +866,7 @@ SEM_FN_NAME (m32r,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -876,7 +892,7 @@ if (NESI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -902,7 +918,7 @@ if (NESI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -928,7 +944,7 @@ if (NESI (* FLD (f_r2), 0)) { CIA SEM_FN_NAME (m32r,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_18_div.f +#define FLD(f) abuf->fields.fmt_19_div.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -950,37 +966,11 @@ if (NESI (* FLD (f_r2), 0)) { #undef FLD } -/* Perform divh: divh $dr,$sr. */ -CIA -SEM_FN_NAME (m32r,divh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.fmt_18_div.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - CIA new_pc = SEM_NEXT_PC (sem_arg); - -if (NESI (* FLD (f_r2), 0)) { -* FLD (f_r1) = DIVSI (EXTHISI (TRUNCSIHI (* FLD (f_r1))), * FLD (f_r2)); - TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); -} - -#if WITH_PROFILE_MODEL_P - if (PROFILE_MODEL_P (current_cpu)) - { - m32r_model_mark_get_h_gr (current_cpu, abuf); - m32r_model_mark_set_h_gr (current_cpu, abuf); - m32r_model_profile_insn (current_cpu, abuf); - } -#endif - - return new_pc; -#undef FLD -} - /* Perform jl: jl $sr. */ CIA SEM_FN_NAME (m32r,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_19_jl.f +#define FLD(f) abuf->fields.fmt_20_jl.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -993,6 +983,7 @@ do { TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1)); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #if WITH_PROFILE_MODEL_P @@ -1012,13 +1003,14 @@ do { CIA SEM_FN_NAME (m32r,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_20_jmp.f +#define FLD(f) abuf->fields.fmt_21_jmp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2))); taken_p = 1; + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -1036,7 +1028,7 @@ SEM_FN_NAME (m32r,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_21_ld.f +#define FLD(f) abuf->fields.fmt_22_ld.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1060,7 +1052,7 @@ SEM_FN_NAME (m32r,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_22_ld_d.f +#define FLD(f) abuf->fields.fmt_23_ld_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1084,7 +1076,7 @@ SEM_FN_NAME (m32r,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_23_ldb.f +#define FLD(f) abuf->fields.fmt_24_ldb.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1108,7 +1100,7 @@ SEM_FN_NAME (m32r,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_24_ldb_d.f +#define FLD(f) abuf->fields.fmt_25_ldb_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1132,7 +1124,7 @@ SEM_FN_NAME (m32r,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_25_ldh.f +#define FLD(f) abuf->fields.fmt_26_ldh.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1156,7 +1148,7 @@ SEM_FN_NAME (m32r,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_26_ldh_d.f +#define FLD(f) abuf->fields.fmt_27_ldh_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1180,7 +1172,7 @@ SEM_FN_NAME (m32r,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_23_ldb.f +#define FLD(f) abuf->fields.fmt_24_ldb.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1204,7 +1196,7 @@ SEM_FN_NAME (m32r,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_24_ldb_d.f +#define FLD(f) abuf->fields.fmt_25_ldb_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1228,7 +1220,7 @@ SEM_FN_NAME (m32r,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_25_ldh.f +#define FLD(f) abuf->fields.fmt_26_ldh.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1252,7 +1244,7 @@ SEM_FN_NAME (m32r,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_26_ldh_d.f +#define FLD(f) abuf->fields.fmt_27_ldh_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1276,7 +1268,7 @@ SEM_FN_NAME (m32r,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_21_ld.f +#define FLD(f) abuf->fields.fmt_28_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1307,7 +1299,7 @@ do { CIA SEM_FN_NAME (m32r,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_27_ld24.f +#define FLD(f) abuf->fields.fmt_29_ld24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1330,7 +1322,7 @@ SEM_FN_NAME (m32r,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_28_ldi8.f +#define FLD(f) abuf->fields.fmt_30_ldi8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1353,7 +1345,7 @@ SEM_FN_NAME (m32r,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_29_ldi16.f +#define FLD(f) abuf->fields.fmt_31_ldi16.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1376,11 +1368,16 @@ SEM_FN_NAME (m32r,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_0_add.f +#define FLD(f) abuf->fields.fmt_32_lock.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); -do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); +do { + CPU (h_lock) = 1; + TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock)); +* FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2)); + TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1)); +} while (0); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -1399,7 +1396,7 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2)); CIA SEM_FN_NAME (m32r,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1422,7 +1419,7 @@ SEM_FN_NAME (m32r,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1445,7 +1442,7 @@ SEM_FN_NAME (m32r,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1468,7 +1465,7 @@ SEM_FN_NAME (m32r,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_30_machi.f +#define FLD(f) abuf->fields.fmt_33_machi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1515,7 +1512,7 @@ SEM_FN_NAME (m32r,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1538,7 +1535,7 @@ SEM_FN_NAME (m32r,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1561,7 +1558,7 @@ SEM_FN_NAME (m32r,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1584,7 +1581,7 @@ SEM_FN_NAME (m32r,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_34_mulhi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1607,7 +1604,7 @@ SEM_FN_NAME (m32r,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_31_mv.f +#define FLD(f) abuf->fields.fmt_35_mv.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1631,7 +1628,7 @@ SEM_FN_NAME (m32r,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_32_mvfachi.f +#define FLD(f) abuf->fields.fmt_36_mvfachi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1654,7 +1651,7 @@ SEM_FN_NAME (m32r,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_32_mvfachi.f +#define FLD(f) abuf->fields.fmt_36_mvfachi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1677,7 +1674,7 @@ SEM_FN_NAME (m32r,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_32_mvfachi.f +#define FLD(f) abuf->fields.fmt_36_mvfachi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1700,7 +1697,7 @@ SEM_FN_NAME (m32r,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_33_mvfc.f +#define FLD(f) abuf->fields.fmt_37_mvfc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1723,7 +1720,7 @@ SEM_FN_NAME (m32r,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_34_mvtachi.f +#define FLD(f) abuf->fields.fmt_38_mvtachi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1746,11 +1743,11 @@ SEM_FN_NAME (m32r,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_34_mvtachi.f +#define FLD(f) abuf->fields.fmt_38_mvtachi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); - CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1))); + CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (f_r1))); TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum)); #if WITH_PROFILE_MODEL_P @@ -1769,7 +1766,7 @@ SEM_FN_NAME (m32r,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_35_mvtc.f +#define FLD(f) abuf->fields.fmt_39_mvtc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1792,7 +1789,7 @@ m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2)); CIA SEM_FN_NAME (m32r,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_31_mv.f +#define FLD(f) abuf->fields.fmt_35_mv.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1816,7 +1813,7 @@ SEM_FN_NAME (m32r,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_36_nop.f +#define FLD(f) abuf->fields.fmt_40_nop.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1837,7 +1834,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); CIA SEM_FN_NAME (m32r,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_31_mv.f +#define FLD(f) abuf->fields.fmt_35_mv.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1861,7 +1858,7 @@ SEM_FN_NAME (m32r,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_37_rac.f +#define FLD(f) abuf->fields.fmt_41_rac.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1888,7 +1885,7 @@ do { CIA SEM_FN_NAME (m32r,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_37_rac.f +#define FLD(f) abuf->fields.fmt_41_rac.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -1924,7 +1921,7 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760 CIA SEM_FN_NAME (m32r,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_38_rte.f +#define FLD(f) abuf->fields.fmt_42_rte.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; @@ -1956,7 +1953,7 @@ do { CIA SEM_FN_NAME (m32r,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_39_seth.f +#define FLD(f) abuf->fields.fmt_43_seth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2003,7 +2000,7 @@ SEM_FN_NAME (m32r,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_44_sll3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2027,7 +2024,7 @@ SEM_FN_NAME (m32r,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_40_slli.f +#define FLD(f) abuf->fields.fmt_45_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2075,7 +2072,7 @@ SEM_FN_NAME (m32r,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_44_sll3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2099,7 +2096,7 @@ SEM_FN_NAME (m32r,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_40_slli.f +#define FLD(f) abuf->fields.fmt_45_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2147,7 +2144,7 @@ SEM_FN_NAME (m32r,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_5_addv3.f +#define FLD(f) abuf->fields.fmt_44_sll3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2171,7 +2168,7 @@ SEM_FN_NAME (m32r,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_40_slli.f +#define FLD(f) abuf->fields.fmt_45_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2195,7 +2192,7 @@ SEM_FN_NAME (m32r,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_46_st.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2218,7 +2215,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_41_st_d.f +#define FLD(f) abuf->fields.fmt_47_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2241,7 +2238,7 @@ SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_48_stb.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2264,7 +2261,7 @@ SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_41_st_d.f +#define FLD(f) abuf->fields.fmt_49_stb_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2287,7 +2284,7 @@ SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_50_sth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2310,7 +2307,7 @@ SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_41_st_d.f +#define FLD(f) abuf->fields.fmt_51_sth_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2333,7 +2330,7 @@ SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_52_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2348,6 +2345,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); if (PROFILE_MODEL_P (current_cpu)) { m32r_model_mark_get_h_gr (current_cpu, abuf); + m32r_model_mark_set_h_gr (current_cpu, abuf); m32r_model_profile_insn (current_cpu, abuf); } #endif @@ -2360,7 +2358,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); CIA SEM_FN_NAME (m32r,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_52_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2375,6 +2373,7 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); if (PROFILE_MODEL_P (current_cpu)) { m32r_model_mark_get_h_gr (current_cpu, abuf); + m32r_model_mark_set_h_gr (current_cpu, abuf); m32r_model_profile_insn (current_cpu, abuf); } #endif @@ -2411,7 +2410,7 @@ SEM_FN_NAME (m32r,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CIA SEM_FN_NAME (m32r,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_0_add.f +#define FLD(f) abuf->fields.fmt_5_addv.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2442,7 +2441,7 @@ do { CIA SEM_FN_NAME (m32r,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_6_addx.f +#define FLD(f) abuf->fields.fmt_7_addx.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); @@ -2473,12 +2472,19 @@ do { CIA SEM_FN_NAME (m32r,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_42_trap.f +#define FLD(f) abuf->fields.fmt_53_trap.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); int taken_p = 0; +do { +m32r_h_cr_set (current_cpu, 6, ADDSI (CPU (h_pc), 4)); + TRACE_RESULT (current_cpu, "h-cr-6", 'x', m32r_h_cr_get (current_cpu, 6)); +m32r_h_cr_set (current_cpu, 0, ANDSI (SRLSI (m32r_h_cr_get (current_cpu, 0), 8), 33488896)); + TRACE_RESULT (current_cpu, "h-cr-0", 'x', m32r_h_cr_get (current_cpu, 0)); do_trap (current_cpu, FLD (f_uimm4)); +; /*clobber*/ +} while (0); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -2495,11 +2501,18 @@ do_trap (current_cpu, FLD (f_uimm4)); CIA SEM_FN_NAME (m32r,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_15_cmp.f +#define FLD(f) abuf->fields.fmt_54_unlock.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = SEM_NEXT_PC (sem_arg); -do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2)); +do { +if (CPU (h_lock)) { +SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1)); + TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2))); +} + CPU (h_lock) = 0; + TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock)); +} while (0); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) diff --git a/sim/m32r/semx.c b/sim/m32r/semx.c index 4e2f8e9..910f231 100644 --- a/sim/m32r/semx.c +++ b/sim/m32r/semx.c @@ -394,6 +394,7 @@ SEM_FN_NAME (m32rx,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe if (OPRND (condbit)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -421,6 +422,7 @@ SEM_FN_NAME (m32rx,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (OPRND (condbit)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -448,6 +450,7 @@ SEM_FN_NAME (m32rx,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe if (EQSI (OPRND (src1), OPRND (src2))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -476,6 +479,7 @@ SEM_FN_NAME (m32rx,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (EQSI (OPRND (src2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -504,6 +508,7 @@ SEM_FN_NAME (m32rx,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (GESI (OPRND (src2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -532,6 +537,7 @@ SEM_FN_NAME (m32rx,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (GTSI (OPRND (src2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -560,6 +566,7 @@ SEM_FN_NAME (m32rx,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (LESI (OPRND (src2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -588,6 +595,7 @@ SEM_FN_NAME (m32rx,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (LTSI (OPRND (src2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -616,6 +624,7 @@ SEM_FN_NAME (m32rx,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (NESI (OPRND (src2), 0)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -646,6 +655,7 @@ do { CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #if WITH_PROFILE_MODEL_P @@ -676,6 +686,7 @@ do { CPU (h_gr[14]) = ADDSI (OPRND (pc), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #if WITH_PROFILE_MODEL_P @@ -707,6 +718,7 @@ do { CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); } @@ -739,6 +751,7 @@ do { CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); } @@ -768,6 +781,7 @@ SEM_FN_NAME (m32rx,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex if (NOTBI (OPRND (condbit))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -795,6 +809,7 @@ SEM_FN_NAME (m32rx,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e if (NOTBI (OPRND (condbit))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -822,6 +837,7 @@ SEM_FN_NAME (m32rx,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe if (NESI (OPRND (src1), OPRND (src2))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -849,6 +865,7 @@ SEM_FN_NAME (m32rx,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex EXTRACT_FMT_16_BRA8_CODE BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -874,6 +891,7 @@ SEM_FN_NAME (m32rx,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_e EXTRACT_FMT_17_BRA24_CODE BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -903,6 +921,7 @@ do { CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); } @@ -935,6 +954,7 @@ do { CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4); TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); } @@ -1265,6 +1285,7 @@ SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec if (OPRND (condbit)) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -1293,6 +1314,7 @@ SEM_FN_NAME (m32rx,jnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe if (NOTBI (OPRND (condbit))) { BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } #if WITH_PROFILE_MODEL_P @@ -1326,6 +1348,7 @@ do { CPU (h_gr[14]) = temp0; TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14])); BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1)); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); } while (0); #if WITH_PROFILE_MODEL_P @@ -1354,6 +1377,7 @@ SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe EXTRACT_FMT_25_JMP_CODE BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (sr))); + TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc)); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -1760,12 +1784,18 @@ SEM_FN_NAME (m32rx,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_ex EXTRACT_FMT_36_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ EXTRACT_FMT_36_LOCK_CODE -do_lock (current_cpu, OPRND (dr), OPRND (sr)); +do { + CPU (h_lock) = 1; + TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock)); + CPU (h_gr[f_r1]) = OPRND (h_memory_sr); + TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); +} while (0); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) { m32rx_model_mark_get_h_gr (current_cpu, abuf); + m32rx_model_mark_set_h_gr (current_cpu, abuf); m32rx_model_profile_insn (current_cpu, abuf); } #endif @@ -2192,76 +2222,16 @@ SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe #undef OPRND } -/* Perform rac-d: rac $accd. */ -CIA -SEM_FN_NAME (m32rx,rac_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) -{ - insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_45_rac_d.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_45_RAC_D_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_45_RAC_D_CODE - -do { - DI tmp_tmp1; - tmp_tmp1 = SLLDI (OPRND (accum), 1); - tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); -m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)))); - TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd)); -} while (0); - -#if WITH_PROFILE_MODEL_P - if (PROFILE_MODEL_P (current_cpu)) - { - m32rx_model_profile_insn (current_cpu, abuf); - } -#endif - - return new_pc; -#undef OPRND -} - -/* Perform rac-ds: rac $accd,$accs. */ -CIA -SEM_FN_NAME (m32rx,rac_ds) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) -{ - insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_46_rac_ds.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_46_RAC_DS_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_46_RAC_DS_CODE - -do { - DI tmp_tmp1; - tmp_tmp1 = SLLDI (OPRND (accs), 1); - tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); -m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)))); - TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd)); -} while (0); - -#if WITH_PROFILE_MODEL_P - if (PROFILE_MODEL_P (current_cpu)) - { - m32rx_model_profile_insn (current_cpu, abuf); - } -#endif - - return new_pc; -#undef OPRND -} - /* Perform rac-dsi: rac $accd,$accs,#$imm1. */ CIA SEM_FN_NAME (m32rx,rac_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_47_rac_dsi.f +#define OPRND(f) par_exec->operands.fmt_45_rac_dsi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_47_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_47_RAC_DSI_CODE + EXTRACT_FMT_45_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ + EXTRACT_FMT_45_RAC_DSI_CODE do { DI tmp_tmp1; @@ -2282,76 +2252,16 @@ m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0 #undef OPRND } -/* Perform rach-d: rach $accd. */ -CIA -SEM_FN_NAME (m32rx,rach_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) -{ - insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_45_rac_d.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_45_RAC_D_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_45_RAC_D_CODE - -do { - DI tmp_tmp1; - tmp_tmp1 = SLLDI (OPRND (accum), 1); - tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); -m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)))); - TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd)); -} while (0); - -#if WITH_PROFILE_MODEL_P - if (PROFILE_MODEL_P (current_cpu)) - { - m32rx_model_profile_insn (current_cpu, abuf); - } -#endif - - return new_pc; -#undef OPRND -} - -/* Perform rach-ds: rach $accd,$accs. */ -CIA -SEM_FN_NAME (m32rx,rach_ds) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) -{ - insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_46_rac_ds.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_46_RAC_DS_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_46_RAC_DS_CODE - -do { - DI tmp_tmp1; - tmp_tmp1 = SLLDI (OPRND (accs), 1); - tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); -m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)))); - TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd)); -} while (0); - -#if WITH_PROFILE_MODEL_P - if (PROFILE_MODEL_P (current_cpu)) - { - m32rx_model_profile_insn (current_cpu, abuf); - } -#endif - - return new_pc; -#undef OPRND -} - /* Perform rach-dsi: rach $accd,$accs,#$imm1. */ CIA SEM_FN_NAME (m32rx,rach_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_47_rac_dsi.f +#define OPRND(f) par_exec->operands.fmt_45_rac_dsi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_47_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_47_RAC_DSI_CODE + EXTRACT_FMT_45_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ + EXTRACT_FMT_45_RAC_DSI_CODE do { DI tmp_tmp1; @@ -2377,12 +2287,12 @@ CIA SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_48_rte.f +#define OPRND(f) par_exec->operands.fmt_46_rte.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; int taken_p = 0; - EXTRACT_FMT_48_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_48_RTE_CODE + EXTRACT_FMT_46_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_46_RTE_CODE do { CPU (h_sm) = OPRND (h_bsm_0); @@ -2411,11 +2321,11 @@ CIA SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_49_seth.f +#define OPRND(f) par_exec->operands.fmt_47_seth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_49_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ - EXTRACT_FMT_49_SETH_CODE + EXTRACT_FMT_47_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ + EXTRACT_FMT_47_SETH_CODE CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2464,11 +2374,11 @@ CIA SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_50_sll3.f +#define OPRND(f) par_exec->operands.fmt_48_sll3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_50_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_50_SLL3_CODE + EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_48_SLL3_CODE CPU (h_gr[f_r1]) = SLLSI (OPRND (sr), ANDSI (OPRND (simm16), 31)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2491,11 +2401,11 @@ CIA SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_51_slli.f +#define OPRND(f) par_exec->operands.fmt_49_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_51_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ - EXTRACT_FMT_51_SLLI_CODE + EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ + EXTRACT_FMT_49_SLLI_CODE CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2545,11 +2455,11 @@ CIA SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_50_sll3.f +#define OPRND(f) par_exec->operands.fmt_48_sll3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_50_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_50_SLL3_CODE + EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_48_SLL3_CODE CPU (h_gr[f_r1]) = SRASI (OPRND (sr), ANDSI (OPRND (simm16), 31)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2572,11 +2482,11 @@ CIA SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_51_slli.f +#define OPRND(f) par_exec->operands.fmt_49_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_51_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ - EXTRACT_FMT_51_SLLI_CODE + EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ + EXTRACT_FMT_49_SLLI_CODE CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2626,11 +2536,11 @@ CIA SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_50_sll3.f +#define OPRND(f) par_exec->operands.fmt_48_sll3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_50_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_50_SLL3_CODE + EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_48_SLL3_CODE CPU (h_gr[f_r1]) = SRLSI (OPRND (sr), ANDSI (OPRND (simm16), 31)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2653,11 +2563,11 @@ CIA SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_51_slli.f +#define OPRND(f) par_exec->operands.fmt_49_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_51_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ - EXTRACT_FMT_51_SLLI_CODE + EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ + EXTRACT_FMT_49_SLLI_CODE CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -2680,11 +2590,11 @@ CIA SEM_FN_NAME (m32rx,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_52_st.f +#define OPRND(f) par_exec->operands.fmt_50_st.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_52_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_52_ST_CODE + EXTRACT_FMT_50_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_50_ST_CODE SETMEMSI (current_cpu, OPRND (src2), OPRND (src1)); TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2))); @@ -2706,11 +2616,11 @@ CIA SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_53_st_d.f +#define OPRND(f) par_exec->operands.fmt_51_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_53_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_53_ST_D_CODE + EXTRACT_FMT_51_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_51_ST_D_CODE SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1)); TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)))); @@ -2732,11 +2642,11 @@ CIA SEM_FN_NAME (m32rx,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_54_stb.f +#define OPRND(f) par_exec->operands.fmt_52_stb.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_54_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_54_STB_CODE + EXTRACT_FMT_52_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_52_STB_CODE SETMEMQI (current_cpu, OPRND (src2), OPRND (src1)); TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, OPRND (src2))); @@ -2758,11 +2668,11 @@ CIA SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_55_stb_d.f +#define OPRND(f) par_exec->operands.fmt_53_stb_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_55_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_55_STB_D_CODE + EXTRACT_FMT_53_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_53_STB_D_CODE SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1)); TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)))); @@ -2784,11 +2694,11 @@ CIA SEM_FN_NAME (m32rx,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_56_sth.f +#define OPRND(f) par_exec->operands.fmt_54_sth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_56_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_56_STH_CODE + EXTRACT_FMT_54_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_54_STH_CODE SETMEMHI (current_cpu, OPRND (src2), OPRND (src1)); TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, OPRND (src2))); @@ -2810,11 +2720,11 @@ CIA SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_57_sth_d.f +#define OPRND(f) par_exec->operands.fmt_55_sth_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_57_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_57_STH_D_CODE + EXTRACT_FMT_55_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_FMT_55_STH_D_CODE SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1)); TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)))); @@ -2836,11 +2746,11 @@ CIA SEM_FN_NAME (m32rx,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_58_st_plus.f +#define OPRND(f) par_exec->operands.fmt_56_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_58_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_58_ST_PLUS_CODE + EXTRACT_FMT_56_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_56_ST_PLUS_CODE do { CPU (h_gr[f_r2]) = ADDSI (OPRND (src2), 4); @@ -2867,11 +2777,11 @@ CIA SEM_FN_NAME (m32rx,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_58_st_plus.f +#define OPRND(f) par_exec->operands.fmt_56_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_58_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_58_ST_PLUS_CODE + EXTRACT_FMT_56_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_56_ST_PLUS_CODE do { CPU (h_gr[f_r2]) = SUBSI (OPRND (src2), 4); @@ -2993,14 +2903,21 @@ CIA SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_59_trap.f +#define OPRND(f) par_exec->operands.fmt_57_trap.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; int taken_p = 0; - EXTRACT_FMT_59_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ - EXTRACT_FMT_59_TRAP_CODE + EXTRACT_FMT_57_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ + EXTRACT_FMT_57_TRAP_CODE +do { +m32rx_h_cr_set (current_cpu, 6, ADDSI (OPRND (pc), 4)); + TRACE_RESULT (current_cpu, "h-cr-6", 'x', m32rx_h_cr_get (current_cpu, 6)); +m32rx_h_cr_set (current_cpu, 0, ANDSI (SRLSI (OPRND (h_cr_0), 8), 33488896)); + TRACE_RESULT (current_cpu, "h-cr-0", 'x', m32rx_h_cr_get (current_cpu, 0)); do_trap (current_cpu, OPRND (uimm4)); +; /*clobber*/ +} while (0); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -3018,13 +2935,20 @@ CIA SEM_FN_NAME (m32rx,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_60_unlock.f +#define OPRND(f) par_exec->operands.fmt_58_unlock.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_60_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_60_UNLOCK_CODE + EXTRACT_FMT_58_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_58_UNLOCK_CODE -do_unlock (current_cpu, OPRND (src1), OPRND (src2)); +do { +if (OPRND (h_lock_0)) { +SETMEMSI (current_cpu, OPRND (src2), OPRND (src1)); + TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2))); +} + CPU (h_lock) = 0; + TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock)); +} while (0); #if WITH_PROFILE_MODEL_P if (PROFILE_MODEL_P (current_cpu)) @@ -3043,11 +2967,11 @@ CIA SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_61_satb.f +#define OPRND(f) par_exec->operands.fmt_59_satb.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_61_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_61_SATB_CODE + EXTRACT_FMT_59_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_FMT_59_SATB_CODE CPU (h_gr[f_r1]) = (GESI (OPRND (sr), 127)) ? (127) : (LESI (OPRND (sr), -128)) ? (-128) : (OPRND (sr)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -3070,11 +2994,11 @@ CIA SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_61_satb.f +#define OPRND(f) par_exec->operands.fmt_59_satb.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_61_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_61_SATB_CODE + EXTRACT_FMT_59_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_FMT_59_SATB_CODE CPU (h_gr[f_r1]) = (GESI (OPRND (sr), 32767)) ? (32767) : (LESI (OPRND (sr), -32768)) ? (-32768) : (OPRND (sr)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -3097,11 +3021,11 @@ CIA SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_62_sat.f +#define OPRND(f) par_exec->operands.fmt_60_sat.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 4; - EXTRACT_FMT_62_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_62_SAT_CODE + EXTRACT_FMT_60_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_FMT_60_SAT_CODE CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (sr), 0)) ? (2147483647) : (0x80000000)) : (OPRND (sr)); TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1])); @@ -3150,11 +3074,11 @@ CIA SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_63_sadd.f +#define OPRND(f) par_exec->operands.fmt_61_sadd.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_63_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_63_SADD_CODE + EXTRACT_FMT_61_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_61_SADD_CODE m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums_1), 16), OPRND (h_accums_0))); TRACE_RESULT (current_cpu, "h-accums-0", 'D', m32rx_h_accums_get (current_cpu, 0)); @@ -3175,11 +3099,11 @@ CIA SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_64_macwu1.f +#define OPRND(f) par_exec->operands.fmt_62_macwu1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_64_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_64_MACWU1_CODE + EXTRACT_FMT_62_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_62_MACWU1_CODE m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8)); TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1)); @@ -3201,11 +3125,11 @@ CIA SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_65_msblo.f +#define OPRND(f) par_exec->operands.fmt_63_msblo.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_65_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_65_MSBLO_CODE + EXTRACT_FMT_63_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_63_MSBLO_CODE CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8); TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum)); @@ -3227,11 +3151,11 @@ CIA SEM_FN_NAME (m32rx,mulwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_66_mulwu1.f +#define OPRND(f) par_exec->operands.fmt_64_mulwu1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_66_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_66_MULWU1_CODE + EXTRACT_FMT_64_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_64_MULWU1_CODE m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535))), 16), 16)); TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1)); @@ -3253,11 +3177,11 @@ CIA SEM_FN_NAME (m32rx,maclh1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_64_macwu1.f +#define OPRND(f) par_exec->operands.fmt_62_macwu1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_64_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_64_MACWU1_CODE + EXTRACT_FMT_62_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_62_MACWU1_CODE m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8)); TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1)); @@ -3279,11 +3203,11 @@ CIA SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_67_sc.f +#define OPRND(f) par_exec->operands.fmt_65_sc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_67_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_67_SC_CODE + EXTRACT_FMT_65_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_65_SC_CODE if (OPRND (condbit)) { CPU (h_abort) = 1; @@ -3306,11 +3230,11 @@ CIA SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec) { insn_t insn = SEM_INSN (sem_arg); -#define OPRND(f) par_exec->operands.fmt_67_sc.f +#define OPRND(f) par_exec->operands.fmt_65_sc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); CIA new_pc = CPU (h_pc) + 2; - EXTRACT_FMT_67_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_67_SC_CODE + EXTRACT_FMT_65_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_FMT_65_SC_CODE if (NOTBI (OPRND (condbit))) { CPU (h_abort) = 1; |