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| author | Adam Nemet <anemet@caviumnetworks.com> | 2009-02-18 20:51:59 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@caviumnetworks.com> | 2009-02-18 20:51:59 +0000 |
| commit | b1c9882d1b9f182538c9babb35fe11d152708fe0 (patch) | |
| tree | 5c370618947dbb2571b223bb9dca2797f03e65ca | |
| parent | 134eb42cf4b2b8363c5e93bac14b4903170880c2 (diff) | |
| download | fsf-binutils-gdb-b1c9882d1b9f182538c9babb35fe11d152708fe0.zip fsf-binutils-gdb-b1c9882d1b9f182538c9babb35fe11d152708fe0.tar.gz fsf-binutils-gdb-b1c9882d1b9f182538c9babb35fe11d152708fe0.tar.bz2 | |
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
dmfc2 and dmtc2 before the architecture-level variants.
gas/testsuite/
* gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2.
* gas/mips/octeon.d: Update.
* gas/mips/octeon-ill.l: Update error message.
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/octeon-ill.l | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/octeon.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/octeon.s | 4 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
6 files changed, 25 insertions, 6 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 5c0b550..18305c6 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2009-02-18 Adam Nemet <anemet@caviumnetworks.com> + + * gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2. + * gas/mips/octeon.d: Update. + * gas/mips/octeon-ill.l: Update error message. + 2009-02-16 Nick Clifton <nickc@redhat.com> * gas/mips/e32-rel2.d: Adjust expected output to remove the 0x4000 diff --git a/gas/testsuite/gas/mips/octeon-ill.l b/gas/testsuite/gas/mips/octeon-ill.l index b90eaf1..cdd1e5a 100644 --- a/gas/testsuite/gas/mips/octeon-ill.l +++ b/gas/testsuite/gas/mips/octeon-ill.l @@ -28,11 +28,11 @@ .*:41: Error: opcode not supported on this processor.* .*:42: Error: opcode not supported on this processor.* .*:43: Error: opcode not supported on this processor.* -.*:45: Error: expression out of range -.*:46: Error: expression out of range -.*:47: Error: register value used as expression +.*:45: Error: illegal operands `dmfc2 \$2,0x10000' +.*:46: Error: illegal operands `dmtc2 \$2,0x12345' +.*:47: Error: illegal operands `dmfc2 \$9,\$12' .*:48: Error: illegal operands `dmfc2 \$4,\$15,4' -.*:49: Error: register value used as expression +.*:49: Error: illegal operands `dmtc2 \$16,\$8' .*:50: Error: illegal operands `dmtc2 \$22,\$7,\$4' .*:52: Error: Improper size \(32\) .*:54: Error: Improper position \(32\) diff --git a/gas/testsuite/gas/mips/octeon.d b/gas/testsuite/gas/mips/octeon.d index 5e32ae6..79b4001 100644 --- a/gas/testsuite/gas/mips/octeon.d +++ b/gas/testsuite/gas/mips/octeon.d @@ -46,7 +46,11 @@ Disassembly of section .text: .*: 41606000 di .*: 41606020 ei .*: 48230084 dmfc2 \$3,0x84 +.*: 48260800 dmfc2 \$6,0x800 +.*: 482c0001 dmfc2 \$12,0x1 .*: 48a84200 dmtc2 \$8,0x4200 +.*: 48a72000 dmtc2 \$7,0x2000 +.*: 48a20004 dmtc2 \$2,0x4 .*: 73400008 mtm0 \$26 .*: 7260000c mtm1 \$19 .*: 7240000d mtm2 \$18 diff --git a/gas/testsuite/gas/mips/octeon.s b/gas/testsuite/gas/mips/octeon.s index 4772b4c..c73ffd9 100644 --- a/gas/testsuite/gas/mips/octeon.s +++ b/gas/testsuite/gas/mips/octeon.s @@ -47,7 +47,11 @@ foo: di ei dmfc2 $3,0x84 + dmfc2 $6,0x800 + dmfc2 $12,0x1 dmtc2 $8,0x4200 + dmtc2 $7,0x2000 + dmtc2 $2,0x4 mtm0 $26 mtm1 $19 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 941aff1..db66f45 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-02-18 Adam Nemet <anemet@caviumnetworks.com> + + * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific + dmfc2 and dmtc2 before the architecture-level variants. + 2009-02-18 Pierre Muller <muller@ics.u-strasbg.fr> * fr30-opc.c: Regenerate. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 12a8cbe..fdf90ae 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1506,12 +1506,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, -{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, +{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, -{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, |