diff options
author | Nick Clifton <nickc@redhat.com> | 2009-11-17 17:20:26 +0000 |
---|---|---|
committer | Nick Clifton <nickc@redhat.com> | 2009-11-17 17:20:26 +0000 |
commit | aefd8a406ce2c3fb7917a232357181d9629b4323 (patch) | |
tree | c134a4935d1d4a4bca0e4f044808b61216625aff | |
parent | 9e3c6df6645d115d2bd5bc11e40c50f03049ebaa (diff) | |
download | fsf-binutils-gdb-aefd8a406ce2c3fb7917a232357181d9629b4323.zip fsf-binutils-gdb-aefd8a406ce2c3fb7917a232357181d9629b4323.tar.gz fsf-binutils-gdb-aefd8a406ce2c3fb7917a232357181d9629b4323.tar.bz2 |
* gas/arm/vfma1.d: Only run on ELF based targets.
PR binutils/10924
* gas/arm/arch4t-eabi.d: Update expected disassembly.
* gas/arm/arch4t.d: Likewise.
* gas/arm/archv6t2.d: Likewise.
* gas/arm/arm7t.d: Likewise.
* gas/arm/inst.d: Likewise.
* gas/arm/xscale.d: Likewise.
PR binutils/10924
* arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB
instruction variants. Add pattern for MRS variant that was being
confused with CMP.
(arm_decode_shift): Place error message in a comment.
(print_insn_arm): Note that writing back to the PC is
unpredictable.
Only print 'p' variants of cmp/cmn/teq/tst instructions if
decoding for pre-V6 architectures.
-rw-r--r-- | gas/testsuite/ChangeLog | 14 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/arch4t-eabi.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/arch4t.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/archv6t2.d | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/arm7t.d | 16 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/inst.d | 32 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/vfma1.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/xscale.d | 2 | ||||
-rw-r--r-- | opcodes/ChangeLog | 12 | ||||
-rw-r--r-- | opcodes/arm-dis.c | 44 |
10 files changed, 93 insertions, 47 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 93d37d1..c974862 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -9,6 +9,20 @@ 2009-11-17 Nick Clifton <nickc@redhat.com> + * gas/arm/vfma1.d: Only run on ELF based targets. + +2009-11-17 Nick Clifton <nickc@redhat.com> + + PR binutils/10924 + * gas/arm/arch4t-eabi.d: Update expected disassembly. + * gas/arm/arch4t.d: Likewise. + * gas/arm/archv6t2.d: Likewise. + * gas/arm/arm7t.d: Likewise. + * gas/arm/inst.d: Likewise. + * gas/arm/xscale.d: Likewise. + +2009-11-17 Nick Clifton <nickc@redhat.com> + * gas/rx/macros.inc (creg): Remove cpen. * gas/rx/mvfc.d: Remove expected uses of cpen register. * gas/rx/mvtc.d: Likewise. diff --git a/gas/testsuite/gas/arm/arch4t-eabi.d b/gas/testsuite/gas/arm/arch4t-eabi.d index afd92f7..959770b 100644 --- a/gas/testsuite/gas/arm/arch4t-eabi.d +++ b/gas/testsuite/gas/arm/arch4t-eabi.d @@ -12,7 +12,7 @@ Disassembly of section .text: 0+04 <[^>]+> 012fff11 ? bxeq r1 .*: R_ARM_V4BX.* 0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> -0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] +0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5, #0\] 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] @@ -22,7 +22,7 @@ Disassembly of section .text: 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3, #0\] 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d index 6655852..dd979cd 100644 --- a/gas/testsuite/gas/arm/arch4t.d +++ b/gas/testsuite/gas/arm/arch4t.d @@ -10,7 +10,7 @@ Disassembly of section .text: 0+00 <[^>]+> e12fff10 ? bx r0 0+04 <[^>]+> 012fff11 ? bxeq r1 0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> -0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] +0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5, #0\] 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] @@ -20,7 +20,7 @@ Disassembly of section .text: 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3, #0\] 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d index cacf641..2c8d5b6 100644 --- a/gas/testsuite/gas/arm/archv6t2.d +++ b/gas/testsuite/gas/arm/archv6t2.d @@ -40,11 +40,11 @@ Disassembly of section .text: 0+80 <[^>]+> e3009000 movw r9, #0 0+84 <[^>]+> e3000999 movw r0, #2457 ; 0x999 0+88 <[^>]+> e3090000 movw r0, #36864 ; 0x9000 -0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\] -0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\] -0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\] -0+98 <[^>]+> e0e900b0 strht r0, \[r9\] -0+9c <[^>]+> 10f900b0 ldrhtne r0, \[r9\] +0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\], #0 +0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\], #0 +0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\], #0 +0+98 <[^>]+> e0e900b0 strht r0, \[r9\], #0 +0+9c <[^>]+> 10f900b0 ldrhtne r0, \[r9\], #0 0+a0 <[^>]+> e0b090b9 ldrht r9, \[r0\], r9 0+a4 <[^>]+> e03090b9 ldrht r9, \[r0\], -r9 0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153.* diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d index 2d16984..4d1ca3c 100644 --- a/gas/testsuite/gas/arm/arm7t.d +++ b/gas/testsuite/gas/arm/arm7t.d @@ -7,8 +7,8 @@ .*: +file format .*arm.* Disassembly of section .text: -0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1\] -0+04 <[^>]*> e1f100b0 ? ldrh r0, \[r1\]! +0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1, #0\] +0+04 <[^>]*> e1f100b0 ? ldrh r0, \[r1, #0\]! 0+08 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] 0+0c <[^>]*> e1b100b2 ? ldrh r0, \[r1, r2\]! 0+10 <[^>]*> e1d100bc ? ldrh r0, \[r1, #12\] @@ -18,8 +18,8 @@ Disassembly of section .text: 0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] ; 0+e0 <[^>]*> 0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*> -0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\] -0+30 <[^>]*> e1e100b0 ? strh r0, \[r1\]! +0+2c <[^>]*> e1c100b0 ? strh r0, \[r1, #0\] +0+30 <[^>]*> e1e100b0 ? strh r0, \[r1, #0\]! 0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\] 0+38 <[^>]*> e1a100b2 ? strh r0, \[r1, r2\]! 0+3c <[^>]*> e1c100bc ? strh r0, \[r1, #12\] @@ -27,8 +27,8 @@ Disassembly of section .text: 0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\] 0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2 0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*> -0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\] -0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1\]! +0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1, #0\] +0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1, #0\]! 0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] 0+5c <[^>]*> e1b100d2 ? ldrsb r0, \[r1, r2\]! 0+60 <[^>]*> e1d100dc ? ldrsb r0, \[r1, #12\] @@ -37,8 +37,8 @@ Disassembly of section .text: 0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2 0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde 0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*> -0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\] -0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1\]! +0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1, #0\] +0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1, #0\]! 0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] 0+84 <[^>]*> e1b100f2 ? ldrsh r0, \[r1, r2\]! 0+88 <[^>]*> e1d100fc ? ldrsh r0, \[r1, #12\] diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index d2ea435..e61bbfd 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -95,22 +95,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 -0+15c <[^>]*> e132f004 ? teqp r2, r4 -0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 -0+16c <[^>]*> e172f004 ? cmnp r2, r4 -0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 -0+17c <[^>]*> e152f004 ? cmpp r2, r4 -0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 -0+18c <[^>]*> e112f004 ? tstp r2, r4 -0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 +0+158 <[^>]*> e330f00a ? teq r0, #10 +0+15c <[^>]*> e132f004 ? teq r2, r4 +0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 +0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 +0+168 <[^>]*> e370f00a ? cmn r0, #10 +0+16c <[^>]*> e172f004 ? cmn r2, r4 +0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 +0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 +0+178 <[^>]*> e350f00a ? cmp r0, #10 +0+17c <[^>]*> e152f004 ? cmp r2, r4 +0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 +0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 +0+188 <[^>]*> e310f00a ? tst r0, #10 +0+18c <[^>]*> e112f004 ? tst r2, r4 +0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 +0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/gas/testsuite/gas/arm/vfma1.d b/gas/testsuite/gas/arm/vfma1.d index 4c638d3..a60e430 100644 --- a/gas/testsuite/gas/arm/vfma1.d +++ b/gas/testsuite/gas/arm/vfma1.d @@ -1,6 +1,8 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: VFMA decoding #as: -mcpu=arm7m +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* # Test VFMA instruction disassembly diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d index da4d1d7..01056cd 100644 --- a/gas/testsuite/gas/arm/xscale.d +++ b/gas/testsuite/gas/arm/xscale.d @@ -23,7 +23,7 @@ Disassembly of section .text: 0+34 <[^>]*> f5d1f789 pld \[r1, #1929\].* 0+38 <[^>]*> f7d2f003 pld \[r2, r3\] 0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] -0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] +0+40 <[^>]*> e1c100d0 ldrd r0, \[r1, #0\] 0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\].* 0+48 <[^>]*> b10540d6 ldrdlt r4, \[r5, -r6\] 0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]!.* diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7f3dee9..ebe6acf 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2009-11-17 Nick Clifton <nickc@redhat.com> + + PR binutils/10924 + * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB + instruction variants. Add pattern for MRS variant that was being + confused with CMP. + (arm_decode_shift): Place error message in a comment. + (print_insn_arm): Note that writing back to the PC is + unpredictable. + Only print 'p' variants of cmp/cmn/teq/tst instructions if + decoding for pre-V6 architectures. + 2009-11-17 Edward Nevill <edward.nevill@arm.com> * arm-dis.c (print_insn_thumb32): Handle undefined instruction. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index ba19f7c..e59cc6c 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -56,7 +56,7 @@ struct opcode32 struct opcode16 { unsigned long arch; /* Architecture defining this insn. */ - unsigned short value, mask; /* Recognise insn if (op&mask)==value. */ + unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ const char *assembler; /* How to disassemble this insn. */ }; @@ -112,7 +112,7 @@ enum opcode_sentinel_enum SENTINEL_GENERIC_START } opcode_sentinels; -#define UNDEFINED_INSTRUCTION "undefined instruction %0-31x" +#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" /* Common coprocessor opcodes shared between Arm and Thumb-2. */ @@ -825,7 +825,10 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %S"}, + + {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %S"}, + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, @@ -1022,7 +1025,10 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15r, %a"}, {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15r, %s"}, {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15r, %s"}, + + {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15r, %s"}, {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, @@ -1069,6 +1075,7 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19r, %o"}, {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + {ARM_EXT_V3, 0x01400000, 0x0ff00010, "mrs%c\t%12-15r, %22?SCPSR"}, {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19r, %o"}, @@ -1693,7 +1700,7 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream, func (stream, ", #%d", amount); } else if ((given & 0x80) == 0x80) - func (stream, ", <illegal shifter operand>"); + func (stream, "\t; <illegal shifter operand>"); else if (print_shift) func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], arm_regnames[(given & 0xf00) >> 8]); @@ -2862,8 +2869,16 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (NEGATIVE_BIT_SET) offset = - offset; - func (stream, "[pc, #%d]\t; ", offset); - info->print_address_func (offset + pc + 8, info); + if (PRE_BIT_SET) + { + func (stream, "[pc, #%d]\t; ", offset); + info->print_address_func (offset + pc + 8, info); + } + else + { + func (stream, "[pc], #%d", offset); + func (stream, UNPREDICTABLE_INSTRUCTION); + } } else { @@ -2880,8 +2895,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) /* Pre-indexed. */ if (IMMEDIATE_BIT_SET) { - if (offset) - func (stream, ", #%d", offset); + /* PR 10924: Offset must be printed, even if it is zero. */ + func (stream, ", #%d", offset); value_in_comment = offset; } else /* Register. */ @@ -2896,11 +2911,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { if (IMMEDIATE_BIT_SET) { - if (offset) - func (stream, "], #%d", offset); - else - func (stream, "]"); - + /* PR 10924: Offset must be printed, even if it is zero. */ + func (stream, "], #%d", offset); value_in_comment = offset; } else /* Register. */ @@ -2966,7 +2978,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'p': if ((given & 0x0000f000) == 0x0000f000) - func (stream, "p"); + { + /* The p-variants of tst/cmp/cmn/teq are the pre-V6 + mechanism for setting PSR flag bits. They are + obsolete in V6 onwards. */ + if (((((arm_feature_set *) info->private_data)->core) & ARM_EXT_V6) == 0) + func (stream, "p"); + } break; case 't': |