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authorPhilipp Tomsich <prt@gnu.org>2021-01-07 15:53:25 +0800
committerNelson Chu <nelson.chu@sifive.com>2021-01-07 16:45:43 +0800
commitaa881ecde48c7a0224b92e2cfa43b37ee9ec9fa2 (patch)
tree1b0e0814c4a7ed9567d8d49aad19de327ea78682
parent4d4490b8d772321e9634541b81be25095a5a06ef (diff)
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RISC-V: Add pause hint instruction.
Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
-rw-r--r--bfd/ChangeLog4
-rw-r--r--bfd/elfxx-riscv.c2
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-riscv.c2
-rw-r--r--gas/testsuite/gas/riscv/pause.d10
-rw-r--r--gas/testsuite/gas/riscv/pause.s2
-rw-r--r--include/ChangeLog6
-rw-r--r--include/opcode/riscv-opc.h3
-rw-r--r--include/opcode/riscv.h1
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/riscv-opc.c3
11 files changed, 44 insertions, 1 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 4843f0a..75fb3a5 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2021-01-07 Philipp Tomsich <prt@gnu.org>
+
+ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
+
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f40a923..42aeed7 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
static const char * const riscv_std_z_ext_strtab[] =
{
- "zicsr", "zifencei", "zba", "zbb", "zbc", NULL
+ "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", NULL
};
static const char * const riscv_std_s_ext_strtab[] =
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c99e1b3..48c21f7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2021-01-07 Philipp Tomsich <prt@gnu.org>
+
+ * config/tc-riscv.c (riscv_multi_subset_supports): Added
+ INSN_CLASS_ZIHINTPAUSE.
+ * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for
+ the pause hint instruction.
+ * testsuite/gas/riscv/pause.s: Likewise.
+
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 052199e..8dc84cb 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -250,6 +250,8 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
return riscv_subset_supports ("zicsr");
case INSN_CLASS_ZIFENCEI:
return riscv_subset_supports ("zifencei");
+ case INSN_CLASS_ZIHINTPAUSE:
+ return riscv_subset_supports ("zihintpause");
case INSN_CLASS_ZBA:
return riscv_subset_supports ("zba");
diff --git a/gas/testsuite/gas/riscv/pause.d b/gas/testsuite/gas/riscv/pause.d
new file mode 100644
index 0000000..13e581d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/pause.d
@@ -0,0 +1,10 @@
+#as: -march=rv32i_zihintpause
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+0100000f[ ]+pause
diff --git a/gas/testsuite/gas/riscv/pause.s b/gas/testsuite/gas/riscv/pause.s
new file mode 100644
index 0000000..4cdf357
--- /dev/null
+++ b/gas/testsuite/gas/riscv/pause.s
@@ -0,0 +1,2 @@
+target:
+ pause
diff --git a/include/ChangeLog b/include/ChangeLog
index 80be817..6345fc5 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2021-01-07 Philipp Tomsich <prt@gnu.org>
+
+ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
+ for pause hint instruction.
+ * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
+
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 7dbe830..38ce41d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -157,6 +157,8 @@
#define MASK_SW 0x707f
#define MATCH_SD 0x3023
#define MASK_SD 0x707f
+#define MATCH_PAUSE 0x0100000f
+#define MASK_PAUSE 0xffffffff
#define MATCH_FENCE 0xf
#define MASK_FENCE 0x707f
#define MATCH_FENCE_I 0x100f
@@ -984,6 +986,7 @@ DECLARE_INSN(sb, MATCH_SB, MASK_SB)
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 326d840..33ef290 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -311,6 +311,7 @@ enum riscv_insn_class
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
+ INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4f4e54e..2add0e7 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2021-01-07 Philipp Tomsich <prt@gnu.org>
+
+ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
+
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index cb980f2..7c262dd 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -345,6 +345,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
+{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 },
{"fence", 0, INSN_CLASS_I, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
@@ -977,6 +978,8 @@ const struct riscv_ext_version riscv_ext_version_table[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
+
{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},