[AArch64] Add missing C_MAX_ELEM flags for SVE conversions

SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.

Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
	to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.

gas/
	* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
	SCVTF, UCVTF, LSR and ASR.
	* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.

6 files changed, 113 insertions, 35 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 05537e2..3a76a05 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
+	SCVTF, UCVTF, LSR and ASR.
+	* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
+	* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
 	to be prefixed by MOVPRFX.
 	* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.d b/gas/testsuite/gas/aarch64/sve-movprfx_26.d
index 00bafdc..1f7a85d 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_26.d
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.d
@@ -16,8 +16,48 @@ Disassembly of section .*:
 [^:]+:	65cba440 	fcvt	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
 [^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
 [^:]+:	65cba440 	fcvt	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d8a440 	fcvtzs	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d8a440 	fcvtzs	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65dca440 	fcvtzs	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65dca440 	fcvtzs	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d9a440 	fcvtzu	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d9a440 	fcvtzu	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65dda440 	fcvtzu	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65dda440 	fcvtzu	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d4a440 	scvtf	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d4a440 	scvtf	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d0a440 	scvtf	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d0a440 	scvtf	z0.d, p1/m, z2.s
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d5a440 	ucvtf	z0.s, p1/m, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d5a440 	ucvtf	z0.s, p1/m, z2.d
+[^:]+:	04912420 	movprfx	z0.s, p1/m, z1.s
+[^:]+:	65d1a440 	ucvtf	z0.d, p1/m, z2.s  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	65d1a440 	ucvtf	z0.d, p1/m, z2.s
 [^:]+:	04112420 	movprfx	z0.b, p1/m, z1.b
 [^:]+:	041b8440 	lsl	z0.b, p1/m, z0.b, z2.d
 [^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
 [^:]+:	041b8440 	lsl	z0.b, p1/m, z0.b, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04112420 	movprfx	z0.b, p1/m, z1.b
+[^:]+:	04198440 	lsr	z0.b, p1/m, z0.b, z2.d
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	04198440 	lsr	z0.b, p1/m, z0.b, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+:	04112420 	movprfx	z0.b, p1/m, z1.b
+[^:]+:	04188440 	asr	z0.b, p1/m, z0.b, z2.d
+[^:]+:	04d12420 	movprfx	z0.d, p1/m, z1.d
+[^:]+:	04188440 	asr	z0.b, p1/m, z0.b, z2.d  // note: register size not compatible with previous `movprfx' at operand 1
 [^:]+:	d65f03c0 	ret
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.l b/gas/testsuite/gas/aarch64/sve-movprfx_26.l
index 695f90f..3595566 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_26.l
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.l
@@ -1,4 +1,14 @@
 [^:]*: Assembler messages:
 .*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.S,P1/M,Z2.D'
 .*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.D,P1/M,Z2.S'
-.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
\ No newline at end of file
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzs Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzs Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzu Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzu Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `scvtf Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `scvtf Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `ucvtf Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `ucvtf Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsr Z0.B,P1/M,Z0.B,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `asr Z0.B,P1/M,Z0.B,Z2.D'
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.s b/gas/testsuite/gas/aarch64/sve-movprfx_26.s
index 15f52db..859a0e2 100644
--- a/gas/testsuite/gas/aarch64/sve-movprfx_26.s
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.s
@@ -4,28 +4,44 @@
   .arch armv8-a+sve
 
 f:
+  .macro test_cvt, insn
+
   /* Not OK, 64-bit operation, upper 32-bits cleared.  */
   movprfx Z0.S, P1/M, Z1.S
-  fcvt Z0.S, P1/M, Z2.D
+  \insn Z0.S, P1/M, Z2.D
 
   /* OK, 64-bit operation, upper 32-bits cleared.  */
   movprfx Z0.D, P1/M, Z1.D
-  fcvt Z0.S, P1/M, Z2.D
+  \insn Z0.S, P1/M, Z2.D
 
   /* Not OK, 64-bit operation ignoring 32-bits.  */
   movprfx Z0.S, P1/M, Z1.S
-  fcvt Z0.D, P1/M, Z2.S
+  \insn Z0.D, P1/M, Z2.S
 
   /* OK, 64-bit operation ignoring 32-bits.  */
   movprfx Z0.D, P1/M, Z1.D
-  fcvt Z0.D, P1/M, Z2.S
+  \insn Z0.D, P1/M, Z2.S
+  .endm test_cvt
 
+  .macro test_shift, insn
   /* OK, 8-bit operation.  */
   movprfx Z0.B, P1/M, Z1.B
-  lsl Z0.B, P1/M, Z0.B, Z2.D
+  \insn Z0.B, P1/M, Z0.B, Z2.D
 
   /* Not Ok, destination register sizes don't match.  */
   movprfx Z0.D, P1/M, Z1.D
-  lsl Z0.B, P1/M, Z0.B, Z2.D
+  \insn Z0.B, P1/M, Z0.B, Z2.D
+  .endm test_shift
+
+  test_cvt fcvt
+  test_cvt fcvtzs
+  test_cvt fcvtzu
+  test_cvt scvtf
+  test_cvt ucvtf
+
+  test_shift lsl
+  test_shift lsr
+  test_shift asr
+
   ret
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8b0da31..064e48e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
+	to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 	registers in an instruction prefixed by MOVPRFX.
 
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 9ee92ea..6216750 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3961,20 +3961,20 @@ struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
   _SVE_INSNC ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
   _SVE_INSNC ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-  _SVE_INSNC ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
   _SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0),
@@ -4370,13 +4370,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSNC ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
   _SVE_INSNC ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0),
-  _SVE_INSNC ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
   _SVE_INSNC ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0),
@@ -4522,13 +4522,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
   _SVE_INSNC ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0),
-  _SVE_INSNC ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX, 0),
-  _SVE_INSNC ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
+  _SVE_INSNC ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
+  _SVE_INSNC ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
   _SVE_INSNC ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
   _SVE_INSNC ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0),