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| author | Robert Suchanek <robert.suchanek@imgtec.com> | 2015-08-10 08:57:31 +0100 |
|---|---|---|
| committer | Robert Suchanek <robert.suchanek@imgtec.com> | 2015-08-10 09:14:07 +0100 |
| commit | 75fb7498c25ba89262867abe5340a8d38f1e19cd (patch) | |
| tree | 59e19e7a21510ce87aa372bce08e1f53e4e2b8d7 | |
| parent | 2bc6d61bf3e4935921ae2612b3c6cd0604428960 (diff) | |
| download | fsf-binutils-gdb-75fb7498c25ba89262867abe5340a8d38f1e19cd.zip fsf-binutils-gdb-75fb7498c25ba89262867abe5340a8d38f1e19cd.tar.gz fsf-binutils-gdb-75fb7498c25ba89262867abe5340a8d38f1e19cd.tar.bz2 | |
Add SIGRIE instruction for MIPS R6
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add "sigrie".
gas/testsuite/
* gas/mips/r6.s: Add tests for "sigrie".
* gas/mips/r6.d: Check for "sigrie".
* gas/mips/r6-n32.d: Likewise.
* gas/mips/r6-n64.d: Likewise.
| -rw-r--r-- | gas/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r6-n32.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r6-n64.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r6.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/r6.s | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 1 |
7 files changed, 21 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 68d1761..e2e3fd4 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> + + * gas/mips/r6.s: Add tests for "sigrie". + * gas/mips/r6.d: Check for "sigrie". + * gas/mips/r6-n32.d: Likewise. + * gas/mips/r6-n64.d: Likewise. + 2015-07-30 H.J. Lu <hongjiu.lu@intel.com> PR binutils/13571 diff --git a/gas/testsuite/gas/mips/r6-n32.d b/gas/testsuite/gas/mips/r6-n32.d index acca6c4..fb55086 100644 --- a/gas/testsuite/gas/mips/r6-n32.d +++ b/gas/testsuite/gas/mips/r6-n32.d @@ -497,4 +497,6 @@ Disassembly of section .text: 0+0598 <[^>]*> 41600024 dvp 0+059c <[^>]*> 41620004 evp v0 0+05a0 <[^>]*> 41620024 dvp v0 +0+05a4 <[^>]*> 41700000 sigrie 0x0 +0+05a8 <[^>]*> 4170ffff sigrie 0xffff \.\.\. diff --git a/gas/testsuite/gas/mips/r6-n64.d b/gas/testsuite/gas/mips/r6-n64.d index 10deeae..fd4da21 100644 --- a/gas/testsuite/gas/mips/r6-n64.d +++ b/gas/testsuite/gas/mips/r6-n64.d @@ -753,4 +753,6 @@ Disassembly of section .text: 0+0598 <[^>]*> 41600024 dvp 0+059c <[^>]*> 41620004 evp v0 0+05a0 <[^>]*> 41620024 dvp v0 +0+05a4 <[^>]*> 41700000 sigrie 0x0 +0+05a8 <[^>]*> 4170ffff sigrie 0xffff \.\.\. diff --git a/gas/testsuite/gas/mips/r6.d b/gas/testsuite/gas/mips/r6.d index cca10a7..8588e92 100644 --- a/gas/testsuite/gas/mips/r6.d +++ b/gas/testsuite/gas/mips/r6.d @@ -496,4 +496,6 @@ Disassembly of section .text: 0+0598 <[^>]*> 41600024 dvp 0+059c <[^>]*> 41620004 evp v0 0+05a0 <[^>]*> 41620024 dvp v0 +0+05a4 <[^>]*> 41700000 sigrie 0x0 +0+05a8 <[^>]*> 4170ffff sigrie 0xffff \.\.\. diff --git a/gas/testsuite/gas/mips/r6.s b/gas/testsuite/gas/mips/r6.s index 0635066..9fc5fcd 100644 --- a/gas/testsuite/gas/mips/r6.s +++ b/gas/testsuite/gas/mips/r6.s @@ -266,6 +266,9 @@ new: maddf.s $f0,$f1,$f2 evp $2 dvp $2 + sigrie 0 + sigrie 0xffff + # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 .space 8 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 995deae..4638e15 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> + + * mips-opc.c (mips_builtin_opcodes): Add "sigrie". + 2015-08-07 Amit Pawar <Amit.Pawar@amd.com> * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index a0b0e26..7349ade 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1858,6 +1858,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, +{"sigrie", "u", 0x41700000, 0xffff0000, TRAP, 0, I37, 0, 0 }, {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 }, {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 }, {"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, |