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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2015-12-16 13:57:44 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2015-12-31 21:55:45 +0000 |
| commit | 5ba8bc973cca60cb06bf41a2808ba6fa4ed02879 (patch) | |
| tree | 340b04bd8cff8e567e27568ee996ff3ea1427135 | |
| parent | 8e26d677a240d3b495b7c565006d75646a15ed53 (diff) | |
| download | fsf-binutils-gdb-5ba8bc973cca60cb06bf41a2808ba6fa4ed02879.zip fsf-binutils-gdb-5ba8bc973cca60cb06bf41a2808ba6fa4ed02879.tar.gz fsf-binutils-gdb-5ba8bc973cca60cb06bf41a2808ba6fa4ed02879.tar.bz2 | |
opcodes/arc: Support dmb instruction with no operands
In this GCC commit:
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg00735.html
GCC started emitting dmb instructions with no operands. The intention
was that dmb with no operands should be an alias for 'dmb 0'.
The following patch extends the arc opcodes library to support dmb with
no operands.
opcodes/ChangeLog:
* arc-tbl.h (dmb): Add a no operand version of dmb.
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arc-tbl.h | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 63ad12b..e5f1202 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2015-12-31 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> + Andrew Burgess <andrew.burgess@embecosm.com> + + * arc-tbl.h (dmb): Add a no operand version of dmb. + 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h index 1b4715d..9aeda7f 100644 --- a/opcodes/arc-tbl.h +++ b/opcodes/arc-tbl.h @@ -4423,6 +4423,9 @@ /* dmb u3 00100011011011110001RRRuuu111111. */ { "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM3_23 }, { 0 }}, +/* dmb 00100011011011110001RRR000111111. */ +{ "dmb", 0x236F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + /* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ { "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, |