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| author | Jim Wilson <jimw@sifive.com> | 2018-09-17 11:43:08 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-09-17 11:43:08 -0700 |
| commit | 4e2b18982ade10897e62590896a1dec496269877 (patch) | |
| tree | 34021948541cad7ad7f094143c72118d74c4dddb | |
| parent | 461464f22632163209937ba5128d1f9f32554ea3 (diff) | |
| download | fsf-binutils-gdb-4e2b18982ade10897e62590896a1dec496269877.zip fsf-binutils-gdb-4e2b18982ade10897e62590896a1dec496269877.tar.gz fsf-binutils-gdb-4e2b18982ade10897e62590896a1dec496269877.tar.bz2 | |
RISC-V: bge[u] should get higher priority than ble[u].
2018-09-17 Kito Cheng <kito@andestech.com>
gas/
* testsuite/gas/riscv/bge.d: New.
* testsuite/gas/riscv/bge.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Adjust the order of ble and
bleu.
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/bge.d | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/bge.s | 5 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
5 files changed, 29 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 3e76800..0a4c566 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2018-09-17 Kito Cheng <kito@andestech.com> + + * testsuite/gas/riscv/bge.d: New. + * testsuite/gas/riscv/bge.s: Likewise. + 2018-09-17 H.J. Lu <hongjiu.lu@intel.com> PR gas/23670 diff --git a/gas/testsuite/gas/riscv/bge.d b/gas/testsuite/gas/riscv/bge.d new file mode 100644 index 0000000..b3db91c --- /dev/null +++ b/gas/testsuite/gas/riscv/bge.d @@ -0,0 +1,13 @@ +#as: +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <foo>: +[ ]+0:[ ]+00c5d063[ ]+bge[ ]+a1,a2,0 \<foo\> +[ ]+4:[ ]+feb65ee3[ ]+bge[ ]+a2,a1,0 \<foo\> +[ ]+8:[ ]+fec5fce3[ ]+bgeu[ ]+a1,a2,0 \<foo\> +[ ]+c:[ ]+feb67ae3[ ]+bgeu[ ]+a2,a1,0 \<foo\> diff --git a/gas/testsuite/gas/riscv/bge.s b/gas/testsuite/gas/riscv/bge.s new file mode 100644 index 0000000..a28d25e --- /dev/null +++ b/gas/testsuite/gas/riscv/bge.s @@ -0,0 +1,5 @@ +foo: + bge a1, a2, foo + ble a1, a2, foo + bgeu a1, a2, foo + bleu a1, a2, foo diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5d57507..19475da 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2018-09-17 Kito Cheng <kito@andestech.com> + + * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu. + 2018-09-17 H.J. Lu <hongjiu.lu@intel.com> PR gas/23670 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 945164a..e0f7118 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -250,10 +250,10 @@ const struct riscv_opcode riscv_opcodes[] = {"beq", 0, {"I", 0}, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH }, {"blez", 0, {"I", 0}, "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bgez", 0, {"I", 0}, "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, -{"ble", 0, {"I", 0}, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, -{"bleu", 0, {"I", 0}, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bge", 0, {"I", 0}, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH }, {"bgeu", 0, {"I", 0}, "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_CONDBRANCH }, +{"ble", 0, {"I", 0}, "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, +{"bleu", 0, {"I", 0}, "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bltz", 0, {"I", 0}, "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bgtz", 0, {"I", 0}, "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"blt", 0, {"I", 0}, "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_CONDBRANCH }, |