gas/

2007-09-06  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (match_template): Handle invlpga, vmload,
	vmrun and vmsave in SVME.
	(process_suffix): Likewise.

gas/testsuite/

2007-09-06  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/svme.s: Updated to allow eax in 64bit.
	* gas/i386/svme.d: Updated.
	* gas/i386/svme64.d: Likewise.

opcodes/

2007-09-06  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Correct SVME instructions to allow 32bit register
	operand in 64bit mode.
	* i386-tbl.h: Regenerated.

9 files changed, 66 insertions, 49 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 155a077..fd303ff 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2007-09-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Handle invlpga, vmload,
+	vmrun and vmsave in SVME.
+	(process_suffix): Likewise.
+
 2007-09-05  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-i386.c (i386_index_check): Don't use RegRex
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a5ac843..54841b1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2664,9 +2664,15 @@ match_template (void)
 	      || !MATCH (overlap1, i.types[1], operand_types[1])
 	      /* monitor in SSE3 is a very special case.  The first
 		 register and the second register may have different
-		 sizes.  The same applies to crc32 in SSE4.2.  */
+		 sizes.  The same applies to crc32 in SSE4.2.  It is
+		 also true for invlpga, vmload, vmrun and vmsave in
+		 SVME.  */
 	      || !((t->base_opcode == 0x0f01
-		    && t->extension_opcode == 0xc8)
+		    && (t->extension_opcode == 0xc8
+			|| t->extension_opcode == 0xd8
+			|| t->extension_opcode == 0xda
+			|| t->extension_opcode == 0xdb
+			|| t->extension_opcode == 0xdf))
 		   || t->base_opcode == 0xf20f38f1
 		   || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
 						 operand_types[0],
@@ -3000,11 +3006,17 @@ process_suffix (void)
       /* Now select between word & dword operations via the operand
 	 size prefix, except for instructions that will ignore this
 	 prefix anyway.  */
-      if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
+      if (i.tm.base_opcode == 0x0f01
+	   && (i.tm.extension_opcode == 0xc8
+	       || i.tm.extension_opcode == 0xd8
+	       || i.tm.extension_opcode == 0xda
+	       || i.tm.extension_opcode == 0xdb
+	       || i.tm.extension_opcode == 0xdf))
 	{
 	  /* monitor in SSE3 is a very special case. The default size
 	     of AX is the size of mode. The address size override
-	     prefix will change the size of AX.  */
+	     prefix will change the size of AX.  It is also true for
+	     invlpga, vmload, vmrun and vmsave in SVME.  */
 	  if (i.op->regs[0].reg_type &
 	      (flag_code == CODE_32BIT ? Reg16 : Reg32))
 	    if (!add_prefix (ADDR_PREFIX_OPCODE))
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index ab8f216..573b354 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2007-09-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/svme.s: Updated to allow eax in 64bit.
+	* gas/i386/svme.d: Updated.
+	* gas/i386/svme64.d: Likewise.
+
 2007-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/svme.s: Updated to accept eax in 32bit and rax in
diff --git a/gas/testsuite/gas/i386/svme.d b/gas/testsuite/gas/i386/svme.d
index 14dcb44..d7682a4 100644
--- a/gas/testsuite/gas/i386/svme.d
+++ b/gas/testsuite/gas/i386/svme.d
@@ -15,15 +15,15 @@ Disassembly of section .text:
 [	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
 [0-9a-f]+ <att32>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
-[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
 [0-9a-f]+ <intel32>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
-[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
 #pass
diff --git a/gas/testsuite/gas/i386/svme.s b/gas/testsuite/gas/i386/svme.s
index 9e517d4..ff1be7c 100644
--- a/gas/testsuite/gas/i386/svme.s
+++ b/gas/testsuite/gas/i386/svme.s
@@ -19,20 +19,18 @@ common:
 .ifdef __amd64__
 att64:
 	do_args	%rax, %ecx
-.else
-att32:
-	do_args	%eax, %ecx
 .endif
+att32:
 	skinit	%eax
+	do_args	%eax, %ecx
 
 .intel_syntax noprefix
 .ifdef __amd64__
 intel64:
 	do_args	rax, ecx
-.else
-intel32:
-	do_args	eax, ecx
 .endif
+intel32:
 	skinit	eax
+	do_args	eax, ecx
 
 	.p2align 4,0
diff --git a/gas/testsuite/gas/i386/svme64.d b/gas/testsuite/gas/i386/svme64.d
index 2ebcda8..640b947 100644
--- a/gas/testsuite/gas/i386/svme64.d
+++ b/gas/testsuite/gas/i386/svme64.d
@@ -21,11 +21,21 @@ Disassembly of section .text:
 [	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <att32>:
 [	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 df[	 ]+addr32 invlpga[	 ]
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 da[	 ]+addr32 vmload[	 ]
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 d8[	 ]+addr32 vmrun[	 ]
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 db[	 ]+addr32 vmsave[	 ]
 [0-9a-f]+ <intel64>:
 [	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <intel32>:
 [	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 df[	 ]+addr32 invlpga[	 ]
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 da[	 ]+addr32 vmload[	 ]
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 d8[	 ]+addr32 vmrun[	 ]
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 db[	 ]+addr32 vmsave[	 ]
 #pass
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b434076..3c9ee7b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2007-09-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-opc.tbl: Correct SVME instructions to allow 32bit register
+	operand in 64bit mode.
+	* i386-tbl.h: Regenerated.
+
 2007-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (OPC_EXT_40...OPC_EXT_45): New.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f0ed6a3..3c4bfaa 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1460,30 +1460,22 @@ rdtscp, 0, 0xf01, 0xf9, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf
 // AMD Pacifica additions.
 clgi, 0, 0xf01, 0xdd, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
 invlpga, 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
-// FIXME: Need to ensure only "invlpga %eax,%ecx" is accepted.
-invlpga, 2, 0xf01, 0xdf, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32, Reg32 }
-// FIXME: Need to ensure only "invlpga %rax,%ecx" is accepted.
-invlpga, 2, 0xf01, 0xdf, CpuSVME|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg32 }
+// FIXME: Need to ensure only "invlpga %[re]ax,%ecx" is accepted.
+invlpga, 2, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg32 }
 skinit, 0, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
 // FIXME: Need to ensure only "skinit %eax" is accepted.
 skinit, 1, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32 }
 stgi, 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
 vmload, 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
-// FIXME: Need to ensure only "vmload %eax" is accepted.
-vmload, 1, 0xf01, 0xda, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32 }
-// FIXME: Need to ensure only "vmload %rax" is accepted.
-vmload, 1, 0xf01, 0xda, CpuSVME|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64 }
+// FIXME: Need to ensure only "vmload %[re]ax" is accepted.
+vmload, 1, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64 }
 vmmcall, 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
 vmrun, 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
-// FIXME: Need to ensure only "vmrun %eax" is accepted.
-vmrun, 1, 0xf01, 0xd8, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32 }
-// FIXME: Need to ensure only "vmrun %rax" is accepted.
-vmrun, 1, 0xf01, 0xd8, CpuSVME|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64 }
+// FIXME: Need to ensure only "vmrun %[re]ax" is accepted.
+vmrun, 1, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64 }
 vmsave, 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
-// FIXME: Need to ensure only "vmsave %eax" is accepted.
-vmsave, 1, 0xf01, 0xdb, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32 }
-// FIXME: Need to ensure only "vmsave %rax" is accepted.
-vmsave, 1, 0xf01, 0xdb, CpuSVME|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64 }
+// FIXME: Need to ensure only "vmsave %[re]ax" is accepted.
+vmsave, 1, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64 }
 
 
 // SSE4a instructions
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 362ae46..f5121e1 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -4189,13 +4189,9 @@ const template i386_optab[] =
   { "invlpga", 0, 0xf01, 0xdf, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
     { 0 } },
-  { "invlpga", 2, 0xf01, 0xdf, CpuSVME|CpuNo64,
-    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
-    { Reg32,
-      Reg32 } },
-  { "invlpga", 2, 0xf01, 0xdf, CpuSVME|Cpu64,
+  { "invlpga", 2, 0xf01, 0xdf, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
-    { Reg64,
+    { Reg32|Reg64,
       Reg32 } },
   { "skinit", 0, 0xf01, 0xde, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
@@ -4209,33 +4205,24 @@ const template i386_optab[] =
   { "vmload", 0, 0xf01, 0xda, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
     { 0 } },
-  { "vmload", 1, 0xf01, 0xda, CpuSVME|CpuNo64,
-    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
-    { Reg32 } },
-  { "vmload", 1, 0xf01, 0xda, CpuSVME|Cpu64,
+  { "vmload", 1, 0xf01, 0xda, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
-    { Reg64 } },
+    { Reg32|Reg64 } },
   { "vmmcall", 0, 0xf01, 0xd9, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
     { 0 } },
   { "vmrun", 0, 0xf01, 0xd8, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
     { 0 } },
-  { "vmrun", 1, 0xf01, 0xd8, CpuSVME|CpuNo64,
-    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
-    { Reg32 } },
-  { "vmrun", 1, 0xf01, 0xd8, CpuSVME|Cpu64,
+  { "vmrun", 1, 0xf01, 0xd8, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
-    { Reg64 } },
+    { Reg32|Reg64 } },
   { "vmsave", 0, 0xf01, 0xdb, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
     { 0 } },
-  { "vmsave", 1, 0xf01, 0xdb, CpuSVME|CpuNo64,
-    No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
-    { Reg32 } },
-  { "vmsave", 1, 0xf01, 0xdb, CpuSVME|Cpu64,
+  { "vmsave", 1, 0xf01, 0xdb, CpuSVME,
     No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
-    { Reg64 } },
+    { Reg32|Reg64 } },
   { "movntsd", 2, 0xf20f2b, None, CpuSSE4a,
     Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
     { RegXMM,