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2023-03-01Bump riscv-isa-sim from `e2a364a` to `d1ae27b`dependabot[bot]1-0/+0
2023-03-01Bump riscv-gnu-toolchain from `65056bd` to `f0b0094`dependabot[bot]1-0/+0
2023-02-01Bump riscv-tests from `55bbcc8` to `a6ab6ae`2023.03.272023.02.02dependabot[bot]1-0/+0
2023-02-01Bump riscv-isa-sim from `3349dc5` to `e2a364a`dependabot[bot]1-0/+0
2023-02-01Bump riscv-openocd from `b337b0c` to `9c3a4b4`dependabot[bot]1-0/+0
2023-02-01Bump fsf-binutils-gdb from `b236b82` to `6cb7f6d`dependabot[bot]1-0/+0
2023-02-01Merge pull request #37 from chipsalliance/dependabot/submodules/riscv-gnu-too...Jiuyang Liu1-0/+0
2023-02-01Bump riscv-gnu-toolchain from `51c7370` to `65056bd`dependabot[bot]1-0/+0
2022-12-22Merge pull request #31 from chipsalliance/dependabot/submodules/riscv-isa-sim...2023.01.302023.01.292023.01.222023.01.202023.01.032022.12.262022.12.23Jiuyang Liu1-0/+0
2022-12-22Merge pull request #30 from chipsalliance/dependabot/submodules/riscv-opcodes...Jiuyang Liu1-0/+0
2022-12-22Merge pull request #29 from chipsalliance/dependabot/submodules/fsf-binutils-...Jiuyang Liu1-0/+0
2022-12-22Merge pull request #28 from chipsalliance/dependabot/submodules/riscv-tests-5...Jiuyang Liu1-0/+0
2022-12-22Merge pull request #27 from chipsalliance/dependabot/submodules/riscv-gnu-too...Jiuyang Liu1-0/+0
2022-12-22Bump riscv-isa-sim from `adfaef0` to `3349dc5`dependabot[bot]1-0/+0
2022-12-22Bump riscv-opcodes from `8df0274` to `902fa8a`dependabot[bot]1-0/+0
2022-12-22Bump fsf-binutils-gdb from `e53a8e8` to `b236b82`dependabot[bot]1-0/+0
2022-12-22Bump riscv-tests from `45f4da6` to `55bbcc8`dependabot[bot]1-0/+0
2022-12-22Bump riscv-gnu-toolchain from `29d02b7` to `51c7370`dependabot[bot]1-0/+0
2022-12-22Merge pull request #26 from ZenithalHourlyRate/dependabot-gitsubmoduleJiuyang Liu1-0/+6
2022-12-22Automate submodule update via dependabotZenithal1-0/+6
2022-12-22Merge pull request #24 from ZenithalHourlyRate/binary-releaseJiuyang Liu1-0/+172
2022-12-22Add nightly binary releaseZenithal1-0/+172
2022-12-19Merge pull request #23 from chipsalliance/bumpJerry Zhao9-2/+4
2022-12-09Bump everythingJerry Zhao9-2/+4
2020-03-29Merge pull request #9 from chipsalliance/tmpAndrew Waterman4-1/+1
2020-03-29bump spike, tests, openocdAndrew Waterman4-1/+1
2020-03-05bump spike, testsAndrew Waterman2-0/+0
2020-02-20s/freechipsproject/chipsalliance/Andrew Waterman1-2/+2
2020-02-13Merge pull request #5 from chipsalliance/fesvr-no-dm-when-dmactive-0Megan Wachs6-2/+5
2020-02-13FSF GDB: bump to 8.3.1 versionfesvr-no-dm-when-dmactive-0Megan Wachs1-0/+0
2020-02-13Build.sh: build GDB after binutilsMegan Wachs1-1/+1
2020-02-12Bump openocd to the latest to match our other bumpsMegan Wachs1-0/+0
2020-02-12Change build.sh to build FSF GDB not riscv-gdbMegan Wachs1-2/+2
2020-02-12Add FSF GDB as a submoduleMegan Wachs2-0/+3
2020-02-12bump riscv-tests now that we've bumped spike and fesvrMegan Wachs1-0/+0
2020-02-11fesvr: bump for merged to master versionMegan Wachs1-0/+0
2020-02-11fesvr: bump to pick up more DMACTIVE fixesMegan Wachs1-0/+0
2020-02-11riscv-isa-sim: bump to master commit with dmactive FESVR fixMegan Wachs1-0/+0
2020-02-10Bump riscv-isa-sim to the latest to pick up DMACTIVE fixMegan Wachs1-0/+0
2020-01-24README.md update, newer distros will require that (libfl-dev/flex-devel) (#4)alex-cscotg1-2/+2
2020-01-04Update riscv-openocd to get dmstatus fix (#3)Ernie Edgar1-0/+0
2019-04-03Update README.mdAndrew Waterman1-22/+9
2019-04-03Merge fesvr into spike repo; bump spike to v1.0.0Andrew Waterman8-13/+4
2019-03-27Merge pull request #283 from riscv/dtm-fixAndrew Waterman1-0/+0
2019-03-26Bump tools for fesvr DTM fixAndrew Waterman1-0/+0
2019-02-28bump spike for fix (#276)Srivatsa Yogendra1-0/+0
2019-02-12bump fesvr for elf2hex improvement (#274)Andrew Waterman1-0/+0
2019-01-28bumping spike for pmp fix (#272)Srivatsa Yogendra1-0/+0
2018-12-21bumping isa-sim for pmp fix (#267)Srivatsa Yogendra1-0/+0
2018-10-18bump spike for pmp registers (#260)Srivatsa Yogendra1-0/+0
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