Directory: /pkgsrc/stable/pkgsrc/cad/MyHDL-iverilog/
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Parent directory/
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CVS/
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2024-Apr-01 21:58
DESCR
498 B
2019-Jul-04 21:07
Makefile
488 B
2016-Oct-09 11:15
PLIST
80 B
2016-Oct-09 11:15