RISC-V Platform-Level Interrupt Controller (PLIC)
-------------------------------------------------

RISC-V cores typically include a PLIC, which route interrupts from multiple
devices to multiple hart contexts.  The PLIC is connected to the interrupt
controller embedded in a RISC-V core via the interrupt-related CSRs.

A hart context is a priviledge mode in a hardware execution thread.  For
example, in an 4 core system with 2-way SMT, you have 8 harts and probably
at least two priviledge modes per hart; machine mode and supervisor mode.

Each interrupt can be enabled on per-context basis. Any context can claim
a pending enabled interrupt and then release it once it has been handled.

Each interrupt has a configurable priority. Higher priority interrupts are
serviced firs. Each context can specify a priority threshold. Interrupts
with priority below this threshold will not cause the PLIC to raise its
interrupt line leading to the context.

Required properties:
- compatible : "riscv,plic0"
- #address-cells : should be <0>
- #interrupt-cells : should be <1>
- interrupt-controller : Identifies the node as an interrupt controller
- reg : Should contain 1 register range (address and length)
- riscv,ndev : Specifies the number of interrupts attached to the PLIC
- interrupts-extended : Specifies which contexts are connected to the PLIC

Example:

	plic: interrupt-controller@c000000 {
		#address-cells = <0>;
		#interrupt-cells = <1>;
		compatible = "riscv,plic0";
		interrupt-controller;
		interrupts-extended = <
			&cpu0-intc 11
			&cpu1-intc 11 &cpu1-intc 9
			&cpu2-intc 11 &cpu2-intc 9
			&cpu3-intc 11 &cpu3-intc 9
			&cpu4-intc 11 &cpu4-intc 9>;
		reg = <0xc000000 0x4000000>;
		riscv,ndev = <10>;
	};
