RISC-V Hart-Level Interrupt Controller (HLIC)
---------------------------------------------

RISC-V cores include Control Status Registers (CSRs) which are local to each
hart and can be read or written by software. Some of these CSRs are used to
control local interrupts connected to the core.

Typical examples of local interrupts on a RISC-V core include: software IPI
interrupts, timer interrupts, and a link to the PLIC interrupt controller.

Required properties:
- compatible : "riscv,cpu-intc"
- #interrupt-cells : should be <1>
- interrupt-controller : Identifies the node as an interrupt controller

Furthermore, this interrupt-controller MUST be embedded inside the cpu
definition of the hart whose CSRs control these local interrupts.

Example:

	cpu1: cpu@1 {
		clock-frequency = <1600000000>;
		compatible = "riscv";
		d-cache-block-size = <64>;
		d-cache-sets = <64>;
		d-cache-size = <16384>;
		d-tlb-sets = <1>;
		d-tlb-size = <32>;
		device_type = "cpu";
		i-cache-block-size = <64>;
		i-cache-sets = <64>;
		i-cache-size = <16384>;
		i-tlb-sets = <1>;
		i-tlb-size = <32>;
		mmu-type = "riscv,sv39";
		next-level-cache = <&L2>;
		reg = <1>;
		riscv,isa = "rv64imac";
		status = "okay";
		tlb-split;
		cpu1-intc: interrupt-controller {
			#interrupt-cells = <1>;
			compatible = "riscv,cpu-intc";
			interrupt-controller;
		};
	};
