// Index auto-generated on 2023-12-21 11:57:12.270603 from ../xml/hwbp_registers.xml
The Trigger Module registers, except \RcsrMscontext, \RcsrScontext, and \RcsrHcontext, are only accessible in machine
and Debug Mode to prevent untrusted user code from causing entry into Debug
Mode without the OS's permission.

In this section XLEN means MXLEN when in M-mode, and DXLEN when in Debug
Mode. On systems where those values of XLEN can differ, this is handled
as follows.
Fields retain their values regardless of XLEN, which only affects where
in the register these fields appear (e.g. \FcsrTdataOneType). Some fields
are wider when XLEN is 64 than when it is 32 (e.g.
\FcsrTextraThirtytwoSvalue). The high bits in such fields retain their
value but are not readable when XLEN is 32.
A modification of a register when XLEN is 32 clears any inaccessible bits
in that register.
[[csr_trigger]]
[cols="1,6",options="header"]
|===
|Address |Name
|0x5a8 | Supervisor Context (`scontext`)
|0x6a8 | Hypervisor Context (`hcontext`)
|0x7a0 | Trigger Select (`tselect`)
|0x7a1 | Trigger Data 1 (`tdata1`)
|0x7a1 | Match Control (`mcontrol`)
|0x7a1 | Match Control Type 6 (`mcontrol6`)
|0x7a1 | Instruction Count (`icount`)
|0x7a1 | Interrupt Trigger (`itrigger`)
|0x7a1 | Exception Trigger (`etrigger`)
|0x7a1 | External Trigger (`tmexttrigger`)
|0x7a2 | Trigger Data 2 (`tdata2`)
|0x7a3 | Trigger Data 3 (`tdata3`)
|0x7a3 | Trigger Extra (RV32) (`textra32`)
|0x7a3 | Trigger Extra (RV64) (`textra64`)
|0x7a4 | Trigger Info (`tinfo`)
|0x7a5 | Trigger Control (`tcontrol`)
|0x7a8 | Machine Context (`mcontext`)
|0x7aa | Machine Supervisor Context (`mscontext`)
|===
// Registers auto-generated on 2023-12-21 11:57:12.293079 from ../xml/hwbp_registers.xml
==== Trigger Select (((tselect)), at 0x7a0)

[[csr_tselect]]
This register determines which trigger is accessible through the other
Trigger Module registers. It is optional if no triggers are implemented.  The
set of accessible triggers must start at 0, and be contiguous.

This register is \warl.
Writes of values greater than or equal to the number of supported
triggers may result in a different value in this register than what was
written or may point to a trigger where \FcsrTdataOneType=0.
To verify that what they wrote is a valid index, debuggers can
read back the value and check that \RcsrTselect holds what they wrote
and read \RcsrTdataOne to see that \FcsrTdataOneType is non-zero.

Since triggers can be used both by Debug Mode and M-mode, the external
debugger must restore this register if it modifies it.

This CSR is read/write.

==== Trigger Data 1 (((tdata1)), at 0x7a1)

[[csr_tdata1]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is optional if no triggers are implemented.

Writing 0 to this register must result in a trigger that is disabled.
If this trigger supports multiple types, then the hardware should
disable it by changing \FcsrTdataOneType to 15.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[tdata1type,tdata1type]] `type`
|

0 (none): There is no trigger at this \RcsrTselect.


1 (legacy): The trigger is a legacy SiFive address match trigger. These +
should not be implemented and aren't further documented here.


2 (mcontrol): The trigger is an address/data match trigger. The remaining bits +
in this register act as described in \RcsrMcontrol.


3 (icount): The trigger is an instruction count trigger. The remaining bits +
in this register act as described in \RcsrIcount.


4 (itrigger): The trigger is an interrupt trigger. The remaining bits +
in this register act as described in \RcsrItrigger.


5 (etrigger): The trigger is an exception trigger. The remaining bits +
in this register act as described in \RcsrEtrigger.


6 (mcontrol6): The trigger is an address/data match trigger. The remaining bits +
in this register act as described in \RcsrMcontrolSix. This is similar +
to a type 2 trigger, but provides additional functionality and +
should be used instead of type 2 in newer implementations.


7 (tmexttrigger): The trigger is a trigger source external to the TM.  The +
remaining bits in this register act as described in \RcsrTmexttrigger.


12--14 (custom): These trigger types are available for non-standard use.


15 (disabled): This trigger is disabled. In this state, \RcsrTdataTwo and +
\RcsrTdataThree can be written with any value that is supported for +
any of the types this trigger implements. +
The remaining bits in this register, except for \FcsrTdataOneDmode, +
are ignored.

Other values are reserved for future use.
|WARL
|Preset
|[[tdata1dmode,tdata1dmode]] `dmode`
|If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.

0 (both): Both Debug and M-mode can write the {\tt tdata} registers at the +
selected \RcsrTselect.


1 (dmode): Only Debug Mode can write the {\tt tdata} registers at the +
selected \RcsrTselect.  Writes from other modes are ignored.

This bit is only writable from Debug Mode. +
In ordinary use, external debuggers will always set this bit when +
configuring a trigger. +
When clearing this bit, debuggers should also set the action field +
(whose location depends on \FcsrTdataOneType) to something other +
than 1.
|WARL
|0
|[[tdata1data,tdata1data]] `data`
|If \FcsrTdataOneType is 0, then this field is hard-wired to 0.

Trigger-specific data.
|WARL
|Preset
|===

==== Trigger Data 2 (((tdata2)), at 0x7a2)

[[csr_tdata2]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

Trigger-specific data. It is optional if no implemented triggers use
it.

If the trigger is disabled, then this register can be written with any
value supported by any of the trigger types supported by this trigger.

If XLEN is less than DXLEN, writes to this register are sign-extended.

This CSR is read/write.

==== Trigger Data 3 (((tdata3)), at 0x7a3)

[[csr_tdata3]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

Trigger-specific data. It is optional if no implemented triggers use
it.

If the trigger is disabled, then this register can be written with any
value supported by any of the trigger types supported by this trigger.

If XLEN is less than DXLEN, writes to this register are sign-extended.

This CSR is read/write.

==== Trigger Info (((tinfo)), at 0x7a4)

[[csr_tinfo]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is optional if no triggers are implemented, or if
\FcsrTdataOneType is not writable and \FcsrTinfoVersion would be 0. In
this case the debugger can read the only supported type from
\RcsrTdataOne.

Writing this read/write CSR has no effect.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[tinfoversion,tinfoversion]] `version`
|Contains the version of the Sdtrig extension implemented.

0 (0): Supports triggers as described in this spec at commit 5a5c078, +
made on February 2, 2023.

\begin{steps}{In these older versions:} +
\item \RcsrMcontrolSix has a timing bit identical to +
\FcsrMcontrolTiming +
\item \FcsrMcontrolSixHitZero behaves just as \FcsrMcontrolHit. +
\item \FcsrMcontrolSixHitOne is read-only 0. +
\item Encodings for \FcsrMcontrolSixSize for access sizes larger +
than 64 bits are different. +
\end{steps}


1 (1): Supports triggers as described in the ratified version 1.0 of +
this document.
|R
|Preset
|[[tinfoinfo,tinfoinfo]] `info`
|One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N +
corresponds to type N. If the bit is set, then that type is +
supported by the currently selected trigger.

If the currently selected trigger doesn't exist, this field +
contains 1.
|R
|Preset
|===

==== Trigger Control (((tcontrol)), at 0x7a5)

[[csr_tcontrol]]
This optional register is only accessible in M-mode and Debug Mode and
provides various control bits related to triggers.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[tcontrolmpte,tcontrolmpte]] `mpte`
|M-mode previous trigger enable field.

\FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem +
regarding triggers with action=0 firing in M-mode trap handlers. See +
Section~\ref{sec:nativetrigger} for more details.

When any trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of +
\FcsrTcontrolMte.
|WARL
|0
|[[tcontrolmte,tcontrolmte]] `mte`
|M-mode trigger enable field.

0 (disabled): Triggers with action=0 do not match/fire while the hart is in M-mode.


1 (enabled): Triggers do match/fire while the hart is in M-mode.

When any trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt +
mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
|WARL
|0
|===

==== Hypervisor Context (((hcontext)), at 0x6a8)

[[csr_hcontext]]
This optional register may be implemented only if the H extension is
implemented. If it is implemented, \RcsrMcontext must also be implemented.

This register is only accessible in HS-Mode, M-mode and Debug Mode. If
Smstateen is implemented, then accessibility of in HS-Mode is
controlled by \Rmstateenzero[57].

This register is an alias of the \RcsrMcontext register, providing
access to the \FcsrMcontextHcontext field from HS-Mode.


==== Supervisor Context (((scontext)), at 0x5a8)

[[csr_scontext]]
This optional register is only accessible in S/HS-mode, VS-mode,
M-mode and Debug Mode.

Accessibility of this CSR is controlled by \Rmstateenzero[57] and
\Rhstateenzero[57] in the Smstateen extension.  Enabling \RcsrScontext
can be a security risk in a virtualized system with a hypervisor that
does not swap \RcsrScontext.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[scontextdata,scontextdata]] `data`
|Supervisor mode software can write a context number to this +
register, which can be used to set triggers that only fire in that +
specific context.

An implementation may tie any number of high bits in this field to +
0. It's recommended to implement no more than 16 bits on RV32, and +
34 on RV64.
|WARL
|0
|===

==== Machine Context (((mcontext)), at 0x7a8)

[[csr_mcontext]]
This register must be implemented if \RcsrHcontext is implemented, and
is optional otherwise.  It is only accessible in M-mode and Debug mode.

\begin{commentary}
\FcsrMcontextHcontext is primarily useful to set triggers on
hypervisor systems that only fire when a given VM is executing. It
is also useful in systems where M-Mode implements something like a
hypervisor directly.
\end{commentary}

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[mcontexthcontext,mcontexthcontext]] `hcontext`
|M-Mode or HS-Mode (using \RcsrHcontext) software can write a context +
number to this register, which can be used to set triggers that only +
fire in that specific context.

An implementation may tie any number of upper bits in this field to +
0. If the H extension is not implemented, it's recommended to implement +
no more than 6 bits on RV32 and 13 on RV64 (as visible through the +
\RcsrMcontext register).  If the H extension is implemented, +
it's recommended to implement no more than 7 bits on RV32 +
and 14 on RV64.
|WARL
|0
|===

==== Machine Supervisor Context (((mscontext)), at 0x7aa)

[[csr_mscontext]]
This optional register is an alias for \RcsrScontext.  It is only
accessible in S/HS-mode, M-mode and Debug Mode.  It is included
for backward compatibility with version 0.13.

\begin{commentary}
The encoding of this CSR does not conform to the CSR Address Mapping
Convention in the Privileged Spec.  It is expected that new
implementations will not support this encoding and that new
debuggers will not use this CSR if \RcsrScontext is available.
\end{commentary}


==== Match Control (((mcontrol)), at 0x7a1)

[[csr_mcontrol]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 2.
This trigger type is deprecated.  It is included for backward compatibility
with version 0.13.

\begin{commentary}
This trigger type only supports a subset of features of the newer
\RcsrMcontrolSix.  It is expected that new implementations will not
support this trigger type and that new debuggers will not use it if
\RcsrMcontrolSix is available.
\end{commentary}

Address and data trigger implementation are heavily dependent on how
the processor core is implemented. To accommodate various
implementations, execute, load, and store address/data triggers may fire at
whatever point in time is most convenient for the implementation.
The debugger may request specific timings as described in \FcsrMcontrolTiming.
Table~\ref{tab:hwbp_timing} suggests timings for the best user experience.

A chain of triggers that don't all have the same \FcsrMcontrolTiming
value will never fire. That means to implement the suggestions in
Table~\ref{tab:hwbp_timing}, both timings should be supported on load
address triggers.

The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the {\tt tval} CSR
with either zero or the faulting virtual address.  The faulting
virtual address for an mcontrol trigger with \FcsrMcontrolAction=0 is the
address being accessed and which caused that trigger to fire.
If multiple mcontrol triggers are chained then the faulting
virtual address is the address which caused any of the chained
triggers to fire.

If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this
trigger, it only matches when the conditions set there are satisfied.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[mcontrolmaskmax,mcontrolmaskmax]] `maskmax`
|Specifies the largest naturally aligned powers-of-two (NAPOT) range +
supported by the hardware when \FcsrMcontrolMatch is 1. The value is the +
logarithm base 2 of the number of bytes in that range. +
A value of 0 indicates \FcsrMcontrolMatch 1 is not supported. +
A value of 63 corresponds to the maximum NAPOT range, which is +
$2^{63}$ bytes in size.
|R
|Preset
|[[mcontrolsizehi,mcontrolsizehi]] `sizehi`
|This field only exists when XLEN is at least 64. +
It contains the 2 high bits of the access size. The low bits +
come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this +
is used.
|WARL
|0
|[[mcontrolhit,mcontrolhit]] `hit`
|If this bit is implemented then it must become set when this +
trigger fires and may become set when this trigger matches. +
The trigger's user can set or clear it at any +
time. It is used to determine which +
trigger(s) matched.  If the bit is not implemented, it is always 0 +
and writing it has no effect.
|WARL
|0
|[[mcontrolselect,mcontrolselect]] `select`
|This bit determines the contents of the XLEN-bit compare values.

0 (address): There is at least one compare value and it contains the lowest +
virtual address of the access. +
It is recommended that there are additional compare values for +
the other accessed virtual addresses. +
(E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 +
and the other addresses are 0x4001, 0x4002, and 0x4003.)


1 (data): There is exactly one compare value and it contains the data +
value loaded or stored, or the instruction executed. +
Any bits beyond the size of the data access will contain 0.
|WARL
|0
|[[mcontroltiming,mcontroltiming]] `timing`
|

0 (before): The action for this trigger will be taken just before the +
instruction that triggered it is retired, but after all preceding +
instructions are retired. \Rxepc or \RcsrDpc (depending +
on \FcsrMcontrolAction) must be set to the virtual address of the +
instruction that matched.

If this is combined with \FcsrMcontrolLoad and +
\FcsrMcontrolSelect=1 then a memory access will be +
performed (including any side effects of performing such an access) even +
though the load will not update its destination register. Debuggers +
should consider this when setting such breakpoints on, for example, +
memory-mapped I/O addresses.

If an instruction matches this trigger and the instruction performs +
multiple memory accesses, it is \unspecified which memory accesses +
have completed before the trigger fires.


1 (after): The action for this trigger will be taken after the instruction +
that triggered it is retired. It should be taken before the next +
instruction is retired, but it is better to implement triggers imprecisely +
than to not implement them at all.  \Rxepc or +
\RcsrDpc (depending on \FcsrMcontrolAction) must be set to +
the virtual address of the next instruction that must be executed to +
preserve the program flow.

Most hardware will only implement one timing or the other, possibly +
dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute, +
\FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit +
primarily exists for the hardware to communicate to the debugger +
what will happen. Hardware may implement the bit fully writable, in +
which case the debugger has a little more control.

Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load +
happening again when the debugger lets the hart run. For data load +
triggers, debuggers must first attempt to set the breakpoint with +
\FcsrMcontrolTiming of 1.

If a trigger with \FcsrMcontrolTiming of 0 matches, it is +
implementation-dependent whether that prevents a trigger with +
\FcsrMcontrolTiming of 1 matching as well.
|WARL
|0
|[[mcontrolsizelo,mcontrolsizelo]] `sizelo`
|This field contains the 2 low bits of the access size. The high bits come +
from \FcsrMcontrolSizehi. The combined value is interpreted as follows:

0 (any): The trigger will attempt to match against an access of any size. +
The behavior is only well-defined if $|select|=0$, or if the access +
size is XLEN.


1 (8bit): The trigger will only match against 8-bit memory accesses.


2 (16bit): The trigger will only match against 16-bit memory accesses or +
execution of 16-bit instructions.


3 (32bit): The trigger will only match against 32-bit memory accesses or +
execution of 32-bit instructions.


4 (48bit): The trigger will only match against execution of 48-bit instructions.


5 (64bit): The trigger will only match against 64-bit memory accesses or +
execution of 64-bit instructions.


6 (80bit): The trigger will only match against execution of 80-bit instructions.


7 (96bit): The trigger will only match against execution of 96-bit instructions.


8 (112bit): The trigger will only match against execution of 112-bit instructions.


9 (128bit): The trigger will only match against 128-bit memory accesses or +
execution of 128-bit instructions.

An implementation must support the value of 0, but all other values +
are optional. When an implementation supports address triggers +
(\FcsrMcontrolSelect=0), it is recommended that those triggers +
support every access size that the hart supports, as well as for +
every instruction size that the hart supports.

Implementations such as RV32D or RV64V are able to perform loads +
and stores that are wider than XLEN. Custom extensions may also +
support instructions that are wider than XLEN. Because +
\RcsrTdataTwo is of size XLEN, there is a known limitation that +
data value triggers (\FcsrMcontrolSelect=1) can only be supported +
for access sizes up to XLEN bits.  When an implementation supports +
data value triggers (\FcsrMcontrolSelect=1), it is recommended +
that those triggers support every access size up to XLEN that the +
hart supports, as well as for every instruction length up to XLEN +
that the hart supports.
|WARL
|0
|[[mcontrolaction,mcontrolaction]] `action`
|The action to take when the trigger fires. The values are explained +
in Table~\ref{tab:action}.
|WARL
|0
|[[mcontrolchain,mcontrolchain]] `chain`
|

0 (disabled): When this trigger matches, the configured action is taken.


1 (enabled): While this trigger does not match, it prevents the trigger with +
the next index from matching.

A trigger chain starts on the first trigger with $|chain|=1$ after +
a trigger with $|chain|=0$, or simply on the first trigger if that +
has $|chain|=1$. It ends on the first trigger after that which has +
$|chain|=0$. This final trigger is part of the chain. The action +
on all but the final trigger is ignored.  The action on that final +
trigger will be taken if and only if all the triggers in the chain +
match at the same time.

Debuggers should not terminate a chain with a trigger with a +
different type. It is undefined when exactly such a chain fires.

Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in +
writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has +
\FcsrTdataOneDmode of 1. +
In addition hardware should ignore writes to \RcsrMcontrol that set +
\FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and +
\FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking +
\FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol.

Implementations that wish to limit the maximum length of a trigger +
chain (eg. to meet timing requirements) may do so by zeroing +
\FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long.
|WARL
|0
|[[mcontrolmatch,mcontrolmatch]] `match`
|

0 (equal): Matches when any compare value equals \RcsrTdataTwo.


1 (napot): Matches when the top $M$ bits of any compare value match the top +
$M$ bits of \RcsrTdataTwo. +
$M$ is $|XLEN|-1$ minus the index of the least-significant +
bit containing 0 in \RcsrTdataTwo. Debuggers should only write values +
to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$ +
and $M\gt0$ , otherwise it's undefined on what conditions the +
trigger will match.


2 (ge): Matches when any compare value is greater than (unsigned) or +
equal to \RcsrTdataTwo.


3 (lt): Matches when any compare value is less than (unsigned) +
\RcsrTdataTwo.


4 (mask low): Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value +
equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after +
$\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with +
$|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.


5 (mask high): Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare +
value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after +
$|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with +
$|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.


8 (not equal): Matches when \FcsrMcontrolMatch$=0$ would not match.


9 (not napot): Matches when \FcsrMcontrolMatch$=1$ would not match.


12 (not mask low): Matches when \FcsrMcontrolMatch$=4$ would not match.


13 (not mask high): Matches when \FcsrMcontrolMatch$=5$ would not match.

Other values are reserved for future use.

All comparisons only look at the lower XLEN (in the current mode) +
bits of the compare values and of \RcsrTdataTwo. +
When \FcsrMcontrolSelect=1 and access size is N, this is further +
reduced, and comparisons only look at the lower N bits of the +
compare values and of \RcsrTdataTwo.
|WARL
|0
|[[mcontrolm,mcontrolm]] `m`
|When set, enable this trigger in M-mode.
|WARL
|0
|[[mcontrols,mcontrols]] `s`
|When set, enable this trigger in S/HS-mode. +
This bit is hard-wired to 0 if the hart does not support +
S-mode.
|WARL
|0
|[[mcontrolu,mcontrolu]] `u`
|When set, enable this trigger in U-mode. +
This bit is hard-wired to 0 if the hart does not support +
U-mode.
|WARL
|0
|[[mcontrolexecute,mcontrolexecute]] `execute`
|When set, the trigger fires on the virtual address or opcode of an +
instruction that is executed.
|WARL
|0
|[[mcontrolstore,mcontrolstore]] `store`
|When set, the trigger fires on the virtual address or data of any +
store.
|WARL
|0
|[[mcontrolload,mcontrolload]] `load`
|When set, the trigger fires on the virtual address or data of any +
load.
|WARL
|0
|===

==== Match Control Type 6 (((mcontrol6)), at 0x7a1)

[[csr_mcontrol6]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 6.

Implementing this trigger as described here requires that
\FcsrTinfoVersion is 1 or higher, which in turn means \RcsrTinfo must
be implemented.

This replaces mcontrol in newer implementations and serves to provide additional
functionality.

Address and data trigger implementation are heavily dependent on how
the processor core is implemented. To accommodate various
implementations, execute, load, and store address/data triggers may fire at
whatever point in time is most convenient for the implementation.

Table~\ref{tab:hwbp_timing} suggests timings for the best user experience.
The underlying principle is that firing just before the instruction
gives a user more insight, so is preferable. However, depending on the
instruction and conditions, it might not be possible to evaluate the
trigger until the instruction has partially executed. In that case it is
better to let the instruction retire before the trigger fires, to avoid
extra memory accesses which might affect the state of the system.

\begin{table}[H]
\centering
\caption{Suggested Trigger Timings}
\label{tab:hwbp_timing}
\begin{tabular}{|r|l|}
\hline
Match Type                  & Suggested Trigger Timing \\
\hline
Execute Address             & Before \\
Execute Instruction         & Before \\
Execute Address+Instruction & Before \\
Load Address                & Before \\
Load Data                   & After \\
Load Address+Data           & After \\
Store Address               & Before \\
Store Data                  & Before \\
Store Address+Data          & Before \\
\hline
\end{tabular}
\end{table}

A chain of triggers must only fire if every trigger in the chain was
matched by the same instruction.

The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the {\tt tval} CSR
with either zero or the faulting virtual address.  The faulting
virtual address for an mcontrol6 trigger with \FcsrMcontrolSixAction=0 is the
address being accessed and which caused that trigger to fire.
If multiple mcontrol6 triggers are chained then the faulting
virtual address is the address which caused any of the chained
triggers to fire.

\begin{steps}{In implementations that support \FcsrMcontrolSixMatch mode 1 (NAPOT), not all
NAPOT ranges may be supported.  All NAPOT ranges between $2^{1}$ and $2^{maskmax6}$
are supported where maskmax6 $\geq$ 1.  The value of maskmax6 can be determined
by the debugger via the following sequence:}
\item Set \FcsrMcontrolSixMatch=1.
\item Read \FcsrMcontrolSixMatch. If it is not 1 then NAPOT matching is not supported.
\item Write all ones to \RcsrTdataTwo.
\item Read \RcsrTdataTwo. The value of maskmax6 is the index of the most significant 0 bit plus 1.
\end{steps}

If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this
trigger, it only matches when the conditions set there are satisfied.

\begin{commentary}
\FcsrMcontrolSixUncertain and \FcsrMcontrolSixUncertainen exist to
accommodate systems where not every memory access is fully observed by
the Trigger Module. Possible examples include data values in far AMOs,
and the address/data/size of accesses by instructions that perform
multiple memory accesses, such as vector, push, and pop instructions.

While the uncertain mechanism exists to deal with these situations, it
can lead to an unusable number of false positives. Users will get a much
better debug experience if the TM does have perfect visibility into the
details of every memory access.
\end{commentary}

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[mcontrol6uncertain,mcontrol6uncertain]] `uncertain`
|If implemented, the TM updates this field every time the trigger +
fires.

0 (certain): The trigger that fired satisfied the configured conditions, or +
this bit is not implemented.


1 (uncertain): The trigger that fired might not have perfectly satisfied the +
configured conditions. Due to the implementation the hardware +
cannot be certain.
|WARL
|0
|[[mcontrol6vs,mcontrol6vs]] `vs`
|When set, enable this trigger in VS-mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[mcontrol6vu,mcontrol6vu]] `vu`
|When set, enable this trigger in VU-mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[mcontrol6hit0,mcontrol6hit0]] `hit0`
|If they are implemented, \FcsrMcontrolSixHitOne (MSB) and +
\FcsrMcontrolSixHitZero (LSB) combine into a single 2-bit field. +
The TM updates this field when the trigger fires. After the debugger +
has seen the update, it will normally write 0 to this field to so it +
can see future changes.

If either of the bits is not implemented, the unimplemented bits +
will be read-only 0.

0 (false): The trigger did not fire.


1 (before): The trigger fired before the instruction that matched it was +
retired, but after all preceding instructions are retired. This +
explicitly allows for instructions to be partially executed, as +
described in Section \ref{sec:multistate}.

\Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set +
to the virtual address of the instruction that matched.


2 (after): The trigger fired after the instruction that triggered and at least +
one additional instruction were retired. +
\Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set +
to the virtual address of the next instruction that must be executed +
to preserve the program flow.


3 (immediately after): The trigger fired just after the instruction that triggered it was +
retired, but before any subsequent instructions were executed. +
\Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set +
to the virtual address of the next instruction that must be executed +
to preserve the program flow.

If the instruction performed multiple memory accesses, all of them +
have been completed.
|WARL
|0
|[[mcontrol6select,mcontrol6select]] `select`
|This bit determines the contents of the XLEN-bit compare values.

0 (address): There is at least one compare value and it contains the lowest +
virtual address of the access. +
In addition, it is recommended that there are additional compare +
values for the other accessed virtual addresses match. +
(E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 +
and the other addresses are 0x4001, 0x4002, and 0x4003.)


1 (data): There is exactly one compare value and it contains the data +
value loaded or stored, or the instruction executed. +
Any bits beyond the size of the data access will contain 0.
|WARL
|0
|[[mcontrol6size,mcontrol6size]] `size`
|

0 (any): The trigger will attempt to match against an access of any size. +
The behavior is only well-defined if $|select|=0$, or if the access +
size is XLEN.


1 (8bit): The trigger will only match against 8-bit memory accesses.


2 (16bit): The trigger will only match against 16-bit memory accesses or +
execution of 16-bit instructions.


3 (32bit): The trigger will only match against 32-bit memory accesses or +
execution of 32-bit instructions.


4 (48bit): The trigger will only match against execution of 48-bit instructions.


5 (64bit): The trigger will only match against 64-bit memory accesses or +
execution of 64-bit instructions.


6 (128bit): The trigger will only match against 128-bit memory accesses or +
execution of 128-bit instructions.

An implementation must support the value of 0, but all other values +
are optional. When an implementation supports address triggers +
(\FcsrMcontrolSixSelect=0), it is recommended that those triggers +
support every access size that the hart supports, as well as for +
every instruction size that the hart supports.

Implementations such as RV32D or RV64V are able to perform loads +
and stores that are wider than XLEN. Custom extensions may also +
support instructions that are wider than XLEN. Because +
\RcsrTdataTwo is of size XLEN, there is a known limitation that +
data value triggers (\FcsrMcontrolSixSelect=1) can only be supported +
for access sizes up to XLEN bits.  When an implementation supports +
data value triggers (\FcsrMcontrolSixSelect=1), it is recommended +
that those triggers support every access size up to XLEN that the +
hart supports, as well as for every instruction length up to XLEN +
that the hart supports.
|WARL
|0
|[[mcontrol6action,mcontrol6action]] `action`
|The action to take when the trigger fires. The values are explained +
in Table~\ref{tab:action}.
|WARL
|0
|[[mcontrol6chain,mcontrol6chain]] `chain`
|

0 (disabled): When this trigger matches, the configured action is taken.


1 (enabled): While this trigger does not match, it prevents the trigger with +
the next index from matching.

A trigger chain starts on the first trigger with $|chain|=1$ after +
a trigger with $|chain|=0$, or simply on the first trigger if that +
has $|chain|=1$. It ends on the first trigger after that which has +
$|chain|=0$. This final trigger is part of the chain. The action +
on all but the final trigger is ignored.  The action on that final +
trigger will be taken if and only if all the triggers in the chain +
match at the same time.

Debuggers should not terminate a chain with a trigger with a +
different type. It is undefined when exactly such a chain fires.

Because \FcsrMcontrolSixChain affects the next trigger, hardware must zero it in +
writes to \RcsrMcontrolSix that set \FcsrTdataOneDmode to 0 if the next trigger has +
\FcsrTdataOneDmode of 1. +
In addition hardware should ignore writes to \RcsrMcontrolSix that set +
\FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and +
\FcsrMcontrolSixChain of 1. Debuggers must avoid the latter case by checking +
\FcsrMcontrolSixChain on the previous trigger if they're writing \RcsrMcontrolSix.

Implementations that wish to limit the maximum length of a trigger +
chain (eg. to meet timing requirements) may do so by zeroing +
\FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long.
|WARL
|0
|[[mcontrol6match,mcontrol6match]] `match`
|

0 (equal): Matches when any compare value equals \RcsrTdataTwo.


1 (napot): Matches when the top $M$ bits of any compare value match the top +
$M$ bits of \RcsrTdataTwo. +
$M$ is $|XLEN|-1$ minus the index of the least-significant bit +
containing 0 in \RcsrTdataTwo. +
\RcsrTdataTwo is WARL and if bits $|maskmax6|-1$:0 are written with all +
ones then bit $|maskmax6|-1$ will be set to 0 while the values of bits $|maskmax6|-2$:0 +
are \unspecified. +
Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$. +
See above for how to determine maskmax6.


2 (ge): Matches when any compare value is greater than (unsigned) or +
equal to \RcsrTdataTwo.


3 (lt): Matches when any compare value is less than (unsigned) +
\RcsrTdataTwo.


4 (mask low): Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value +
equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after +
$\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with +
$|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.


5 (mask high): Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare +
value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after +
$|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with +
$|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.


8 (not equal): Matches when \FcsrMcontrolSixMatch$=0$ would not match.


9 (not napot): Matches when \FcsrMcontrolSixMatch$=1$ would not match.


12 (not mask low): Matches when \FcsrMcontrolSixMatch$=4$ would not match.


13 (not mask high): Matches when \FcsrMcontrolSixMatch$=5$ would not match.

Other values are reserved for future use.

All comparisons only look at the lower XLEN (in the current mode) +
bits of the compare values and of \RcsrTdataTwo. +
When \FcsrMcontrolSelect=1 and access size is N, this is further +
reduced, and comparisons only look at the lower N bits of the +
compare values and of \RcsrTdataTwo.
|WARL
|0
|[[mcontrol6m,mcontrol6m]] `m`
|When set, enable this trigger in M-mode.
|WARL
|0
|[[mcontrol6uncertainen,mcontrol6uncertainen]] `uncertainen`
|

0 (disabled): This trigger will only match if the hardware can perfectly +
evaluate it.


1 (enabled): This trigger will match if it's possible that it would match if +
the Trigger Module had perfect information about the operations +
being performed.
|WARL
|0
|[[mcontrol6s,mcontrol6s]] `s`
|When set, enable this trigger in S/HS-mode. +
This bit is hard-wired to 0 if the hart does not support +
S-mode.
|WARL
|0
|[[mcontrol6u,mcontrol6u]] `u`
|When set, enable this trigger in U-mode. +
This bit is hard-wired to 0 if the hart does not support +
U-mode.
|WARL
|0
|[[mcontrol6execute,mcontrol6execute]] `execute`
|When set, the trigger fires on the virtual address or opcode of an +
instruction that is executed.
|WARL
|0
|[[mcontrol6store,mcontrol6store]] `store`
|When set, the trigger fires on the virtual address or data of any +
store.
|WARL
|0
|[[mcontrol6load,mcontrol6load]] `load`
|When set, the trigger fires on the virtual address or data of any +
load.
|WARL
|0
|===

==== Instruction Count (((icount)), at 0x7a1)

[[csr_icount]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 3.

\begin{steps}{This trigger matches when:}
\item
An instruction retires after having been fetched in a privilege
mode where the trigger is enabled.
This explicitly includes {\em x}\/RET instructions.
\item A trap is taken from a privilege mode where the trigger is enabled.
This explicitly includes traps taken due to interrupts.
\end{steps}

If more than one of the above events occur during a single instruction
execution, the trigger still only matches once for that instruction.

\begin{commentary}
For use in single step, icount must match for traps where the
instruction will not be reexecuted after the handler, such as
illegal instructions that are emulated by privileged software and
the instruction being emulated never retires. Ideally, icount would
not match for traps where the instruction will later be retried by
the handler, such as page faults where privileged software modifies
the page tables and returns to the faulting instruction which
ultimately retires. Trying to distinguish the two cases leads to
complex rules, so instead the rule is simply that all traps match.
See also Section~\ref{stepIcount}.
\end{commentary}

When \FcsrIcountCount is greater than 1 and the trigger matches, then
\FcsrIcountCount is decremented by 1.

When \FcsrIcountCount is 1 and the trigger matches, then \FcsrIcountPending
becomes set. In addition \FcsrIcountCount will become 0 unless it is
hard-wired to 1.

The only exception to the above is when the instruction the trigger matched on is a
write to the icount trigger. In that case \FcsrIcountPending might or might
not become set if \FcsrIcountCount was 1. Afterwards \FcsrIcountCount
contains the newly written value.

When \FcsrIcountCount is 0 it stays at 0 until explicitly written.

When \FcsrIcountPending is set, the trigger fires just
before any further instructions are executed in a mode where the
trigger is enabled. As the trigger fires, \FcsrIcountPending is
cleared. In addition, if \FcsrIcountCount is hard-wired to 1 then \FcsrIcountM,
\FcsrIcountS, \FcsrIcountU, \FcsrIcountVs, and \FcsrIcountVu are all
cleared.

If the trigger fires with \FcsrIcountAction=0 then zero is written to the
{\tt tval} CSR on the breakpoint trap.

\begin{commentary}
The intent of \FcsrIcountPending is to cleanly handle the case where
\FcsrIcountAction is 0, \FcsrIcountM is 0, \FcsrIcountU is 1,
\FcsrIcountCount is 1, and the U-mode instruction being executed
causes a trap into M-mode. In that case we want the entire M-mode
handler to be executed, and the debug trap to be taken before the
next U-mode instruction.
\end{commentary}

\begin{commentary}
This trigger type is intended to be used as a single step for software
monitor programs or native debug.  Systems that support multiple
privilege modes that want to debug software running in lower privilege
modes don't need to support \FcsrIcountCount greater than 1.
\end{commentary}

If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this
trigger, it only matches when the conditions set there are satisfied.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[icountvs,icountvs]] `vs`
|When set, enable this trigger in VS-mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[icountvu,icountvu]] `vu`
|When set, enable this trigger in VU-mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[icounthit,icounthit]] `hit`
|If this bit is implemented, the hardware sets it when this +
trigger fires. The trigger's user can set or clear it at any +
time. It is used to determine which +
trigger(s) fires.  If the bit is not implemented, it is always 0 +
and writing it has no effect.
|WARL
|0
|[[icountcount,icountcount]] `count`
|The trigger will generally fire after \FcsrIcountCount instructions +
in enabled modes have been executed. See above for the precise behavior.
|WARL
|1
|[[icountm,icountm]] `m`
|When set, enable this trigger in M-mode.
|WARL
|0
|[[icountpending,icountpending]] `pending`
|This bit becomes set when \FcsrIcountCount is decremented from 1 +
to 0. It is cleared when the trigger fires, which will happen just +
before executing the next instruction in one of the enabled modes.
|R/W
|0
|[[icounts,icounts]] `s`
|When set, enable this trigger in S/HS-mode. +
This bit is hard-wired to 0 if the hart does not support +
S-mode.
|WARL
|0
|[[icountu,icountu]] `u`
|When set, enable this trigger in U-mode. +
This bit is hard-wired to 0 if the hart does not support +
U-mode.
|WARL
|0
|[[icountaction,icountaction]] `action`
|The action to take when the trigger fires. The values are explained +
in Table~\ref{tab:action}.
|WARL
|0
|===

==== Interrupt Trigger (((itrigger)), at 0x7a1)

[[csr_itrigger]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 4.

This trigger can fire when an interrupt trap is taken.

It can be enabled for individual interrupt numbers by setting the bit
corresponding to the interrupt number in \RcsrTdataTwo. The interrupt
number is interpreted in the mode that the trap handler executes in.
(E.g. virtualized interrupt numbers are not the same in every mode.)
In addition the trigger can be enabled for non-maskable interrupts using
\FcsrItriggerNmi.

\begin{commentary}
If XLEN is 32, then it is not possible to set a trigger for interrupts
with Exception Code larger than 31. A future version of the RISC-V
Privileged Spec will likely define interrupt Exception Codes 32 through
47. Some of those numbers are already being used by the RISC-V Advanced
Interrupt Architecture.
\end{commentary}

Hardware may only support a subset of interrupts for this trigger.  A
debugger must read back \RcsrTdataTwo after writing it to confirm the
requested functionality is actually supported.

When the trigger matches, it fires after the trap occurs, just before
the first instruction of the trap handler is executed.  If
\FcsrItriggerAction=0, the standard CSRs are updated for taking the
breakpoint trap, and zero is written to the relevant {\tt tval} CSR.  If
the breakpoint trap does not go to a higher privilege mode, this will
lose CSR information for the original trap.  See
Section~\ref{sec:nativetrigger} for more information about this case.

If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this
trigger, it only matches when the conditions set there are satisfied.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[itriggerhit,itriggerhit]] `hit`
|If this bit is implemented, the hardware sets it when this +
trigger matches. The trigger's user can set or clear it at any +
time. It is used to determine which +
trigger(s) matched.  If the bit is not implemented, it is always 0 +
and writing it has no effect.
|WARL
|0
|[[itriggervs,itriggervs]] `vs`
|When set, enable this trigger for interrupts that are taken from VS +
mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[itriggervu,itriggervu]] `vu`
|When set, enable this trigger for interrupts that are taken from VU +
mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[itriggernmi,itriggernmi]] `nmi`
|When set, non-maskable interrupts cause this +
trigger to fire if the trigger is enabled for the current mode.
|WARL
|0
|[[itriggerm,itriggerm]] `m`
|When set, enable this trigger for interrupts that are taken from M +
mode.
|WARL
|0
|[[itriggers,itriggers]] `s`
|When set, enable this trigger for interrupts that are taken from S/HS +
mode. +
This bit is hard-wired to 0 if the hart does not support +
S-mode.
|WARL
|0
|[[itriggeru,itriggeru]] `u`
|When set, enable this trigger for interrupts that are taken from U +
mode. +
This bit is hard-wired to 0 if the hart does not support +
U-mode.
|WARL
|0
|[[itriggeraction,itriggeraction]] `action`
|The action to take when the trigger fires. The values are explained +
in Table~\ref{tab:action}.
|WARL
|0
|===

==== Exception Trigger (((etrigger)), at 0x7a1)

[[csr_etrigger]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 5.

This trigger may fire on up to XLEN of the Exception Codes defined in
\Rmcause (described in the Privileged Spec, with Interrupt=0). Those
causes are configured by writing the corresponding bit in \RcsrTdataTwo.
(E.g.\  to trap on an illegal instruction, the debugger sets bit 2 in
\RcsrTdataTwo.)

\begin{commentary}
If XLEN is 32, then it is not possible to set a trigger on Exception
Codes higher than 31. A future version of the RISC-V Privileged Spec
will likely define Exception Codes 32 through 47.

\end{commentary}

Hardware may support only a subset of exceptions. A debugger must read
back \RcsrTdataTwo after writing it to confirm the requested functionality
is actually supported.

When the trigger matches, it fires after the trap occurs, just before
the first instruction of the trap handler is executed.  If
\FcsrEtriggerAction=0, the standard CSRs are updated for taking the
breakpoint trap, and zero is written to the relevant {\tt tval} CSR.  If
the breakpoint trap does not go to a higher privilege mode, this will
lose CSR information for the original trap.  See
Section~\ref{sec:nativetrigger} for more information about this case.

If \RcsrTextraThirtytwo or \RcsrTextraSixtyfour are implemented for this
trigger, it only matches when the conditions set there are satisfied.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[etriggerhit,etriggerhit]] `hit`
|If this bit is implemented, the hardware sets it when this +
trigger matches. The trigger's user can set or clear it at any +
time. It is used to determine which +
trigger(s) matched.  If the bit is not implemented, it is always 0 +
and writing it has no effect.
|WARL
|0
|[[etriggervs,etriggervs]] `vs`
|When set, enable this trigger for exceptions that are taken from VS +
mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[etriggervu,etriggervu]] `vu`
|When set, enable this trigger for exceptions that are taken from VU +
mode. +
This bit is hard-wired to 0 if the hart does not support +
virtualization mode.
|WARL
|0
|[[etriggerm,etriggerm]] `m`
|When set, enable this trigger for exceptions that are taken from M +
mode.
|WARL
|0
|[[etriggers,etriggers]] `s`
|When set, enable this trigger for exceptions that are taken from S/HS +
mode. +
This bit is hard-wired to 0 if the hart does not support +
S-mode.
|WARL
|0
|[[etriggeru,etriggeru]] `u`
|When set, enable this trigger for exceptions that are taken from U +
mode. +
This bit is hard-wired to 0 if the hart does not support +
U-mode.
|WARL
|0
|[[etriggeraction,etriggeraction]] `action`
|The action to take when the trigger fires. The values are explained +
in Table~\ref{tab:action}.
|WARL
|0
|===

==== External Trigger (((tmexttrigger)), at 0x7a1)

[[csr_tmexttrigger]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataOne when \FcsrTdataOneType is 7.

This trigger fires when any selected TM external trigger input
signals.  Up to 16 TM external
trigger inputs coming from other blocks outside the TM,
(e.g. signaling an hpmcounter overflow) can be selected.  Hardware
may support none or just a few TM external trigger inputs
(starting with TM external trigger input 0 and continuing
sequentially).  Unsupported inputs are hardwired to be inactive.

If the trigger fires with \FcsrTmexttriggerAction=0 then zero is written to the
{\tt tval} CSR on the breakpoint trap.  This trigger fires
asynchronously but it is subject to delegation by medeleg[3] like
the other triggers.

The TM external trigger input can signal when the trigger is prevented
from firing due to one of the mechanisms in section ~\ref{sec:nativetrigger}.
An implementation may either ignore the signal altogether when it cannot
fire (dropping the trigger event) or it may hold the action as pending
and fire the trigger once it is legal to do so.

\begin{commentary}
\FcsrTmexttriggerIntctl is intended to be used by the {\tt clicinttrig}
mechanism from the Core-Local Interrupt Controller (CLIC) RISC-V
Privileged Architecture Extensions.
\end{commentary}

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[tmexttriggerhit,tmexttriggerhit]] `hit`
|If this bit is implemented, the hardware sets it when this +
trigger matches. The trigger's user can set or clear it at any +
time. It is used to determine which +
trigger(s) matched.  If the bit is not implemented, it is always 0 +
and writing it has no effect.
|WARL
|0
|[[tmexttriggerintctl,tmexttriggerintctl]] `intctl`
|This optional bit, when set, causes this trigger to fire whenever an attached +
interrupt controller signals a trigger.
|WARL
|0
|[[tmexttriggerselect,tmexttriggerselect]] `select`
|Selects any combination of up to 16 TM external trigger inputs +
that cause this trigger to fire.
|WARL
|0
|[[tmexttriggeraction,tmexttriggeraction]] `action`
|The action to take when the trigger fires. The values are explained +
in Table~\ref{tab:action}.
|WARL
|0
|===

==== Trigger Extra (RV32) (((textra32)), at 0x7a3)

[[csr_textra32]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataThree when \FcsrTdataOneType is 2, 3, 4,
5, or 6 and XLEN=32.

All functionality in this register is optional. The $|value|$ bits may
tie any number of upper bits to 0. The $|select|$ bits may only support
0 (ignore).

Byte-granular comparison of \RcsrScontext to \FcsrTextraThirtytwoSvalue
allows \RcsrScontext to be defined to include more than one element of comparison.
For example, software instrumentation can program the \RcsrScontext value to be
the concatenation of different ID contexts such as process ID and thread ID.
The user can then program byte compares based on \FcsrTextraThirtytwoSbytemask
to include one or more of the contexts in the compare.

Byte masking only applies to \RcsrScontext comparison; i.e when \FcsrTextraThirtytwoSselect is 1.

\begin{commentary}
Note that sselect and mhselect filtering apply in all modes, including M-mode
and S-mode.  If desired, debuggers can use a trigger's mode filtering bits to
restrict the matching to modes where it considers ASID/VMID/scontext/hcontext
to be active.
\end{commentary}

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[textra32mhvalue,textra32mhvalue]] `mhvalue`
|Data used together with \FcsrTextraThirtytwoMhselect.
|WARL
|0
|[[textra32mhselect,textra32mhselect]] `mhselect`
|

0 (ignore): Ignore \FcsrTextraThirtytwoMhvalue.


4 (mcontext): This trigger will only match or fire if the low bits of +
\RcsrMcontext/\RcsrHcontext equal \FcsrTextraThirtytwoMhvalue.

1, 5 (mcontext\_select): This trigger will only match or fire if the +
low bits of +
\RcsrMcontext/\RcsrHcontext equal \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.

2, 6 (vmid\_select): This trigger will only match or fire if VMID in +
hgatp equals the lower VMIDMAX +
(defined in the Privileged Spec) bits of \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.

3, 7 (reserved): Reserved.

If the H extension is not supported, the only legal values are 0 and 4.
|WARL
|0
|[[textra32sbytemask,textra32sbytemask]] `sbytemask`
|When the least significant bit of this field is 1, it causes bits 7:0 +
in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1. +
When the next most significant bit of this field is 1, it causes bits 15:8 +
to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1.
|WARL
|0
|[[textra32svalue,textra32svalue]] `svalue`
|Data used together with \FcsrTextraThirtytwoSselect.

This field should be tied to 0 when S-mode is not supported.
|WARL
|0
|[[textra32sselect,textra32sselect]] `sselect`
|

0 (ignore): Ignore \FcsrTextraThirtytwoSvalue.


1 (scontext): This trigger will only match or fire if the low bits of +
\RcsrScontext equal \FcsrTextraThirtytwoSvalue.


2 (asid): This trigger will only match or fire if: +
\begin{itemize}[noitemsep,nolistsep] +
\item the mode is VS-mode or VU-mode and ASID in \Rvsatp +
equals the lower ASIDMAX (defined in the Privileged Spec) bits +
of \FcsrTextraThirtytwoSvalue. +
\item in all other modes, ASID in \Rsatp equals the lower +
ASIDMAX (defined in the Privileged Spec) bits of +
\FcsrTextraThirtytwoSvalue. +
\end{itemize}

This field should be tied to 0 when S-mode is not supported.
|WARL
|0
|===

==== Trigger Extra (RV64) (((textra64)), at 0x7a3)

[[csr_textra64]]
This register provides access to the trigger selected by \RcsrTselect.
The reset values listed here apply to every underlying trigger.

This register is accessible as \RcsrTdataThree when \FcsrTdataOneType is 2, 3, 4,
5, or 6 and XLEN=64. The fields are defined
above, in \RcsrTextraThirtytwo.

Byte-granular comparison of \RcsrScontext to \FcsrTextraSixtyfourSvalue in
\RcsrTextraSixtyfour allows \RcsrScontext to be defined to include
more than one element of comparison.  For example, software instrumentation
can program the \RcsrScontext value to be the concatenation of different ID contexts
such as process ID and thread ID.  The user can then program byte compares based on
\FcsrTextraSixtyfourSbytemask to include one or more of the contexts in the compare.

Byte masking only applies to \RcsrScontext comparison; i.e when \FcsrTextraSixtyfourSselect is 1.

This CSR is read/write.
[float="center",align="center",cols="<2,<3,^1,^1",options="header"]
|===
|Field |Description |Access |Reset
|[[textra64sbytemask,textra64sbytemask]] `sbytemask`
|When the least significant bit of this field is 1, it causes bits 7:0 +
in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1. +
Likewise, the second bit controls the comparison of bits 15:8, +
third bit controls the comparison of bits 23:16, +
fourth bit controls the comparison of bits 31:24, and +
fifth bit controls the comparison of bits 33:32.
|WARL
|0
|===

