[[crypto-vector-instruction-constraints]]
=== Instruction Constraints
The following is a quick reference for the various constraints of specific Vector Crypto instructions.

vl and vstart constraints::
Since `vl` and `vstart` refer to elements, Vector Crypto instructions that use elements groups
(See <<crypto-vector-element-groups>>) require that these values are an integer multiple of the
Element Group Size (`EGS`).

- Instructions that violate the `vl` or `vstart` requirements are _reserved_.

[%autowidth]
[%header,cols="4,4"]
|===
| Instructions 
| EGS

| vaes*   | 4
| vsha2*  | 4
| vgh*    | 4
| vsm3*   | 8 
| vsm4*   | 4

|===

LMUL constraints::
For element-group instructions, `LMUL`*`VLEN` must always be at least as large as `EGW`, otherwise an
_illegal instruction exception_ is raised, even if `vl`=0.

[%autowidth]
[%header,cols="4,2,2"]
|===
| Instructions
| SEW 
| EGW

| vaes*   | 32 | 128
| vsha2*  | 32 | 128
| vsha2*  | 64 | 256
| vgh*    | 32 | 128
| vsm3*   | 32 | 256 
| vsm4*   | 32 | 128

|===


SEW constraints::
Some Vector Crypto instructions are only defined for a specific `SEW`. In such a case
all other `SEW` values are _reserved_.

[%autowidth]
[%header,cols="4,4"]
|===
| Instructions 
| Required SEW

| vaes*          | 32
| Zvknha: vsha2* | 32
| Zvknhb: vsha2* | 32 or 64
| vclmul[h]      | 64
| vgh*           | 32
| vsm3*          | 32
| vsm4*          | 32


|===

Source/Destination overlap constraints::
Some Vector Crypto instructions have overlap constraints. Encodings that violate these constraints are _reserved_.

In the case of the `.vs` instructions defined in this specification, `vs2` holds a 128-bit scalar element group.
For implementations with `VLEN` ≥ 128, `vs2` refers to a single register. Thus, the `vd` register group must not
overlap the `vs2` register.
However, in implementations where `VLEN` < 128, `vs2` refers to a register group comprised of the number
of registers needed to hold the 128-bit scalar element group. In this case, the `vd` register group must not
overlap this `vs2` register group.

[%autowidth]
[%header,cols="4,4,4"]
|===
| Instruction
| Register 
| Cannot Overlap

| vaes*.vs      | vs2      | vd
| vsm4r.vs      | vs2      | vd 
| vsha2c[hl]    | vs1, vs2 | vd
| vsha2ms       | vs1, vs2 | vd
| sm3me         | vs2      | vd
| vsm3c         | vs2      | vd


|===

