
This document describes the proposed {\em scalar} cryptography
extension for RISC-V.
All instructions proposed here use the general-purpose {\tt X}
registers, and obey the 2-read-1-write register access constraint.
These instructions are designed to be lightweight, and be suitable
for $32$ and $64$ bit base architectures, from embedded, IoT class
cores to large, application class cores which do not implement a
vector unit.
This document also describes the architectural interface to an
Entropy Source, which can be used to generate cryptographic secrets.
A companion document ``Volume II: Vector Instructions'', describes
instruction proposals which build on the RISC-V Vector Extension.
