[#insns-sha512sig1l, reftext="SHA2-512 Sigma1 low (RV32)"]
=== sha512sig1l

Synopsis::
Implements the _low half_ of the Sigma1 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).

Mnemonic::
sha512sig1l rd, rs1, rs2

Encoding::
[wavedrom, , svg]
....
{reg:[
{bits: 7, name: 0x33},
{bits: 5, name: 'rd'},
{bits: 3, name: 0x0},
{bits: 5, name: 'rs1'},
{bits: 5, name: 'rs2'},
{bits: 5, name: 0xb},
{bits: 2, name: 0x1},
]}
....

Description:: 
This instruction is implemented on RV32 only.
Used to compute the Sigma1 transform of the SHA2-512 hash function
in conjunction with the <<insns-sha512sig1h,`sha512sig1h`>> instruction.
The transform is a 64-bit to 64-bit function, so the input and output
are each represented by two 32-bit registers.
This instruction must _always_ be implemented such that its execution
latency does not depend on the data being operated on.

[TIP]
.Note to software developers
====
The entire Sigma1 transform for SHA2-512 may be computed on RV32
using the following instruction sequence:

 sha512sig1l    t0, a0, a1 
 sha512sig1h    t1, a1, a0

====

Operation::
[source,sail]
--
function clause execute (SHA512SIG1L(rs2, rs1, rd)) = {
  X(rd) = EXTS((X(rs1) <<  3) ^ (X(rs1) >>  6) ^ (X(rs1) >> 19) ^
               (X(rs2) >> 29) ^ (X(rs2) << 26) ^ (X(rs2) << 13) );
  RETIRE_SUCCESS
}
--

Included in::
[%header,cols="4,2,2"]
|===
|Extension
|Minimum version
|Lifecycle state

| <<zknh>> (RV32)
| v1.0.0
| Frozen
| <<zkn>> (RV32)
| v1.0.0
| Frozen
| <<zk>> (RV32)
| v1.0.0
| Frozen
|===


