[[crypto_scalar_introduction]]
== Introduction

This document describes the _scalar_ cryptography
extension for RISC-V.
All instructions described herein use the general-purpose `X`
registers, and obey the 2-read-1-write register access constraint.
These instructions are designed to be lightweight and suitable
for `32` and `64` bit base architectures; from embedded IoT class
cores to large, application class cores which do not implement a
vector unit.

This document also describes the architectural interface to an
Entropy Source, which can be used to generate cryptographic secrets.
This is found in <<crypto_scalar_es>>.

It also contains a mechanism allowing core implementers to provide
_"Constant Time Execution"_ guarantees in <<crypto_scalar_zkt>>.

A companion document _Volume II: Vector Instructions_, describes
instruction proposals which build on the RISC-V Vector Extension.
The Vector Cryptography extension is currently a work in progress
waiting for the base Vector extension to stabilise.
We expect to pick up this work in earnest in Q4-2021 or Q1-2022.

