Existing Extensions
===================

This page lists known existing RISCV ISA extensions for code-size reduction

* [Huawei Custom Extension](https://github.com/riscv/riscv-code-size-reduction/blob/master/existing_extensions/Huawei%20Custom%20Extension/README.md)
* [PULP platform extension pdf](https://pulp-platform.org/docs/ri5cy_user_manual.pdf) or [html](https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/instruction_set_extensions.html#)
   * post-incrementing load/stores, compare-immediate branches and hardware loops
* [Andes CoDense](http://www.andestech.com/en/products-solutions/product-documentation/)
   * Download "ISA -> AndeStar V5 Instruction Extension Specification 1.2	2019-07-22" from the link above
* [Alibaba/T-head](https://github.com/isrc-cas/c910-llvm), and [Chinese presentation](http://crva.ict.ac.cn/crvs2020/index/slides/2-8.pdf)
   * these seem to be aimed at performance and code size, but information is limited
* WCH [QingKeV2](http://www.wch-ic.com/downloads/QingKeV2_Processor_Manual_PDF.html) and [GinqKeV4](http://www.wch-ic.com/downloads/QingKeV4_Processor_Manual_PDF.html)

There are probably several others, please let me know

