<<<
[#insns-c_zext_h,reftext="Zero extend halfword, 16-bit encoding"]
=== c.zext.h

Synopsis::
Zero extend halfword, 16-bit encoding

Mnemonic::
c.zext.h _rd'/rs1'_

Encoding (RV32, RV64)::
[wavedrom, , svg]
....
{reg:[
    { bits:  2, name: 0x1, attr: ['C1'] },
    { bits:  3, name: 0x2, attr: ['C.ZEXT.H'] },
    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
    { bits:  3, name: 0x7 },
    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
],config:{bits:16}}
....

Description::
This instruction takes a single source/destination operand. 
It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of
the bits more significant than 15.

[NOTE]
  _rd'/rs1'_ is from the standard 8-register set x8-x15.

Prerequisites::
Zbb is also required.

32-bit equivalent::
<<insns-zext_h>> from Zbb

[NOTE]

  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.

Operation::
[source,sail]
--
X(rsdc) = EXTZ(X(rsdc)[15..0]);
--

include::Zcb_footer.adoc[]

