<<<
[#insns-cm_decbnez,reftext="Decrement and branch, 16-bit encoding"]
=== cm.decbnez: This is in the _development_ phase, for benchmarking and prototyping only

Synopsis::
Decrement and branch, 16-bit encoding

Mnemonic::
cm.decbnez _t0_, _offset_

Encoding (RV32, RV64)::
[wavedrom, , svg]
....
{reg:[
    { bits:  2, name: 0x2,              attr: ['C2'] },
    { bits:  6, name: 'imm[6|7|3:1|5]', attr: [] },
    { bits:  1, name: 0x1,              attr: [] },
    { bits:  3, name: 'imm[4|9:8]',     attr: [] },
    { bits:  1, name: 0x1,              attr: [] },
    { bits:  3, name: 0x5,              attr: ['FUNCT3'] },
],config:{bits:16}}
....

[NOTE]

  In the current proposal only t0 can be decremented, future versions may allow more registers

Description::
This instruction decrements _t0_, and increments the PC by the sign extended immediate if _t0_ is zero *after* the decrement.

Prerequisites::
C or Zca

32-bit equivalent::
None

Operation::
[source,sail]
--

//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.

t0 = 5;
X(t0) = X(t0)-1;
if (X(t0)==0) PC+=sext(imm); else PC+=2;

--

include::Zcmd_footer.adoc[]

