<<<
[#csrs-jvt,reftext="JVT CSR, table jump base vector and control register"]
=== JVT CSR

Synopsis::
Table jump base vector and control register

Address::
0x0017

Permissions::
URW

Format (RV32)::
[wavedrom, , svg]
....
{reg:[
    { bits:  6, name: 'mode',  attr: ['6'] },
    { bits: 26, name: 'base[XLEN-1:6] (WARL)}',  attr: ['XLEN-6'] },
],config:{bits:32}}
....

Format (RV64)::
[wavedrom, , svg]
....
{reg:[
    { bits:  6, name: 'mode',  attr: ['6'] },
    { bits: 58, name: 'base[XLEN-1:6] (WARL)',  attr: ['XLEN-6'] },
],config:{bits:64}}
....

Description::

The _JVT_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).

If <<Zcmt>> is implemented then _JVT_ must also be implemented, but can contain a read-only value. If _JVT_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary.

_JVT.base_ is a virtual address, whenever virtual memory is enabled.

The memory pointed to by _JVT.base_ is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission. 

[#JVT-config-table]
._JVT.mode_ definition
[width="60%",options=header]
|=============================================================================================
| JVT.mode | Comment
| 000000 | Jump table mode
| others | *reserved for future standard use*
|=============================================================================================

_JVT.mode_ is a *WARL* field, so can only be programmed to modes which are implemented. Therefore the discovery mechanism is to 
attempt to program different modes and read back the values to see which are available. Jump table mode _must_ be implemented.

NOTE: in future the RISC-V Unified Discovery method will report the available modes.

Architectural State::

_JVT_ adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. 

State Enable::

If the Smstateen extension is implemented, then bit 2 in _mstateen0_, _sstateen0_, and _hstateen0_ is implemented.  If bit 2 of a controlling _stateen0_ CSR is zero, then access to the _JVT_ CSR and execution of a _cm.jalt_ or _cm.jt_ instruction by a lower privilege level results in an Illegal Instruction trap (or, if appropriate, a Virtual Instruction trap).

include::Zcmt_footer.adoc[]

