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[#csrs-jvt,reftext="JVT CSR, table jump base vector and control register"]
=== JVT CSR

Synopsis::
Table jump base vector and control register

Address::
0x0017

Permissions::
URW

Format (RV32, RV64)::
[wavedrom, , svg]
....
{reg:[
    { bits:  6, name: 'mode',  attr: ['6'] },
    { bits: 26, name: 'base',  attr: ['XLEN-6'] },
],config:{bits:32}}
....

Description::

_JVT.base_ is a virtual address, whenever virtual memory is enabled.

_JVT.base[5:0]_ is implicitly zero, and is naturally aligned for all legal values of _XLEN_.

_JVT.base_ is a WARL field as the set of values the register may hold can vary by implementation. 

The memory pointed to by _JVT.base_ is treated as instruction memory for the purpose of executing table jump instructions. 

[#JVT-config-table]
._JVT.mode_ definition
[width="60%",options=header]
|=============================================================================================
| JVT.mode | Comment
| 000000 | Jump table mode
| others | *reserved for future standard use*
|=============================================================================================

_JVT.mode_ is a WARL field, so can only be programmed to modes which are implemented. Therefore the discovery mechanism is to 
attempt to program different modes and read back the values to see which are available. Jump table mode _must_ be implemented.

Architectural State::

JVT adds architectural state to the context, therefore must be saved/restored on context switches. 

State Enable::

Bit 2 of the Smstateen CSRs are allocated to control access to JVT. If the Smstateen extension is implemented, the following text is valid:

Bit 2 applies only for the case that Zcmt is implemented, which includes the JVT CSR and the _cm.jt_ and _cm.jalt_ instructions.
If bit 2 of a controlling stateen0 CSR is zero, then the _cm.jt_ and _cm.jalt_ instructions both cause an illegal instruction trap 
(or virtual instruction trap, if relevant). 

include::Zcmt_footer.adoc[]

