<<<
[#insns-c_zext_w,reftext="Zero extend word, 16-bit encoding"]
=== c.zext.w

Synopsis::
Zero extend word, 16-bit encoding

Mnemonic::
c.zext.w _rd'/rs1'_

Encoding (RV64)::
[wavedrom, , svg]
....
{reg:[
    { bits:  2, name: 0x1, attr: ['C1'] },
    { bits:  3, name: 0x4, attr: ['C.ZEXT.W'] },
    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
    { bits:  3, name: 0x7 },
    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
],config:{bits:16}}
....

Description::
This instruction takes a single source/destination operand. 
It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of
the bits more significant than 31.

[NOTE]
  _rd'/rs1'_ is from the standard 8-register set x8-x15.

Prerequisites::
Zba is also required.
 
32-bit equivalent::
[source,sail]
--
add.uw rd'/rs1', rd'/rs1', zero
--

[NOTE]

  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.

Operation::
[source,sail]
--
X(rsdc) = EXTZ(X(rsdc)[31..0]);
--

include::Zcb_footer.adoc[]
