//### Figure 2.2

//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done.

[wavedrom, ,]
....
{reg: [
  {bits: 7,  name: 'opcode', type: 8},
  {bits: 5,  name: 'rd', type: 2},
  {bits: 3,  name: 'func3', type: 8},
  {bits: 5,  name: 'rs1', type: 4},
  {bits: 5,  name: 'rs2', type: 4},
  {bits: 7,  name: 'funct7', type: 8}
], config: {label: {right: 'R-Type'}}}
....

[wavedrom, ,]
....
{reg: [
  {bits: 7,  name: 'opcode', type: 8},
  {bits: 5,  name: 'rd', type: 2},
  {bits: 3,  name: 'func3', type: 8},
  {bits: 5,  name: 'rs1', type: 4},
  {bits: 12, name: 'imm[11:0]', type: 3},
], config: {label: {right: 'I-Type'}}}
....

[wavedrom, ,]
....
{reg: [
  {bits: 7,  name: 'opcode', type: 8},
  {bits: 5,  name: 'imm[4:0]', type: 3},
  {bits: 3,  name: 'func3', type: 8},
  {bits: 5,  name: 'rs1', type: 4},
  {bits: 5,  name: 'rs2', type: 4},
  {bits: 7,  name: 'imm[11:5]', type: 3}
], config: {label: {right: 'S-Type'}}}
....

[wavedrom, ,]
....
{reg: [
  {bits: 7,  name: 'opcode', type: 8},
  {bits: 5,  name: 'rd', type: 2},
  {bits: 20,  name: 'imm[31:12]', type: 3}
], config: {label: {right: 'U-Type'}}}
....
