
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b14 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b14)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rd == rs2 == rs3 != rs1, rs1==f27, rs2==f30, rs3==f30, rd==f30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f27; op2:f30; op3:f30; dest:f30; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x7f35fb9d; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f30, f27, f30, f30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f7, rs2==f7, rs3==f12, rd==f13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x66 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f7; op2:f7; op3:f12; dest:f13; op1val:0x7f378efe; op2val:0x7f378efe;
op3val:0x3338bca8; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f13, f7, f7, f12, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f8, rs2==f12, rs3==f7, rd==f7,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x67 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f8; op2:f12; op3:f7; dest:f7; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x33b8bca8; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f7, f8, f12, f7, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f3, rs2==f13, rs3==f13, rd==f23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x68 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f3; op2:f13; op3:f13; dest:f23; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x7f35fb9d; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f23, f3, f13, f13, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f20, rs2==f26, rs3==f17, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x69 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f20; op2:f26; op3:f17; dest:f20; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x34b8bca8; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f20, f20, f26, f17, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f21, rs2==f31, rs3==f26, rd==f11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6a and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f21; op2:f31; op3:f26; dest:f11; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3538bca8; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f11, f21, f31, f26, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f1, rs2==f15, rs3==f31, rd==f15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6b and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f1; op2:f15; op3:f31; dest:f15; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x35b8bca8; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f15, f1, f15, f31, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f14, rs2==f14, rs3==f3, rd==f14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6c and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f14; op2:f14; op3:f3; dest:f14; op1val:0x7f378efe; op2val:0x7f378efe;
op3val:0x3638bca8; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f14, f14, f14, f3, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f19, rs2==f5, rs3==f19, rd==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6d and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f19; op2:f5; op3:f19; dest:f2; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x7f378efe; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f2, f19, f5, f19, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rd == rs3 != rs2, rs1==f10, rs2==f24, rs3==f10, rd==f10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6e and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f10; op2:f24; op3:f10; dest:f10; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x7f378efe; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f10, f10, f24, f10, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6f and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f22; op2:f22; op3:f22; dest:f21; op1val:0x7f378efe; op2val:0x7f378efe;
op3val:0x7f378efe; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f21, f22, f22, f22, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rs2 == rs3 == rd, rs1==f6, rs2==f6, rs3==f6, rd==f6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x70 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f6; op2:f6; op3:f6; dest:f6; op1val:0x7f378efe; op2val:0x7f378efe;
op3val:0x7f378efe; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f6, f6, f6, f6, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f28, rs2==f21, rs3==f15, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x71 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f28; op2:f21; op3:f15; dest:f4; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x38b8bca8; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f4, f28, f21, f15, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f15, rs2==f16, rs3==f0, rd==f1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x72 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f15; op2:f16; op3:f0; dest:f1; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3938bca8; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f1, f15, f16, f0, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f31, rs2==f9, rs3==f4, rd==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x73 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f31; op2:f9; op3:f4; dest:f0; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x39b8bca8; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f0, f31, f9, f4, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f5, rs2==f4, rs3==f27, rd==f24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x74 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f5; op2:f4; op3:f27; dest:f24; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3a38bca8; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f24, f5, f4, f27, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f0, rs2==f1, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f0; op2:f1; op3:f16; dest:f18; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3ab8bca8; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f18, f0, f1, f16, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f24, rs2==f20, rs3==f14, rd==f16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x76 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f24; op2:f20; op3:f14; dest:f16; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3b38bca8; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f16, f24, f20, f14, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f4, rs2==f23, rs3==f8, rd==f5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x77 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f4; op2:f23; op3:f8; dest:f5; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3bb8bca8; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f5, f4, f23, f8, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f9, rs2==f25, rs3==f18, rd==f28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x78 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f9; op2:f25; op3:f18; dest:f28; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3c38bca8; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f28, f9, f25, f18, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f26, rs2==f29, rs3==f5, rd==f9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x79 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f26; op2:f29; op3:f5; dest:f9; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3cb8bca8; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f9, f26, f29, f5, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f23, rs2==f11, rs3==f1, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x7a and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f23; op2:f11; op3:f1; dest:f26; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3d38bca8; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f26, f23, f11, f1, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f30, rs2==f27, rs3==f28, rd==f29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x7b and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f27; op3:f28; dest:f29; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3db8bca8; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f29, f30, f27, f28, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f16, rs2==f19, rs3==f20, rd==f31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x7c and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f16; op2:f19; op3:f20; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3e38bca8; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f16, f19, f20, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f13, rs2==f10, rs3==f23, rd==f8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x7d and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f13; op2:f10; op3:f23; dest:f8; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3eb8bca8; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f8, f13, f10, f23, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f17, rs2==f0, rs3==f29, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x7e and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f17; op2:f0; op3:f29; dest:f27; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3f38bca8; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f27, f17, f0, f29, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f29, rs2==f2, rs3==f24, rd==f12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f29; op2:f2; op3:f24; dest:f12; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3fb8bca8; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f12, f29, f2, f24, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f11, rs2==f18, rs3==f9, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x80 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f11; op2:f18; op3:f9; dest:f19; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4038bca8; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f19, f11, f18, f9, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f25, rs2==f28, rs3==f11, rd==f3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x81 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f25; op2:f28; op3:f11; dest:f3; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x40b8bca8; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f3, f25, f28, f11, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f12, rs2==f3, rs3==f25, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x82 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f12; op2:f3; op3:f25; dest:f22; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4138bca8; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f22, f12, f3, f25, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f18, rs2==f8, rs3==f2, rd==f25,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x83 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f18; op2:f8; op3:f2; dest:f25; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x41b8bca8; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f25, f18, f8, f2, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x84 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f2; op2:f26; op3:f23; dest:f4; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4238bca8; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f4, f2, f26, f23, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x85 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f3; op2:f17; op3:f31; dest:f2; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x42b8bca8; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f2, f3, f17, f31, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x86 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f2; op2:f19; op3:f21; dest:f12; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4338bca8; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f12, f2, f19, f21, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x87 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f29; op2:f11; op3:f13; dest:f17; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x43b8bca8; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f17, f29, f11, f13, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x88 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4438bca8; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x89 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x44b8bca8; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x8a and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4538bca8; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x8b and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x45b8bca8; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x8c and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4638bca8; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x8d and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x46b8bca8; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x8e and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4738bca8; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x8f and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x47b8bca8; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x90 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4838bca8; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x91 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x48b8bca8; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x92 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4938bca8; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x93 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x49b8bca8; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x94 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4a38bca8; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x95 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4ab8bca8; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x96 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4b38bca8; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x97 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4bb8bca8; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x98 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4c38bca8; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x99 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4cb8bca8; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x9a and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4d38bca8; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x9b and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4db8bca8; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x9c and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4e38bca8; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x9d and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4eb8bca8; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x9e and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4f38bca8; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x9f and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x4fb8bca8; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa0 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5038bca8; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa1 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x50b8bca8; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa2 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5138bca8; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa3 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x51b8bca8; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa4 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5238bca8; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa5 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x52b8bca8; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa6 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5338bca8; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa7 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x53b8bca8; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa8 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5438bca8; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xa9 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x54b8bca8; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xaa and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5538bca8; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xab and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x55b8bca8; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xac and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x5638bca8; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0xdb and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x6db8bca8; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x538bca8; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x66 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3338bca8; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x67 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x33b8bca8; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x68 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3438bca8; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x69 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x34b8bca8; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6b and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x35b8bca8; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6c and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3638bca8; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6d and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x36b8bca8; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6e and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3738bca8; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x6f and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x37b8bca8; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x35fb9d and fs3 == 0 and fe3 == 0x70 and fm3 == 0x38bca8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f378efe; op2val:0x7f35fb9d;
op3val:0x3838bca8; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(859356328,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(867744936,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(884522152,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(892910760,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(901299368,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(909687976,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(951631016,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(960019624,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(968408232,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(976796840,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(985185448,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(993574056,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1001962664,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1010351272,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1018739880,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1027128488,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1035517096,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1043905704,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1052294312,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1060682920,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1069071528,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1077460136,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1085848744,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1094237352,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1102625960,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1111014568,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1119403176,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1127791784,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1136180392,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1144569000,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1152957608,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1161346216,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1169734824,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1178123432,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1186512040,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1194900648,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1203289256,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1211677864,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1220066472,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1228455080,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1236843688,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1245232296,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1253620904,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1262009512,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1270398120,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1278786728,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1287175336,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1295563944,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1303952552,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1312341160,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1320729768,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1329118376,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1337506984,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1345895592,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1354284200,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1362672808,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1371061416,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1379450024,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1387838632,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1396227240,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1404615848,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1413004456,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1421393064,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1429781672,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1438170280,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1446558888,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(1840823464,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(87604392,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(859356328,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(867744936,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(876133544,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(884522152,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(901299368,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(909687976,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(918076584,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(926465192,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(934853800,32,FLEN)
NAN_BOXED(2134347518,32,FLEN)
NAN_BOXED(2134244253,32,FLEN)
NAN_BOXED(943242408,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 168*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
