
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b5 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b5)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rd == rs2 == rs3 != rs1, rs1==f24, rs2==f17, rs3==f17, rd==f17,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f24; op2:f17; op3:f17; dest:f17; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x44b76ad3; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f17, f24, f17, f17, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f23, rs2==f23, rs3==f0, rd==f21,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f23; op2:f23; op3:f0; dest:f21; op1val:0x79b19f1b; op2val:0x79b19f1b;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f21, f23, f23, f0, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f13, rs3==f30, rd==f30,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f28; op2:f13; op3:f30; dest:f30; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f30, f28, f13, f30, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f19, rs2==f22, rs3==f22, rd==f11,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f19; op2:f22; op3:f22; dest:f11; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x44b76ad3; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f11, f19, f22, f22, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f2, rs2==f19, rs3==f27, rd==f2,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f2; op2:f19; op3:f27; dest:f2; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f2, f2, f19, f27, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f18, rs2==f8, rs3==f14, rd==f4,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f18; op2:f8; op3:f14; dest:f4; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f4, f18, f8, f14, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f8, rs2==f29, rs3==f2, rd==f29,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f8; op2:f29; op3:f2; dest:f29; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f29, f8, f29, f2, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f12, rs2==f12, rs3==f28, rd==f12,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f12; op2:f12; op3:f28; dest:f12; op1val:0x7cae9fe8; op2val:0x7cae9fe8;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f12, f12, f12, f28, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f29, rs2==f9, rs3==f29, rd==f28,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f29; op2:f9; op3:f29; dest:f28; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7cae9fe8; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f28, f29, f9, f29, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rd == rs3 != rs2, rs1==f25, rs2==f30, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f25; op2:f30; op3:f25; dest:f25; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7cae9fe8; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f25, f25, f30, f25, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs2 == rs3 != rd, rs1==f10, rs2==f10, rs3==f10, rd==f27,fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f10; op2:f10; op3:f10; dest:f27; op1val:0x7d255773; op2val:0x7d255773;
op3val:0x7d255773; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f27, f10, f10, f10, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rs2 == rs3 == rd, rs1==f1, rs2==f1, rs3==f1, rd==f1,fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f1; op2:f1; op3:f1; dest:f1; op1val:0x7d255773; op2val:0x7d255773;
op3val:0x7d255773; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f1, f1, f1, f1, dyn, 32, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f31, rs2==f21, rs3==f24, rd==f10,fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f31; op2:f21; op3:f24; dest:f10; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f10, f31, f21, f24, dyn, 64, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f15, rs2==f6, rs3==f9, rd==f8,fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f15; op2:f6; op3:f9; dest:f8; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f8, f15, f6, f9, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f13, rs2==f28, rs3==f16, rd==f14,fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f13; op2:f28; op3:f16; dest:f14; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f14, f13, f28, f16, dyn, 128, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f20, rs2==f2, rs3==f11, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f20; op2:f2; op3:f11; dest:f16; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f16, f20, f2, f11, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f0, rs2==f16, rs3==f5, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f0; op2:f16; op3:f5; dest:f23; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f23, f0, f16, f5, dyn, 32, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f16, rs2==f27, rs3==f15, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f16; op2:f27; op3:f15; dest:f3; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f3, f16, f27, f15, dyn, 64, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f14, rs2==f26, rs3==f6, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f14; op2:f26; op3:f6; dest:f19; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f19, f14, f26, f6, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f22, rs2==f7, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f22; op2:f7; op3:f13; dest:f15; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f15, f22, f7, f13, dyn, 128, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f27, rs2==f3, rs3==f21, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f27; op2:f3; op3:f21; dest:f18; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f18, f27, f3, f21, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f3, rs2==f31, rs3==f19, rd==f6,fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f3; op2:f31; op3:f19; dest:f6; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f6, f3, f31, f19, dyn, 32, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f30, rs2==f18, rs3==f4, rd==f7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f18; op3:f4; dest:f7; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f7, f30, f18, f4, dyn, 64, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f6, rs2==f11, rs3==f12, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f6; op2:f11; op3:f12; dest:f24; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f24, f6, f11, f12, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f11, rs2==f15, rs3==f3, rd==f13,fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f11; op2:f15; op3:f3; dest:f13; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f13, f11, f15, f3, dyn, 128, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f9, rs2==f5, rs3==f7, rd==f20,fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f9; op2:f5; op3:f7; dest:f20; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f20, f9, f5, f7, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f7, rs2==f4, rs3==f20, rd==f5,fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f7; op2:f4; op3:f20; dest:f5; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f5, f7, f4, f20, dyn, 32, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f17, rs2==f24, rs3==f18, rd==f31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f17; op2:f24; op3:f18; dest:f31; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f17, f24, f18, dyn, 64, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f5, rs2==f20, rs3==f26, rd==f9,fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f5; op2:f20; op3:f26; dest:f9; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f9, f5, f20, f26, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f4, rs2==f14, rs3==f31, rd==f26,fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f4; op2:f14; op3:f31; dest:f26; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f26, f4, f14, f31, dyn, 128, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f21, rs2==f0, rs3==f8, rd==f22,fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f21; op2:f0; op3:f8; dest:f22; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f22, f21, f0, f8, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f26, rs2==f25, rs3==f23, rd==f0,fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f26; op2:f25; op3:f23; dest:f0; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f0, f26, f25, f23, dyn, 32, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 690*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(1090219463,32,FLEN)
NAN_BOXED(2124571557,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(1090219463,32,FLEN)
NAN_BOXED(2124571557,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(1090219463,32,FLEN)
NAN_BOXED(2124571557,32,FLEN)
NAN_BOXED(2106527234,32,FLEN)
NAN_BOXED(1091140588,32,FLEN)
NAN_BOXED(2132387710,32,FLEN)
NAN_BOXED(2106527234,32,FLEN)
NAN_BOXED(1091140588,32,FLEN)
NAN_BOXED(2132387710,32,FLEN)
NAN_BOXED(2106527234,32,FLEN)
NAN_BOXED(1091140588,32,FLEN)
NAN_BOXED(2132387710,32,FLEN)
NAN_BOXED(2106527234,32,FLEN)
NAN_BOXED(1091140588,32,FLEN)
NAN_BOXED(2132387710,32,FLEN)
NAN_BOXED(2106527234,32,FLEN)
NAN_BOXED(1091140588,32,FLEN)
NAN_BOXED(2132387710,32,FLEN)
NAN_BOXED(2106592241,32,FLEN)
NAN_BOXED(1074171239,32,FLEN)
NAN_BOXED(2115464098,32,FLEN)
NAN_BOXED(2106592241,32,FLEN)
NAN_BOXED(1074171239,32,FLEN)
NAN_BOXED(2115464098,32,FLEN)
NAN_BOXED(2106592241,32,FLEN)
NAN_BOXED(1074171239,32,FLEN)
NAN_BOXED(2115464098,32,FLEN)
NAN_BOXED(2106592241,32,FLEN)
NAN_BOXED(1074171239,32,FLEN)
NAN_BOXED(2115464098,32,FLEN)
NAN_BOXED(2106592241,32,FLEN)
NAN_BOXED(1074171239,32,FLEN)
NAN_BOXED(2115464098,32,FLEN)
NAN_BOXED(2108911927,32,FLEN)
NAN_BOXED(1085638902,32,FLEN)
NAN_BOXED(2130607643,32,FLEN)
NAN_BOXED(2108911927,32,FLEN)
NAN_BOXED(1085638902,32,FLEN)
NAN_BOXED(2130607643,32,FLEN)
NAN_BOXED(2108911927,32,FLEN)
NAN_BOXED(1085638902,32,FLEN)
NAN_BOXED(2130607643,32,FLEN)
NAN_BOXED(2108911927,32,FLEN)
NAN_BOXED(1085638902,32,FLEN)
NAN_BOXED(2130607643,32,FLEN)
NAN_BOXED(2108911927,32,FLEN)
NAN_BOXED(1085638902,32,FLEN)
NAN_BOXED(2130607643,32,FLEN)
NAN_BOXED(2109919601,32,FLEN)
NAN_BOXED(1090274342,32,FLEN)
NAN_BOXED(2134899207,32,FLEN)
NAN_BOXED(2109919601,32,FLEN)
NAN_BOXED(1090274342,32,FLEN)
NAN_BOXED(2134899207,32,FLEN)
NAN_BOXED(2109919601,32,FLEN)
NAN_BOXED(1090274342,32,FLEN)
NAN_BOXED(2134899207,32,FLEN)
NAN_BOXED(2109919601,32,FLEN)
NAN_BOXED(1090274342,32,FLEN)
NAN_BOXED(2134899207,32,FLEN)
NAN_BOXED(2109919601,32,FLEN)
NAN_BOXED(1090274342,32,FLEN)
NAN_BOXED(2134899207,32,FLEN)
NAN_BOXED(2115253854,32,FLEN)
NAN_BOXED(1077385403,32,FLEN)
NAN_BOXED(2127861397,32,FLEN)
NAN_BOXED(2115253854,32,FLEN)
NAN_BOXED(1077385403,32,FLEN)
NAN_BOXED(2127861397,32,FLEN)
NAN_BOXED(2115253854,32,FLEN)
NAN_BOXED(1077385403,32,FLEN)
NAN_BOXED(2127861397,32,FLEN)
NAN_BOXED(2115253854,32,FLEN)
NAN_BOXED(1077385403,32,FLEN)
NAN_BOXED(2127861397,32,FLEN)
NAN_BOXED(2115253854,32,FLEN)
NAN_BOXED(1077385403,32,FLEN)
NAN_BOXED(2127861397,32,FLEN)
NAN_BOXED(2115650943,32,FLEN)
NAN_BOXED(1079038208,32,FLEN)
NAN_BOXED(2130422996,32,FLEN)
NAN_BOXED(2115650943,32,FLEN)
NAN_BOXED(1079038208,32,FLEN)
NAN_BOXED(2130422996,32,FLEN)
NAN_BOXED(2115650943,32,FLEN)
NAN_BOXED(1079038208,32,FLEN)
NAN_BOXED(2130422996,32,FLEN)
NAN_BOXED(2115650943,32,FLEN)
NAN_BOXED(1079038208,32,FLEN)
NAN_BOXED(2130422996,32,FLEN)
NAN_BOXED(2115650943,32,FLEN)
NAN_BOXED(1079038208,32,FLEN)
NAN_BOXED(2130422996,32,FLEN)
NAN_BOXED(2116104479,32,FLEN)
NAN_BOXED(1082390202,32,FLEN)
NAN_BOXED(2133208827,32,FLEN)
NAN_BOXED(2116104479,32,FLEN)
NAN_BOXED(1082390202,32,FLEN)
NAN_BOXED(2133208827,32,FLEN)
NAN_BOXED(2116104479,32,FLEN)
NAN_BOXED(1082390202,32,FLEN)
NAN_BOXED(2133208827,32,FLEN)
NAN_BOXED(2116104479,32,FLEN)
NAN_BOXED(1082390202,32,FLEN)
NAN_BOXED(2133208827,32,FLEN)
NAN_BOXED(2116104479,32,FLEN)
NAN_BOXED(1082390202,32,FLEN)
NAN_BOXED(2133208827,32,FLEN)
NAN_BOXED(2119265951,32,FLEN)
NAN_BOXED(1077687286,32,FLEN)
NAN_BOXED(2132408255,32,FLEN)
NAN_BOXED(2119265951,32,FLEN)
NAN_BOXED(1077687286,32,FLEN)
NAN_BOXED(2132408255,32,FLEN)
NAN_BOXED(2119265951,32,FLEN)
NAN_BOXED(1077687286,32,FLEN)
NAN_BOXED(2132408255,32,FLEN)
NAN_BOXED(2119265951,32,FLEN)
NAN_BOXED(1077687286,32,FLEN)
NAN_BOXED(2132408255,32,FLEN)
NAN_BOXED(2119265951,32,FLEN)
NAN_BOXED(1077687286,32,FLEN)
NAN_BOXED(2132408255,32,FLEN)
NAN_BOXED(2121258207,32,FLEN)
NAN_BOXED(1059118102,32,FLEN)
NAN_BOXED(2115416891,32,FLEN)
NAN_BOXED(2121258207,32,FLEN)
NAN_BOXED(1059118102,32,FLEN)
NAN_BOXED(2115416891,32,FLEN)
NAN_BOXED(2121258207,32,FLEN)
NAN_BOXED(1059118102,32,FLEN)
NAN_BOXED(2115416891,32,FLEN)
NAN_BOXED(2121258207,32,FLEN)
NAN_BOXED(1059118102,32,FLEN)
NAN_BOXED(2115416891,32,FLEN)
NAN_BOXED(2121258207,32,FLEN)
NAN_BOXED(1059118102,32,FLEN)
NAN_BOXED(2115416891,32,FLEN)
NAN_BOXED(2122296620,32,FLEN)
NAN_BOXED(1076748078,32,FLEN)
NAN_BOXED(2133698285,32,FLEN)
NAN_BOXED(2122296620,32,FLEN)
NAN_BOXED(1076748078,32,FLEN)
NAN_BOXED(2133698285,32,FLEN)
NAN_BOXED(2122296620,32,FLEN)
NAN_BOXED(1076748078,32,FLEN)
NAN_BOXED(2133698285,32,FLEN)
NAN_BOXED(2122296620,32,FLEN)
NAN_BOXED(1076748078,32,FLEN)
NAN_BOXED(2133698285,32,FLEN)
NAN_BOXED(2122296620,32,FLEN)
NAN_BOXED(1076748078,32,FLEN)
NAN_BOXED(2133698285,32,FLEN)
NAN_BOXED(2122998464,32,FLEN)
NAN_BOXED(1076208946,32,FLEN)
NAN_BOXED(2134054373,32,FLEN)
NAN_BOXED(2122998464,32,FLEN)
NAN_BOXED(1076208946,32,FLEN)
NAN_BOXED(2134054373,32,FLEN)
NAN_BOXED(2122998464,32,FLEN)
NAN_BOXED(1076208946,32,FLEN)
NAN_BOXED(2134054373,32,FLEN)
NAN_BOXED(2122998464,32,FLEN)
NAN_BOXED(1076208946,32,FLEN)
NAN_BOXED(2134054373,32,FLEN)
NAN_BOXED(2122998464,32,FLEN)
NAN_BOXED(1076208946,32,FLEN)
NAN_BOXED(2134054373,32,FLEN)
NAN_BOXED(2123320103,32,FLEN)
NAN_BOXED(1074009549,32,FLEN)
NAN_BOXED(2132008425,32,FLEN)
NAN_BOXED(2123320103,32,FLEN)
NAN_BOXED(1074009549,32,FLEN)
NAN_BOXED(2132008425,32,FLEN)
NAN_BOXED(2123320103,32,FLEN)
NAN_BOXED(1074009549,32,FLEN)
NAN_BOXED(2132008425,32,FLEN)
NAN_BOXED(2123320103,32,FLEN)
NAN_BOXED(1074009549,32,FLEN)
NAN_BOXED(2132008425,32,FLEN)
NAN_BOXED(2123320103,32,FLEN)
NAN_BOXED(1074009549,32,FLEN)
NAN_BOXED(2132008425,32,FLEN)
NAN_BOXED(2123426918,32,FLEN)
NAN_BOXED(1065614623,32,FLEN)
NAN_BOXED(2123722888,32,FLEN)
NAN_BOXED(2123426918,32,FLEN)
NAN_BOXED(1065614623,32,FLEN)
NAN_BOXED(2123722888,32,FLEN)
NAN_BOXED(2123426918,32,FLEN)
NAN_BOXED(1065614623,32,FLEN)
NAN_BOXED(2123722888,32,FLEN)
NAN_BOXED(2123426918,32,FLEN)
NAN_BOXED(1065614623,32,FLEN)
NAN_BOXED(2123722888,32,FLEN)
NAN_BOXED(2123426918,32,FLEN)
NAN_BOXED(1065614623,32,FLEN)
NAN_BOXED(2123722888,32,FLEN)
NAN_BOXED(2125183225,32,FLEN)
NAN_BOXED(1072557633,32,FLEN)
NAN_BOXED(2132777488,32,FLEN)
NAN_BOXED(2125183225,32,FLEN)
NAN_BOXED(1072557633,32,FLEN)
NAN_BOXED(2132777488,32,FLEN)
NAN_BOXED(2125183225,32,FLEN)
NAN_BOXED(1072557633,32,FLEN)
NAN_BOXED(2132777488,32,FLEN)
NAN_BOXED(2125183225,32,FLEN)
NAN_BOXED(1072557633,32,FLEN)
NAN_BOXED(2132777488,32,FLEN)
NAN_BOXED(2125183225,32,FLEN)
NAN_BOXED(1072557633,32,FLEN)
NAN_BOXED(2132777488,32,FLEN)
NAN_BOXED(2125763551,32,FLEN)
NAN_BOXED(1070517026,32,FLEN)
NAN_BOXED(2131877447,32,FLEN)
NAN_BOXED(2125763551,32,FLEN)
NAN_BOXED(1070517026,32,FLEN)
NAN_BOXED(2131877447,32,FLEN)
NAN_BOXED(2125763551,32,FLEN)
NAN_BOXED(1070517026,32,FLEN)
NAN_BOXED(2131877447,32,FLEN)
NAN_BOXED(2125763551,32,FLEN)
NAN_BOXED(1070517026,32,FLEN)
NAN_BOXED(2131877447,32,FLEN)
NAN_BOXED(2125763551,32,FLEN)
NAN_BOXED(1070517026,32,FLEN)
NAN_BOXED(2131877447,32,FLEN)
NAN_BOXED(2125780552,32,FLEN)
NAN_BOXED(1069534663,32,FLEN)
NAN_BOXED(2131197244,32,FLEN)
NAN_BOXED(2125780552,32,FLEN)
NAN_BOXED(1069534663,32,FLEN)
NAN_BOXED(2131197244,32,FLEN)
NAN_BOXED(2125780552,32,FLEN)
NAN_BOXED(1069534663,32,FLEN)
NAN_BOXED(2131197244,32,FLEN)
NAN_BOXED(2125780552,32,FLEN)
NAN_BOXED(1069534663,32,FLEN)
NAN_BOXED(2131197244,32,FLEN)
NAN_BOXED(2125780552,32,FLEN)
NAN_BOXED(1069534663,32,FLEN)
NAN_BOXED(2131197244,32,FLEN)
NAN_BOXED(2126103038,32,FLEN)
NAN_BOXED(1049766943,32,FLEN)
NAN_BOXED(2111054158,32,FLEN)
NAN_BOXED(2126103038,32,FLEN)
NAN_BOXED(1049766943,32,FLEN)
NAN_BOXED(2111054158,32,FLEN)
NAN_BOXED(2126103038,32,FLEN)
NAN_BOXED(1049766943,32,FLEN)
NAN_BOXED(2111054158,32,FLEN)
NAN_BOXED(2126103038,32,FLEN)
NAN_BOXED(1049766943,32,FLEN)
NAN_BOXED(2111054158,32,FLEN)
NAN_BOXED(2126103038,32,FLEN)
NAN_BOXED(1049766943,32,FLEN)
NAN_BOXED(2111054158,32,FLEN)
NAN_BOXED(2126135511,32,FLEN)
NAN_BOXED(1057625416,32,FLEN)
NAN_BOXED(2118708447,32,FLEN)
NAN_BOXED(2126135511,32,FLEN)
NAN_BOXED(1057625416,32,FLEN)
NAN_BOXED(2118708447,32,FLEN)
NAN_BOXED(2126135511,32,FLEN)
NAN_BOXED(1057625416,32,FLEN)
NAN_BOXED(2118708447,32,FLEN)
NAN_BOXED(2126135511,32,FLEN)
NAN_BOXED(1057625416,32,FLEN)
NAN_BOXED(2118708447,32,FLEN)
NAN_BOXED(2126135511,32,FLEN)
NAN_BOXED(1057625416,32,FLEN)
NAN_BOXED(2118708447,32,FLEN)
NAN_BOXED(2127476109,32,FLEN)
NAN_BOXED(1067593270,32,FLEN)
NAN_BOXED(2130900020,32,FLEN)
NAN_BOXED(2127476109,32,FLEN)
NAN_BOXED(1067593270,32,FLEN)
NAN_BOXED(2130900020,32,FLEN)
NAN_BOXED(2127476109,32,FLEN)
NAN_BOXED(1067593270,32,FLEN)
NAN_BOXED(2130900020,32,FLEN)
NAN_BOXED(2127476109,32,FLEN)
NAN_BOXED(1067593270,32,FLEN)
NAN_BOXED(2130900020,32,FLEN)
NAN_BOXED(2127476109,32,FLEN)
NAN_BOXED(1067593270,32,FLEN)
NAN_BOXED(2130900020,32,FLEN)
NAN_BOXED(2128755830,32,FLEN)
NAN_BOXED(1042014781,32,FLEN)
NAN_BOXED(2106180235,32,FLEN)
NAN_BOXED(2128755830,32,FLEN)
NAN_BOXED(1042014781,32,FLEN)
NAN_BOXED(2106180235,32,FLEN)
NAN_BOXED(2128755830,32,FLEN)
NAN_BOXED(1042014781,32,FLEN)
NAN_BOXED(2106180235,32,FLEN)
NAN_BOXED(2128755830,32,FLEN)
NAN_BOXED(1042014781,32,FLEN)
NAN_BOXED(2106180235,32,FLEN)
NAN_BOXED(2128755830,32,FLEN)
NAN_BOXED(1042014781,32,FLEN)
NAN_BOXED(2106180235,32,FLEN)
NAN_BOXED(2129072680,32,FLEN)
NAN_BOXED(1057060818,32,FLEN)
NAN_BOXED(2120857756,32,FLEN)
NAN_BOXED(2129072680,32,FLEN)
NAN_BOXED(1057060818,32,FLEN)
NAN_BOXED(2120857756,32,FLEN)
NAN_BOXED(2129072680,32,FLEN)
NAN_BOXED(1057060818,32,FLEN)
NAN_BOXED(2120857756,32,FLEN)
NAN_BOXED(2129072680,32,FLEN)
NAN_BOXED(1057060818,32,FLEN)
NAN_BOXED(2120857756,32,FLEN)
NAN_BOXED(2129072680,32,FLEN)
NAN_BOXED(1057060818,32,FLEN)
NAN_BOXED(2120857756,32,FLEN)
NAN_BOXED(2129538701,32,FLEN)
NAN_BOXED(1056747782,32,FLEN)
NAN_BOXED(2120948359,32,FLEN)
NAN_BOXED(2129538701,32,FLEN)
NAN_BOXED(1056747782,32,FLEN)
NAN_BOXED(2120948359,32,FLEN)
NAN_BOXED(2129538701,32,FLEN)
NAN_BOXED(1056747782,32,FLEN)
NAN_BOXED(2120948359,32,FLEN)
NAN_BOXED(2129538701,32,FLEN)
NAN_BOXED(1056747782,32,FLEN)
NAN_BOXED(2120948359,32,FLEN)
NAN_BOXED(2129538701,32,FLEN)
NAN_BOXED(1056747782,32,FLEN)
NAN_BOXED(2120948359,32,FLEN)
NAN_BOXED(2129907471,32,FLEN)
NAN_BOXED(1055575971,32,FLEN)
NAN_BOXED(2120196355,32,FLEN)
NAN_BOXED(2129907471,32,FLEN)
NAN_BOXED(1055575971,32,FLEN)
NAN_BOXED(2120196355,32,FLEN)
NAN_BOXED(2129907471,32,FLEN)
NAN_BOXED(1055575971,32,FLEN)
NAN_BOXED(2120196355,32,FLEN)
NAN_BOXED(2129907471,32,FLEN)
NAN_BOXED(1055575971,32,FLEN)
NAN_BOXED(2120196355,32,FLEN)
NAN_BOXED(2129907471,32,FLEN)
NAN_BOXED(1055575971,32,FLEN)
NAN_BOXED(2120196355,32,FLEN)
NAN_BOXED(2130150396,32,FLEN)
NAN_BOXED(1066047376,32,FLEN)
NAN_BOXED(2131099568,32,FLEN)
NAN_BOXED(2130150396,32,FLEN)
NAN_BOXED(1066047376,32,FLEN)
NAN_BOXED(2131099568,32,FLEN)
NAN_BOXED(2130150396,32,FLEN)
NAN_BOXED(1066047376,32,FLEN)
NAN_BOXED(2131099568,32,FLEN)
NAN_BOXED(2130150396,32,FLEN)
NAN_BOXED(1066047376,32,FLEN)
NAN_BOXED(2131099568,32,FLEN)
NAN_BOXED(2130150396,32,FLEN)
NAN_BOXED(1066047376,32,FLEN)
NAN_BOXED(2131099568,32,FLEN)
NAN_BOXED(2130751106,32,FLEN)
NAN_BOXED(1068097973,32,FLEN)
NAN_BOXED(2133510481,32,FLEN)
NAN_BOXED(2130751106,32,FLEN)
NAN_BOXED(1068097973,32,FLEN)
NAN_BOXED(2133510481,32,FLEN)
NAN_BOXED(2130751106,32,FLEN)
NAN_BOXED(1068097973,32,FLEN)
NAN_BOXED(2133510481,32,FLEN)
NAN_BOXED(2130751106,32,FLEN)
NAN_BOXED(1068097973,32,FLEN)
NAN_BOXED(2133510481,32,FLEN)
NAN_BOXED(2130751106,32,FLEN)
NAN_BOXED(1068097973,32,FLEN)
NAN_BOXED(2133510481,32,FLEN)
NAN_BOXED(2131103511,32,FLEN)
NAN_BOXED(1016261782,32,FLEN)
NAN_BOXED(2082070784,32,FLEN)
NAN_BOXED(2131103511,32,FLEN)
NAN_BOXED(1016261782,32,FLEN)
NAN_BOXED(2082070784,32,FLEN)
NAN_BOXED(2131103511,32,FLEN)
NAN_BOXED(1016261782,32,FLEN)
NAN_BOXED(2082070784,32,FLEN)
NAN_BOXED(2131103511,32,FLEN)
NAN_BOXED(1016261782,32,FLEN)
NAN_BOXED(2082070784,32,FLEN)
NAN_BOXED(2131103511,32,FLEN)
NAN_BOXED(1016261782,32,FLEN)
NAN_BOXED(2082070784,32,FLEN)
NAN_BOXED(2131501145,32,FLEN)
NAN_BOXED(1058093181,32,FLEN)
NAN_BOXED(2124348028,32,FLEN)
NAN_BOXED(2131501145,32,FLEN)
NAN_BOXED(1058093181,32,FLEN)
NAN_BOXED(2124348028,32,FLEN)
NAN_BOXED(2131501145,32,FLEN)
NAN_BOXED(1058093181,32,FLEN)
NAN_BOXED(2124348028,32,FLEN)
NAN_BOXED(2131501145,32,FLEN)
NAN_BOXED(1058093181,32,FLEN)
NAN_BOXED(2124348028,32,FLEN)
NAN_BOXED(2131501145,32,FLEN)
NAN_BOXED(1058093181,32,FLEN)
NAN_BOXED(2124348028,32,FLEN)
NAN_BOXED(2131708614,32,FLEN)
NAN_BOXED(1057517794,32,FLEN)
NAN_BOXED(2123939281,32,FLEN)
NAN_BOXED(2131708614,32,FLEN)
NAN_BOXED(1057517794,32,FLEN)
NAN_BOXED(2123939281,32,FLEN)
NAN_BOXED(2131708614,32,FLEN)
NAN_BOXED(1057517794,32,FLEN)
NAN_BOXED(2123939281,32,FLEN)
NAN_BOXED(2131708614,32,FLEN)
NAN_BOXED(1057517794,32,FLEN)
NAN_BOXED(2123939281,32,FLEN)
NAN_BOXED(2131708614,32,FLEN)
NAN_BOXED(1057517794,32,FLEN)
NAN_BOXED(2123939281,32,FLEN)
NAN_BOXED(2132108052,32,FLEN)
NAN_BOXED(1018403743,32,FLEN)
NAN_BOXED(2085723695,32,FLEN)
NAN_BOXED(2132108052,32,FLEN)
NAN_BOXED(1018403743,32,FLEN)
NAN_BOXED(2085723695,32,FLEN)
NAN_BOXED(2132108052,32,FLEN)
NAN_BOXED(1018403743,32,FLEN)
NAN_BOXED(2085723695,32,FLEN)
NAN_BOXED(2132108052,32,FLEN)
NAN_BOXED(1018403743,32,FLEN)
NAN_BOXED(2085723695,32,FLEN)
NAN_BOXED(2132108052,32,FLEN)
NAN_BOXED(1018403743,32,FLEN)
NAN_BOXED(2085723695,32,FLEN)
NAN_BOXED(2132300352,32,FLEN)
NAN_BOXED(1065655773,32,FLEN)
NAN_BOXED(2132660398,32,FLEN)
NAN_BOXED(2132300352,32,FLEN)
NAN_BOXED(1065655773,32,FLEN)
NAN_BOXED(2132660398,32,FLEN)
NAN_BOXED(2132300352,32,FLEN)
NAN_BOXED(1065655773,32,FLEN)
NAN_BOXED(2132660398,32,FLEN)
NAN_BOXED(2132300352,32,FLEN)
NAN_BOXED(1065655773,32,FLEN)
NAN_BOXED(2132660398,32,FLEN)
NAN_BOXED(2132300352,32,FLEN)
NAN_BOXED(1065655773,32,FLEN)
NAN_BOXED(2132660398,32,FLEN)
NAN_BOXED(2132335065,32,FLEN)
NAN_BOXED(1059464803,32,FLEN)
NAN_BOXED(2126932061,32,FLEN)
NAN_BOXED(2132335065,32,FLEN)
NAN_BOXED(1059464803,32,FLEN)
NAN_BOXED(2126932061,32,FLEN)
NAN_BOXED(2132335065,32,FLEN)
NAN_BOXED(1059464803,32,FLEN)
NAN_BOXED(2126932061,32,FLEN)
NAN_BOXED(2132335065,32,FLEN)
NAN_BOXED(1059464803,32,FLEN)
NAN_BOXED(2126932061,32,FLEN)
NAN_BOXED(2132335065,32,FLEN)
NAN_BOXED(1059464803,32,FLEN)
NAN_BOXED(2126932061,32,FLEN)
NAN_BOXED(2132426498,32,FLEN)
NAN_BOXED(1062895721,32,FLEN)
NAN_BOXED(2130945799,32,FLEN)
NAN_BOXED(2132426498,32,FLEN)
NAN_BOXED(1062895721,32,FLEN)
NAN_BOXED(2130945799,32,FLEN)
NAN_BOXED(2132426498,32,FLEN)
NAN_BOXED(1062895721,32,FLEN)
NAN_BOXED(2130945799,32,FLEN)
NAN_BOXED(2132426498,32,FLEN)
NAN_BOXED(1062895721,32,FLEN)
NAN_BOXED(2130945799,32,FLEN)
NAN_BOXED(2132426498,32,FLEN)
NAN_BOXED(1062895721,32,FLEN)
NAN_BOXED(2130945799,32,FLEN)
NAN_BOXED(2132444318,32,FLEN)
NAN_BOXED(1057857307,32,FLEN)
NAN_BOXED(2125133352,32,FLEN)
NAN_BOXED(2132444318,32,FLEN)
NAN_BOXED(1057857307,32,FLEN)
NAN_BOXED(2125133352,32,FLEN)
NAN_BOXED(2132444318,32,FLEN)
NAN_BOXED(1057857307,32,FLEN)
NAN_BOXED(2125133352,32,FLEN)
NAN_BOXED(2132444318,32,FLEN)
NAN_BOXED(1057857307,32,FLEN)
NAN_BOXED(2125133352,32,FLEN)
NAN_BOXED(2132444318,32,FLEN)
NAN_BOXED(1057857307,32,FLEN)
NAN_BOXED(2125133352,32,FLEN)
NAN_BOXED(2132448628,32,FLEN)
NAN_BOXED(1051253274,32,FLEN)
NAN_BOXED(2118904719,32,FLEN)
NAN_BOXED(2132448628,32,FLEN)
NAN_BOXED(1051253274,32,FLEN)
NAN_BOXED(2118904719,32,FLEN)
NAN_BOXED(2132448628,32,FLEN)
NAN_BOXED(1051253274,32,FLEN)
NAN_BOXED(2118904719,32,FLEN)
NAN_BOXED(2132448628,32,FLEN)
NAN_BOXED(1051253274,32,FLEN)
NAN_BOXED(2118904719,32,FLEN)
NAN_BOXED(2132448628,32,FLEN)
NAN_BOXED(1051253274,32,FLEN)
NAN_BOXED(2118904719,32,FLEN)
NAN_BOXED(2132453421,32,FLEN)
NAN_BOXED(1067132673,32,FLEN)
NAN_BOXED(2134603464,32,FLEN)
NAN_BOXED(2132453421,32,FLEN)
NAN_BOXED(1067132673,32,FLEN)
NAN_BOXED(2134603464,32,FLEN)
NAN_BOXED(2132453421,32,FLEN)
NAN_BOXED(1067132673,32,FLEN)
NAN_BOXED(2134603464,32,FLEN)
NAN_BOXED(2132453421,32,FLEN)
NAN_BOXED(1067132673,32,FLEN)
NAN_BOXED(2134603464,32,FLEN)
NAN_BOXED(2132453421,32,FLEN)
NAN_BOXED(1067132673,32,FLEN)
NAN_BOXED(2134603464,32,FLEN)
NAN_BOXED(2132941353,32,FLEN)
NAN_BOXED(1053524475,32,FLEN)
NAN_BOXED(2122374413,32,FLEN)
NAN_BOXED(2132941353,32,FLEN)
NAN_BOXED(1053524475,32,FLEN)
NAN_BOXED(2122374413,32,FLEN)
NAN_BOXED(2132941353,32,FLEN)
NAN_BOXED(1053524475,32,FLEN)
NAN_BOXED(2122374413,32,FLEN)
NAN_BOXED(2132941353,32,FLEN)
NAN_BOXED(1053524475,32,FLEN)
NAN_BOXED(2122374413,32,FLEN)
NAN_BOXED(2132941353,32,FLEN)
NAN_BOXED(1053524475,32,FLEN)
NAN_BOXED(2122374413,32,FLEN)
NAN_BOXED(2133391778,32,FLEN)
NAN_BOXED(1058589255,32,FLEN)
NAN_BOXED(2127147896,32,FLEN)
NAN_BOXED(2133391778,32,FLEN)
NAN_BOXED(1058589255,32,FLEN)
NAN_BOXED(2127147896,32,FLEN)
NAN_BOXED(2133391778,32,FLEN)
NAN_BOXED(1058589255,32,FLEN)
NAN_BOXED(2127147896,32,FLEN)
NAN_BOXED(2133391778,32,FLEN)
NAN_BOXED(1058589255,32,FLEN)
NAN_BOXED(2127147896,32,FLEN)
NAN_BOXED(2133391778,32,FLEN)
NAN_BOXED(1058589255,32,FLEN)
NAN_BOXED(2127147896,32,FLEN)
NAN_BOXED(2133762122,32,FLEN)
NAN_BOXED(1058069466,32,FLEN)
NAN_BOXED(2126880836,32,FLEN)
NAN_BOXED(2133762122,32,FLEN)
NAN_BOXED(1058069466,32,FLEN)
NAN_BOXED(2126880836,32,FLEN)
NAN_BOXED(2133762122,32,FLEN)
NAN_BOXED(1058069466,32,FLEN)
NAN_BOXED(2126880836,32,FLEN)
NAN_BOXED(2133762122,32,FLEN)
NAN_BOXED(1058069466,32,FLEN)
NAN_BOXED(2126880836,32,FLEN)
NAN_BOXED(2133762122,32,FLEN)
NAN_BOXED(1058069466,32,FLEN)
NAN_BOXED(2126880836,32,FLEN)
NAN_BOXED(2134288866,32,FLEN)
NAN_BOXED(1058955275,32,FLEN)
NAN_BOXED(2128741059,32,FLEN)
NAN_BOXED(2134288866,32,FLEN)
NAN_BOXED(1058955275,32,FLEN)
NAN_BOXED(2128741059,32,FLEN)
NAN_BOXED(2134288866,32,FLEN)
NAN_BOXED(1058955275,32,FLEN)
NAN_BOXED(2128741059,32,FLEN)
NAN_BOXED(2134288866,32,FLEN)
NAN_BOXED(1058955275,32,FLEN)
NAN_BOXED(2128741059,32,FLEN)
NAN_BOXED(2134288866,32,FLEN)
NAN_BOXED(1058955275,32,FLEN)
NAN_BOXED(2128741059,32,FLEN)
NAN_BOXED(2134639716,32,FLEN)
NAN_BOXED(1063862694,32,FLEN)
NAN_BOXED(2133545014,32,FLEN)
NAN_BOXED(2134639716,32,FLEN)
NAN_BOXED(1063862694,32,FLEN)
NAN_BOXED(2133545014,32,FLEN)
NAN_BOXED(2134639716,32,FLEN)
NAN_BOXED(1063862694,32,FLEN)
NAN_BOXED(2133545014,32,FLEN)
NAN_BOXED(2134639716,32,FLEN)
NAN_BOXED(1063862694,32,FLEN)
NAN_BOXED(2133545014,32,FLEN)
NAN_BOXED(2134639716,32,FLEN)
NAN_BOXED(1063862694,32,FLEN)
NAN_BOXED(2133545014,32,FLEN)
NAN_BOXED(2134661327,32,FLEN)
NAN_BOXED(1048578314,32,FLEN)
NAN_BOXED(2117887516,32,FLEN)
NAN_BOXED(2134661327,32,FLEN)
NAN_BOXED(1048578314,32,FLEN)
NAN_BOXED(2117887516,32,FLEN)
NAN_BOXED(2134661327,32,FLEN)
NAN_BOXED(1048578314,32,FLEN)
NAN_BOXED(2117887516,32,FLEN)
NAN_BOXED(2134661327,32,FLEN)
NAN_BOXED(1048578314,32,FLEN)
NAN_BOXED(2117887516,32,FLEN)
NAN_BOXED(2134661327,32,FLEN)
NAN_BOXED(1048578314,32,FLEN)
NAN_BOXED(2117887516,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2041683739,32,FLEN)
NAN_BOXED(1152871123,32,FLEN)
NAN_BOXED(2130609590,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2091818984,32,FLEN)
NAN_BOXED(1095462741,32,FLEN)
NAN_BOXED(2123023551,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(1090219463,32,FLEN)
NAN_BOXED(2124571557,32,FLEN)
NAN_BOXED(2099599219,32,FLEN)
NAN_BOXED(1090219463,32,FLEN)
NAN_BOXED(2124571557,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 206*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
