
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Sat May  6 11:00:27 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fsub_b4 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fsub_b4)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f31; dest:f31; op1val:0x704c; op2val:0xfaeb;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f31; op2:f29; dest:f30; op1val:0x704c; op2val:0xfaeb;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f30, f31, f29, dyn, 32, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 != rd, rs1==f28, rs2==f28, rd==f29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f28; op2:f28; dest:f29; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f29, f28, f28, dyn, 64, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rd != rs2, rs1==f27, rs2==f30, rd==f27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f27; op2:f30; dest:f27; op1val:0x704c; op2val:0xfaeb;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f27, f27, f30, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f26; op2:f26; dest:f26; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f26, f26, f26, dyn, 128, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_5:
// rs1==f29, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f29; op2:f27; dest:f28; op1val:0x7a1b; op2val:0x7bff;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f28, f29, f27, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_6:
// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f24; op2:f23; dest:f25; op1val:0x7a1b; op2val:0x7bff;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f25, f24, f23, dyn, 32, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_7:
// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f23; op2:f25; dest:f24; op1val:0x7a1b; op2val:0x7bff;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f24, f23, f25, dyn, 64, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_8:
// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f25; op2:f24; dest:f23; op1val:0x7a1b; op2val:0x7bff;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f23, f25, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_9:
// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f21; op2:f20; dest:f22; op1val:0x7a1b; op2val:0x7bff;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f22, f21, f20, dyn, 128, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_10:
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f20; op2:f22; dest:f21; op1val:0x77ec; op2val:0xf808;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_11:
// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f22; op2:f21; dest:f20; op1val:0x77ec; op2val:0xf808;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f20, f22, f21, dyn, 32, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f18; op2:f17; dest:f19; op1val:0x77ec; op2val:0xf808;
   valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f19, f18, f17, dyn, 64, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f17; op2:f19; dest:f18; op1val:0x77ec; op2val:0xf808;
   valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f18, f17, f19, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x008 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f19; op2:f18; dest:f17; op1val:0x77ec; op2val:0xf808;
   valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f17, f19, f18, dyn, 128, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f15; op2:f14; dest:f16; op1val:0x7935; op2val:0x7bff;
   valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f16, f15, f14, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f14; op2:f16; dest:f15; op1val:0x7935; op2val:0x7bff;
   valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f15, f14, f16, dyn, 32, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f16; op2:f15; dest:f14; op1val:0x7935; op2val:0x7bff;
   valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f14, f16, f15, dyn, 64, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f12; op2:f11; dest:f13; op1val:0x7935; op2val:0x7bff;
   valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f13, f12, f11, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f11; op2:f13; dest:f12; op1val:0x7935; op2val:0x7bff;
   valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f12, f11, f13, dyn, 128, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f13; op2:f12; dest:f11; op1val:0x6e01; op2val:0xfb3e;
   valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f11, f13, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f9; op2:f8; dest:f10; op1val:0x6e01; op2val:0xfb3e;
   valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f10, f9, f8, dyn, 32, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f8; op2:f10; dest:f9; op1val:0x6e01; op2val:0xfb3e;
   valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f9, f8, f10, dyn, 64, 0, x3, 44*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f10; op2:f9; dest:f8; op1val:0x6e01; op2val:0xfb3e;
   valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f8, f10, f9, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f5, rd==f7,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x33e and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f6; op2:f5; dest:f7; op1val:0x6e01; op2val:0xfb3e;
   valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f7, f6, f5, dyn, 128, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f5; op2:f7; dest:f6; op1val:0x7aae; op2val:0x7bff;
   valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f6, f5, f7, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f7, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f7; op2:f6; dest:f5; op1val:0x7aae; op2val:0x7bff;
   valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f5, f7, f6, dyn, 32, 0, x3, 52*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f3; op2:f2; dest:f4; op1val:0x7aae; op2val:0x7bff;
   valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f4, f3, f2, dyn, 64, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f2; op2:f4; dest:f3; op1val:0x7aae; op2val:0x7bff;
   valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f4, rs2==f3, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f4; op2:f3; dest:f2; op1val:0x7aae; op2val:0x7bff;
   valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f2, f4, f3, dyn, 128, 0, x3, 58*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f1; op2:f30; dest:f31; op1val:0x7a18; op2val:0xf39a;
   valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f1, f30, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f0; op2:f30; dest:f31; op1val:0x7a18; op2val:0xf39a;
   valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f0, f30, dyn, 32, 0, x3, 62*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f1; dest:f31; op1val:0x7a18; op2val:0xf39a;
   valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f1, dyn, 64, 0, x3, 64*FLEN/8, x4, x1, x2)

inst_33:
// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f0; dest:f31; op1val:0x7a18; op2val:0xf39a;
   valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f0, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_34:
// rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x39a and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f31; op2:f30; dest:f1; op1val:0x7a18; op2val:0xf39a;
   valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f1, f31, f30, dyn, 128, 0, x3, 68*FLEN/8, x4, x1, x2)

inst_35:
// rd==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f31; op2:f30; dest:f0; op1val:0x771f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f0, f31, f30, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x771f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x771f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 74*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x771f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x771f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7351; op2val:0xfa2a;
   valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7351; op2val:0xfa2a;
   valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 82*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7351; op2val:0xfa2a;
   valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7351; op2val:0xfa2a;
   valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x22a and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7351; op2val:0xfa2a;
   valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 88*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b35; op2val:0x7bff;
   valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b35; op2val:0x7bff;
   valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 92*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b35; op2val:0x7bff;
   valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 94*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b35; op2val:0x7bff;
   valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b35; op2val:0x7bff;
   valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 98*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6683; op2val:0xfbca;
   valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6683; op2val:0xfbca;
   valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6683; op2val:0xfbca;
   valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 104*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6683; op2val:0xfbca;
   valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ca and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6683; op2val:0xfbca;
   valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b82; op2val:0x7bff;
   valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b82; op2val:0x7bff;
   valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 112*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b82; op2val:0x7bff;
   valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b82; op2val:0x7bff;
   valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 116*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b82; op2val:0x7bff;
   valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 118*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ed; op2val:0xfa43;
   valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ed; op2val:0xfa43;
   valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 122*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ed; op2val:0xfa43;
   valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 124*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ed; op2val:0xfa43;
   valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x1e and fm2 == 0x243 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ed; op2val:0xfa43;
   valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 128*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x676f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x676f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x676f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 134*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x676f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 136*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x676f; op2val:0x7bff;
   valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7700; op2val:0x7500;
   valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7700; op2val:0x7500;
   valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 142*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7700; op2val:0x7500;
   valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7700; op2val:0x7500;
   valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 146*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x100 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7700; op2val:0x7500;
   valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 148*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7374; op2val:0x75ba;
   valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7374; op2val:0x75ba;
   valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 152*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7374; op2val:0x75ba;
   valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 154*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7374; op2val:0x75ba;
   valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1ba and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7374; op2val:0x75ba;
   valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 158*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ff; op2val:0xe7fc;
   valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ff; op2val:0xe7fc;
   valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ff; op2val:0xe7fc;
   valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 164*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ff; op2val:0xe7fc;
   valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 166*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x19 and fm2 == 0x3fc and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x72ff; op2val:0xe7fc;
   valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74a2; op2val:0x7850;
   valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74a2; op2val:0x7850;
   valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 172*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74a2; op2val:0x7850;
   valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74a2; op2val:0x7850;
   valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 176*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x050 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74a2; op2val:0x7850;
   valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 178*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ab2; op2val:0x7566;
   valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ab2; op2val:0x7566;
   valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 182*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ab2; op2val:0x7566;
   valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 184*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ab2; op2val:0x7566;
   valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x166 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ab2; op2val:0x7566;
   valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 188*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7922; op2val:0x7bff;
   valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 190*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7922; op2val:0x7bff;
   valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7922; op2val:0x7bff;
   valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 194*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7922; op2val:0x7bff;
   valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 196*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7922; op2val:0x7bff;
   valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bef; op2val:0xdfa1;
   valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 200*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bef; op2val:0xdfa1;
   valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 202*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bef; op2val:0xdfa1;
   valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bef; op2val:0xdfa1;
   valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 206*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 1 and fe2 == 0x17 and fm2 == 0x3a1 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bef; op2val:0xdfa1;
   valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 208*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6fbb; op2val:0x7bff;
   valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6fbb; op2val:0x7bff;
   valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 212*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6fbb; op2val:0x7bff;
   valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 214*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6fbb; op2val:0x7bff;
   valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x6fbb; op2val:0x7bff;
   valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 218*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x79c4; op2val:0xfbff;
   valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 220*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x79c4; op2val:0xfbff;
   valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x79c4; op2val:0xfbff;
   valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 224*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x79c4; op2val:0xfbff;
   valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 226*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x79c4; op2val:0xfbff;
   valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b7c; op2val:0x7bff;
   valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 230*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b7c; op2val:0x7bff;
   valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 232*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b7c; op2val:0x7bff;
   valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b7c; op2val:0x7bff;
   valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 236*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b7c; op2val:0x7bff;
   valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 238*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7aa3; op2val:0xfbff;
   valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7aa3; op2val:0xfbff;
   valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 242*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7aa3; op2val:0xfbff;
   valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 244*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7aa3; op2val:0xfbff;
   valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7aa3; op2val:0xfbff;
   valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 248*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74da; op2val:0x7bff;
   valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 250*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74da; op2val:0x7bff;
   valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74da; op2val:0x7bff;
   valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 254*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74da; op2val:0x7bff;
   valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 256*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x74da; op2val:0x7bff;
   valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0e; op2val:0xfbff;
   valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 260*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0e; op2val:0xfbff;
   valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 262*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0e; op2val:0xfbff;
   valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0e; op2val:0xfbff;
   valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 266*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0e; op2val:0xfbff;
   valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 268*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
   valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
   valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 32, 0, x3, 272*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
   valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 274*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
   valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 96, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
   valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 278*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x704c; op2val:0xfaeb;
   valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 64, 0, x3, 280*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2eb and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fsub.h ; op1:f30; op2:f29; dest:f31; op1val:0x704c; op2val:0xfaeb;
   valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2*/
TEST_FPRR_OP(fsub.h, f31, f30, f29, dyn, 128, 0, x3, 282*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(64235,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(64235,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(64235,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31259,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31259,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31259,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31259,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31259,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30700,16,FLEN)
NAN_BOXED(63496,16,FLEN)
NAN_BOXED(30700,16,FLEN)
NAN_BOXED(63496,16,FLEN)
NAN_BOXED(30700,16,FLEN)
NAN_BOXED(63496,16,FLEN)
NAN_BOXED(30700,16,FLEN)
NAN_BOXED(63496,16,FLEN)
NAN_BOXED(30700,16,FLEN)
NAN_BOXED(63496,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(64318,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(64318,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(64318,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(64318,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(64318,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(62362,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(62362,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(62362,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(62362,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(62362,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(64042,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(64042,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(64042,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(64042,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(64042,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(64458,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(64458,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(64458,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(64458,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(64458,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(64067,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(64067,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(64067,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(64067,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(64067,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(29952,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(29952,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(29952,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(29952,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(29952,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(30138,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(30138,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(30138,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(30138,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(30138,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(59388,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(59388,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(59388,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(59388,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(59388,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(30800,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(30800,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(30800,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(30800,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(30800,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(30054,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(30054,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(30054,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(30054,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(30054,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(57249,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(57249,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(57249,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(57249,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(57249,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(64235,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(64235,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
