
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Feb  5 07:30:48 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fnmadd_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fnmadd_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x30, rs2==x31, rs3==x29, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x31; op3:x29; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x31, x29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x29, rs2==x29, rs3==x31, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x29; op2:x29; op3:x31; dest:x30; op1val:0x0; op2val:0x0;
op3val:0x80000000; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x30, x29, x29, x31, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 == rd != rs3, rs1==x28, rs2==x28, rs3==x30, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x28; op2:x28; op3:x30; dest:x28; op1val:0x0; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x28, x28, x28, x30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rd == rs3 != rs2, rs1==x27, rs2==x30, rs3==x27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x27; op2:x30; op3:x27; dest:x27; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x27, x27, x30, x27, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x26, rs2==x27, rs3==x28, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x26; op2:x27; op3:x28; dest:x26; op1val:0x0; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x26, x26, x27, x28, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 == rs2 == rs3 != rd, rs1==x25, rs2==x25, rs3==x25, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x25; op2:x25; op3:x25; dest:x29; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x29, x25, x25, x25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rd == rs2 == rs3 != rs1, rs1==x31, rs2==x24, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x31; op2:x24; op3:x24; dest:x24; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x24, x31, x24, x24, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x24, rs2==x26, rs3==x26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x24; op2:x26; op3:x26; dest:x25; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x25, x24, x26, x26, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x22, rs2==x21, rs3==x20, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x22; op2:x21; op3:x20; dest:x23; op1val:0x0; op2val:0x0;
op3val:0x800000; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x23, x22, x21, x20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 == rs3 == rd, rs1==x19, rs2==x19, rs3==x19, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x19; op2:x19; op3:x19; dest:x19; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x19, x19, x19, x19, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x23, rs2==x20, rs3==x22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x23; op2:x20; op3:x22; dest:x22; op1val:0x0; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x22, x23, x20, x22, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x18, rs2==x23, rs3==x18, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x18; op2:x23; op3:x18; dest:x21; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x21, x18, x23, x18, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==x21, rs2==x22, rs3==x23, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x21; op2:x22; op3:x23; dest:x20; op1val:0x0; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x20, x21, x22, x23, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==x20, rs2==x17, rs3==x21, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x20; op2:x17; op3:x21; dest:x18; op1val:0x0; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x18, x20, x17, x21, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==x16, rs2==x18, rs3==x15, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x16; op2:x18; op3:x15; dest:x17; op1val:0x0; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x17, x16, x18, x15, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==x17, rs2==x15, rs3==x14, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x17; op2:x15; op3:x14; dest:x16; op1val:0x0; op2val:0x0;
op3val:0xff800000; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x16, x17, x15, x14, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==x14, rs2==x16, rs3==x17, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x14; op2:x16; op3:x17; dest:x15; op1val:0x0; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x15, x14, x16, x17, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==x15, rs2==x13, rs3==x16, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x15; op2:x13; op3:x16; dest:x14; op1val:0x0; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x14, x15, x13, x16, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==x12, rs2==x14, rs3==x11, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x12; op2:x14; op3:x11; dest:x13; op1val:0x0; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x13, x12, x14, x11, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==x13, rs2==x11, rs3==x10, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x13; op2:x11; op3:x10; dest:x12; op1val:0x0; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x12, x13, x11, x10, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==x10, rs2==x12, rs3==x13, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x10; op2:x12; op3:x13; dest:x11; op1val:0x0; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x11, x10, x12, x13, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x12,test_dataset_1)

inst_21:
// rs1==x11, rs2==x9, rs3==x12, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x11; op2:x9; op3:x12; dest:x10; op1val:0x0; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x10, x11, x9, x12, dyn, 0, 0, x12, 0*FLEN/8, x13, x1, x2)

inst_22:
// rs1==x8, rs2==x10, rs3==x7, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x8; op2:x10; op3:x7; dest:x9; op1val:0x0; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x9, x8, x10, x7, dyn, 0, 0, x12, 3*FLEN/8, x13, x1, x2)

inst_23:
// rs1==x9, rs2==x7, rs3==x6, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x9; op2:x7; op3:x6; dest:x8; op1val:0x0; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x8, x9, x7, x6, dyn, 0, 0, x12, 6*FLEN/8, x13, x1, x10)
RVTEST_SIGBASE(x9,signature_x9_0)

inst_24:
// rs1==x6, rs2==x8, rs3==x9, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x6; op2:x8; op3:x9; dest:x7; op1val:0x0; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:9*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x7, x6, x8, x9, dyn, 0, 0, x12, 9*FLEN/8, x13, x9, x10)

inst_25:
// rs1==x7, rs2==x5, rs3==x8, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x7; op2:x5; op3:x8; dest:x6; op1val:0x0; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x6, x7, x5, x8, dyn, 0, 0, x12, 12*FLEN/8, x13, x9, x10)

inst_26:
// rs1==x4, rs2==x6, rs3==x3, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x4; op2:x6; op3:x3; dest:x5; op1val:0x0; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:15*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x5, x4, x6, x3, dyn, 0, 0, x12, 15*FLEN/8, x13, x9, x10)

inst_27:
// rs1==x5, rs2==x3, rs3==x2, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x5; op2:x3; op3:x2; dest:x4; op1val:0x0; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x4, x5, x3, x2, dyn, 0, 0, x12, 18*FLEN/8, x13, x9, x10)

inst_28:
// rs1==x2, rs2==x4, rs3==x5, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x2; op2:x4; op3:x5; dest:x3; op1val:0x0; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:21*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x3, x2, x4, x5, dyn, 0, 0, x12, 21*FLEN/8, x13, x9, x10)

inst_29:
// rs1==x3, rs2==x1, rs3==x4, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x3; op2:x1; op3:x4; dest:x2; op1val:0x0; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x2, x3, x1, x4, dyn, 0, 0, x12, 24*FLEN/8, x13, x9, x10)

inst_30:
// rs1==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x1; op2:x30; op3:x29; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x1, x30, x29, dyn, 0, 0, x12, 27*FLEN/8, x13, x9, x10)

inst_31:
// rs1==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x0; op2:x30; op3:x29; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x0, x30, x29, dyn, 0, 0, x12, 30*FLEN/8, x13, x9, x10)

inst_32:
// rs2==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x2; op3:x29; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:33*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x2, x29, dyn, 0, 0, x12, 33*FLEN/8, x13, x9, x10)

inst_33:
// rs2==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x0; op3:x29; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:36*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x0, x29, dyn, 0, 0, x12, 36*FLEN/8, x13, x9, x10)

inst_34:
// rs3==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x1; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:39*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x1, dyn, 0, 0, x12, 39*FLEN/8, x13, x9, x10)

inst_35:
// rs3==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x0; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:42*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x0, dyn, 0, 0, x12, 42*FLEN/8, x13, x9, x10)

inst_36:
// rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x31; op2:x30; op3:x29; dest:x1; op1val:0x0; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:45*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x1, x31, x30, x29, dyn, 0, 0, x12, 45*FLEN/8, x13, x9, x10)

inst_37:
// rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x31; op2:x30; op3:x29; dest:x0; op1val:0x0; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:48*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x0, x31, x30, x29, dyn, 0, 0, x12, 48*FLEN/8, x13, x9, x10)

inst_38:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:51*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 51*FLEN/8, x13, x9, x10)

inst_39:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:54*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 54*FLEN/8, x13, x9, x10)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:57*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 57*FLEN/8, x13, x9, x10)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:60*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 60*FLEN/8, x13, x9, x10)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:63*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 63*FLEN/8, x13, x9, x10)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:66*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 66*FLEN/8, x13, x9, x10)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:69*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 69*FLEN/8, x13, x9, x10)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:72*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 72*FLEN/8, x13, x9, x10)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:75*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 75*FLEN/8, x13, x9, x10)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:78*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 78*FLEN/8, x13, x9, x10)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:81*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 81*FLEN/8, x13, x9, x10)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:84*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 84*FLEN/8, x13, x9, x10)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:87*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 87*FLEN/8, x13, x9, x10)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:90*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 90*FLEN/8, x13, x9, x10)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:93*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 93*FLEN/8, x13, x9, x10)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:96*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96*FLEN/8, x13, x9, x10)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:99*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 99*FLEN/8, x13, x9, x10)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 102*FLEN/8, x13, x9, x10)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 105*FLEN/8, x13, x9, x10)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 108*FLEN/8, x13, x9, x10)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 111*FLEN/8, x13, x9, x10)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 114*FLEN/8, x13, x9, x10)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 117*FLEN/8, x13, x9, x10)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 120*FLEN/8, x13, x9, x10)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 123*FLEN/8, x13, x9, x10)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 126*FLEN/8, x13, x9, x10)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 129*FLEN/8, x13, x9, x10)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 132*FLEN/8, x13, x9, x10)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 135*FLEN/8, x13, x9, x10)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 138*FLEN/8, x13, x9, x10)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 141*FLEN/8, x13, x9, x10)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 144*FLEN/8, x13, x9, x10)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 147*FLEN/8, x13, x9, x10)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 150*FLEN/8, x13, x9, x10)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 153*FLEN/8, x13, x9, x10)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 156*FLEN/8, x13, x9, x10)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 159*FLEN/8, x13, x9, x10)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 162*FLEN/8, x13, x9, x10)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 165*FLEN/8, x13, x9, x10)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 168*FLEN/8, x13, x9, x10)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 171*FLEN/8, x13, x9, x10)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 174*FLEN/8, x13, x9, x10)

inst_80:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 177*FLEN/8, x13, x9, x10)

inst_81:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 180*FLEN/8, x13, x9, x10)

inst_82:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 183*FLEN/8, x13, x9, x10)

inst_83:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 186*FLEN/8, x13, x9, x10)

inst_84:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 189*FLEN/8, x13, x9, x10)

inst_85:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 192*FLEN/8, x13, x9, x10)

inst_86:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 195*FLEN/8, x13, x9, x10)

inst_87:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 198*FLEN/8, x13, x9, x10)

inst_88:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 201*FLEN/8, x13, x9, x10)

inst_89:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 204*FLEN/8, x13, x9, x10)

inst_90:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 207*FLEN/8, x13, x9, x10)

inst_91:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 210*FLEN/8, x13, x9, x10)

inst_92:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 213*FLEN/8, x13, x9, x10)

inst_93:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 216*FLEN/8, x13, x9, x10)

inst_94:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 219*FLEN/8, x13, x9, x10)

inst_95:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 222*FLEN/8, x13, x9, x10)

inst_96:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 225*FLEN/8, x13, x9, x10)

inst_97:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 228*FLEN/8, x13, x9, x10)

inst_98:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 231*FLEN/8, x13, x9, x10)

inst_99:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 234*FLEN/8, x13, x9, x10)

inst_100:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 237*FLEN/8, x13, x9, x10)

inst_101:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 240*FLEN/8, x13, x9, x10)

inst_102:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 243*FLEN/8, x13, x9, x10)

inst_103:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 246*FLEN/8, x13, x9, x10)

inst_104:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 249*FLEN/8, x13, x9, x10)

inst_105:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 252*FLEN/8, x13, x9, x10)

inst_106:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 255*FLEN/8, x13, x9, x10)

inst_107:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 258*FLEN/8, x13, x9, x10)

inst_108:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 261*FLEN/8, x13, x9, x10)

inst_109:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 264*FLEN/8, x13, x9, x10)

inst_110:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 267*FLEN/8, x13, x9, x10)

inst_111:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 270*FLEN/8, x13, x9, x10)

inst_112:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 273*FLEN/8, x13, x9, x10)

inst_113:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 276*FLEN/8, x13, x9, x10)

inst_114:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 279*FLEN/8, x13, x9, x10)

inst_115:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 282*FLEN/8, x13, x9, x10)

inst_116:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 285*FLEN/8, x13, x9, x10)

inst_117:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 288*FLEN/8, x13, x9, x10)

inst_118:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 291*FLEN/8, x13, x9, x10)

inst_119:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 294*FLEN/8, x13, x9, x10)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 297*FLEN/8, x13, x9, x10)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 300*FLEN/8, x13, x9, x10)

inst_122:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 303*FLEN/8, x13, x9, x10)

inst_123:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 306*FLEN/8, x13, x9, x10)

inst_124:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 309*FLEN/8, x13, x9, x10)

inst_125:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 312*FLEN/8, x13, x9, x10)

inst_126:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 315*FLEN/8, x13, x9, x10)

inst_127:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 318*FLEN/8, x13, x9, x10)

inst_128:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 321*FLEN/8, x13, x9, x10)

inst_129:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 324*FLEN/8, x13, x9, x10)

inst_130:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 327*FLEN/8, x13, x9, x10)

inst_131:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 330*FLEN/8, x13, x9, x10)

inst_132:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 333*FLEN/8, x13, x9, x10)

inst_133:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 336*FLEN/8, x13, x9, x10)

inst_134:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 339*FLEN/8, x13, x9, x10)

inst_135:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 342*FLEN/8, x13, x9, x10)

inst_136:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 345*FLEN/8, x13, x9, x10)

inst_137:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 348*FLEN/8, x13, x9, x10)

inst_138:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 351*FLEN/8, x13, x9, x10)

inst_139:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 354*FLEN/8, x13, x9, x10)

inst_140:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 357*FLEN/8, x13, x9, x10)

inst_141:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 360*FLEN/8, x13, x9, x10)

inst_142:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 363*FLEN/8, x13, x9, x10)

inst_143:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 366*FLEN/8, x13, x9, x10)

inst_144:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 369*FLEN/8, x13, x9, x10)

inst_145:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 372*FLEN/8, x13, x9, x10)

inst_146:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 375*FLEN/8, x13, x9, x10)

inst_147:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 378*FLEN/8, x13, x9, x10)

inst_148:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 381*FLEN/8, x13, x9, x10)

inst_149:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 384*FLEN/8, x13, x9, x10)

inst_150:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 387*FLEN/8, x13, x9, x10)

inst_151:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 390*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_1)

inst_152:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 393*FLEN/8, x13, x9, x10)

inst_153:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 396*FLEN/8, x13, x9, x10)

inst_154:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 399*FLEN/8, x13, x9, x10)

inst_155:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 402*FLEN/8, x13, x9, x10)

inst_156:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 405*FLEN/8, x13, x9, x10)

inst_157:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 408*FLEN/8, x13, x9, x10)

inst_158:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 411*FLEN/8, x13, x9, x10)

inst_159:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 414*FLEN/8, x13, x9, x10)

inst_160:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 417*FLEN/8, x13, x9, x10)

inst_161:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 420*FLEN/8, x13, x9, x10)

inst_162:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 423*FLEN/8, x13, x9, x10)

inst_163:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 426*FLEN/8, x13, x9, x10)

inst_164:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 429*FLEN/8, x13, x9, x10)

inst_165:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 432*FLEN/8, x13, x9, x10)

inst_166:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 435*FLEN/8, x13, x9, x10)

inst_167:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 438*FLEN/8, x13, x9, x10)

inst_168:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 441*FLEN/8, x13, x9, x10)

inst_169:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 444*FLEN/8, x13, x9, x10)

inst_170:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 447*FLEN/8, x13, x9, x10)

inst_171:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 450*FLEN/8, x13, x9, x10)

inst_172:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 453*FLEN/8, x13, x9, x10)

inst_173:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 456*FLEN/8, x13, x9, x10)

inst_174:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 459*FLEN/8, x13, x9, x10)

inst_175:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 462*FLEN/8, x13, x9, x10)

inst_176:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 465*FLEN/8, x13, x9, x10)

inst_177:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 468*FLEN/8, x13, x9, x10)

inst_178:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 471*FLEN/8, x13, x9, x10)

inst_179:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 474*FLEN/8, x13, x9, x10)

inst_180:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 477*FLEN/8, x13, x9, x10)

inst_181:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 480*FLEN/8, x13, x9, x10)

inst_182:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 483*FLEN/8, x13, x9, x10)

inst_183:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 486*FLEN/8, x13, x9, x10)

inst_184:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 489*FLEN/8, x13, x9, x10)

inst_185:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 492*FLEN/8, x13, x9, x10)

inst_186:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 495*FLEN/8, x13, x9, x10)

inst_187:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 498*FLEN/8, x13, x9, x10)

inst_188:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 501*FLEN/8, x13, x9, x10)

inst_189:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 504*FLEN/8, x13, x9, x10)

inst_190:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 507*FLEN/8, x13, x9, x10)

inst_191:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 510*FLEN/8, x13, x9, x10)

inst_192:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 513*FLEN/8, x13, x9, x10)

inst_193:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 516*FLEN/8, x13, x9, x10)

inst_194:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 519*FLEN/8, x13, x9, x10)

inst_195:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 522*FLEN/8, x13, x9, x10)

inst_196:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 525*FLEN/8, x13, x9, x10)

inst_197:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 528*FLEN/8, x13, x9, x10)

inst_198:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 531*FLEN/8, x13, x9, x10)

inst_199:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 534*FLEN/8, x13, x9, x10)

inst_200:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 537*FLEN/8, x13, x9, x10)

inst_201:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 540*FLEN/8, x13, x9, x10)

inst_202:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 543*FLEN/8, x13, x9, x10)

inst_203:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 546*FLEN/8, x13, x9, x10)

inst_204:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 549*FLEN/8, x13, x9, x10)

inst_205:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 552*FLEN/8, x13, x9, x10)

inst_206:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 555*FLEN/8, x13, x9, x10)

inst_207:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 558*FLEN/8, x13, x9, x10)

inst_208:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 561*FLEN/8, x13, x9, x10)

inst_209:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 564*FLEN/8, x13, x9, x10)

inst_210:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 567*FLEN/8, x13, x9, x10)

inst_211:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 570*FLEN/8, x13, x9, x10)

inst_212:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 573*FLEN/8, x13, x9, x10)

inst_213:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 576*FLEN/8, x13, x9, x10)

inst_214:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 579*FLEN/8, x13, x9, x10)

inst_215:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 582*FLEN/8, x13, x9, x10)

inst_216:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 585*FLEN/8, x13, x9, x10)

inst_217:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 588*FLEN/8, x13, x9, x10)

inst_218:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 591*FLEN/8, x13, x9, x10)

inst_219:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 594*FLEN/8, x13, x9, x10)

inst_220:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 597*FLEN/8, x13, x9, x10)

inst_221:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 600*FLEN/8, x13, x9, x10)

inst_222:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 603*FLEN/8, x13, x9, x10)

inst_223:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 606*FLEN/8, x13, x9, x10)

inst_224:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 609*FLEN/8, x13, x9, x10)

inst_225:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 612*FLEN/8, x13, x9, x10)

inst_226:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 615*FLEN/8, x13, x9, x10)

inst_227:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 618*FLEN/8, x13, x9, x10)

inst_228:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 621*FLEN/8, x13, x9, x10)

inst_229:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 624*FLEN/8, x13, x9, x10)

inst_230:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 627*FLEN/8, x13, x9, x10)

inst_231:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 630*FLEN/8, x13, x9, x10)

inst_232:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 633*FLEN/8, x13, x9, x10)

inst_233:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 636*FLEN/8, x13, x9, x10)

inst_234:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 639*FLEN/8, x13, x9, x10)

inst_235:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 642*FLEN/8, x13, x9, x10)

inst_236:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 645*FLEN/8, x13, x9, x10)

inst_237:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 648*FLEN/8, x13, x9, x10)

inst_238:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 651*FLEN/8, x13, x9, x10)

inst_239:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 654*FLEN/8, x13, x9, x10)

inst_240:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 657*FLEN/8, x13, x9, x10)

inst_241:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 660*FLEN/8, x13, x9, x10)

inst_242:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 663*FLEN/8, x13, x9, x10)

inst_243:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 666*FLEN/8, x13, x9, x10)

inst_244:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 669*FLEN/8, x13, x9, x10)

inst_245:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 672*FLEN/8, x13, x9, x10)

inst_246:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 675*FLEN/8, x13, x9, x10)

inst_247:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 678*FLEN/8, x13, x9, x10)

inst_248:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 681*FLEN/8, x13, x9, x10)

inst_249:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 684*FLEN/8, x13, x9, x10)

inst_250:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 687*FLEN/8, x13, x9, x10)

inst_251:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 690*FLEN/8, x13, x9, x10)

inst_252:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 693*FLEN/8, x13, x9, x10)

inst_253:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 696*FLEN/8, x13, x9, x10)

inst_254:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 699*FLEN/8, x13, x9, x10)

inst_255:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 702*FLEN/8, x13, x9, x10)

inst_256:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 705*FLEN/8, x13, x9, x10)

inst_257:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 708*FLEN/8, x13, x9, x10)

inst_258:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 711*FLEN/8, x13, x9, x10)

inst_259:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 714*FLEN/8, x13, x9, x10)

inst_260:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 717*FLEN/8, x13, x9, x10)

inst_261:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 720*FLEN/8, x13, x9, x10)

inst_262:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 723*FLEN/8, x13, x9, x10)

inst_263:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 726*FLEN/8, x13, x9, x10)

inst_264:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 729*FLEN/8, x13, x9, x10)

inst_265:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 732*FLEN/8, x13, x9, x10)

inst_266:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 735*FLEN/8, x13, x9, x10)

inst_267:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 738*FLEN/8, x13, x9, x10)

inst_268:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 741*FLEN/8, x13, x9, x10)

inst_269:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 744*FLEN/8, x13, x9, x10)

inst_270:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 747*FLEN/8, x13, x9, x10)

inst_271:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 750*FLEN/8, x13, x9, x10)

inst_272:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 753*FLEN/8, x13, x9, x10)

inst_273:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 756*FLEN/8, x13, x9, x10)

inst_274:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 759*FLEN/8, x13, x9, x10)

inst_275:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 762*FLEN/8, x13, x9, x10)

inst_276:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 765*FLEN/8, x13, x9, x10)

inst_277:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 768*FLEN/8, x13, x9, x10)

inst_278:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 771*FLEN/8, x13, x9, x10)

inst_279:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 774*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_2)

inst_280:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 777*FLEN/8, x13, x9, x10)

inst_281:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 780*FLEN/8, x13, x9, x10)

inst_282:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 783*FLEN/8, x13, x9, x10)

inst_283:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 786*FLEN/8, x13, x9, x10)

inst_284:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 789*FLEN/8, x13, x9, x10)

inst_285:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 792*FLEN/8, x13, x9, x10)

inst_286:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 795*FLEN/8, x13, x9, x10)

inst_287:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 798*FLEN/8, x13, x9, x10)

inst_288:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 801*FLEN/8, x13, x9, x10)

inst_289:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 804*FLEN/8, x13, x9, x10)

inst_290:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 807*FLEN/8, x13, x9, x10)

inst_291:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 810*FLEN/8, x13, x9, x10)

inst_292:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 813*FLEN/8, x13, x9, x10)

inst_293:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 816*FLEN/8, x13, x9, x10)

inst_294:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 819*FLEN/8, x13, x9, x10)

inst_295:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 822*FLEN/8, x13, x9, x10)

inst_296:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 825*FLEN/8, x13, x9, x10)

inst_297:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 828*FLEN/8, x13, x9, x10)

inst_298:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 831*FLEN/8, x13, x9, x10)

inst_299:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 834*FLEN/8, x13, x9, x10)

inst_300:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 837*FLEN/8, x13, x9, x10)

inst_301:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 840*FLEN/8, x13, x9, x10)

inst_302:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 843*FLEN/8, x13, x9, x10)

inst_303:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 846*FLEN/8, x13, x9, x10)

inst_304:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 849*FLEN/8, x13, x9, x10)

inst_305:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 852*FLEN/8, x13, x9, x10)

inst_306:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 855*FLEN/8, x13, x9, x10)

inst_307:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 858*FLEN/8, x13, x9, x10)

inst_308:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 861*FLEN/8, x13, x9, x10)

inst_309:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 864*FLEN/8, x13, x9, x10)

inst_310:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 867*FLEN/8, x13, x9, x10)

inst_311:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 870*FLEN/8, x13, x9, x10)

inst_312:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 873*FLEN/8, x13, x9, x10)

inst_313:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 876*FLEN/8, x13, x9, x10)

inst_314:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 879*FLEN/8, x13, x9, x10)

inst_315:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 882*FLEN/8, x13, x9, x10)

inst_316:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 885*FLEN/8, x13, x9, x10)

inst_317:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 888*FLEN/8, x13, x9, x10)

inst_318:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 891*FLEN/8, x13, x9, x10)

inst_319:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 894*FLEN/8, x13, x9, x10)

inst_320:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 897*FLEN/8, x13, x9, x10)

inst_321:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 900*FLEN/8, x13, x9, x10)

inst_322:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 903*FLEN/8, x13, x9, x10)

inst_323:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 906*FLEN/8, x13, x9, x10)

inst_324:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 909*FLEN/8, x13, x9, x10)

inst_325:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 912*FLEN/8, x13, x9, x10)

inst_326:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 915*FLEN/8, x13, x9, x10)

inst_327:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 918*FLEN/8, x13, x9, x10)

inst_328:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 921*FLEN/8, x13, x9, x10)

inst_329:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 924*FLEN/8, x13, x9, x10)

inst_330:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 927*FLEN/8, x13, x9, x10)

inst_331:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 930*FLEN/8, x13, x9, x10)

inst_332:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 933*FLEN/8, x13, x9, x10)

inst_333:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 936*FLEN/8, x13, x9, x10)

inst_334:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 939*FLEN/8, x13, x9, x10)

inst_335:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 942*FLEN/8, x13, x9, x10)

inst_336:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 945*FLEN/8, x13, x9, x10)

inst_337:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 948*FLEN/8, x13, x9, x10)

inst_338:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 951*FLEN/8, x13, x9, x10)

inst_339:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 954*FLEN/8, x13, x9, x10)

inst_340:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 957*FLEN/8, x13, x9, x10)

inst_341:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 960*FLEN/8, x13, x9, x10)

inst_342:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 963*FLEN/8, x13, x9, x10)

inst_343:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 966*FLEN/8, x13, x9, x10)

inst_344:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 969*FLEN/8, x13, x9, x10)

inst_345:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 972*FLEN/8, x13, x9, x10)

inst_346:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 975*FLEN/8, x13, x9, x10)

inst_347:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 978*FLEN/8, x13, x9, x10)

inst_348:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 981*FLEN/8, x13, x9, x10)

inst_349:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 984*FLEN/8, x13, x9, x10)

inst_350:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 987*FLEN/8, x13, x9, x10)

inst_351:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 990*FLEN/8, x13, x9, x10)

inst_352:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 993*FLEN/8, x13, x9, x10)

inst_353:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 996*FLEN/8, x13, x9, x10)

inst_354:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 999*FLEN/8, x13, x9, x10)

inst_355:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1002*FLEN/8, x13, x9, x10)

inst_356:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1005*FLEN/8, x13, x9, x10)

inst_357:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1008*FLEN/8, x13, x9, x10)

inst_358:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1011*FLEN/8, x13, x9, x10)

inst_359:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1014*FLEN/8, x13, x9, x10)

inst_360:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:1017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1017*FLEN/8, x13, x9, x10)

inst_361:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:1020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1020*FLEN/8, x13, x9, x10)

inst_362:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:1023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1023*FLEN/8, x13, x9, x10)

inst_363:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:1026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1026*FLEN/8, x13, x9, x10)

inst_364:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:1029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1029*FLEN/8, x13, x9, x10)

inst_365:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1032*FLEN/8, x13, x9, x10)

inst_366:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1035*FLEN/8, x13, x9, x10)

inst_367:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1038*FLEN/8, x13, x9, x10)

inst_368:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:1041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1041*FLEN/8, x13, x9, x10)

inst_369:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:1044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1044*FLEN/8, x13, x9, x10)

inst_370:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:1047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1047*FLEN/8, x13, x9, x10)

inst_371:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:1050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1050*FLEN/8, x13, x9, x10)

inst_372:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1053*FLEN/8, x13, x9, x10)

inst_373:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1056*FLEN/8, x13, x9, x10)

inst_374:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1059*FLEN/8, x13, x9, x10)

inst_375:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:1062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1062*FLEN/8, x13, x9, x10)

inst_376:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1065*FLEN/8, x13, x9, x10)

inst_377:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1068*FLEN/8, x13, x9, x10)

inst_378:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1071*FLEN/8, x13, x9, x10)

inst_379:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1074*FLEN/8, x13, x9, x10)

inst_380:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1077*FLEN/8, x13, x9, x10)

inst_381:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1080*FLEN/8, x13, x9, x10)

inst_382:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1083*FLEN/8, x13, x9, x10)

inst_383:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1086*FLEN/8, x13, x9, x10)

inst_384:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:1089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1089*FLEN/8, x13, x9, x10)

inst_385:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:1092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1092*FLEN/8, x13, x9, x10)

inst_386:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:1095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1095*FLEN/8, x13, x9, x10)

inst_387:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:1098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1098*FLEN/8, x13, x9, x10)

inst_388:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:1101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1101*FLEN/8, x13, x9, x10)

inst_389:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1104*FLEN/8, x13, x9, x10)

inst_390:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1107*FLEN/8, x13, x9, x10)

inst_391:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1110*FLEN/8, x13, x9, x10)

inst_392:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:1113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1113*FLEN/8, x13, x9, x10)

inst_393:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:1116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1116*FLEN/8, x13, x9, x10)

inst_394:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:1119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1119*FLEN/8, x13, x9, x10)

inst_395:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:1122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1122*FLEN/8, x13, x9, x10)

inst_396:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1125*FLEN/8, x13, x9, x10)

inst_397:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1128*FLEN/8, x13, x9, x10)

inst_398:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1131*FLEN/8, x13, x9, x10)

inst_399:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:1134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1134*FLEN/8, x13, x9, x10)

inst_400:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1137*FLEN/8, x13, x9, x10)

inst_401:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1140*FLEN/8, x13, x9, x10)

inst_402:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1143*FLEN/8, x13, x9, x10)

inst_403:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1146*FLEN/8, x13, x9, x10)

inst_404:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1149*FLEN/8, x13, x9, x10)

inst_405:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1152*FLEN/8, x13, x9, x10)

inst_406:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1155*FLEN/8, x13, x9, x10)

inst_407:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1158*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_3)

inst_408:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:1161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1161*FLEN/8, x13, x9, x10)

inst_409:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:1164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1164*FLEN/8, x13, x9, x10)

inst_410:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:1167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1167*FLEN/8, x13, x9, x10)

inst_411:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:1170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1170*FLEN/8, x13, x9, x10)

inst_412:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:1173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1173*FLEN/8, x13, x9, x10)

inst_413:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1176*FLEN/8, x13, x9, x10)

inst_414:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1179*FLEN/8, x13, x9, x10)

inst_415:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1182*FLEN/8, x13, x9, x10)

inst_416:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:1185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1185*FLEN/8, x13, x9, x10)

inst_417:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:1188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1188*FLEN/8, x13, x9, x10)

inst_418:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:1191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1191*FLEN/8, x13, x9, x10)

inst_419:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:1194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1194*FLEN/8, x13, x9, x10)

inst_420:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1197*FLEN/8, x13, x9, x10)

inst_421:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1200*FLEN/8, x13, x9, x10)

inst_422:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1203*FLEN/8, x13, x9, x10)

inst_423:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:1206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1206*FLEN/8, x13, x9, x10)

inst_424:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1209*FLEN/8, x13, x9, x10)

inst_425:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1212*FLEN/8, x13, x9, x10)

inst_426:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1215*FLEN/8, x13, x9, x10)

inst_427:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1218*FLEN/8, x13, x9, x10)

inst_428:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1221*FLEN/8, x13, x9, x10)

inst_429:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1224*FLEN/8, x13, x9, x10)

inst_430:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1227*FLEN/8, x13, x9, x10)

inst_431:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1230*FLEN/8, x13, x9, x10)

inst_432:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:1233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1233*FLEN/8, x13, x9, x10)

inst_433:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:1236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1236*FLEN/8, x13, x9, x10)

inst_434:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:1239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1239*FLEN/8, x13, x9, x10)

inst_435:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:1242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1242*FLEN/8, x13, x9, x10)

inst_436:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:1245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1245*FLEN/8, x13, x9, x10)

inst_437:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1248*FLEN/8, x13, x9, x10)

inst_438:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1251*FLEN/8, x13, x9, x10)

inst_439:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1254*FLEN/8, x13, x9, x10)

inst_440:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:1257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1257*FLEN/8, x13, x9, x10)

inst_441:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:1260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1260*FLEN/8, x13, x9, x10)

inst_442:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:1263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1263*FLEN/8, x13, x9, x10)

inst_443:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:1266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1266*FLEN/8, x13, x9, x10)

inst_444:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1269*FLEN/8, x13, x9, x10)

inst_445:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1272*FLEN/8, x13, x9, x10)

inst_446:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1275*FLEN/8, x13, x9, x10)

inst_447:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:1278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1278*FLEN/8, x13, x9, x10)

inst_448:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1281*FLEN/8, x13, x9, x10)

inst_449:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1284*FLEN/8, x13, x9, x10)

inst_450:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1287*FLEN/8, x13, x9, x10)

inst_451:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1290*FLEN/8, x13, x9, x10)

inst_452:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1293*FLEN/8, x13, x9, x10)

inst_453:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1296*FLEN/8, x13, x9, x10)

inst_454:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1299*FLEN/8, x13, x9, x10)

inst_455:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1302*FLEN/8, x13, x9, x10)

inst_456:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:1305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1305*FLEN/8, x13, x9, x10)

inst_457:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:1308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1308*FLEN/8, x13, x9, x10)

inst_458:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:1311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1311*FLEN/8, x13, x9, x10)

inst_459:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:1314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1314*FLEN/8, x13, x9, x10)

inst_460:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:1317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1317*FLEN/8, x13, x9, x10)

inst_461:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1320*FLEN/8, x13, x9, x10)

inst_462:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1323*FLEN/8, x13, x9, x10)

inst_463:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1326*FLEN/8, x13, x9, x10)

inst_464:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:1329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1329*FLEN/8, x13, x9, x10)

inst_465:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:1332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1332*FLEN/8, x13, x9, x10)

inst_466:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:1335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1335*FLEN/8, x13, x9, x10)

inst_467:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:1338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1338*FLEN/8, x13, x9, x10)

inst_468:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1341*FLEN/8, x13, x9, x10)

inst_469:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1344*FLEN/8, x13, x9, x10)

inst_470:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1347*FLEN/8, x13, x9, x10)

inst_471:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:1350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1350*FLEN/8, x13, x9, x10)

inst_472:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1353*FLEN/8, x13, x9, x10)

inst_473:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1356*FLEN/8, x13, x9, x10)

inst_474:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1359*FLEN/8, x13, x9, x10)

inst_475:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1362*FLEN/8, x13, x9, x10)

inst_476:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1365*FLEN/8, x13, x9, x10)

inst_477:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1368*FLEN/8, x13, x9, x10)

inst_478:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1371*FLEN/8, x13, x9, x10)

inst_479:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1374*FLEN/8, x13, x9, x10)

inst_480:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:1377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1377*FLEN/8, x13, x9, x10)

inst_481:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:1380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1380*FLEN/8, x13, x9, x10)

inst_482:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:1383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1383*FLEN/8, x13, x9, x10)

inst_483:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:1386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1386*FLEN/8, x13, x9, x10)

inst_484:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:1389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1389*FLEN/8, x13, x9, x10)

inst_485:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1392*FLEN/8, x13, x9, x10)

inst_486:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1395*FLEN/8, x13, x9, x10)

inst_487:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1398*FLEN/8, x13, x9, x10)

inst_488:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:1401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1401*FLEN/8, x13, x9, x10)

inst_489:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:1404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1404*FLEN/8, x13, x9, x10)

inst_490:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:1407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1407*FLEN/8, x13, x9, x10)

inst_491:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:1410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1410*FLEN/8, x13, x9, x10)

inst_492:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1413*FLEN/8, x13, x9, x10)

inst_493:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1416*FLEN/8, x13, x9, x10)

inst_494:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1419*FLEN/8, x13, x9, x10)

inst_495:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:1422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1422*FLEN/8, x13, x9, x10)

inst_496:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1425*FLEN/8, x13, x9, x10)

inst_497:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1428*FLEN/8, x13, x9, x10)

inst_498:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1431*FLEN/8, x13, x9, x10)

inst_499:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1434*FLEN/8, x13, x9, x10)

inst_500:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1437*FLEN/8, x13, x9, x10)

inst_501:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1440*FLEN/8, x13, x9, x10)

inst_502:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1443*FLEN/8, x13, x9, x10)

inst_503:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1446*FLEN/8, x13, x9, x10)

inst_504:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:1449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1449*FLEN/8, x13, x9, x10)

inst_505:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:1452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1452*FLEN/8, x13, x9, x10)

inst_506:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:1455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1455*FLEN/8, x13, x9, x10)

inst_507:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:1458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1458*FLEN/8, x13, x9, x10)

inst_508:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:1461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1461*FLEN/8, x13, x9, x10)

inst_509:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1464*FLEN/8, x13, x9, x10)

inst_510:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1467*FLEN/8, x13, x9, x10)

inst_511:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1470*FLEN/8, x13, x9, x10)

inst_512:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:1473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1473*FLEN/8, x13, x9, x10)

inst_513:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:1476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1476*FLEN/8, x13, x9, x10)

inst_514:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:1479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1479*FLEN/8, x13, x9, x10)

inst_515:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:1482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1482*FLEN/8, x13, x9, x10)

inst_516:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1485*FLEN/8, x13, x9, x10)

inst_517:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1488*FLEN/8, x13, x9, x10)

inst_518:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1491*FLEN/8, x13, x9, x10)

inst_519:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:1494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1494*FLEN/8, x13, x9, x10)

inst_520:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1497*FLEN/8, x13, x9, x10)

inst_521:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1500*FLEN/8, x13, x9, x10)

inst_522:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1503*FLEN/8, x13, x9, x10)

inst_523:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1506*FLEN/8, x13, x9, x10)

inst_524:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1509*FLEN/8, x13, x9, x10)

inst_525:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1512*FLEN/8, x13, x9, x10)

inst_526:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1515*FLEN/8, x13, x9, x10)

inst_527:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1518*FLEN/8, x13, x9, x10)

inst_528:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:1521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1521*FLEN/8, x13, x9, x10)

inst_529:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:1524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1524*FLEN/8, x13, x9, x10)

inst_530:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:1527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1527*FLEN/8, x13, x9, x10)

inst_531:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:1530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1530*FLEN/8, x13, x9, x10)

inst_532:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:1533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1533*FLEN/8, x13, x9, x10)

inst_533:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1536*FLEN/8, x13, x9, x10)

inst_534:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1539*FLEN/8, x13, x9, x10)

inst_535:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1542*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_4)

inst_536:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:1545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1545*FLEN/8, x13, x9, x10)

inst_537:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:1548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1548*FLEN/8, x13, x9, x10)

inst_538:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:1551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1551*FLEN/8, x13, x9, x10)

inst_539:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:1554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1554*FLEN/8, x13, x9, x10)

inst_540:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1557*FLEN/8, x13, x9, x10)

inst_541:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1560*FLEN/8, x13, x9, x10)

inst_542:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1563*FLEN/8, x13, x9, x10)

inst_543:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:1566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1566*FLEN/8, x13, x9, x10)

inst_544:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1569*FLEN/8, x13, x9, x10)

inst_545:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1572*FLEN/8, x13, x9, x10)

inst_546:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1575*FLEN/8, x13, x9, x10)

inst_547:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1578*FLEN/8, x13, x9, x10)

inst_548:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1581*FLEN/8, x13, x9, x10)

inst_549:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1584*FLEN/8, x13, x9, x10)

inst_550:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1587*FLEN/8, x13, x9, x10)

inst_551:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1590*FLEN/8, x13, x9, x10)

inst_552:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:1593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1593*FLEN/8, x13, x9, x10)

inst_553:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:1596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1596*FLEN/8, x13, x9, x10)

inst_554:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:1599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1599*FLEN/8, x13, x9, x10)

inst_555:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:1602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1602*FLEN/8, x13, x9, x10)

inst_556:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:1605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1605*FLEN/8, x13, x9, x10)

inst_557:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1608*FLEN/8, x13, x9, x10)

inst_558:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1611*FLEN/8, x13, x9, x10)

inst_559:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1614*FLEN/8, x13, x9, x10)

inst_560:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:1617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1617*FLEN/8, x13, x9, x10)

inst_561:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:1620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1620*FLEN/8, x13, x9, x10)

inst_562:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:1623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1623*FLEN/8, x13, x9, x10)

inst_563:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:1626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1626*FLEN/8, x13, x9, x10)

inst_564:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1629*FLEN/8, x13, x9, x10)

inst_565:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1632*FLEN/8, x13, x9, x10)

inst_566:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1635*FLEN/8, x13, x9, x10)

inst_567:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:1638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1638*FLEN/8, x13, x9, x10)

inst_568:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1641*FLEN/8, x13, x9, x10)

inst_569:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1644*FLEN/8, x13, x9, x10)

inst_570:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1647*FLEN/8, x13, x9, x10)

inst_571:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1650*FLEN/8, x13, x9, x10)

inst_572:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1653*FLEN/8, x13, x9, x10)

inst_573:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1656*FLEN/8, x13, x9, x10)

inst_574:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1659*FLEN/8, x13, x9, x10)

inst_575:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1662*FLEN/8, x13, x9, x10)

inst_576:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:1665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1665*FLEN/8, x13, x9, x10)

inst_577:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:1668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1668*FLEN/8, x13, x9, x10)

inst_578:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:1671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1671*FLEN/8, x13, x9, x10)

inst_579:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:1674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1674*FLEN/8, x13, x9, x10)

inst_580:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:1677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1677*FLEN/8, x13, x9, x10)

inst_581:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1680*FLEN/8, x13, x9, x10)

inst_582:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1683*FLEN/8, x13, x9, x10)

inst_583:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1686*FLEN/8, x13, x9, x10)

inst_584:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:1689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1689*FLEN/8, x13, x9, x10)

inst_585:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:1692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1692*FLEN/8, x13, x9, x10)

inst_586:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:1695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1695*FLEN/8, x13, x9, x10)

inst_587:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:1698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1698*FLEN/8, x13, x9, x10)

inst_588:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1701*FLEN/8, x13, x9, x10)

inst_589:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1704*FLEN/8, x13, x9, x10)

inst_590:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1707*FLEN/8, x13, x9, x10)

inst_591:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:1710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1710*FLEN/8, x13, x9, x10)

inst_592:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1713*FLEN/8, x13, x9, x10)

inst_593:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1716*FLEN/8, x13, x9, x10)

inst_594:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1719*FLEN/8, x13, x9, x10)

inst_595:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1722*FLEN/8, x13, x9, x10)

inst_596:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1725*FLEN/8, x13, x9, x10)

inst_597:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1728*FLEN/8, x13, x9, x10)

inst_598:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1731*FLEN/8, x13, x9, x10)

inst_599:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1734*FLEN/8, x13, x9, x10)

inst_600:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:1737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1737*FLEN/8, x13, x9, x10)

inst_601:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:1740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1740*FLEN/8, x13, x9, x10)

inst_602:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:1743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1743*FLEN/8, x13, x9, x10)

inst_603:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:1746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1746*FLEN/8, x13, x9, x10)

inst_604:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:1749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1749*FLEN/8, x13, x9, x10)

inst_605:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1752*FLEN/8, x13, x9, x10)

inst_606:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1755*FLEN/8, x13, x9, x10)

inst_607:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1758*FLEN/8, x13, x9, x10)

inst_608:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:1761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1761*FLEN/8, x13, x9, x10)

inst_609:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:1764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1764*FLEN/8, x13, x9, x10)

inst_610:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:1767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1767*FLEN/8, x13, x9, x10)

inst_611:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:1770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1770*FLEN/8, x13, x9, x10)

inst_612:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1773*FLEN/8, x13, x9, x10)

inst_613:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1776*FLEN/8, x13, x9, x10)

inst_614:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1779*FLEN/8, x13, x9, x10)

inst_615:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:1782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1782*FLEN/8, x13, x9, x10)

inst_616:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1785*FLEN/8, x13, x9, x10)

inst_617:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1788*FLEN/8, x13, x9, x10)

inst_618:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1791*FLEN/8, x13, x9, x10)

inst_619:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1794*FLEN/8, x13, x9, x10)

inst_620:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1797*FLEN/8, x13, x9, x10)

inst_621:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1800*FLEN/8, x13, x9, x10)

inst_622:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1803*FLEN/8, x13, x9, x10)

inst_623:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1806*FLEN/8, x13, x9, x10)

inst_624:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:1809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1809*FLEN/8, x13, x9, x10)

inst_625:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:1812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1812*FLEN/8, x13, x9, x10)

inst_626:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:1815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1815*FLEN/8, x13, x9, x10)

inst_627:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:1818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1818*FLEN/8, x13, x9, x10)

inst_628:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:1821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1821*FLEN/8, x13, x9, x10)

inst_629:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1824*FLEN/8, x13, x9, x10)

inst_630:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1827*FLEN/8, x13, x9, x10)

inst_631:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1830*FLEN/8, x13, x9, x10)

inst_632:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:1833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1833*FLEN/8, x13, x9, x10)

inst_633:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:1836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1836*FLEN/8, x13, x9, x10)

inst_634:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:1839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1839*FLEN/8, x13, x9, x10)

inst_635:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:1842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1842*FLEN/8, x13, x9, x10)

inst_636:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1845*FLEN/8, x13, x9, x10)

inst_637:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1848*FLEN/8, x13, x9, x10)

inst_638:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1851*FLEN/8, x13, x9, x10)

inst_639:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:1854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1854*FLEN/8, x13, x9, x10)

inst_640:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1857*FLEN/8, x13, x9, x10)

inst_641:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1860*FLEN/8, x13, x9, x10)

inst_642:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1863*FLEN/8, x13, x9, x10)

inst_643:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1866*FLEN/8, x13, x9, x10)

inst_644:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1869*FLEN/8, x13, x9, x10)

inst_645:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1872*FLEN/8, x13, x9, x10)

inst_646:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1875*FLEN/8, x13, x9, x10)

inst_647:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1878*FLEN/8, x13, x9, x10)

inst_648:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:1881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1881*FLEN/8, x13, x9, x10)

inst_649:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:1884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1884*FLEN/8, x13, x9, x10)

inst_650:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:1887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1887*FLEN/8, x13, x9, x10)

inst_651:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:1890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1890*FLEN/8, x13, x9, x10)

inst_652:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:1893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1893*FLEN/8, x13, x9, x10)

inst_653:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1896*FLEN/8, x13, x9, x10)

inst_654:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1899*FLEN/8, x13, x9, x10)

inst_655:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1902*FLEN/8, x13, x9, x10)

inst_656:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:1905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1905*FLEN/8, x13, x9, x10)

inst_657:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:1908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1908*FLEN/8, x13, x9, x10)

inst_658:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:1911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1911*FLEN/8, x13, x9, x10)

inst_659:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:1914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1914*FLEN/8, x13, x9, x10)

inst_660:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1917*FLEN/8, x13, x9, x10)

inst_661:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1920*FLEN/8, x13, x9, x10)

inst_662:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1923*FLEN/8, x13, x9, x10)

inst_663:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:1926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1926*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_5)

inst_664:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:1929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1929*FLEN/8, x13, x9, x10)

inst_665:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:1932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1932*FLEN/8, x13, x9, x10)

inst_666:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:1935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1935*FLEN/8, x13, x9, x10)

inst_667:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:1938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1938*FLEN/8, x13, x9, x10)

inst_668:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:1941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1941*FLEN/8, x13, x9, x10)

inst_669:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:1944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1944*FLEN/8, x13, x9, x10)

inst_670:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:1947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1947*FLEN/8, x13, x9, x10)

inst_671:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:1950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1950*FLEN/8, x13, x9, x10)

inst_672:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:1953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1953*FLEN/8, x13, x9, x10)

inst_673:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:1956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1956*FLEN/8, x13, x9, x10)

inst_674:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:1959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1959*FLEN/8, x13, x9, x10)

inst_675:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:1962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1962*FLEN/8, x13, x9, x10)

inst_676:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:1965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1965*FLEN/8, x13, x9, x10)

inst_677:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:1968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1968*FLEN/8, x13, x9, x10)

inst_678:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:1971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1971*FLEN/8, x13, x9, x10)

inst_679:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:1974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1974*FLEN/8, x13, x9, x10)

inst_680:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:1977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1977*FLEN/8, x13, x9, x10)

inst_681:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:1980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1980*FLEN/8, x13, x9, x10)

inst_682:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:1983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1983*FLEN/8, x13, x9, x10)

inst_683:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:1986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1986*FLEN/8, x13, x9, x10)

inst_684:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:1989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1989*FLEN/8, x13, x9, x10)

inst_685:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:1992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1992*FLEN/8, x13, x9, x10)

inst_686:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:1995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1995*FLEN/8, x13, x9, x10)

inst_687:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:1998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 1998*FLEN/8, x13, x9, x10)

inst_688:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2001*FLEN/8, x13, x9, x10)

inst_689:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2004*FLEN/8, x13, x9, x10)

inst_690:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2007*FLEN/8, x13, x9, x10)

inst_691:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2010*FLEN/8, x13, x9, x10)

inst_692:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2013*FLEN/8, x13, x9, x10)

inst_693:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2016*FLEN/8, x13, x9, x10)

inst_694:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2019*FLEN/8, x13, x9, x10)

inst_695:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2022*FLEN/8, x13, x9, x10)

inst_696:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:2025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2025*FLEN/8, x13, x9, x10)

inst_697:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:2028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2028*FLEN/8, x13, x9, x10)

inst_698:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:2031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2031*FLEN/8, x13, x9, x10)

inst_699:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:2034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2034*FLEN/8, x13, x9, x10)

inst_700:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:2037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2037*FLEN/8, x13, x9, x10)

inst_701:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2040*FLEN/8, x13, x9, x10)

inst_702:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2043*FLEN/8, x13, x9, x10)

inst_703:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2046*FLEN/8, x13, x9, x10)

inst_704:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:2049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2049*FLEN/8, x13, x9, x10)

inst_705:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:2052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2052*FLEN/8, x13, x9, x10)

inst_706:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:2055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2055*FLEN/8, x13, x9, x10)

inst_707:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:2058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2058*FLEN/8, x13, x9, x10)

inst_708:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2061*FLEN/8, x13, x9, x10)

inst_709:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2064*FLEN/8, x13, x9, x10)

inst_710:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2067*FLEN/8, x13, x9, x10)

inst_711:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:2070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2070*FLEN/8, x13, x9, x10)

inst_712:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2073*FLEN/8, x13, x9, x10)

inst_713:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2076*FLEN/8, x13, x9, x10)

inst_714:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2079*FLEN/8, x13, x9, x10)

inst_715:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2082*FLEN/8, x13, x9, x10)

inst_716:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2085*FLEN/8, x13, x9, x10)

inst_717:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2088*FLEN/8, x13, x9, x10)

inst_718:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2091*FLEN/8, x13, x9, x10)

inst_719:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2094*FLEN/8, x13, x9, x10)

inst_720:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:2097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2097*FLEN/8, x13, x9, x10)

inst_721:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:2100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2100*FLEN/8, x13, x9, x10)

inst_722:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:2103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2103*FLEN/8, x13, x9, x10)

inst_723:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:2106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2106*FLEN/8, x13, x9, x10)

inst_724:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:2109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2109*FLEN/8, x13, x9, x10)

inst_725:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2112*FLEN/8, x13, x9, x10)

inst_726:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2115*FLEN/8, x13, x9, x10)

inst_727:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2118*FLEN/8, x13, x9, x10)

inst_728:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:2121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2121*FLEN/8, x13, x9, x10)

inst_729:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:2124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2124*FLEN/8, x13, x9, x10)

inst_730:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:2127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2127*FLEN/8, x13, x9, x10)

inst_731:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:2130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2130*FLEN/8, x13, x9, x10)

inst_732:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2133*FLEN/8, x13, x9, x10)

inst_733:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2136*FLEN/8, x13, x9, x10)

inst_734:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2139*FLEN/8, x13, x9, x10)

inst_735:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:2142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2142*FLEN/8, x13, x9, x10)

inst_736:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2145*FLEN/8, x13, x9, x10)

inst_737:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2148*FLEN/8, x13, x9, x10)

inst_738:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2151*FLEN/8, x13, x9, x10)

inst_739:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2154*FLEN/8, x13, x9, x10)

inst_740:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2157*FLEN/8, x13, x9, x10)

inst_741:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2160*FLEN/8, x13, x9, x10)

inst_742:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2163*FLEN/8, x13, x9, x10)

inst_743:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2166*FLEN/8, x13, x9, x10)

inst_744:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:2169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2169*FLEN/8, x13, x9, x10)

inst_745:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:2172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2172*FLEN/8, x13, x9, x10)

inst_746:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:2175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2175*FLEN/8, x13, x9, x10)

inst_747:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:2178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2178*FLEN/8, x13, x9, x10)

inst_748:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:2181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2181*FLEN/8, x13, x9, x10)

inst_749:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2184*FLEN/8, x13, x9, x10)

inst_750:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2187*FLEN/8, x13, x9, x10)

inst_751:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2190*FLEN/8, x13, x9, x10)

inst_752:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:2193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2193*FLEN/8, x13, x9, x10)

inst_753:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:2196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2196*FLEN/8, x13, x9, x10)

inst_754:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:2199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2199*FLEN/8, x13, x9, x10)

inst_755:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:2202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2202*FLEN/8, x13, x9, x10)

inst_756:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2205*FLEN/8, x13, x9, x10)

inst_757:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2208*FLEN/8, x13, x9, x10)

inst_758:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2211*FLEN/8, x13, x9, x10)

inst_759:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:2214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2214*FLEN/8, x13, x9, x10)

inst_760:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2217*FLEN/8, x13, x9, x10)

inst_761:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2220*FLEN/8, x13, x9, x10)

inst_762:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2223*FLEN/8, x13, x9, x10)

inst_763:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2226*FLEN/8, x13, x9, x10)

inst_764:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2229*FLEN/8, x13, x9, x10)

inst_765:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2232*FLEN/8, x13, x9, x10)

inst_766:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2235*FLEN/8, x13, x9, x10)

inst_767:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2238*FLEN/8, x13, x9, x10)

inst_768:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:2241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2241*FLEN/8, x13, x9, x10)

inst_769:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:2244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2244*FLEN/8, x13, x9, x10)

inst_770:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:2247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2247*FLEN/8, x13, x9, x10)

inst_771:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:2250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2250*FLEN/8, x13, x9, x10)

inst_772:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:2253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2253*FLEN/8, x13, x9, x10)

inst_773:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2256*FLEN/8, x13, x9, x10)

inst_774:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2259*FLEN/8, x13, x9, x10)

inst_775:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2262*FLEN/8, x13, x9, x10)

inst_776:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:2265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2265*FLEN/8, x13, x9, x10)

inst_777:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:2268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2268*FLEN/8, x13, x9, x10)

inst_778:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:2271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2271*FLEN/8, x13, x9, x10)

inst_779:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:2274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2274*FLEN/8, x13, x9, x10)

inst_780:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2277*FLEN/8, x13, x9, x10)

inst_781:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2280*FLEN/8, x13, x9, x10)

inst_782:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2283*FLEN/8, x13, x9, x10)

inst_783:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:2286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2286*FLEN/8, x13, x9, x10)

inst_784:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2289*FLEN/8, x13, x9, x10)

inst_785:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2292*FLEN/8, x13, x9, x10)

inst_786:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2295*FLEN/8, x13, x9, x10)

inst_787:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2298*FLEN/8, x13, x9, x10)

inst_788:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2301*FLEN/8, x13, x9, x10)

inst_789:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2304*FLEN/8, x13, x9, x10)

inst_790:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2307*FLEN/8, x13, x9, x10)

inst_791:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2310*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_6)

inst_792:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:2313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2313*FLEN/8, x13, x9, x10)

inst_793:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:2316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2316*FLEN/8, x13, x9, x10)

inst_794:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:2319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2319*FLEN/8, x13, x9, x10)

inst_795:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:2322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2322*FLEN/8, x13, x9, x10)

inst_796:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:2325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2325*FLEN/8, x13, x9, x10)

inst_797:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2328*FLEN/8, x13, x9, x10)

inst_798:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2331*FLEN/8, x13, x9, x10)

inst_799:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2334*FLEN/8, x13, x9, x10)

inst_800:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:2337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2337*FLEN/8, x13, x9, x10)

inst_801:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:2340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2340*FLEN/8, x13, x9, x10)

inst_802:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:2343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2343*FLEN/8, x13, x9, x10)

inst_803:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:2346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2346*FLEN/8, x13, x9, x10)

inst_804:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2349*FLEN/8, x13, x9, x10)

inst_805:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2352*FLEN/8, x13, x9, x10)

inst_806:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2355*FLEN/8, x13, x9, x10)

inst_807:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:2358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2358*FLEN/8, x13, x9, x10)

inst_808:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2361*FLEN/8, x13, x9, x10)

inst_809:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2364*FLEN/8, x13, x9, x10)

inst_810:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2367*FLEN/8, x13, x9, x10)

inst_811:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2370*FLEN/8, x13, x9, x10)

inst_812:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2373*FLEN/8, x13, x9, x10)

inst_813:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2376*FLEN/8, x13, x9, x10)

inst_814:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2379*FLEN/8, x13, x9, x10)

inst_815:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2382*FLEN/8, x13, x9, x10)

inst_816:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:2385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2385*FLEN/8, x13, x9, x10)

inst_817:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:2388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2388*FLEN/8, x13, x9, x10)

inst_818:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:2391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2391*FLEN/8, x13, x9, x10)

inst_819:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:2394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2394*FLEN/8, x13, x9, x10)

inst_820:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:2397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2397*FLEN/8, x13, x9, x10)

inst_821:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2400*FLEN/8, x13, x9, x10)

inst_822:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2403*FLEN/8, x13, x9, x10)

inst_823:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2406*FLEN/8, x13, x9, x10)

inst_824:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:2409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2409*FLEN/8, x13, x9, x10)

inst_825:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:2412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2412*FLEN/8, x13, x9, x10)

inst_826:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:2415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2415*FLEN/8, x13, x9, x10)

inst_827:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:2418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2418*FLEN/8, x13, x9, x10)

inst_828:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2421*FLEN/8, x13, x9, x10)

inst_829:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2424*FLEN/8, x13, x9, x10)

inst_830:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2427*FLEN/8, x13, x9, x10)

inst_831:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:2430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2430*FLEN/8, x13, x9, x10)

inst_832:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2433*FLEN/8, x13, x9, x10)

inst_833:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2436*FLEN/8, x13, x9, x10)

inst_834:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2439*FLEN/8, x13, x9, x10)

inst_835:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2442*FLEN/8, x13, x9, x10)

inst_836:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2445*FLEN/8, x13, x9, x10)

inst_837:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2448*FLEN/8, x13, x9, x10)

inst_838:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2451*FLEN/8, x13, x9, x10)

inst_839:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2454*FLEN/8, x13, x9, x10)

inst_840:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:2457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2457*FLEN/8, x13, x9, x10)

inst_841:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:2460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2460*FLEN/8, x13, x9, x10)

inst_842:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:2463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2463*FLEN/8, x13, x9, x10)

inst_843:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:2466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2466*FLEN/8, x13, x9, x10)

inst_844:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:2469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2469*FLEN/8, x13, x9, x10)

inst_845:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2472*FLEN/8, x13, x9, x10)

inst_846:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2475*FLEN/8, x13, x9, x10)

inst_847:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2478*FLEN/8, x13, x9, x10)

inst_848:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:2481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2481*FLEN/8, x13, x9, x10)

inst_849:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:2484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2484*FLEN/8, x13, x9, x10)

inst_850:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:2487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2487*FLEN/8, x13, x9, x10)

inst_851:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:2490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2490*FLEN/8, x13, x9, x10)

inst_852:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2493*FLEN/8, x13, x9, x10)

inst_853:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2496*FLEN/8, x13, x9, x10)

inst_854:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2499*FLEN/8, x13, x9, x10)

inst_855:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:2502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2502*FLEN/8, x13, x9, x10)

inst_856:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2505*FLEN/8, x13, x9, x10)

inst_857:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2508*FLEN/8, x13, x9, x10)

inst_858:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2511*FLEN/8, x13, x9, x10)

inst_859:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2514*FLEN/8, x13, x9, x10)

inst_860:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2517*FLEN/8, x13, x9, x10)

inst_861:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2520*FLEN/8, x13, x9, x10)

inst_862:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2523*FLEN/8, x13, x9, x10)

inst_863:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2526*FLEN/8, x13, x9, x10)

inst_864:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:2529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2529*FLEN/8, x13, x9, x10)

inst_865:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:2532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2532*FLEN/8, x13, x9, x10)

inst_866:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:2535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2535*FLEN/8, x13, x9, x10)

inst_867:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:2538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2538*FLEN/8, x13, x9, x10)

inst_868:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:2541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2541*FLEN/8, x13, x9, x10)

inst_869:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2544*FLEN/8, x13, x9, x10)

inst_870:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2547*FLEN/8, x13, x9, x10)

inst_871:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2550*FLEN/8, x13, x9, x10)

inst_872:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:2553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2553*FLEN/8, x13, x9, x10)

inst_873:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:2556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2556*FLEN/8, x13, x9, x10)

inst_874:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:2559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2559*FLEN/8, x13, x9, x10)

inst_875:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:2562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2562*FLEN/8, x13, x9, x10)

inst_876:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2565*FLEN/8, x13, x9, x10)

inst_877:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2568*FLEN/8, x13, x9, x10)

inst_878:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2571*FLEN/8, x13, x9, x10)

inst_879:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:2574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2574*FLEN/8, x13, x9, x10)

inst_880:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2577*FLEN/8, x13, x9, x10)

inst_881:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2580*FLEN/8, x13, x9, x10)

inst_882:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2583*FLEN/8, x13, x9, x10)

inst_883:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2586*FLEN/8, x13, x9, x10)

inst_884:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2589*FLEN/8, x13, x9, x10)

inst_885:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2592*FLEN/8, x13, x9, x10)

inst_886:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2595*FLEN/8, x13, x9, x10)

inst_887:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2598*FLEN/8, x13, x9, x10)

inst_888:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:2601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2601*FLEN/8, x13, x9, x10)

inst_889:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:2604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2604*FLEN/8, x13, x9, x10)

inst_890:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:2607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2607*FLEN/8, x13, x9, x10)

inst_891:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:2610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2610*FLEN/8, x13, x9, x10)

inst_892:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:2613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2613*FLEN/8, x13, x9, x10)

inst_893:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2616*FLEN/8, x13, x9, x10)

inst_894:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2619*FLEN/8, x13, x9, x10)

inst_895:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2622*FLEN/8, x13, x9, x10)

inst_896:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:2625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2625*FLEN/8, x13, x9, x10)

inst_897:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:2628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2628*FLEN/8, x13, x9, x10)

inst_898:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:2631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2631*FLEN/8, x13, x9, x10)

inst_899:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:2634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2634*FLEN/8, x13, x9, x10)

inst_900:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2637*FLEN/8, x13, x9, x10)

inst_901:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2640*FLEN/8, x13, x9, x10)

inst_902:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2643*FLEN/8, x13, x9, x10)

inst_903:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:2646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2646*FLEN/8, x13, x9, x10)

inst_904:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2649*FLEN/8, x13, x9, x10)

inst_905:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2652*FLEN/8, x13, x9, x10)

inst_906:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2655*FLEN/8, x13, x9, x10)

inst_907:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2658*FLEN/8, x13, x9, x10)

inst_908:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2661*FLEN/8, x13, x9, x10)

inst_909:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2664*FLEN/8, x13, x9, x10)

inst_910:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2667*FLEN/8, x13, x9, x10)

inst_911:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2670*FLEN/8, x13, x9, x10)

inst_912:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:2673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2673*FLEN/8, x13, x9, x10)

inst_913:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:2676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2676*FLEN/8, x13, x9, x10)

inst_914:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:2679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2679*FLEN/8, x13, x9, x10)

inst_915:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:2682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2682*FLEN/8, x13, x9, x10)

inst_916:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:2685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2685*FLEN/8, x13, x9, x10)

inst_917:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2688*FLEN/8, x13, x9, x10)

inst_918:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2691*FLEN/8, x13, x9, x10)

inst_919:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2694*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_7)

inst_920:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:2697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2697*FLEN/8, x13, x9, x10)

inst_921:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:2700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2700*FLEN/8, x13, x9, x10)

inst_922:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:2703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2703*FLEN/8, x13, x9, x10)

inst_923:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:2706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2706*FLEN/8, x13, x9, x10)

inst_924:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2709*FLEN/8, x13, x9, x10)

inst_925:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2712*FLEN/8, x13, x9, x10)

inst_926:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2715*FLEN/8, x13, x9, x10)

inst_927:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:2718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2718*FLEN/8, x13, x9, x10)

inst_928:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2721*FLEN/8, x13, x9, x10)

inst_929:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2724*FLEN/8, x13, x9, x10)

inst_930:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2727*FLEN/8, x13, x9, x10)

inst_931:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2730*FLEN/8, x13, x9, x10)

inst_932:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2733*FLEN/8, x13, x9, x10)

inst_933:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2736*FLEN/8, x13, x9, x10)

inst_934:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2739*FLEN/8, x13, x9, x10)

inst_935:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2742*FLEN/8, x13, x9, x10)

inst_936:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:2745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2745*FLEN/8, x13, x9, x10)

inst_937:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:2748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2748*FLEN/8, x13, x9, x10)

inst_938:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:2751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2751*FLEN/8, x13, x9, x10)

inst_939:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:2754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2754*FLEN/8, x13, x9, x10)

inst_940:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:2757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2757*FLEN/8, x13, x9, x10)

inst_941:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2760*FLEN/8, x13, x9, x10)

inst_942:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2763*FLEN/8, x13, x9, x10)

inst_943:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2766*FLEN/8, x13, x9, x10)

inst_944:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:2769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2769*FLEN/8, x13, x9, x10)

inst_945:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:2772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2772*FLEN/8, x13, x9, x10)

inst_946:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:2775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2775*FLEN/8, x13, x9, x10)

inst_947:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:2778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2778*FLEN/8, x13, x9, x10)

inst_948:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2781*FLEN/8, x13, x9, x10)

inst_949:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2784*FLEN/8, x13, x9, x10)

inst_950:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2787*FLEN/8, x13, x9, x10)

inst_951:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:2790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2790*FLEN/8, x13, x9, x10)

inst_952:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2793*FLEN/8, x13, x9, x10)

inst_953:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2796*FLEN/8, x13, x9, x10)

inst_954:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2799*FLEN/8, x13, x9, x10)

inst_955:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2802*FLEN/8, x13, x9, x10)

inst_956:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2805*FLEN/8, x13, x9, x10)

inst_957:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2808*FLEN/8, x13, x9, x10)

inst_958:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2811*FLEN/8, x13, x9, x10)

inst_959:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2814*FLEN/8, x13, x9, x10)

inst_960:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:2817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2817*FLEN/8, x13, x9, x10)

inst_961:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:2820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2820*FLEN/8, x13, x9, x10)

inst_962:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:2823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2823*FLEN/8, x13, x9, x10)

inst_963:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:2826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2826*FLEN/8, x13, x9, x10)

inst_964:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:2829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2829*FLEN/8, x13, x9, x10)

inst_965:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2832*FLEN/8, x13, x9, x10)

inst_966:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2835*FLEN/8, x13, x9, x10)

inst_967:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2838*FLEN/8, x13, x9, x10)

inst_968:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:2841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2841*FLEN/8, x13, x9, x10)

inst_969:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:2844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2844*FLEN/8, x13, x9, x10)

inst_970:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:2847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2847*FLEN/8, x13, x9, x10)

inst_971:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:2850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2850*FLEN/8, x13, x9, x10)

inst_972:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2853*FLEN/8, x13, x9, x10)

inst_973:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2856*FLEN/8, x13, x9, x10)

inst_974:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2859*FLEN/8, x13, x9, x10)

inst_975:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:2862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2862*FLEN/8, x13, x9, x10)

inst_976:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2865*FLEN/8, x13, x9, x10)

inst_977:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2868*FLEN/8, x13, x9, x10)

inst_978:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2871*FLEN/8, x13, x9, x10)

inst_979:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2874*FLEN/8, x13, x9, x10)

inst_980:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2877*FLEN/8, x13, x9, x10)

inst_981:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2880*FLEN/8, x13, x9, x10)

inst_982:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2883*FLEN/8, x13, x9, x10)

inst_983:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2886*FLEN/8, x13, x9, x10)

inst_984:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:2889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2889*FLEN/8, x13, x9, x10)

inst_985:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:2892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2892*FLEN/8, x13, x9, x10)

inst_986:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:2895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2895*FLEN/8, x13, x9, x10)

inst_987:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:2898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2898*FLEN/8, x13, x9, x10)

inst_988:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:2901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2901*FLEN/8, x13, x9, x10)

inst_989:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2904*FLEN/8, x13, x9, x10)

inst_990:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2907*FLEN/8, x13, x9, x10)

inst_991:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2910*FLEN/8, x13, x9, x10)

inst_992:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:2913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2913*FLEN/8, x13, x9, x10)

inst_993:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:2916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2916*FLEN/8, x13, x9, x10)

inst_994:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:2919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2919*FLEN/8, x13, x9, x10)

inst_995:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:2922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2922*FLEN/8, x13, x9, x10)

inst_996:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2925*FLEN/8, x13, x9, x10)

inst_997:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:2928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2928*FLEN/8, x13, x9, x10)

inst_998:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:2931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2931*FLEN/8, x13, x9, x10)

inst_999:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:2934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2934*FLEN/8, x13, x9, x10)

inst_1000:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:2937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2937*FLEN/8, x13, x9, x10)

inst_1001:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:2940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2940*FLEN/8, x13, x9, x10)

inst_1002:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:2943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2943*FLEN/8, x13, x9, x10)

inst_1003:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:2946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2946*FLEN/8, x13, x9, x10)

inst_1004:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:2949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2949*FLEN/8, x13, x9, x10)

inst_1005:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:2952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2952*FLEN/8, x13, x9, x10)

inst_1006:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:2955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2955*FLEN/8, x13, x9, x10)

inst_1007:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:2958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2958*FLEN/8, x13, x9, x10)

inst_1008:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:2961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2961*FLEN/8, x13, x9, x10)

inst_1009:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:2964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2964*FLEN/8, x13, x9, x10)

inst_1010:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:2967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2967*FLEN/8, x13, x9, x10)

inst_1011:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:2970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2970*FLEN/8, x13, x9, x10)

inst_1012:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:2973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2973*FLEN/8, x13, x9, x10)

inst_1013:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:2976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2976*FLEN/8, x13, x9, x10)

inst_1014:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:2979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2979*FLEN/8, x13, x9, x10)

inst_1015:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:2982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2982*FLEN/8, x13, x9, x10)

inst_1016:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:2985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2985*FLEN/8, x13, x9, x10)

inst_1017:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:2988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2988*FLEN/8, x13, x9, x10)

inst_1018:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:2991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2991*FLEN/8, x13, x9, x10)

inst_1019:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:2994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2994*FLEN/8, x13, x9, x10)

inst_1020:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:2997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 2997*FLEN/8, x13, x9, x10)

inst_1021:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3000*FLEN/8, x13, x9, x10)

inst_1022:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3003*FLEN/8, x13, x9, x10)

inst_1023:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:3006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3006*FLEN/8, x13, x9, x10)

inst_1024:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3009*FLEN/8, x13, x9, x10)

inst_1025:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3012*FLEN/8, x13, x9, x10)

inst_1026:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3015*FLEN/8, x13, x9, x10)

inst_1027:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3018*FLEN/8, x13, x9, x10)

inst_1028:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3021*FLEN/8, x13, x9, x10)

inst_1029:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3024*FLEN/8, x13, x9, x10)

inst_1030:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3027*FLEN/8, x13, x9, x10)

inst_1031:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3030*FLEN/8, x13, x9, x10)

inst_1032:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:3033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3033*FLEN/8, x13, x9, x10)

inst_1033:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:3036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3036*FLEN/8, x13, x9, x10)

inst_1034:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:3039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3039*FLEN/8, x13, x9, x10)

inst_1035:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:3042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3042*FLEN/8, x13, x9, x10)

inst_1036:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:3045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3045*FLEN/8, x13, x9, x10)

inst_1037:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3048*FLEN/8, x13, x9, x10)

inst_1038:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3051*FLEN/8, x13, x9, x10)

inst_1039:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3054*FLEN/8, x13, x9, x10)

inst_1040:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:3057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3057*FLEN/8, x13, x9, x10)

inst_1041:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:3060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3060*FLEN/8, x13, x9, x10)

inst_1042:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:3063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3063*FLEN/8, x13, x9, x10)

inst_1043:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:3066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3066*FLEN/8, x13, x9, x10)

inst_1044:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3069*FLEN/8, x13, x9, x10)

inst_1045:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3072*FLEN/8, x13, x9, x10)

inst_1046:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3075*FLEN/8, x13, x9, x10)

inst_1047:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:3078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3078*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_8)

inst_1048:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3081*FLEN/8, x13, x9, x10)

inst_1049:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3084*FLEN/8, x13, x9, x10)

inst_1050:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3087*FLEN/8, x13, x9, x10)

inst_1051:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3090*FLEN/8, x13, x9, x10)

inst_1052:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3093*FLEN/8, x13, x9, x10)

inst_1053:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3096*FLEN/8, x13, x9, x10)

inst_1054:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3099*FLEN/8, x13, x9, x10)

inst_1055:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3102*FLEN/8, x13, x9, x10)

inst_1056:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:3105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3105*FLEN/8, x13, x9, x10)

inst_1057:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:3108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3108*FLEN/8, x13, x9, x10)

inst_1058:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:3111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3111*FLEN/8, x13, x9, x10)

inst_1059:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:3114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3114*FLEN/8, x13, x9, x10)

inst_1060:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:3117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3117*FLEN/8, x13, x9, x10)

inst_1061:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3120*FLEN/8, x13, x9, x10)

inst_1062:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3123*FLEN/8, x13, x9, x10)

inst_1063:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3126*FLEN/8, x13, x9, x10)

inst_1064:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:3129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3129*FLEN/8, x13, x9, x10)

inst_1065:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:3132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3132*FLEN/8, x13, x9, x10)

inst_1066:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:3135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3135*FLEN/8, x13, x9, x10)

inst_1067:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:3138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3138*FLEN/8, x13, x9, x10)

inst_1068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3141*FLEN/8, x13, x9, x10)

inst_1069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3144*FLEN/8, x13, x9, x10)

inst_1070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3147*FLEN/8, x13, x9, x10)

inst_1071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:3150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3150*FLEN/8, x13, x9, x10)

inst_1072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3153*FLEN/8, x13, x9, x10)

inst_1073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3156*FLEN/8, x13, x9, x10)

inst_1074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3159*FLEN/8, x13, x9, x10)

inst_1075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3162*FLEN/8, x13, x9, x10)

inst_1076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3165*FLEN/8, x13, x9, x10)

inst_1077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3168*FLEN/8, x13, x9, x10)

inst_1078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3171*FLEN/8, x13, x9, x10)

inst_1079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3174*FLEN/8, x13, x9, x10)

inst_1080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:3177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3177*FLEN/8, x13, x9, x10)

inst_1081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:3180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3180*FLEN/8, x13, x9, x10)

inst_1082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:3183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3183*FLEN/8, x13, x9, x10)

inst_1083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:3186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3186*FLEN/8, x13, x9, x10)

inst_1084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:3189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3189*FLEN/8, x13, x9, x10)

inst_1085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3192*FLEN/8, x13, x9, x10)

inst_1086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3195*FLEN/8, x13, x9, x10)

inst_1087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3198*FLEN/8, x13, x9, x10)

inst_1088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:3201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3201*FLEN/8, x13, x9, x10)

inst_1089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:3204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3204*FLEN/8, x13, x9, x10)

inst_1090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:3207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3207*FLEN/8, x13, x9, x10)

inst_1091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:3210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3210*FLEN/8, x13, x9, x10)

inst_1092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3213*FLEN/8, x13, x9, x10)

inst_1093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3216*FLEN/8, x13, x9, x10)

inst_1094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3219*FLEN/8, x13, x9, x10)

inst_1095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:3222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3222*FLEN/8, x13, x9, x10)

inst_1096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3225*FLEN/8, x13, x9, x10)

inst_1097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3228*FLEN/8, x13, x9, x10)

inst_1098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3231*FLEN/8, x13, x9, x10)

inst_1099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3234*FLEN/8, x13, x9, x10)

inst_1100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3237*FLEN/8, x13, x9, x10)

inst_1101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3240*FLEN/8, x13, x9, x10)

inst_1102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3243*FLEN/8, x13, x9, x10)

inst_1103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3246*FLEN/8, x13, x9, x10)

inst_1104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:3249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3249*FLEN/8, x13, x9, x10)

inst_1105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:3252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3252*FLEN/8, x13, x9, x10)

inst_1106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:3255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3255*FLEN/8, x13, x9, x10)

inst_1107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:3258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3258*FLEN/8, x13, x9, x10)

inst_1108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:3261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3261*FLEN/8, x13, x9, x10)

inst_1109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3264*FLEN/8, x13, x9, x10)

inst_1110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3267*FLEN/8, x13, x9, x10)

inst_1111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3270*FLEN/8, x13, x9, x10)

inst_1112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:3273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3273*FLEN/8, x13, x9, x10)

inst_1113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:3276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3276*FLEN/8, x13, x9, x10)

inst_1114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:3279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3279*FLEN/8, x13, x9, x10)

inst_1115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:3282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3282*FLEN/8, x13, x9, x10)

inst_1116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3285*FLEN/8, x13, x9, x10)

inst_1117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3288*FLEN/8, x13, x9, x10)

inst_1118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3291*FLEN/8, x13, x9, x10)

inst_1119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:3294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3294*FLEN/8, x13, x9, x10)

inst_1120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3297*FLEN/8, x13, x9, x10)

inst_1121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3300*FLEN/8, x13, x9, x10)

inst_1122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3303*FLEN/8, x13, x9, x10)

inst_1123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3306*FLEN/8, x13, x9, x10)

inst_1124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3309*FLEN/8, x13, x9, x10)

inst_1125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3312*FLEN/8, x13, x9, x10)

inst_1126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3315*FLEN/8, x13, x9, x10)

inst_1127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3318*FLEN/8, x13, x9, x10)

inst_1128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:3321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3321*FLEN/8, x13, x9, x10)

inst_1129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:3324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3324*FLEN/8, x13, x9, x10)

inst_1130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:3327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3327*FLEN/8, x13, x9, x10)

inst_1131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:3330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3330*FLEN/8, x13, x9, x10)

inst_1132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:3333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3333*FLEN/8, x13, x9, x10)

inst_1133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3336*FLEN/8, x13, x9, x10)

inst_1134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3339*FLEN/8, x13, x9, x10)

inst_1135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3342*FLEN/8, x13, x9, x10)

inst_1136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:3345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3345*FLEN/8, x13, x9, x10)

inst_1137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:3348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3348*FLEN/8, x13, x9, x10)

inst_1138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:3351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3351*FLEN/8, x13, x9, x10)

inst_1139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:3354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3354*FLEN/8, x13, x9, x10)

inst_1140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3357*FLEN/8, x13, x9, x10)

inst_1141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3360*FLEN/8, x13, x9, x10)

inst_1142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3363*FLEN/8, x13, x9, x10)

inst_1143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:3366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3366*FLEN/8, x13, x9, x10)

inst_1144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3369*FLEN/8, x13, x9, x10)

inst_1145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3372*FLEN/8, x13, x9, x10)

inst_1146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3375*FLEN/8, x13, x9, x10)

inst_1147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3378*FLEN/8, x13, x9, x10)

inst_1148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3381*FLEN/8, x13, x9, x10)

inst_1149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3384*FLEN/8, x13, x9, x10)

inst_1150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3387*FLEN/8, x13, x9, x10)

inst_1151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3390*FLEN/8, x13, x9, x10)

inst_1152:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:3393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3393*FLEN/8, x13, x9, x10)

inst_1153:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:3396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3396*FLEN/8, x13, x9, x10)

inst_1154:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:3399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3399*FLEN/8, x13, x9, x10)

inst_1155:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:3402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3402*FLEN/8, x13, x9, x10)

inst_1156:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:3405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3405*FLEN/8, x13, x9, x10)

inst_1157:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3408*FLEN/8, x13, x9, x10)

inst_1158:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3411*FLEN/8, x13, x9, x10)

inst_1159:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3414*FLEN/8, x13, x9, x10)

inst_1160:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:3417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3417*FLEN/8, x13, x9, x10)

inst_1161:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:3420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3420*FLEN/8, x13, x9, x10)

inst_1162:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:3423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3423*FLEN/8, x13, x9, x10)

inst_1163:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:3426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3426*FLEN/8, x13, x9, x10)

inst_1164:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3429*FLEN/8, x13, x9, x10)

inst_1165:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3432*FLEN/8, x13, x9, x10)

inst_1166:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3435*FLEN/8, x13, x9, x10)

inst_1167:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:3438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3438*FLEN/8, x13, x9, x10)

inst_1168:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3441*FLEN/8, x13, x9, x10)

inst_1169:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3444*FLEN/8, x13, x9, x10)

inst_1170:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3447*FLEN/8, x13, x9, x10)

inst_1171:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3450*FLEN/8, x13, x9, x10)

inst_1172:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3453*FLEN/8, x13, x9, x10)

inst_1173:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3456*FLEN/8, x13, x9, x10)

inst_1174:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3459*FLEN/8, x13, x9, x10)

inst_1175:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3462*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_9)

inst_1176:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:3465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3465*FLEN/8, x13, x9, x10)

inst_1177:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:3468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3468*FLEN/8, x13, x9, x10)

inst_1178:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:3471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3471*FLEN/8, x13, x9, x10)

inst_1179:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:3474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3474*FLEN/8, x13, x9, x10)

inst_1180:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:3477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3477*FLEN/8, x13, x9, x10)

inst_1181:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3480*FLEN/8, x13, x9, x10)

inst_1182:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3483*FLEN/8, x13, x9, x10)

inst_1183:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3486*FLEN/8, x13, x9, x10)

inst_1184:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:3489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3489*FLEN/8, x13, x9, x10)

inst_1185:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:3492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3492*FLEN/8, x13, x9, x10)

inst_1186:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:3495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3495*FLEN/8, x13, x9, x10)

inst_1187:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:3498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3498*FLEN/8, x13, x9, x10)

inst_1188:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3501*FLEN/8, x13, x9, x10)

inst_1189:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3504*FLEN/8, x13, x9, x10)

inst_1190:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3507*FLEN/8, x13, x9, x10)

inst_1191:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:3510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3510*FLEN/8, x13, x9, x10)

inst_1192:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3513*FLEN/8, x13, x9, x10)

inst_1193:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3516*FLEN/8, x13, x9, x10)

inst_1194:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3519*FLEN/8, x13, x9, x10)

inst_1195:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3522*FLEN/8, x13, x9, x10)

inst_1196:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3525*FLEN/8, x13, x9, x10)

inst_1197:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3528*FLEN/8, x13, x9, x10)

inst_1198:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3531*FLEN/8, x13, x9, x10)

inst_1199:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3534*FLEN/8, x13, x9, x10)

inst_1200:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:3537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3537*FLEN/8, x13, x9, x10)

inst_1201:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:3540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3540*FLEN/8, x13, x9, x10)

inst_1202:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:3543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3543*FLEN/8, x13, x9, x10)

inst_1203:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:3546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3546*FLEN/8, x13, x9, x10)

inst_1204:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:3549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3549*FLEN/8, x13, x9, x10)

inst_1205:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3552*FLEN/8, x13, x9, x10)

inst_1206:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3555*FLEN/8, x13, x9, x10)

inst_1207:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3558*FLEN/8, x13, x9, x10)

inst_1208:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:3561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3561*FLEN/8, x13, x9, x10)

inst_1209:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:3564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3564*FLEN/8, x13, x9, x10)

inst_1210:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:3567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3567*FLEN/8, x13, x9, x10)

inst_1211:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:3570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3570*FLEN/8, x13, x9, x10)

inst_1212:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3573*FLEN/8, x13, x9, x10)

inst_1213:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3576*FLEN/8, x13, x9, x10)

inst_1214:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3579*FLEN/8, x13, x9, x10)

inst_1215:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:3582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3582*FLEN/8, x13, x9, x10)

inst_1216:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3585*FLEN/8, x13, x9, x10)

inst_1217:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3588*FLEN/8, x13, x9, x10)

inst_1218:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3591*FLEN/8, x13, x9, x10)

inst_1219:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3594*FLEN/8, x13, x9, x10)

inst_1220:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3597*FLEN/8, x13, x9, x10)

inst_1221:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3600*FLEN/8, x13, x9, x10)

inst_1222:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3603*FLEN/8, x13, x9, x10)

inst_1223:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3606*FLEN/8, x13, x9, x10)

inst_1224:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:3609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3609*FLEN/8, x13, x9, x10)

inst_1225:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:3612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3612*FLEN/8, x13, x9, x10)

inst_1226:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:3615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3615*FLEN/8, x13, x9, x10)

inst_1227:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:3618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3618*FLEN/8, x13, x9, x10)

inst_1228:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:3621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3621*FLEN/8, x13, x9, x10)

inst_1229:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3624*FLEN/8, x13, x9, x10)

inst_1230:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3627*FLEN/8, x13, x9, x10)

inst_1231:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3630*FLEN/8, x13, x9, x10)

inst_1232:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:3633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3633*FLEN/8, x13, x9, x10)

inst_1233:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:3636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3636*FLEN/8, x13, x9, x10)

inst_1234:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:3639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3639*FLEN/8, x13, x9, x10)

inst_1235:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:3642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3642*FLEN/8, x13, x9, x10)

inst_1236:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3645*FLEN/8, x13, x9, x10)

inst_1237:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3648*FLEN/8, x13, x9, x10)

inst_1238:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3651*FLEN/8, x13, x9, x10)

inst_1239:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:3654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3654*FLEN/8, x13, x9, x10)

inst_1240:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3657*FLEN/8, x13, x9, x10)

inst_1241:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3660*FLEN/8, x13, x9, x10)

inst_1242:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3663*FLEN/8, x13, x9, x10)

inst_1243:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3666*FLEN/8, x13, x9, x10)

inst_1244:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3669*FLEN/8, x13, x9, x10)

inst_1245:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3672*FLEN/8, x13, x9, x10)

inst_1246:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3675*FLEN/8, x13, x9, x10)

inst_1247:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3678*FLEN/8, x13, x9, x10)

inst_1248:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:3681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3681*FLEN/8, x13, x9, x10)

inst_1249:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:3684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3684*FLEN/8, x13, x9, x10)

inst_1250:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:3687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3687*FLEN/8, x13, x9, x10)

inst_1251:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:3690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3690*FLEN/8, x13, x9, x10)

inst_1252:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:3693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3693*FLEN/8, x13, x9, x10)

inst_1253:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3696*FLEN/8, x13, x9, x10)

inst_1254:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3699*FLEN/8, x13, x9, x10)

inst_1255:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3702*FLEN/8, x13, x9, x10)

inst_1256:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:3705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3705*FLEN/8, x13, x9, x10)

inst_1257:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:3708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3708*FLEN/8, x13, x9, x10)

inst_1258:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:3711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3711*FLEN/8, x13, x9, x10)

inst_1259:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:3714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3714*FLEN/8, x13, x9, x10)

inst_1260:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3717*FLEN/8, x13, x9, x10)

inst_1261:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3720*FLEN/8, x13, x9, x10)

inst_1262:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3723*FLEN/8, x13, x9, x10)

inst_1263:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:3726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3726*FLEN/8, x13, x9, x10)

inst_1264:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3729*FLEN/8, x13, x9, x10)

inst_1265:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3732*FLEN/8, x13, x9, x10)

inst_1266:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3735*FLEN/8, x13, x9, x10)

inst_1267:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3738*FLEN/8, x13, x9, x10)

inst_1268:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3741*FLEN/8, x13, x9, x10)

inst_1269:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3744*FLEN/8, x13, x9, x10)

inst_1270:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3747*FLEN/8, x13, x9, x10)

inst_1271:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3750*FLEN/8, x13, x9, x10)

inst_1272:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:3753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3753*FLEN/8, x13, x9, x10)

inst_1273:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:3756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3756*FLEN/8, x13, x9, x10)

inst_1274:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:3759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3759*FLEN/8, x13, x9, x10)

inst_1275:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:3762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3762*FLEN/8, x13, x9, x10)

inst_1276:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:3765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3765*FLEN/8, x13, x9, x10)

inst_1277:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3768*FLEN/8, x13, x9, x10)

inst_1278:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3771*FLEN/8, x13, x9, x10)

inst_1279:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3774*FLEN/8, x13, x9, x10)

inst_1280:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:3777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3777*FLEN/8, x13, x9, x10)

inst_1281:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:3780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3780*FLEN/8, x13, x9, x10)

inst_1282:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:3783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3783*FLEN/8, x13, x9, x10)

inst_1283:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:3786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3786*FLEN/8, x13, x9, x10)

inst_1284:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3789*FLEN/8, x13, x9, x10)

inst_1285:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3792*FLEN/8, x13, x9, x10)

inst_1286:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3795*FLEN/8, x13, x9, x10)

inst_1287:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:3798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3798*FLEN/8, x13, x9, x10)

inst_1288:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3801*FLEN/8, x13, x9, x10)

inst_1289:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3804*FLEN/8, x13, x9, x10)

inst_1290:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3807*FLEN/8, x13, x9, x10)

inst_1291:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3810*FLEN/8, x13, x9, x10)

inst_1292:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3813*FLEN/8, x13, x9, x10)

inst_1293:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3816*FLEN/8, x13, x9, x10)

inst_1294:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3819*FLEN/8, x13, x9, x10)

inst_1295:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3822*FLEN/8, x13, x9, x10)

inst_1296:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:3825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3825*FLEN/8, x13, x9, x10)

inst_1297:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:3828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3828*FLEN/8, x13, x9, x10)

inst_1298:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:3831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3831*FLEN/8, x13, x9, x10)

inst_1299:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:3834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3834*FLEN/8, x13, x9, x10)

inst_1300:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:3837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3837*FLEN/8, x13, x9, x10)

inst_1301:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3840*FLEN/8, x13, x9, x10)

inst_1302:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3843*FLEN/8, x13, x9, x10)

inst_1303:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3846*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_10)

inst_1304:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:3849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3849*FLEN/8, x13, x9, x10)

inst_1305:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:3852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3852*FLEN/8, x13, x9, x10)

inst_1306:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:3855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3855*FLEN/8, x13, x9, x10)

inst_1307:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:3858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3858*FLEN/8, x13, x9, x10)

inst_1308:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3861*FLEN/8, x13, x9, x10)

inst_1309:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3864*FLEN/8, x13, x9, x10)

inst_1310:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3867*FLEN/8, x13, x9, x10)

inst_1311:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:3870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3870*FLEN/8, x13, x9, x10)

inst_1312:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3873*FLEN/8, x13, x9, x10)

inst_1313:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3876*FLEN/8, x13, x9, x10)

inst_1314:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3879*FLEN/8, x13, x9, x10)

inst_1315:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3882*FLEN/8, x13, x9, x10)

inst_1316:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3885*FLEN/8, x13, x9, x10)

inst_1317:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3888*FLEN/8, x13, x9, x10)

inst_1318:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3891*FLEN/8, x13, x9, x10)

inst_1319:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3894*FLEN/8, x13, x9, x10)

inst_1320:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:3897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3897*FLEN/8, x13, x9, x10)

inst_1321:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:3900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3900*FLEN/8, x13, x9, x10)

inst_1322:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:3903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3903*FLEN/8, x13, x9, x10)

inst_1323:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:3906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3906*FLEN/8, x13, x9, x10)

inst_1324:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:3909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3909*FLEN/8, x13, x9, x10)

inst_1325:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3912*FLEN/8, x13, x9, x10)

inst_1326:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3915*FLEN/8, x13, x9, x10)

inst_1327:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3918*FLEN/8, x13, x9, x10)

inst_1328:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:3921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3921*FLEN/8, x13, x9, x10)

inst_1329:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:3924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3924*FLEN/8, x13, x9, x10)

inst_1330:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:3927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3927*FLEN/8, x13, x9, x10)

inst_1331:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:3930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3930*FLEN/8, x13, x9, x10)

inst_1332:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:3933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3933*FLEN/8, x13, x9, x10)

inst_1333:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:3936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3936*FLEN/8, x13, x9, x10)

inst_1334:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:3939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3939*FLEN/8, x13, x9, x10)

inst_1335:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:3942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3942*FLEN/8, x13, x9, x10)

inst_1336:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:3945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3945*FLEN/8, x13, x9, x10)

inst_1337:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:3948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3948*FLEN/8, x13, x9, x10)

inst_1338:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:3951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3951*FLEN/8, x13, x9, x10)

inst_1339:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:3954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3954*FLEN/8, x13, x9, x10)

inst_1340:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:3957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3957*FLEN/8, x13, x9, x10)

inst_1341:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:3960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3960*FLEN/8, x13, x9, x10)

inst_1342:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:3963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3963*FLEN/8, x13, x9, x10)

inst_1343:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:3966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3966*FLEN/8, x13, x9, x10)

inst_1344:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:3969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3969*FLEN/8, x13, x9, x10)

inst_1345:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:3972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3972*FLEN/8, x13, x9, x10)

inst_1346:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:3975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3975*FLEN/8, x13, x9, x10)

inst_1347:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:3978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3978*FLEN/8, x13, x9, x10)

inst_1348:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:3981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3981*FLEN/8, x13, x9, x10)

inst_1349:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:3984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3984*FLEN/8, x13, x9, x10)

inst_1350:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:3987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3987*FLEN/8, x13, x9, x10)

inst_1351:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:3990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3990*FLEN/8, x13, x9, x10)

inst_1352:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:3993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3993*FLEN/8, x13, x9, x10)

inst_1353:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:3996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3996*FLEN/8, x13, x9, x10)

inst_1354:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:3999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 3999*FLEN/8, x13, x9, x10)

inst_1355:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:4002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4002*FLEN/8, x13, x9, x10)

inst_1356:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4005*FLEN/8, x13, x9, x10)

inst_1357:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4008*FLEN/8, x13, x9, x10)

inst_1358:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4011*FLEN/8, x13, x9, x10)

inst_1359:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:4014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4014*FLEN/8, x13, x9, x10)

inst_1360:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4017*FLEN/8, x13, x9, x10)

inst_1361:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4020*FLEN/8, x13, x9, x10)

inst_1362:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4023*FLEN/8, x13, x9, x10)

inst_1363:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4026*FLEN/8, x13, x9, x10)

inst_1364:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4029*FLEN/8, x13, x9, x10)

inst_1365:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4032*FLEN/8, x13, x9, x10)

inst_1366:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4035*FLEN/8, x13, x9, x10)

inst_1367:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4038*FLEN/8, x13, x9, x10)

inst_1368:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:4041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4041*FLEN/8, x13, x9, x10)

inst_1369:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:4044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4044*FLEN/8, x13, x9, x10)

inst_1370:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:4047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4047*FLEN/8, x13, x9, x10)

inst_1371:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:4050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4050*FLEN/8, x13, x9, x10)

inst_1372:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:4053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4053*FLEN/8, x13, x9, x10)

inst_1373:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4056*FLEN/8, x13, x9, x10)

inst_1374:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4059*FLEN/8, x13, x9, x10)

inst_1375:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4062*FLEN/8, x13, x9, x10)

inst_1376:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:4065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4065*FLEN/8, x13, x9, x10)

inst_1377:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:4068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4068*FLEN/8, x13, x9, x10)

inst_1378:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:4071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4071*FLEN/8, x13, x9, x10)

inst_1379:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:4074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4074*FLEN/8, x13, x9, x10)

inst_1380:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4077*FLEN/8, x13, x9, x10)

inst_1381:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4080*FLEN/8, x13, x9, x10)

inst_1382:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4083*FLEN/8, x13, x9, x10)

inst_1383:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:4086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4086*FLEN/8, x13, x9, x10)

inst_1384:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4089*FLEN/8, x13, x9, x10)

inst_1385:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4092*FLEN/8, x13, x9, x10)

inst_1386:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4095*FLEN/8, x13, x9, x10)

inst_1387:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4098*FLEN/8, x13, x9, x10)

inst_1388:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4101*FLEN/8, x13, x9, x10)

inst_1389:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4104*FLEN/8, x13, x9, x10)

inst_1390:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4107*FLEN/8, x13, x9, x10)

inst_1391:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4110*FLEN/8, x13, x9, x10)

inst_1392:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:4113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4113*FLEN/8, x13, x9, x10)

inst_1393:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:4116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4116*FLEN/8, x13, x9, x10)

inst_1394:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:4119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4119*FLEN/8, x13, x9, x10)

inst_1395:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:4122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4122*FLEN/8, x13, x9, x10)

inst_1396:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:4125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4125*FLEN/8, x13, x9, x10)

inst_1397:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4128*FLEN/8, x13, x9, x10)

inst_1398:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4131*FLEN/8, x13, x9, x10)

inst_1399:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4134*FLEN/8, x13, x9, x10)

inst_1400:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:4137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4137*FLEN/8, x13, x9, x10)

inst_1401:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:4140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4140*FLEN/8, x13, x9, x10)

inst_1402:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:4143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4143*FLEN/8, x13, x9, x10)

inst_1403:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:4146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4146*FLEN/8, x13, x9, x10)

inst_1404:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4149*FLEN/8, x13, x9, x10)

inst_1405:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4152*FLEN/8, x13, x9, x10)

inst_1406:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4155*FLEN/8, x13, x9, x10)

inst_1407:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:4158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4158*FLEN/8, x13, x9, x10)

inst_1408:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4161*FLEN/8, x13, x9, x10)

inst_1409:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4164*FLEN/8, x13, x9, x10)

inst_1410:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4167*FLEN/8, x13, x9, x10)

inst_1411:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4170*FLEN/8, x13, x9, x10)

inst_1412:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4173*FLEN/8, x13, x9, x10)

inst_1413:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4176*FLEN/8, x13, x9, x10)

inst_1414:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4179*FLEN/8, x13, x9, x10)

inst_1415:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4182*FLEN/8, x13, x9, x10)

inst_1416:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:4185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4185*FLEN/8, x13, x9, x10)

inst_1417:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:4188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4188*FLEN/8, x13, x9, x10)

inst_1418:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:4191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4191*FLEN/8, x13, x9, x10)

inst_1419:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:4194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4194*FLEN/8, x13, x9, x10)

inst_1420:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:4197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4197*FLEN/8, x13, x9, x10)

inst_1421:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4200*FLEN/8, x13, x9, x10)

inst_1422:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4203*FLEN/8, x13, x9, x10)

inst_1423:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4206*FLEN/8, x13, x9, x10)

inst_1424:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:4209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4209*FLEN/8, x13, x9, x10)

inst_1425:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:4212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4212*FLEN/8, x13, x9, x10)

inst_1426:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:4215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4215*FLEN/8, x13, x9, x10)

inst_1427:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:4218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4218*FLEN/8, x13, x9, x10)

inst_1428:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4221*FLEN/8, x13, x9, x10)

inst_1429:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4224*FLEN/8, x13, x9, x10)

inst_1430:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4227*FLEN/8, x13, x9, x10)

inst_1431:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:4230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4230*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_11)

inst_1432:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4233*FLEN/8, x13, x9, x10)

inst_1433:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4236*FLEN/8, x13, x9, x10)

inst_1434:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4239*FLEN/8, x13, x9, x10)

inst_1435:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4242*FLEN/8, x13, x9, x10)

inst_1436:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4245*FLEN/8, x13, x9, x10)

inst_1437:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4248*FLEN/8, x13, x9, x10)

inst_1438:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4251*FLEN/8, x13, x9, x10)

inst_1439:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4254*FLEN/8, x13, x9, x10)

inst_1440:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:4257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4257*FLEN/8, x13, x9, x10)

inst_1441:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:4260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4260*FLEN/8, x13, x9, x10)

inst_1442:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:4263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4263*FLEN/8, x13, x9, x10)

inst_1443:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:4266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4266*FLEN/8, x13, x9, x10)

inst_1444:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:4269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4269*FLEN/8, x13, x9, x10)

inst_1445:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4272*FLEN/8, x13, x9, x10)

inst_1446:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4275*FLEN/8, x13, x9, x10)

inst_1447:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4278*FLEN/8, x13, x9, x10)

inst_1448:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:4281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4281*FLEN/8, x13, x9, x10)

inst_1449:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:4284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4284*FLEN/8, x13, x9, x10)

inst_1450:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:4287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4287*FLEN/8, x13, x9, x10)

inst_1451:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:4290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4290*FLEN/8, x13, x9, x10)

inst_1452:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4293*FLEN/8, x13, x9, x10)

inst_1453:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4296*FLEN/8, x13, x9, x10)

inst_1454:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4299*FLEN/8, x13, x9, x10)

inst_1455:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:4302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4302*FLEN/8, x13, x9, x10)

inst_1456:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4305*FLEN/8, x13, x9, x10)

inst_1457:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4308*FLEN/8, x13, x9, x10)

inst_1458:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4311*FLEN/8, x13, x9, x10)

inst_1459:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4314*FLEN/8, x13, x9, x10)

inst_1460:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4317*FLEN/8, x13, x9, x10)

inst_1461:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4320*FLEN/8, x13, x9, x10)

inst_1462:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4323*FLEN/8, x13, x9, x10)

inst_1463:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4326*FLEN/8, x13, x9, x10)

inst_1464:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:4329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4329*FLEN/8, x13, x9, x10)

inst_1465:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:4332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4332*FLEN/8, x13, x9, x10)

inst_1466:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:4335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4335*FLEN/8, x13, x9, x10)

inst_1467:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:4338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4338*FLEN/8, x13, x9, x10)

inst_1468:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:4341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4341*FLEN/8, x13, x9, x10)

inst_1469:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4344*FLEN/8, x13, x9, x10)

inst_1470:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4347*FLEN/8, x13, x9, x10)

inst_1471:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4350*FLEN/8, x13, x9, x10)

inst_1472:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:4353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4353*FLEN/8, x13, x9, x10)

inst_1473:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:4356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4356*FLEN/8, x13, x9, x10)

inst_1474:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:4359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4359*FLEN/8, x13, x9, x10)

inst_1475:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:4362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4362*FLEN/8, x13, x9, x10)

inst_1476:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4365*FLEN/8, x13, x9, x10)

inst_1477:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4368*FLEN/8, x13, x9, x10)

inst_1478:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4371*FLEN/8, x13, x9, x10)

inst_1479:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:4374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4374*FLEN/8, x13, x9, x10)

inst_1480:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4377*FLEN/8, x13, x9, x10)

inst_1481:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4380*FLEN/8, x13, x9, x10)

inst_1482:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4383*FLEN/8, x13, x9, x10)

inst_1483:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4386*FLEN/8, x13, x9, x10)

inst_1484:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4389*FLEN/8, x13, x9, x10)

inst_1485:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4392*FLEN/8, x13, x9, x10)

inst_1486:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4395*FLEN/8, x13, x9, x10)

inst_1487:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4398*FLEN/8, x13, x9, x10)

inst_1488:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:4401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4401*FLEN/8, x13, x9, x10)

inst_1489:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:4404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4404*FLEN/8, x13, x9, x10)

inst_1490:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:4407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4407*FLEN/8, x13, x9, x10)

inst_1491:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:4410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4410*FLEN/8, x13, x9, x10)

inst_1492:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:4413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4413*FLEN/8, x13, x9, x10)

inst_1493:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4416*FLEN/8, x13, x9, x10)

inst_1494:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4419*FLEN/8, x13, x9, x10)

inst_1495:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4422*FLEN/8, x13, x9, x10)

inst_1496:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:4425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4425*FLEN/8, x13, x9, x10)

inst_1497:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:4428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4428*FLEN/8, x13, x9, x10)

inst_1498:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:4431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4431*FLEN/8, x13, x9, x10)

inst_1499:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:4434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4434*FLEN/8, x13, x9, x10)

inst_1500:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4437*FLEN/8, x13, x9, x10)

inst_1501:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4440*FLEN/8, x13, x9, x10)

inst_1502:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4443*FLEN/8, x13, x9, x10)

inst_1503:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:4446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4446*FLEN/8, x13, x9, x10)

inst_1504:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4449*FLEN/8, x13, x9, x10)

inst_1505:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4452*FLEN/8, x13, x9, x10)

inst_1506:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4455*FLEN/8, x13, x9, x10)

inst_1507:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4458*FLEN/8, x13, x9, x10)

inst_1508:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4461*FLEN/8, x13, x9, x10)

inst_1509:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4464*FLEN/8, x13, x9, x10)

inst_1510:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4467*FLEN/8, x13, x9, x10)

inst_1511:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4470*FLEN/8, x13, x9, x10)

inst_1512:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:4473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4473*FLEN/8, x13, x9, x10)

inst_1513:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:4476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4476*FLEN/8, x13, x9, x10)

inst_1514:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:4479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4479*FLEN/8, x13, x9, x10)

inst_1515:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:4482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4482*FLEN/8, x13, x9, x10)

inst_1516:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:4485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4485*FLEN/8, x13, x9, x10)

inst_1517:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4488*FLEN/8, x13, x9, x10)

inst_1518:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4491*FLEN/8, x13, x9, x10)

inst_1519:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4494*FLEN/8, x13, x9, x10)

inst_1520:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:4497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4497*FLEN/8, x13, x9, x10)

inst_1521:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:4500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4500*FLEN/8, x13, x9, x10)

inst_1522:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:4503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4503*FLEN/8, x13, x9, x10)

inst_1523:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:4506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4506*FLEN/8, x13, x9, x10)

inst_1524:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4509*FLEN/8, x13, x9, x10)

inst_1525:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4512*FLEN/8, x13, x9, x10)

inst_1526:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4515*FLEN/8, x13, x9, x10)

inst_1527:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:4518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4518*FLEN/8, x13, x9, x10)

inst_1528:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4521*FLEN/8, x13, x9, x10)

inst_1529:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4524*FLEN/8, x13, x9, x10)

inst_1530:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4527*FLEN/8, x13, x9, x10)

inst_1531:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4530*FLEN/8, x13, x9, x10)

inst_1532:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4533*FLEN/8, x13, x9, x10)

inst_1533:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4536*FLEN/8, x13, x9, x10)

inst_1534:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4539*FLEN/8, x13, x9, x10)

inst_1535:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4542*FLEN/8, x13, x9, x10)

inst_1536:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:4545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4545*FLEN/8, x13, x9, x10)

inst_1537:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:4548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4548*FLEN/8, x13, x9, x10)

inst_1538:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:4551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4551*FLEN/8, x13, x9, x10)

inst_1539:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:4554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4554*FLEN/8, x13, x9, x10)

inst_1540:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:4557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4557*FLEN/8, x13, x9, x10)

inst_1541:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4560*FLEN/8, x13, x9, x10)

inst_1542:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4563*FLEN/8, x13, x9, x10)

inst_1543:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4566*FLEN/8, x13, x9, x10)

inst_1544:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:4569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4569*FLEN/8, x13, x9, x10)

inst_1545:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:4572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4572*FLEN/8, x13, x9, x10)

inst_1546:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:4575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4575*FLEN/8, x13, x9, x10)

inst_1547:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:4578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4578*FLEN/8, x13, x9, x10)

inst_1548:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4581*FLEN/8, x13, x9, x10)

inst_1549:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4584*FLEN/8, x13, x9, x10)

inst_1550:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4587*FLEN/8, x13, x9, x10)

inst_1551:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:4590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4590*FLEN/8, x13, x9, x10)

inst_1552:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4593*FLEN/8, x13, x9, x10)

inst_1553:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4596*FLEN/8, x13, x9, x10)

inst_1554:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4599*FLEN/8, x13, x9, x10)

inst_1555:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4602*FLEN/8, x13, x9, x10)

inst_1556:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4605*FLEN/8, x13, x9, x10)

inst_1557:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4608*FLEN/8, x13, x9, x10)

inst_1558:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4611*FLEN/8, x13, x9, x10)

inst_1559:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4614*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_12)

inst_1560:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:4617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4617*FLEN/8, x13, x9, x10)

inst_1561:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:4620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4620*FLEN/8, x13, x9, x10)

inst_1562:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:4623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4623*FLEN/8, x13, x9, x10)

inst_1563:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:4626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4626*FLEN/8, x13, x9, x10)

inst_1564:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:4629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4629*FLEN/8, x13, x9, x10)

inst_1565:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4632*FLEN/8, x13, x9, x10)

inst_1566:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4635*FLEN/8, x13, x9, x10)

inst_1567:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4638*FLEN/8, x13, x9, x10)

inst_1568:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:4641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4641*FLEN/8, x13, x9, x10)

inst_1569:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:4644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4644*FLEN/8, x13, x9, x10)

inst_1570:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:4647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4647*FLEN/8, x13, x9, x10)

inst_1571:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:4650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4650*FLEN/8, x13, x9, x10)

inst_1572:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4653*FLEN/8, x13, x9, x10)

inst_1573:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4656*FLEN/8, x13, x9, x10)

inst_1574:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4659*FLEN/8, x13, x9, x10)

inst_1575:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:4662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4662*FLEN/8, x13, x9, x10)

inst_1576:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4665*FLEN/8, x13, x9, x10)

inst_1577:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4668*FLEN/8, x13, x9, x10)

inst_1578:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4671*FLEN/8, x13, x9, x10)

inst_1579:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4674*FLEN/8, x13, x9, x10)

inst_1580:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4677*FLEN/8, x13, x9, x10)

inst_1581:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4680*FLEN/8, x13, x9, x10)

inst_1582:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4683*FLEN/8, x13, x9, x10)

inst_1583:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4686*FLEN/8, x13, x9, x10)

inst_1584:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:4689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4689*FLEN/8, x13, x9, x10)

inst_1585:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:4692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4692*FLEN/8, x13, x9, x10)

inst_1586:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:4695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4695*FLEN/8, x13, x9, x10)

inst_1587:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:4698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4698*FLEN/8, x13, x9, x10)

inst_1588:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:4701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4701*FLEN/8, x13, x9, x10)

inst_1589:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4704*FLEN/8, x13, x9, x10)

inst_1590:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4707*FLEN/8, x13, x9, x10)

inst_1591:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4710*FLEN/8, x13, x9, x10)

inst_1592:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:4713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4713*FLEN/8, x13, x9, x10)

inst_1593:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:4716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4716*FLEN/8, x13, x9, x10)

inst_1594:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:4719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4719*FLEN/8, x13, x9, x10)

inst_1595:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:4722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4722*FLEN/8, x13, x9, x10)

inst_1596:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4725*FLEN/8, x13, x9, x10)

inst_1597:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4728*FLEN/8, x13, x9, x10)

inst_1598:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4731*FLEN/8, x13, x9, x10)

inst_1599:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:4734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4734*FLEN/8, x13, x9, x10)

inst_1600:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4737*FLEN/8, x13, x9, x10)

inst_1601:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4740*FLEN/8, x13, x9, x10)

inst_1602:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4743*FLEN/8, x13, x9, x10)

inst_1603:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4746*FLEN/8, x13, x9, x10)

inst_1604:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4749*FLEN/8, x13, x9, x10)

inst_1605:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4752*FLEN/8, x13, x9, x10)

inst_1606:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4755*FLEN/8, x13, x9, x10)

inst_1607:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4758*FLEN/8, x13, x9, x10)

inst_1608:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:4761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4761*FLEN/8, x13, x9, x10)

inst_1609:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:4764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4764*FLEN/8, x13, x9, x10)

inst_1610:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:4767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4767*FLEN/8, x13, x9, x10)

inst_1611:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:4770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4770*FLEN/8, x13, x9, x10)

inst_1612:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:4773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4773*FLEN/8, x13, x9, x10)

inst_1613:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4776*FLEN/8, x13, x9, x10)

inst_1614:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4779*FLEN/8, x13, x9, x10)

inst_1615:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4782*FLEN/8, x13, x9, x10)

inst_1616:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:4785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4785*FLEN/8, x13, x9, x10)

inst_1617:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:4788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4788*FLEN/8, x13, x9, x10)

inst_1618:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:4791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4791*FLEN/8, x13, x9, x10)

inst_1619:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:4794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4794*FLEN/8, x13, x9, x10)

inst_1620:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4797*FLEN/8, x13, x9, x10)

inst_1621:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4800*FLEN/8, x13, x9, x10)

inst_1622:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4803*FLEN/8, x13, x9, x10)

inst_1623:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:4806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4806*FLEN/8, x13, x9, x10)

inst_1624:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4809*FLEN/8, x13, x9, x10)

inst_1625:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4812*FLEN/8, x13, x9, x10)

inst_1626:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4815*FLEN/8, x13, x9, x10)

inst_1627:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4818*FLEN/8, x13, x9, x10)

inst_1628:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4821*FLEN/8, x13, x9, x10)

inst_1629:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4824*FLEN/8, x13, x9, x10)

inst_1630:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4827*FLEN/8, x13, x9, x10)

inst_1631:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4830*FLEN/8, x13, x9, x10)

inst_1632:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:4833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4833*FLEN/8, x13, x9, x10)

inst_1633:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:4836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4836*FLEN/8, x13, x9, x10)

inst_1634:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:4839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4839*FLEN/8, x13, x9, x10)

inst_1635:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:4842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4842*FLEN/8, x13, x9, x10)

inst_1636:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:4845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4845*FLEN/8, x13, x9, x10)

inst_1637:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4848*FLEN/8, x13, x9, x10)

inst_1638:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4851*FLEN/8, x13, x9, x10)

inst_1639:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4854*FLEN/8, x13, x9, x10)

inst_1640:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:4857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4857*FLEN/8, x13, x9, x10)

inst_1641:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:4860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4860*FLEN/8, x13, x9, x10)

inst_1642:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:4863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4863*FLEN/8, x13, x9, x10)

inst_1643:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:4866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4866*FLEN/8, x13, x9, x10)

inst_1644:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4869*FLEN/8, x13, x9, x10)

inst_1645:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4872*FLEN/8, x13, x9, x10)

inst_1646:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4875*FLEN/8, x13, x9, x10)

inst_1647:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:4878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4878*FLEN/8, x13, x9, x10)

inst_1648:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4881*FLEN/8, x13, x9, x10)

inst_1649:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4884*FLEN/8, x13, x9, x10)

inst_1650:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4887*FLEN/8, x13, x9, x10)

inst_1651:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4890*FLEN/8, x13, x9, x10)

inst_1652:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4893*FLEN/8, x13, x9, x10)

inst_1653:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4896*FLEN/8, x13, x9, x10)

inst_1654:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4899*FLEN/8, x13, x9, x10)

inst_1655:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4902*FLEN/8, x13, x9, x10)

inst_1656:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:4905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4905*FLEN/8, x13, x9, x10)

inst_1657:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:4908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4908*FLEN/8, x13, x9, x10)

inst_1658:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:4911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4911*FLEN/8, x13, x9, x10)

inst_1659:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:4914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4914*FLEN/8, x13, x9, x10)

inst_1660:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:4917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4917*FLEN/8, x13, x9, x10)

inst_1661:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4920*FLEN/8, x13, x9, x10)

inst_1662:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4923*FLEN/8, x13, x9, x10)

inst_1663:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4926*FLEN/8, x13, x9, x10)

inst_1664:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:4929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4929*FLEN/8, x13, x9, x10)

inst_1665:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:4932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4932*FLEN/8, x13, x9, x10)

inst_1666:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:4935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4935*FLEN/8, x13, x9, x10)

inst_1667:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:4938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4938*FLEN/8, x13, x9, x10)

inst_1668:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:4941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4941*FLEN/8, x13, x9, x10)

inst_1669:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:4944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4944*FLEN/8, x13, x9, x10)

inst_1670:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:4947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4947*FLEN/8, x13, x9, x10)

inst_1671:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:4950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4950*FLEN/8, x13, x9, x10)

inst_1672:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:4953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4953*FLEN/8, x13, x9, x10)

inst_1673:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:4956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4956*FLEN/8, x13, x9, x10)

inst_1674:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:4959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4959*FLEN/8, x13, x9, x10)

inst_1675:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:4962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4962*FLEN/8, x13, x9, x10)

inst_1676:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:4965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4965*FLEN/8, x13, x9, x10)

inst_1677:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:4968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4968*FLEN/8, x13, x9, x10)

inst_1678:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:4971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4971*FLEN/8, x13, x9, x10)

inst_1679:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:4974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4974*FLEN/8, x13, x9, x10)

inst_1680:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:4977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4977*FLEN/8, x13, x9, x10)

inst_1681:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:4980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4980*FLEN/8, x13, x9, x10)

inst_1682:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:4983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4983*FLEN/8, x13, x9, x10)

inst_1683:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:4986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4986*FLEN/8, x13, x9, x10)

inst_1684:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:4989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4989*FLEN/8, x13, x9, x10)

inst_1685:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:4992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4992*FLEN/8, x13, x9, x10)

inst_1686:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:4995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4995*FLEN/8, x13, x9, x10)

inst_1687:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:4998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 4998*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_13)

inst_1688:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:5001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5001*FLEN/8, x13, x9, x10)

inst_1689:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:5004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5004*FLEN/8, x13, x9, x10)

inst_1690:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:5007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5007*FLEN/8, x13, x9, x10)

inst_1691:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:5010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5010*FLEN/8, x13, x9, x10)

inst_1692:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5013*FLEN/8, x13, x9, x10)

inst_1693:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5016*FLEN/8, x13, x9, x10)

inst_1694:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5019*FLEN/8, x13, x9, x10)

inst_1695:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:5022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5022*FLEN/8, x13, x9, x10)

inst_1696:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5025*FLEN/8, x13, x9, x10)

inst_1697:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5028*FLEN/8, x13, x9, x10)

inst_1698:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5031*FLEN/8, x13, x9, x10)

inst_1699:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5034*FLEN/8, x13, x9, x10)

inst_1700:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5037*FLEN/8, x13, x9, x10)

inst_1701:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5040*FLEN/8, x13, x9, x10)

inst_1702:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5043*FLEN/8, x13, x9, x10)

inst_1703:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5046*FLEN/8, x13, x9, x10)

inst_1704:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:5049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5049*FLEN/8, x13, x9, x10)

inst_1705:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:5052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5052*FLEN/8, x13, x9, x10)

inst_1706:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:5055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5055*FLEN/8, x13, x9, x10)

inst_1707:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:5058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5058*FLEN/8, x13, x9, x10)

inst_1708:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:5061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5061*FLEN/8, x13, x9, x10)

inst_1709:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5064*FLEN/8, x13, x9, x10)

inst_1710:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5067*FLEN/8, x13, x9, x10)

inst_1711:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5070*FLEN/8, x13, x9, x10)

inst_1712:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:5073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5073*FLEN/8, x13, x9, x10)

inst_1713:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:5076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5076*FLEN/8, x13, x9, x10)

inst_1714:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:5079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5079*FLEN/8, x13, x9, x10)

inst_1715:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:5082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5082*FLEN/8, x13, x9, x10)

inst_1716:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5085*FLEN/8, x13, x9, x10)

inst_1717:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5088*FLEN/8, x13, x9, x10)

inst_1718:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5091*FLEN/8, x13, x9, x10)

inst_1719:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:5094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5094*FLEN/8, x13, x9, x10)

inst_1720:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5097*FLEN/8, x13, x9, x10)

inst_1721:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5100*FLEN/8, x13, x9, x10)

inst_1722:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5103*FLEN/8, x13, x9, x10)

inst_1723:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5106*FLEN/8, x13, x9, x10)

inst_1724:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5109*FLEN/8, x13, x9, x10)

inst_1725:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5112*FLEN/8, x13, x9, x10)

inst_1726:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5115*FLEN/8, x13, x9, x10)

inst_1727:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5118*FLEN/8, x13, x9, x10)

inst_1728:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:5121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5121*FLEN/8, x13, x9, x10)

inst_1729:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:5124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5124*FLEN/8, x13, x9, x10)

inst_1730:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:5127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5127*FLEN/8, x13, x9, x10)

inst_1731:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:5130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5130*FLEN/8, x13, x9, x10)

inst_1732:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:5133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5133*FLEN/8, x13, x9, x10)

inst_1733:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5136*FLEN/8, x13, x9, x10)

inst_1734:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5139*FLEN/8, x13, x9, x10)

inst_1735:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5142*FLEN/8, x13, x9, x10)

inst_1736:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:5145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5145*FLEN/8, x13, x9, x10)

inst_1737:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:5148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5148*FLEN/8, x13, x9, x10)

inst_1738:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:5151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5151*FLEN/8, x13, x9, x10)

inst_1739:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:5154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5154*FLEN/8, x13, x9, x10)

inst_1740:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5157*FLEN/8, x13, x9, x10)

inst_1741:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5160*FLEN/8, x13, x9, x10)

inst_1742:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5163*FLEN/8, x13, x9, x10)

inst_1743:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:5166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5166*FLEN/8, x13, x9, x10)

inst_1744:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5169*FLEN/8, x13, x9, x10)

inst_1745:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5172*FLEN/8, x13, x9, x10)

inst_1746:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5175*FLEN/8, x13, x9, x10)

inst_1747:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5178*FLEN/8, x13, x9, x10)

inst_1748:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5181*FLEN/8, x13, x9, x10)

inst_1749:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5184*FLEN/8, x13, x9, x10)

inst_1750:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5187*FLEN/8, x13, x9, x10)

inst_1751:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5190*FLEN/8, x13, x9, x10)

inst_1752:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:5193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5193*FLEN/8, x13, x9, x10)

inst_1753:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:5196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5196*FLEN/8, x13, x9, x10)

inst_1754:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:5199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5199*FLEN/8, x13, x9, x10)

inst_1755:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:5202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5202*FLEN/8, x13, x9, x10)

inst_1756:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:5205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5205*FLEN/8, x13, x9, x10)

inst_1757:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5208*FLEN/8, x13, x9, x10)

inst_1758:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5211*FLEN/8, x13, x9, x10)

inst_1759:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5214*FLEN/8, x13, x9, x10)

inst_1760:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:5217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5217*FLEN/8, x13, x9, x10)

inst_1761:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:5220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5220*FLEN/8, x13, x9, x10)

inst_1762:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:5223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5223*FLEN/8, x13, x9, x10)

inst_1763:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:5226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5226*FLEN/8, x13, x9, x10)

inst_1764:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5229*FLEN/8, x13, x9, x10)

inst_1765:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5232*FLEN/8, x13, x9, x10)

inst_1766:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5235*FLEN/8, x13, x9, x10)

inst_1767:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:5238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5238*FLEN/8, x13, x9, x10)

inst_1768:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5241*FLEN/8, x13, x9, x10)

inst_1769:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5244*FLEN/8, x13, x9, x10)

inst_1770:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5247*FLEN/8, x13, x9, x10)

inst_1771:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5250*FLEN/8, x13, x9, x10)

inst_1772:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5253*FLEN/8, x13, x9, x10)

inst_1773:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5256*FLEN/8, x13, x9, x10)

inst_1774:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5259*FLEN/8, x13, x9, x10)

inst_1775:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5262*FLEN/8, x13, x9, x10)

inst_1776:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:5265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5265*FLEN/8, x13, x9, x10)

inst_1777:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:5268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5268*FLEN/8, x13, x9, x10)

inst_1778:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:5271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5271*FLEN/8, x13, x9, x10)

inst_1779:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:5274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5274*FLEN/8, x13, x9, x10)

inst_1780:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:5277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5277*FLEN/8, x13, x9, x10)

inst_1781:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5280*FLEN/8, x13, x9, x10)

inst_1782:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5283*FLEN/8, x13, x9, x10)

inst_1783:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5286*FLEN/8, x13, x9, x10)

inst_1784:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:5289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5289*FLEN/8, x13, x9, x10)

inst_1785:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:5292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5292*FLEN/8, x13, x9, x10)

inst_1786:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:5295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5295*FLEN/8, x13, x9, x10)

inst_1787:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:5298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5298*FLEN/8, x13, x9, x10)

inst_1788:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5301*FLEN/8, x13, x9, x10)

inst_1789:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5304*FLEN/8, x13, x9, x10)

inst_1790:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5307*FLEN/8, x13, x9, x10)

inst_1791:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:5310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5310*FLEN/8, x13, x9, x10)

inst_1792:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5313*FLEN/8, x13, x9, x10)

inst_1793:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5316*FLEN/8, x13, x9, x10)

inst_1794:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5319*FLEN/8, x13, x9, x10)

inst_1795:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5322*FLEN/8, x13, x9, x10)

inst_1796:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5325*FLEN/8, x13, x9, x10)

inst_1797:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5328*FLEN/8, x13, x9, x10)

inst_1798:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5331*FLEN/8, x13, x9, x10)

inst_1799:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5334*FLEN/8, x13, x9, x10)

inst_1800:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:5337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5337*FLEN/8, x13, x9, x10)

inst_1801:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:5340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5340*FLEN/8, x13, x9, x10)

inst_1802:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:5343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5343*FLEN/8, x13, x9, x10)

inst_1803:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:5346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5346*FLEN/8, x13, x9, x10)

inst_1804:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:5349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5349*FLEN/8, x13, x9, x10)

inst_1805:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5352*FLEN/8, x13, x9, x10)

inst_1806:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5355*FLEN/8, x13, x9, x10)

inst_1807:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5358*FLEN/8, x13, x9, x10)

inst_1808:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:5361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5361*FLEN/8, x13, x9, x10)

inst_1809:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:5364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5364*FLEN/8, x13, x9, x10)

inst_1810:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:5367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5367*FLEN/8, x13, x9, x10)

inst_1811:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:5370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5370*FLEN/8, x13, x9, x10)

inst_1812:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5373*FLEN/8, x13, x9, x10)

inst_1813:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5376*FLEN/8, x13, x9, x10)

inst_1814:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5379*FLEN/8, x13, x9, x10)

inst_1815:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:5382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5382*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_14)

inst_1816:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5385*FLEN/8, x13, x9, x10)

inst_1817:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5388*FLEN/8, x13, x9, x10)

inst_1818:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5391*FLEN/8, x13, x9, x10)

inst_1819:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5394*FLEN/8, x13, x9, x10)

inst_1820:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5397*FLEN/8, x13, x9, x10)

inst_1821:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5400*FLEN/8, x13, x9, x10)

inst_1822:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5403*FLEN/8, x13, x9, x10)

inst_1823:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5406*FLEN/8, x13, x9, x10)

inst_1824:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:5409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5409*FLEN/8, x13, x9, x10)

inst_1825:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:5412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5412*FLEN/8, x13, x9, x10)

inst_1826:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:5415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5415*FLEN/8, x13, x9, x10)

inst_1827:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:5418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5418*FLEN/8, x13, x9, x10)

inst_1828:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:5421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5421*FLEN/8, x13, x9, x10)

inst_1829:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5424*FLEN/8, x13, x9, x10)

inst_1830:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5427*FLEN/8, x13, x9, x10)

inst_1831:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5430*FLEN/8, x13, x9, x10)

inst_1832:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:5433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5433*FLEN/8, x13, x9, x10)

inst_1833:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:5436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5436*FLEN/8, x13, x9, x10)

inst_1834:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:5439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5439*FLEN/8, x13, x9, x10)

inst_1835:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:5442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5442*FLEN/8, x13, x9, x10)

inst_1836:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5445*FLEN/8, x13, x9, x10)

inst_1837:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5448*FLEN/8, x13, x9, x10)

inst_1838:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5451*FLEN/8, x13, x9, x10)

inst_1839:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:5454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5454*FLEN/8, x13, x9, x10)

inst_1840:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5457*FLEN/8, x13, x9, x10)

inst_1841:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5460*FLEN/8, x13, x9, x10)

inst_1842:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5463*FLEN/8, x13, x9, x10)

inst_1843:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5466*FLEN/8, x13, x9, x10)

inst_1844:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5469*FLEN/8, x13, x9, x10)

inst_1845:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5472*FLEN/8, x13, x9, x10)

inst_1846:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5475*FLEN/8, x13, x9, x10)

inst_1847:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5478*FLEN/8, x13, x9, x10)

inst_1848:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:5481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5481*FLEN/8, x13, x9, x10)

inst_1849:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:5484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5484*FLEN/8, x13, x9, x10)

inst_1850:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:5487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5487*FLEN/8, x13, x9, x10)

inst_1851:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:5490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5490*FLEN/8, x13, x9, x10)

inst_1852:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:5493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5493*FLEN/8, x13, x9, x10)

inst_1853:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5496*FLEN/8, x13, x9, x10)

inst_1854:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5499*FLEN/8, x13, x9, x10)

inst_1855:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5502*FLEN/8, x13, x9, x10)

inst_1856:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:5505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5505*FLEN/8, x13, x9, x10)

inst_1857:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:5508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5508*FLEN/8, x13, x9, x10)

inst_1858:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:5511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5511*FLEN/8, x13, x9, x10)

inst_1859:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:5514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5514*FLEN/8, x13, x9, x10)

inst_1860:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5517*FLEN/8, x13, x9, x10)

inst_1861:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5520*FLEN/8, x13, x9, x10)

inst_1862:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5523*FLEN/8, x13, x9, x10)

inst_1863:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:5526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5526*FLEN/8, x13, x9, x10)

inst_1864:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5529*FLEN/8, x13, x9, x10)

inst_1865:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5532*FLEN/8, x13, x9, x10)

inst_1866:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5535*FLEN/8, x13, x9, x10)

inst_1867:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5538*FLEN/8, x13, x9, x10)

inst_1868:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5541*FLEN/8, x13, x9, x10)

inst_1869:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5544*FLEN/8, x13, x9, x10)

inst_1870:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5547*FLEN/8, x13, x9, x10)

inst_1871:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5550*FLEN/8, x13, x9, x10)

inst_1872:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:5553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5553*FLEN/8, x13, x9, x10)

inst_1873:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:5556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5556*FLEN/8, x13, x9, x10)

inst_1874:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:5559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5559*FLEN/8, x13, x9, x10)

inst_1875:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:5562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5562*FLEN/8, x13, x9, x10)

inst_1876:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:5565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5565*FLEN/8, x13, x9, x10)

inst_1877:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5568*FLEN/8, x13, x9, x10)

inst_1878:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5571*FLEN/8, x13, x9, x10)

inst_1879:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5574*FLEN/8, x13, x9, x10)

inst_1880:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:5577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5577*FLEN/8, x13, x9, x10)

inst_1881:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:5580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5580*FLEN/8, x13, x9, x10)

inst_1882:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:5583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5583*FLEN/8, x13, x9, x10)

inst_1883:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:5586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5586*FLEN/8, x13, x9, x10)

inst_1884:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5589*FLEN/8, x13, x9, x10)

inst_1885:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5592*FLEN/8, x13, x9, x10)

inst_1886:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5595*FLEN/8, x13, x9, x10)

inst_1887:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:5598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5598*FLEN/8, x13, x9, x10)

inst_1888:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5601*FLEN/8, x13, x9, x10)

inst_1889:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5604*FLEN/8, x13, x9, x10)

inst_1890:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5607*FLEN/8, x13, x9, x10)

inst_1891:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5610*FLEN/8, x13, x9, x10)

inst_1892:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5613*FLEN/8, x13, x9, x10)

inst_1893:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5616*FLEN/8, x13, x9, x10)

inst_1894:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5619*FLEN/8, x13, x9, x10)

inst_1895:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5622*FLEN/8, x13, x9, x10)

inst_1896:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:5625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5625*FLEN/8, x13, x9, x10)

inst_1897:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:5628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5628*FLEN/8, x13, x9, x10)

inst_1898:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:5631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5631*FLEN/8, x13, x9, x10)

inst_1899:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:5634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5634*FLEN/8, x13, x9, x10)

inst_1900:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:5637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5637*FLEN/8, x13, x9, x10)

inst_1901:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5640*FLEN/8, x13, x9, x10)

inst_1902:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5643*FLEN/8, x13, x9, x10)

inst_1903:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5646*FLEN/8, x13, x9, x10)

inst_1904:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:5649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5649*FLEN/8, x13, x9, x10)

inst_1905:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:5652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5652*FLEN/8, x13, x9, x10)

inst_1906:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:5655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5655*FLEN/8, x13, x9, x10)

inst_1907:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:5658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5658*FLEN/8, x13, x9, x10)

inst_1908:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5661*FLEN/8, x13, x9, x10)

inst_1909:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5664*FLEN/8, x13, x9, x10)

inst_1910:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5667*FLEN/8, x13, x9, x10)

inst_1911:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:5670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5670*FLEN/8, x13, x9, x10)

inst_1912:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5673*FLEN/8, x13, x9, x10)

inst_1913:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5676*FLEN/8, x13, x9, x10)

inst_1914:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5679*FLEN/8, x13, x9, x10)

inst_1915:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5682*FLEN/8, x13, x9, x10)

inst_1916:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5685*FLEN/8, x13, x9, x10)

inst_1917:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5688*FLEN/8, x13, x9, x10)

inst_1918:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5691*FLEN/8, x13, x9, x10)

inst_1919:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5694*FLEN/8, x13, x9, x10)

inst_1920:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:5697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5697*FLEN/8, x13, x9, x10)

inst_1921:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:5700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5700*FLEN/8, x13, x9, x10)

inst_1922:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:5703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5703*FLEN/8, x13, x9, x10)

inst_1923:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:5706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5706*FLEN/8, x13, x9, x10)

inst_1924:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:5709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5709*FLEN/8, x13, x9, x10)

inst_1925:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5712*FLEN/8, x13, x9, x10)

inst_1926:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5715*FLEN/8, x13, x9, x10)

inst_1927:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5718*FLEN/8, x13, x9, x10)

inst_1928:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:5721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5721*FLEN/8, x13, x9, x10)

inst_1929:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:5724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5724*FLEN/8, x13, x9, x10)

inst_1930:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:5727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5727*FLEN/8, x13, x9, x10)

inst_1931:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:5730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5730*FLEN/8, x13, x9, x10)

inst_1932:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5733*FLEN/8, x13, x9, x10)

inst_1933:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5736*FLEN/8, x13, x9, x10)

inst_1934:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5739*FLEN/8, x13, x9, x10)

inst_1935:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:5742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5742*FLEN/8, x13, x9, x10)

inst_1936:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5745*FLEN/8, x13, x9, x10)

inst_1937:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5748*FLEN/8, x13, x9, x10)

inst_1938:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5751*FLEN/8, x13, x9, x10)

inst_1939:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5754*FLEN/8, x13, x9, x10)

inst_1940:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5757*FLEN/8, x13, x9, x10)

inst_1941:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5760*FLEN/8, x13, x9, x10)

inst_1942:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5763*FLEN/8, x13, x9, x10)

inst_1943:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5766*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_15)

inst_1944:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:5769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5769*FLEN/8, x13, x9, x10)

inst_1945:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:5772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5772*FLEN/8, x13, x9, x10)

inst_1946:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:5775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5775*FLEN/8, x13, x9, x10)

inst_1947:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:5778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5778*FLEN/8, x13, x9, x10)

inst_1948:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:5781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5781*FLEN/8, x13, x9, x10)

inst_1949:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5784*FLEN/8, x13, x9, x10)

inst_1950:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5787*FLEN/8, x13, x9, x10)

inst_1951:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5790*FLEN/8, x13, x9, x10)

inst_1952:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:5793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5793*FLEN/8, x13, x9, x10)

inst_1953:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:5796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5796*FLEN/8, x13, x9, x10)

inst_1954:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:5799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5799*FLEN/8, x13, x9, x10)

inst_1955:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:5802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5802*FLEN/8, x13, x9, x10)

inst_1956:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5805*FLEN/8, x13, x9, x10)

inst_1957:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5808*FLEN/8, x13, x9, x10)

inst_1958:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5811*FLEN/8, x13, x9, x10)

inst_1959:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:5814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5814*FLEN/8, x13, x9, x10)

inst_1960:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5817*FLEN/8, x13, x9, x10)

inst_1961:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5820*FLEN/8, x13, x9, x10)

inst_1962:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5823*FLEN/8, x13, x9, x10)

inst_1963:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5826*FLEN/8, x13, x9, x10)

inst_1964:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5829*FLEN/8, x13, x9, x10)

inst_1965:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5832*FLEN/8, x13, x9, x10)

inst_1966:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5835*FLEN/8, x13, x9, x10)

inst_1967:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5838*FLEN/8, x13, x9, x10)

inst_1968:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:5841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5841*FLEN/8, x13, x9, x10)

inst_1969:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:5844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5844*FLEN/8, x13, x9, x10)

inst_1970:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:5847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5847*FLEN/8, x13, x9, x10)

inst_1971:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:5850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5850*FLEN/8, x13, x9, x10)

inst_1972:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:5853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5853*FLEN/8, x13, x9, x10)

inst_1973:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5856*FLEN/8, x13, x9, x10)

inst_1974:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5859*FLEN/8, x13, x9, x10)

inst_1975:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5862*FLEN/8, x13, x9, x10)

inst_1976:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:5865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5865*FLEN/8, x13, x9, x10)

inst_1977:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:5868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5868*FLEN/8, x13, x9, x10)

inst_1978:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:5871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5871*FLEN/8, x13, x9, x10)

inst_1979:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:5874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5874*FLEN/8, x13, x9, x10)

inst_1980:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5877*FLEN/8, x13, x9, x10)

inst_1981:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5880*FLEN/8, x13, x9, x10)

inst_1982:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5883*FLEN/8, x13, x9, x10)

inst_1983:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:5886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5886*FLEN/8, x13, x9, x10)

inst_1984:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5889*FLEN/8, x13, x9, x10)

inst_1985:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5892*FLEN/8, x13, x9, x10)

inst_1986:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5895*FLEN/8, x13, x9, x10)

inst_1987:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5898*FLEN/8, x13, x9, x10)

inst_1988:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5901*FLEN/8, x13, x9, x10)

inst_1989:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5904*FLEN/8, x13, x9, x10)

inst_1990:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5907*FLEN/8, x13, x9, x10)

inst_1991:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5910*FLEN/8, x13, x9, x10)

inst_1992:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:5913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5913*FLEN/8, x13, x9, x10)

inst_1993:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:5916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5916*FLEN/8, x13, x9, x10)

inst_1994:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:5919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5919*FLEN/8, x13, x9, x10)

inst_1995:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:5922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5922*FLEN/8, x13, x9, x10)

inst_1996:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:5925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5925*FLEN/8, x13, x9, x10)

inst_1997:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:5928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5928*FLEN/8, x13, x9, x10)

inst_1998:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:5931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5931*FLEN/8, x13, x9, x10)

inst_1999:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:5934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5934*FLEN/8, x13, x9, x10)

inst_2000:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:5937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5937*FLEN/8, x13, x9, x10)

inst_2001:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:5940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5940*FLEN/8, x13, x9, x10)

inst_2002:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:5943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5943*FLEN/8, x13, x9, x10)

inst_2003:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:5946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5946*FLEN/8, x13, x9, x10)

inst_2004:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:5949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5949*FLEN/8, x13, x9, x10)

inst_2005:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:5952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5952*FLEN/8, x13, x9, x10)

inst_2006:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:5955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5955*FLEN/8, x13, x9, x10)

inst_2007:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:5958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5958*FLEN/8, x13, x9, x10)

inst_2008:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:5961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5961*FLEN/8, x13, x9, x10)

inst_2009:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:5964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5964*FLEN/8, x13, x9, x10)

inst_2010:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:5967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5967*FLEN/8, x13, x9, x10)

inst_2011:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:5970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5970*FLEN/8, x13, x9, x10)

inst_2012:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:5973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5973*FLEN/8, x13, x9, x10)

inst_2013:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:5976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5976*FLEN/8, x13, x9, x10)

inst_2014:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:5979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5979*FLEN/8, x13, x9, x10)

inst_2015:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:5982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5982*FLEN/8, x13, x9, x10)

inst_2016:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:5985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5985*FLEN/8, x13, x9, x10)

inst_2017:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:5988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5988*FLEN/8, x13, x9, x10)

inst_2018:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:5991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5991*FLEN/8, x13, x9, x10)

inst_2019:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:5994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5994*FLEN/8, x13, x9, x10)

inst_2020:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:5997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 5997*FLEN/8, x13, x9, x10)

inst_2021:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6000*FLEN/8, x13, x9, x10)

inst_2022:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6003*FLEN/8, x13, x9, x10)

inst_2023:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6006*FLEN/8, x13, x9, x10)

inst_2024:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:6009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6009*FLEN/8, x13, x9, x10)

inst_2025:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:6012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6012*FLEN/8, x13, x9, x10)

inst_2026:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:6015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6015*FLEN/8, x13, x9, x10)

inst_2027:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:6018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6018*FLEN/8, x13, x9, x10)

inst_2028:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6021*FLEN/8, x13, x9, x10)

inst_2029:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6024*FLEN/8, x13, x9, x10)

inst_2030:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6027*FLEN/8, x13, x9, x10)

inst_2031:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:6030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6030*FLEN/8, x13, x9, x10)

inst_2032:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6033*FLEN/8, x13, x9, x10)

inst_2033:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6036*FLEN/8, x13, x9, x10)

inst_2034:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6039*FLEN/8, x13, x9, x10)

inst_2035:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6042*FLEN/8, x13, x9, x10)

inst_2036:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6045*FLEN/8, x13, x9, x10)

inst_2037:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6048*FLEN/8, x13, x9, x10)

inst_2038:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6051*FLEN/8, x13, x9, x10)

inst_2039:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6054*FLEN/8, x13, x9, x10)

inst_2040:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:6057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6057*FLEN/8, x13, x9, x10)

inst_2041:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:6060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6060*FLEN/8, x13, x9, x10)

inst_2042:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:6063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6063*FLEN/8, x13, x9, x10)

inst_2043:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:6066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6066*FLEN/8, x13, x9, x10)

inst_2044:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:6069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6069*FLEN/8, x13, x9, x10)

inst_2045:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6072*FLEN/8, x13, x9, x10)

inst_2046:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6075*FLEN/8, x13, x9, x10)

inst_2047:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6078*FLEN/8, x13, x9, x10)

inst_2048:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:6081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6081*FLEN/8, x13, x9, x10)

inst_2049:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:6084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6084*FLEN/8, x13, x9, x10)

inst_2050:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:6087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6087*FLEN/8, x13, x9, x10)

inst_2051:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:6090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6090*FLEN/8, x13, x9, x10)

inst_2052:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6093*FLEN/8, x13, x9, x10)

inst_2053:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6096*FLEN/8, x13, x9, x10)

inst_2054:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6099*FLEN/8, x13, x9, x10)

inst_2055:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:6102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6102*FLEN/8, x13, x9, x10)

inst_2056:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6105*FLEN/8, x13, x9, x10)

inst_2057:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6108*FLEN/8, x13, x9, x10)

inst_2058:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6111*FLEN/8, x13, x9, x10)

inst_2059:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6114*FLEN/8, x13, x9, x10)

inst_2060:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6117*FLEN/8, x13, x9, x10)

inst_2061:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6120*FLEN/8, x13, x9, x10)

inst_2062:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6123*FLEN/8, x13, x9, x10)

inst_2063:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6126*FLEN/8, x13, x9, x10)

inst_2064:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:6129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6129*FLEN/8, x13, x9, x10)

inst_2065:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6132*FLEN/8, x13, x9, x10)

inst_2066:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:6135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6135*FLEN/8, x13, x9, x10)

inst_2067:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6138*FLEN/8, x13, x9, x10)

inst_2068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:6141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6141*FLEN/8, x13, x9, x10)

inst_2069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6144*FLEN/8, x13, x9, x10)

inst_2070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6147*FLEN/8, x13, x9, x10)

inst_2071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6150*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_16)

inst_2072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:6153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6153*FLEN/8, x13, x9, x10)

inst_2073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6156*FLEN/8, x13, x9, x10)

inst_2074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:6159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6159*FLEN/8, x13, x9, x10)

inst_2075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6162*FLEN/8, x13, x9, x10)

inst_2076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6165*FLEN/8, x13, x9, x10)

inst_2077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6168*FLEN/8, x13, x9, x10)

inst_2078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6171*FLEN/8, x13, x9, x10)

inst_2079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6174*FLEN/8, x13, x9, x10)

inst_2080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6177*FLEN/8, x13, x9, x10)

inst_2081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6180*FLEN/8, x13, x9, x10)

inst_2082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6183*FLEN/8, x13, x9, x10)

inst_2083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6186*FLEN/8, x13, x9, x10)

inst_2084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6189*FLEN/8, x13, x9, x10)

inst_2085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6192*FLEN/8, x13, x9, x10)

inst_2086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6195*FLEN/8, x13, x9, x10)

inst_2087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6198*FLEN/8, x13, x9, x10)

inst_2088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:6201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6201*FLEN/8, x13, x9, x10)

inst_2089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6204*FLEN/8, x13, x9, x10)

inst_2090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:6207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6207*FLEN/8, x13, x9, x10)

inst_2091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6210*FLEN/8, x13, x9, x10)

inst_2092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:6213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6213*FLEN/8, x13, x9, x10)

inst_2093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6216*FLEN/8, x13, x9, x10)

inst_2094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6219*FLEN/8, x13, x9, x10)

inst_2095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6222*FLEN/8, x13, x9, x10)

inst_2096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:6225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6225*FLEN/8, x13, x9, x10)

inst_2097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6228*FLEN/8, x13, x9, x10)

inst_2098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:6231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6231*FLEN/8, x13, x9, x10)

inst_2099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6234*FLEN/8, x13, x9, x10)

inst_2100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6237*FLEN/8, x13, x9, x10)

inst_2101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6240*FLEN/8, x13, x9, x10)

inst_2102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6243*FLEN/8, x13, x9, x10)

inst_2103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6246*FLEN/8, x13, x9, x10)

inst_2104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6249*FLEN/8, x13, x9, x10)

inst_2105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6252*FLEN/8, x13, x9, x10)

inst_2106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6255*FLEN/8, x13, x9, x10)

inst_2107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6258*FLEN/8, x13, x9, x10)

inst_2108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6261*FLEN/8, x13, x9, x10)

inst_2109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6264*FLEN/8, x13, x9, x10)

inst_2110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6267*FLEN/8, x13, x9, x10)

inst_2111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6270*FLEN/8, x13, x9, x10)

inst_2112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:6273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6273*FLEN/8, x13, x9, x10)

inst_2113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6276*FLEN/8, x13, x9, x10)

inst_2114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:6279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6279*FLEN/8, x13, x9, x10)

inst_2115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6282*FLEN/8, x13, x9, x10)

inst_2116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:6285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6285*FLEN/8, x13, x9, x10)

inst_2117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6288*FLEN/8, x13, x9, x10)

inst_2118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6291*FLEN/8, x13, x9, x10)

inst_2119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6294*FLEN/8, x13, x9, x10)

inst_2120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:6297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6297*FLEN/8, x13, x9, x10)

inst_2121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6300*FLEN/8, x13, x9, x10)

inst_2122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:6303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6303*FLEN/8, x13, x9, x10)

inst_2123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6306*FLEN/8, x13, x9, x10)

inst_2124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6309*FLEN/8, x13, x9, x10)

inst_2125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6312*FLEN/8, x13, x9, x10)

inst_2126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6315*FLEN/8, x13, x9, x10)

inst_2127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6318*FLEN/8, x13, x9, x10)

inst_2128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6321*FLEN/8, x13, x9, x10)

inst_2129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6324*FLEN/8, x13, x9, x10)

inst_2130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6327*FLEN/8, x13, x9, x10)

inst_2131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6330*FLEN/8, x13, x9, x10)

inst_2132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6333*FLEN/8, x13, x9, x10)

inst_2133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6336*FLEN/8, x13, x9, x10)

inst_2134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6339*FLEN/8, x13, x9, x10)

inst_2135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6342*FLEN/8, x13, x9, x10)

inst_2136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:6345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6345*FLEN/8, x13, x9, x10)

inst_2137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6348*FLEN/8, x13, x9, x10)

inst_2138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:6351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6351*FLEN/8, x13, x9, x10)

inst_2139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6354*FLEN/8, x13, x9, x10)

inst_2140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:6357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6357*FLEN/8, x13, x9, x10)

inst_2141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6360*FLEN/8, x13, x9, x10)

inst_2142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6363*FLEN/8, x13, x9, x10)

inst_2143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6366*FLEN/8, x13, x9, x10)

inst_2144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:6369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6369*FLEN/8, x13, x9, x10)

inst_2145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6372*FLEN/8, x13, x9, x10)

inst_2146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:6375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6375*FLEN/8, x13, x9, x10)

inst_2147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6378*FLEN/8, x13, x9, x10)

inst_2148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6381*FLEN/8, x13, x9, x10)

inst_2149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6384*FLEN/8, x13, x9, x10)

inst_2150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6387*FLEN/8, x13, x9, x10)

inst_2151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6390*FLEN/8, x13, x9, x10)

inst_2152:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6393*FLEN/8, x13, x9, x10)

inst_2153:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6396*FLEN/8, x13, x9, x10)

inst_2154:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6399*FLEN/8, x13, x9, x10)

inst_2155:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6402*FLEN/8, x13, x9, x10)

inst_2156:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6405*FLEN/8, x13, x9, x10)

inst_2157:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6408*FLEN/8, x13, x9, x10)

inst_2158:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6411*FLEN/8, x13, x9, x10)

inst_2159:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6414*FLEN/8, x13, x9, x10)

inst_2160:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:6417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6417*FLEN/8, x13, x9, x10)

inst_2161:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:6420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6420*FLEN/8, x13, x9, x10)

inst_2162:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:6423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6423*FLEN/8, x13, x9, x10)

inst_2163:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:6426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6426*FLEN/8, x13, x9, x10)

inst_2164:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:6429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6429*FLEN/8, x13, x9, x10)

inst_2165:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6432*FLEN/8, x13, x9, x10)

inst_2166:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6435*FLEN/8, x13, x9, x10)

inst_2167:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6438*FLEN/8, x13, x9, x10)

inst_2168:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:6441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6441*FLEN/8, x13, x9, x10)

inst_2169:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:6444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6444*FLEN/8, x13, x9, x10)

inst_2170:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:6447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6447*FLEN/8, x13, x9, x10)

inst_2171:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:6450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6450*FLEN/8, x13, x9, x10)

inst_2172:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6453*FLEN/8, x13, x9, x10)

inst_2173:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6456*FLEN/8, x13, x9, x10)

inst_2174:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6459*FLEN/8, x13, x9, x10)

inst_2175:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:6462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6462*FLEN/8, x13, x9, x10)

inst_2176:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6465*FLEN/8, x13, x9, x10)

inst_2177:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6468*FLEN/8, x13, x9, x10)

inst_2178:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6471*FLEN/8, x13, x9, x10)

inst_2179:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6474*FLEN/8, x13, x9, x10)

inst_2180:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6477*FLEN/8, x13, x9, x10)

inst_2181:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6480*FLEN/8, x13, x9, x10)

inst_2182:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6483*FLEN/8, x13, x9, x10)

inst_2183:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6486*FLEN/8, x13, x9, x10)

inst_2184:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:6489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6489*FLEN/8, x13, x9, x10)

inst_2185:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:6492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6492*FLEN/8, x13, x9, x10)

inst_2186:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:6495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6495*FLEN/8, x13, x9, x10)

inst_2187:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:6498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6498*FLEN/8, x13, x9, x10)

inst_2188:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:6501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6501*FLEN/8, x13, x9, x10)

inst_2189:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6504*FLEN/8, x13, x9, x10)

inst_2190:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6507*FLEN/8, x13, x9, x10)

inst_2191:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6510*FLEN/8, x13, x9, x10)

inst_2192:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:6513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6513*FLEN/8, x13, x9, x10)

inst_2193:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:6516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6516*FLEN/8, x13, x9, x10)

inst_2194:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:6519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6519*FLEN/8, x13, x9, x10)

inst_2195:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:6522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6522*FLEN/8, x13, x9, x10)

inst_2196:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6525*FLEN/8, x13, x9, x10)

inst_2197:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6528*FLEN/8, x13, x9, x10)

inst_2198:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6531*FLEN/8, x13, x9, x10)

inst_2199:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:6534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6534*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_17)

inst_2200:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6537*FLEN/8, x13, x9, x10)

inst_2201:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6540*FLEN/8, x13, x9, x10)

inst_2202:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6543*FLEN/8, x13, x9, x10)

inst_2203:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6546*FLEN/8, x13, x9, x10)

inst_2204:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6549*FLEN/8, x13, x9, x10)

inst_2205:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6552*FLEN/8, x13, x9, x10)

inst_2206:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6555*FLEN/8, x13, x9, x10)

inst_2207:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6558*FLEN/8, x13, x9, x10)

inst_2208:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:6561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6561*FLEN/8, x13, x9, x10)

inst_2209:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:6564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6564*FLEN/8, x13, x9, x10)

inst_2210:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:6567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6567*FLEN/8, x13, x9, x10)

inst_2211:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:6570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6570*FLEN/8, x13, x9, x10)

inst_2212:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:6573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6573*FLEN/8, x13, x9, x10)

inst_2213:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6576*FLEN/8, x13, x9, x10)

inst_2214:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6579*FLEN/8, x13, x9, x10)

inst_2215:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6582*FLEN/8, x13, x9, x10)

inst_2216:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:6585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6585*FLEN/8, x13, x9, x10)

inst_2217:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:6588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6588*FLEN/8, x13, x9, x10)

inst_2218:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:6591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6591*FLEN/8, x13, x9, x10)

inst_2219:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:6594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6594*FLEN/8, x13, x9, x10)

inst_2220:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6597*FLEN/8, x13, x9, x10)

inst_2221:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6600*FLEN/8, x13, x9, x10)

inst_2222:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6603*FLEN/8, x13, x9, x10)

inst_2223:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:6606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6606*FLEN/8, x13, x9, x10)

inst_2224:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6609*FLEN/8, x13, x9, x10)

inst_2225:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6612*FLEN/8, x13, x9, x10)

inst_2226:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6615*FLEN/8, x13, x9, x10)

inst_2227:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6618*FLEN/8, x13, x9, x10)

inst_2228:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6621*FLEN/8, x13, x9, x10)

inst_2229:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6624*FLEN/8, x13, x9, x10)

inst_2230:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6627*FLEN/8, x13, x9, x10)

inst_2231:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6630*FLEN/8, x13, x9, x10)

inst_2232:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:6633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6633*FLEN/8, x13, x9, x10)

inst_2233:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:6636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6636*FLEN/8, x13, x9, x10)

inst_2234:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:6639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6639*FLEN/8, x13, x9, x10)

inst_2235:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:6642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6642*FLEN/8, x13, x9, x10)

inst_2236:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:6645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6645*FLEN/8, x13, x9, x10)

inst_2237:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6648*FLEN/8, x13, x9, x10)

inst_2238:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6651*FLEN/8, x13, x9, x10)

inst_2239:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6654*FLEN/8, x13, x9, x10)

inst_2240:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:6657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6657*FLEN/8, x13, x9, x10)

inst_2241:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:6660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6660*FLEN/8, x13, x9, x10)

inst_2242:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:6663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6663*FLEN/8, x13, x9, x10)

inst_2243:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:6666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6666*FLEN/8, x13, x9, x10)

inst_2244:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6669*FLEN/8, x13, x9, x10)

inst_2245:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6672*FLEN/8, x13, x9, x10)

inst_2246:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6675*FLEN/8, x13, x9, x10)

inst_2247:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:6678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6678*FLEN/8, x13, x9, x10)

inst_2248:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6681*FLEN/8, x13, x9, x10)

inst_2249:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6684*FLEN/8, x13, x9, x10)

inst_2250:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6687*FLEN/8, x13, x9, x10)

inst_2251:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6690*FLEN/8, x13, x9, x10)

inst_2252:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6693*FLEN/8, x13, x9, x10)

inst_2253:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6696*FLEN/8, x13, x9, x10)

inst_2254:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6699*FLEN/8, x13, x9, x10)

inst_2255:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6702*FLEN/8, x13, x9, x10)

inst_2256:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:6705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6705*FLEN/8, x13, x9, x10)

inst_2257:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6708*FLEN/8, x13, x9, x10)

inst_2258:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:6711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6711*FLEN/8, x13, x9, x10)

inst_2259:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6714*FLEN/8, x13, x9, x10)

inst_2260:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:6717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6717*FLEN/8, x13, x9, x10)

inst_2261:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6720*FLEN/8, x13, x9, x10)

inst_2262:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6723*FLEN/8, x13, x9, x10)

inst_2263:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6726*FLEN/8, x13, x9, x10)

inst_2264:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:6729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6729*FLEN/8, x13, x9, x10)

inst_2265:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6732*FLEN/8, x13, x9, x10)

inst_2266:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:6735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6735*FLEN/8, x13, x9, x10)

inst_2267:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6738*FLEN/8, x13, x9, x10)

inst_2268:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6741*FLEN/8, x13, x9, x10)

inst_2269:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6744*FLEN/8, x13, x9, x10)

inst_2270:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6747*FLEN/8, x13, x9, x10)

inst_2271:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6750*FLEN/8, x13, x9, x10)

inst_2272:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6753*FLEN/8, x13, x9, x10)

inst_2273:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6756*FLEN/8, x13, x9, x10)

inst_2274:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6759*FLEN/8, x13, x9, x10)

inst_2275:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6762*FLEN/8, x13, x9, x10)

inst_2276:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6765*FLEN/8, x13, x9, x10)

inst_2277:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6768*FLEN/8, x13, x9, x10)

inst_2278:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6771*FLEN/8, x13, x9, x10)

inst_2279:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6774*FLEN/8, x13, x9, x10)

inst_2280:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:6777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6777*FLEN/8, x13, x9, x10)

inst_2281:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6780*FLEN/8, x13, x9, x10)

inst_2282:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:6783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6783*FLEN/8, x13, x9, x10)

inst_2283:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6786*FLEN/8, x13, x9, x10)

inst_2284:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:6789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6789*FLEN/8, x13, x9, x10)

inst_2285:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6792*FLEN/8, x13, x9, x10)

inst_2286:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6795*FLEN/8, x13, x9, x10)

inst_2287:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6798*FLEN/8, x13, x9, x10)

inst_2288:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:6801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6801*FLEN/8, x13, x9, x10)

inst_2289:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6804*FLEN/8, x13, x9, x10)

inst_2290:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:6807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6807*FLEN/8, x13, x9, x10)

inst_2291:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6810*FLEN/8, x13, x9, x10)

inst_2292:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6813*FLEN/8, x13, x9, x10)

inst_2293:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6816*FLEN/8, x13, x9, x10)

inst_2294:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6819*FLEN/8, x13, x9, x10)

inst_2295:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6822*FLEN/8, x13, x9, x10)

inst_2296:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6825*FLEN/8, x13, x9, x10)

inst_2297:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6828*FLEN/8, x13, x9, x10)

inst_2298:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6831*FLEN/8, x13, x9, x10)

inst_2299:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6834*FLEN/8, x13, x9, x10)

inst_2300:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6837*FLEN/8, x13, x9, x10)

inst_2301:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6840*FLEN/8, x13, x9, x10)

inst_2302:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6843*FLEN/8, x13, x9, x10)

inst_2303:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80000001; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6846*FLEN/8, x13, x9, x10)

inst_2304:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:6849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6849*FLEN/8, x13, x9, x10)

inst_2305:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:6852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6852*FLEN/8, x13, x9, x10)

inst_2306:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:6855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6855*FLEN/8, x13, x9, x10)

inst_2307:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:6858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6858*FLEN/8, x13, x9, x10)

inst_2308:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:6861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6861*FLEN/8, x13, x9, x10)

inst_2309:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6864*FLEN/8, x13, x9, x10)

inst_2310:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6867*FLEN/8, x13, x9, x10)

inst_2311:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6870*FLEN/8, x13, x9, x10)

inst_2312:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:6873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6873*FLEN/8, x13, x9, x10)

inst_2313:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:6876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6876*FLEN/8, x13, x9, x10)

inst_2314:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:6879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6879*FLEN/8, x13, x9, x10)

inst_2315:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:6882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6882*FLEN/8, x13, x9, x10)

inst_2316:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6885*FLEN/8, x13, x9, x10)

inst_2317:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6888*FLEN/8, x13, x9, x10)

inst_2318:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6891*FLEN/8, x13, x9, x10)

inst_2319:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:6894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6894*FLEN/8, x13, x9, x10)

inst_2320:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6897*FLEN/8, x13, x9, x10)

inst_2321:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6900*FLEN/8, x13, x9, x10)

inst_2322:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6903*FLEN/8, x13, x9, x10)

inst_2323:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6906*FLEN/8, x13, x9, x10)

inst_2324:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6909*FLEN/8, x13, x9, x10)

inst_2325:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6912*FLEN/8, x13, x9, x10)

inst_2326:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6915*FLEN/8, x13, x9, x10)

inst_2327:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6918*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_18)

inst_2328:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:6921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6921*FLEN/8, x13, x9, x10)

inst_2329:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:6924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6924*FLEN/8, x13, x9, x10)

inst_2330:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:6927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6927*FLEN/8, x13, x9, x10)

inst_2331:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:6930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6930*FLEN/8, x13, x9, x10)

inst_2332:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:6933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6933*FLEN/8, x13, x9, x10)

inst_2333:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:6936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6936*FLEN/8, x13, x9, x10)

inst_2334:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:6939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6939*FLEN/8, x13, x9, x10)

inst_2335:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:6942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6942*FLEN/8, x13, x9, x10)

inst_2336:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:6945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6945*FLEN/8, x13, x9, x10)

inst_2337:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:6948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6948*FLEN/8, x13, x9, x10)

inst_2338:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:6951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6951*FLEN/8, x13, x9, x10)

inst_2339:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:6954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6954*FLEN/8, x13, x9, x10)

inst_2340:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:6957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6957*FLEN/8, x13, x9, x10)

inst_2341:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:6960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6960*FLEN/8, x13, x9, x10)

inst_2342:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:6963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6963*FLEN/8, x13, x9, x10)

inst_2343:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:6966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6966*FLEN/8, x13, x9, x10)

inst_2344:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:6969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6969*FLEN/8, x13, x9, x10)

inst_2345:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:6972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6972*FLEN/8, x13, x9, x10)

inst_2346:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:6975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6975*FLEN/8, x13, x9, x10)

inst_2347:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:6978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6978*FLEN/8, x13, x9, x10)

inst_2348:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:6981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6981*FLEN/8, x13, x9, x10)

inst_2349:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:6984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6984*FLEN/8, x13, x9, x10)

inst_2350:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:6987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6987*FLEN/8, x13, x9, x10)

inst_2351:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:6990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6990*FLEN/8, x13, x9, x10)

inst_2352:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:6993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6993*FLEN/8, x13, x9, x10)

inst_2353:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:6996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6996*FLEN/8, x13, x9, x10)

inst_2354:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:6999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 6999*FLEN/8, x13, x9, x10)

inst_2355:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:7002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7002*FLEN/8, x13, x9, x10)

inst_2356:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:7005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7005*FLEN/8, x13, x9, x10)

inst_2357:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7008*FLEN/8, x13, x9, x10)

inst_2358:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7011*FLEN/8, x13, x9, x10)

inst_2359:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7014*FLEN/8, x13, x9, x10)

inst_2360:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:7017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7017*FLEN/8, x13, x9, x10)

inst_2361:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:7020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7020*FLEN/8, x13, x9, x10)

inst_2362:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:7023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7023*FLEN/8, x13, x9, x10)

inst_2363:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:7026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7026*FLEN/8, x13, x9, x10)

inst_2364:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7029*FLEN/8, x13, x9, x10)

inst_2365:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7032*FLEN/8, x13, x9, x10)

inst_2366:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7035*FLEN/8, x13, x9, x10)

inst_2367:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:7038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7038*FLEN/8, x13, x9, x10)

inst_2368:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7041*FLEN/8, x13, x9, x10)

inst_2369:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7044*FLEN/8, x13, x9, x10)

inst_2370:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7047*FLEN/8, x13, x9, x10)

inst_2371:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7050*FLEN/8, x13, x9, x10)

inst_2372:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7053*FLEN/8, x13, x9, x10)

inst_2373:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7056*FLEN/8, x13, x9, x10)

inst_2374:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7059*FLEN/8, x13, x9, x10)

inst_2375:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7062*FLEN/8, x13, x9, x10)

inst_2376:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:7065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7065*FLEN/8, x13, x9, x10)

inst_2377:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:7068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7068*FLEN/8, x13, x9, x10)

inst_2378:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:7071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7071*FLEN/8, x13, x9, x10)

inst_2379:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:7074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7074*FLEN/8, x13, x9, x10)

inst_2380:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:7077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7077*FLEN/8, x13, x9, x10)

inst_2381:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7080*FLEN/8, x13, x9, x10)

inst_2382:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7083*FLEN/8, x13, x9, x10)

inst_2383:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7086*FLEN/8, x13, x9, x10)

inst_2384:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:7089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7089*FLEN/8, x13, x9, x10)

inst_2385:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:7092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7092*FLEN/8, x13, x9, x10)

inst_2386:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:7095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7095*FLEN/8, x13, x9, x10)

inst_2387:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:7098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7098*FLEN/8, x13, x9, x10)

inst_2388:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7101*FLEN/8, x13, x9, x10)

inst_2389:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7104*FLEN/8, x13, x9, x10)

inst_2390:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7107*FLEN/8, x13, x9, x10)

inst_2391:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:7110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7110*FLEN/8, x13, x9, x10)

inst_2392:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7113*FLEN/8, x13, x9, x10)

inst_2393:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7116*FLEN/8, x13, x9, x10)

inst_2394:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7119*FLEN/8, x13, x9, x10)

inst_2395:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7122*FLEN/8, x13, x9, x10)

inst_2396:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7125*FLEN/8, x13, x9, x10)

inst_2397:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7128*FLEN/8, x13, x9, x10)

inst_2398:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7131*FLEN/8, x13, x9, x10)

inst_2399:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7134*FLEN/8, x13, x9, x10)

inst_2400:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:7137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7137*FLEN/8, x13, x9, x10)

inst_2401:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:7140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7140*FLEN/8, x13, x9, x10)

inst_2402:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:7143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7143*FLEN/8, x13, x9, x10)

inst_2403:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:7146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7146*FLEN/8, x13, x9, x10)

inst_2404:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:7149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7149*FLEN/8, x13, x9, x10)

inst_2405:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7152*FLEN/8, x13, x9, x10)

inst_2406:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7155*FLEN/8, x13, x9, x10)

inst_2407:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7158*FLEN/8, x13, x9, x10)

inst_2408:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:7161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7161*FLEN/8, x13, x9, x10)

inst_2409:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:7164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7164*FLEN/8, x13, x9, x10)

inst_2410:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:7167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7167*FLEN/8, x13, x9, x10)

inst_2411:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:7170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7170*FLEN/8, x13, x9, x10)

inst_2412:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7173*FLEN/8, x13, x9, x10)

inst_2413:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7176*FLEN/8, x13, x9, x10)

inst_2414:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7179*FLEN/8, x13, x9, x10)

inst_2415:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:7182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7182*FLEN/8, x13, x9, x10)

inst_2416:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7185*FLEN/8, x13, x9, x10)

inst_2417:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7188*FLEN/8, x13, x9, x10)

inst_2418:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7191*FLEN/8, x13, x9, x10)

inst_2419:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7194*FLEN/8, x13, x9, x10)

inst_2420:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7197*FLEN/8, x13, x9, x10)

inst_2421:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7200*FLEN/8, x13, x9, x10)

inst_2422:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7203*FLEN/8, x13, x9, x10)

inst_2423:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7206*FLEN/8, x13, x9, x10)

inst_2424:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:7209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7209*FLEN/8, x13, x9, x10)

inst_2425:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:7212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7212*FLEN/8, x13, x9, x10)

inst_2426:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:7215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7215*FLEN/8, x13, x9, x10)

inst_2427:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:7218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7218*FLEN/8, x13, x9, x10)

inst_2428:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:7221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7221*FLEN/8, x13, x9, x10)

inst_2429:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7224*FLEN/8, x13, x9, x10)

inst_2430:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7227*FLEN/8, x13, x9, x10)

inst_2431:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7230*FLEN/8, x13, x9, x10)

inst_2432:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:7233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7233*FLEN/8, x13, x9, x10)

inst_2433:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:7236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7236*FLEN/8, x13, x9, x10)

inst_2434:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:7239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7239*FLEN/8, x13, x9, x10)

inst_2435:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:7242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7242*FLEN/8, x13, x9, x10)

inst_2436:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7245*FLEN/8, x13, x9, x10)

inst_2437:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7248*FLEN/8, x13, x9, x10)

inst_2438:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7251*FLEN/8, x13, x9, x10)

inst_2439:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:7254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7254*FLEN/8, x13, x9, x10)

inst_2440:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7257*FLEN/8, x13, x9, x10)

inst_2441:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7260*FLEN/8, x13, x9, x10)

inst_2442:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7263*FLEN/8, x13, x9, x10)

inst_2443:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7266*FLEN/8, x13, x9, x10)

inst_2444:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7269*FLEN/8, x13, x9, x10)

inst_2445:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7272*FLEN/8, x13, x9, x10)

inst_2446:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7275*FLEN/8, x13, x9, x10)

inst_2447:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7278*FLEN/8, x13, x9, x10)

inst_2448:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:7281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7281*FLEN/8, x13, x9, x10)

inst_2449:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:7284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7284*FLEN/8, x13, x9, x10)

inst_2450:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:7287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7287*FLEN/8, x13, x9, x10)

inst_2451:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:7290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7290*FLEN/8, x13, x9, x10)

inst_2452:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:7293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7293*FLEN/8, x13, x9, x10)

inst_2453:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7296*FLEN/8, x13, x9, x10)

inst_2454:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7299*FLEN/8, x13, x9, x10)

inst_2455:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7302*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_19)

inst_2456:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:7305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7305*FLEN/8, x13, x9, x10)

inst_2457:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:7308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7308*FLEN/8, x13, x9, x10)

inst_2458:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:7311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7311*FLEN/8, x13, x9, x10)

inst_2459:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:7314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7314*FLEN/8, x13, x9, x10)

inst_2460:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7317*FLEN/8, x13, x9, x10)

inst_2461:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7320*FLEN/8, x13, x9, x10)

inst_2462:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7323*FLEN/8, x13, x9, x10)

inst_2463:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:7326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7326*FLEN/8, x13, x9, x10)

inst_2464:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7329*FLEN/8, x13, x9, x10)

inst_2465:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7332*FLEN/8, x13, x9, x10)

inst_2466:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7335*FLEN/8, x13, x9, x10)

inst_2467:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7338*FLEN/8, x13, x9, x10)

inst_2468:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7341*FLEN/8, x13, x9, x10)

inst_2469:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7344*FLEN/8, x13, x9, x10)

inst_2470:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7347*FLEN/8, x13, x9, x10)

inst_2471:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7350*FLEN/8, x13, x9, x10)

inst_2472:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:7353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7353*FLEN/8, x13, x9, x10)

inst_2473:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:7356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7356*FLEN/8, x13, x9, x10)

inst_2474:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:7359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7359*FLEN/8, x13, x9, x10)

inst_2475:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:7362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7362*FLEN/8, x13, x9, x10)

inst_2476:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:7365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7365*FLEN/8, x13, x9, x10)

inst_2477:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7368*FLEN/8, x13, x9, x10)

inst_2478:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7371*FLEN/8, x13, x9, x10)

inst_2479:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7374*FLEN/8, x13, x9, x10)

inst_2480:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:7377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7377*FLEN/8, x13, x9, x10)

inst_2481:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:7380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7380*FLEN/8, x13, x9, x10)

inst_2482:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:7383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7383*FLEN/8, x13, x9, x10)

inst_2483:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:7386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7386*FLEN/8, x13, x9, x10)

inst_2484:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7389*FLEN/8, x13, x9, x10)

inst_2485:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7392*FLEN/8, x13, x9, x10)

inst_2486:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7395*FLEN/8, x13, x9, x10)

inst_2487:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:7398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7398*FLEN/8, x13, x9, x10)

inst_2488:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7401*FLEN/8, x13, x9, x10)

inst_2489:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7404*FLEN/8, x13, x9, x10)

inst_2490:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7407*FLEN/8, x13, x9, x10)

inst_2491:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7410*FLEN/8, x13, x9, x10)

inst_2492:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7413*FLEN/8, x13, x9, x10)

inst_2493:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7416*FLEN/8, x13, x9, x10)

inst_2494:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7419*FLEN/8, x13, x9, x10)

inst_2495:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7422*FLEN/8, x13, x9, x10)

inst_2496:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:7425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7425*FLEN/8, x13, x9, x10)

inst_2497:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:7428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7428*FLEN/8, x13, x9, x10)

inst_2498:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:7431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7431*FLEN/8, x13, x9, x10)

inst_2499:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:7434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7434*FLEN/8, x13, x9, x10)

inst_2500:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:7437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7437*FLEN/8, x13, x9, x10)

inst_2501:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7440*FLEN/8, x13, x9, x10)

inst_2502:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7443*FLEN/8, x13, x9, x10)

inst_2503:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7446*FLEN/8, x13, x9, x10)

inst_2504:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:7449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7449*FLEN/8, x13, x9, x10)

inst_2505:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:7452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7452*FLEN/8, x13, x9, x10)

inst_2506:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:7455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7455*FLEN/8, x13, x9, x10)

inst_2507:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:7458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7458*FLEN/8, x13, x9, x10)

inst_2508:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7461*FLEN/8, x13, x9, x10)

inst_2509:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7464*FLEN/8, x13, x9, x10)

inst_2510:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7467*FLEN/8, x13, x9, x10)

inst_2511:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:7470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7470*FLEN/8, x13, x9, x10)

inst_2512:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7473*FLEN/8, x13, x9, x10)

inst_2513:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7476*FLEN/8, x13, x9, x10)

inst_2514:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7479*FLEN/8, x13, x9, x10)

inst_2515:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7482*FLEN/8, x13, x9, x10)

inst_2516:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7485*FLEN/8, x13, x9, x10)

inst_2517:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7488*FLEN/8, x13, x9, x10)

inst_2518:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7491*FLEN/8, x13, x9, x10)

inst_2519:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7494*FLEN/8, x13, x9, x10)

inst_2520:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:7497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7497*FLEN/8, x13, x9, x10)

inst_2521:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:7500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7500*FLEN/8, x13, x9, x10)

inst_2522:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:7503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7503*FLEN/8, x13, x9, x10)

inst_2523:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:7506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7506*FLEN/8, x13, x9, x10)

inst_2524:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:7509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7509*FLEN/8, x13, x9, x10)

inst_2525:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7512*FLEN/8, x13, x9, x10)

inst_2526:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7515*FLEN/8, x13, x9, x10)

inst_2527:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7518*FLEN/8, x13, x9, x10)

inst_2528:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:7521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7521*FLEN/8, x13, x9, x10)

inst_2529:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:7524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7524*FLEN/8, x13, x9, x10)

inst_2530:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:7527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7527*FLEN/8, x13, x9, x10)

inst_2531:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:7530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7530*FLEN/8, x13, x9, x10)

inst_2532:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7533*FLEN/8, x13, x9, x10)

inst_2533:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7536*FLEN/8, x13, x9, x10)

inst_2534:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7539*FLEN/8, x13, x9, x10)

inst_2535:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:7542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7542*FLEN/8, x13, x9, x10)

inst_2536:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7545*FLEN/8, x13, x9, x10)

inst_2537:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7548*FLEN/8, x13, x9, x10)

inst_2538:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7551*FLEN/8, x13, x9, x10)

inst_2539:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7554*FLEN/8, x13, x9, x10)

inst_2540:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7557*FLEN/8, x13, x9, x10)

inst_2541:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7560*FLEN/8, x13, x9, x10)

inst_2542:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7563*FLEN/8, x13, x9, x10)

inst_2543:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7566*FLEN/8, x13, x9, x10)

inst_2544:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:7569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7569*FLEN/8, x13, x9, x10)

inst_2545:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:7572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7572*FLEN/8, x13, x9, x10)

inst_2546:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:7575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7575*FLEN/8, x13, x9, x10)

inst_2547:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:7578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7578*FLEN/8, x13, x9, x10)

inst_2548:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:7581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7581*FLEN/8, x13, x9, x10)

inst_2549:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7584*FLEN/8, x13, x9, x10)

inst_2550:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7587*FLEN/8, x13, x9, x10)

inst_2551:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7590*FLEN/8, x13, x9, x10)

inst_2552:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:7593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7593*FLEN/8, x13, x9, x10)

inst_2553:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:7596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7596*FLEN/8, x13, x9, x10)

inst_2554:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:7599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7599*FLEN/8, x13, x9, x10)

inst_2555:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:7602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7602*FLEN/8, x13, x9, x10)

inst_2556:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7605*FLEN/8, x13, x9, x10)

inst_2557:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7608*FLEN/8, x13, x9, x10)

inst_2558:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7611*FLEN/8, x13, x9, x10)

inst_2559:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:7614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7614*FLEN/8, x13, x9, x10)

inst_2560:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7617*FLEN/8, x13, x9, x10)

inst_2561:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7620*FLEN/8, x13, x9, x10)

inst_2562:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7623*FLEN/8, x13, x9, x10)

inst_2563:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7626*FLEN/8, x13, x9, x10)

inst_2564:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7629*FLEN/8, x13, x9, x10)

inst_2565:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7632*FLEN/8, x13, x9, x10)

inst_2566:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7635*FLEN/8, x13, x9, x10)

inst_2567:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7638*FLEN/8, x13, x9, x10)

inst_2568:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:7641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7641*FLEN/8, x13, x9, x10)

inst_2569:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:7644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7644*FLEN/8, x13, x9, x10)

inst_2570:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:7647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7647*FLEN/8, x13, x9, x10)

inst_2571:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:7650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7650*FLEN/8, x13, x9, x10)

inst_2572:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:7653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7653*FLEN/8, x13, x9, x10)

inst_2573:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7656*FLEN/8, x13, x9, x10)

inst_2574:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7659*FLEN/8, x13, x9, x10)

inst_2575:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7662*FLEN/8, x13, x9, x10)

inst_2576:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:7665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7665*FLEN/8, x13, x9, x10)

inst_2577:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:7668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7668*FLEN/8, x13, x9, x10)

inst_2578:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:7671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7671*FLEN/8, x13, x9, x10)

inst_2579:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:7674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7674*FLEN/8, x13, x9, x10)

inst_2580:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7677*FLEN/8, x13, x9, x10)

inst_2581:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7680*FLEN/8, x13, x9, x10)

inst_2582:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7683*FLEN/8, x13, x9, x10)

inst_2583:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:7686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7686*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_20)

inst_2584:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7689*FLEN/8, x13, x9, x10)

inst_2585:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7692*FLEN/8, x13, x9, x10)

inst_2586:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7695*FLEN/8, x13, x9, x10)

inst_2587:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7698*FLEN/8, x13, x9, x10)

inst_2588:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7701*FLEN/8, x13, x9, x10)

inst_2589:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7704*FLEN/8, x13, x9, x10)

inst_2590:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7707*FLEN/8, x13, x9, x10)

inst_2591:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7710*FLEN/8, x13, x9, x10)

inst_2592:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:7713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7713*FLEN/8, x13, x9, x10)

inst_2593:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:7716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7716*FLEN/8, x13, x9, x10)

inst_2594:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:7719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7719*FLEN/8, x13, x9, x10)

inst_2595:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:7722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7722*FLEN/8, x13, x9, x10)

inst_2596:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:7725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7725*FLEN/8, x13, x9, x10)

inst_2597:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7728*FLEN/8, x13, x9, x10)

inst_2598:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7731*FLEN/8, x13, x9, x10)

inst_2599:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7734*FLEN/8, x13, x9, x10)

inst_2600:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:7737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7737*FLEN/8, x13, x9, x10)

inst_2601:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:7740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7740*FLEN/8, x13, x9, x10)

inst_2602:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:7743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7743*FLEN/8, x13, x9, x10)

inst_2603:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:7746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7746*FLEN/8, x13, x9, x10)

inst_2604:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7749*FLEN/8, x13, x9, x10)

inst_2605:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7752*FLEN/8, x13, x9, x10)

inst_2606:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7755*FLEN/8, x13, x9, x10)

inst_2607:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:7758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7758*FLEN/8, x13, x9, x10)

inst_2608:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7761*FLEN/8, x13, x9, x10)

inst_2609:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7764*FLEN/8, x13, x9, x10)

inst_2610:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7767*FLEN/8, x13, x9, x10)

inst_2611:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7770*FLEN/8, x13, x9, x10)

inst_2612:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7773*FLEN/8, x13, x9, x10)

inst_2613:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7776*FLEN/8, x13, x9, x10)

inst_2614:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7779*FLEN/8, x13, x9, x10)

inst_2615:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7782*FLEN/8, x13, x9, x10)

inst_2616:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:7785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7785*FLEN/8, x13, x9, x10)

inst_2617:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:7788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7788*FLEN/8, x13, x9, x10)

inst_2618:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:7791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7791*FLEN/8, x13, x9, x10)

inst_2619:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:7794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7794*FLEN/8, x13, x9, x10)

inst_2620:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:7797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7797*FLEN/8, x13, x9, x10)

inst_2621:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7800*FLEN/8, x13, x9, x10)

inst_2622:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7803*FLEN/8, x13, x9, x10)

inst_2623:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7806*FLEN/8, x13, x9, x10)

inst_2624:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:7809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7809*FLEN/8, x13, x9, x10)

inst_2625:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:7812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7812*FLEN/8, x13, x9, x10)

inst_2626:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:7815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7815*FLEN/8, x13, x9, x10)

inst_2627:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:7818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7818*FLEN/8, x13, x9, x10)

inst_2628:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7821*FLEN/8, x13, x9, x10)

inst_2629:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7824*FLEN/8, x13, x9, x10)

inst_2630:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7827*FLEN/8, x13, x9, x10)

inst_2631:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:7830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7830*FLEN/8, x13, x9, x10)

inst_2632:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7833*FLEN/8, x13, x9, x10)

inst_2633:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7836*FLEN/8, x13, x9, x10)

inst_2634:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7839*FLEN/8, x13, x9, x10)

inst_2635:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7842*FLEN/8, x13, x9, x10)

inst_2636:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7845*FLEN/8, x13, x9, x10)

inst_2637:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7848*FLEN/8, x13, x9, x10)

inst_2638:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7851*FLEN/8, x13, x9, x10)

inst_2639:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7854*FLEN/8, x13, x9, x10)

inst_2640:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:7857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7857*FLEN/8, x13, x9, x10)

inst_2641:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:7860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7860*FLEN/8, x13, x9, x10)

inst_2642:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:7863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7863*FLEN/8, x13, x9, x10)

inst_2643:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:7866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7866*FLEN/8, x13, x9, x10)

inst_2644:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:7869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7869*FLEN/8, x13, x9, x10)

inst_2645:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7872*FLEN/8, x13, x9, x10)

inst_2646:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7875*FLEN/8, x13, x9, x10)

inst_2647:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7878*FLEN/8, x13, x9, x10)

inst_2648:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:7881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7881*FLEN/8, x13, x9, x10)

inst_2649:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:7884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7884*FLEN/8, x13, x9, x10)

inst_2650:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:7887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7887*FLEN/8, x13, x9, x10)

inst_2651:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:7890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7890*FLEN/8, x13, x9, x10)

inst_2652:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7893*FLEN/8, x13, x9, x10)

inst_2653:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7896*FLEN/8, x13, x9, x10)

inst_2654:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7899*FLEN/8, x13, x9, x10)

inst_2655:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:7902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7902*FLEN/8, x13, x9, x10)

inst_2656:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7905*FLEN/8, x13, x9, x10)

inst_2657:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7908*FLEN/8, x13, x9, x10)

inst_2658:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7911*FLEN/8, x13, x9, x10)

inst_2659:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7914*FLEN/8, x13, x9, x10)

inst_2660:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7917*FLEN/8, x13, x9, x10)

inst_2661:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7920*FLEN/8, x13, x9, x10)

inst_2662:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7923*FLEN/8, x13, x9, x10)

inst_2663:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7926*FLEN/8, x13, x9, x10)

inst_2664:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:7929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7929*FLEN/8, x13, x9, x10)

inst_2665:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:7932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7932*FLEN/8, x13, x9, x10)

inst_2666:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:7935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7935*FLEN/8, x13, x9, x10)

inst_2667:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:7938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7938*FLEN/8, x13, x9, x10)

inst_2668:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:7941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7941*FLEN/8, x13, x9, x10)

inst_2669:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:7944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7944*FLEN/8, x13, x9, x10)

inst_2670:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:7947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7947*FLEN/8, x13, x9, x10)

inst_2671:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:7950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7950*FLEN/8, x13, x9, x10)

inst_2672:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:7953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7953*FLEN/8, x13, x9, x10)

inst_2673:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:7956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7956*FLEN/8, x13, x9, x10)

inst_2674:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:7959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7959*FLEN/8, x13, x9, x10)

inst_2675:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:7962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7962*FLEN/8, x13, x9, x10)

inst_2676:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:7965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7965*FLEN/8, x13, x9, x10)

inst_2677:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:7968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7968*FLEN/8, x13, x9, x10)

inst_2678:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:7971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7971*FLEN/8, x13, x9, x10)

inst_2679:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:7974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7974*FLEN/8, x13, x9, x10)

inst_2680:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:7977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7977*FLEN/8, x13, x9, x10)

inst_2681:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:7980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7980*FLEN/8, x13, x9, x10)

inst_2682:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:7983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7983*FLEN/8, x13, x9, x10)

inst_2683:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:7986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7986*FLEN/8, x13, x9, x10)

inst_2684:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:7989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7989*FLEN/8, x13, x9, x10)

inst_2685:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:7992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7992*FLEN/8, x13, x9, x10)

inst_2686:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:7995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7995*FLEN/8, x13, x9, x10)

inst_2687:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:7998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 7998*FLEN/8, x13, x9, x10)

inst_2688:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:8001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8001*FLEN/8, x13, x9, x10)

inst_2689:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:8004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8004*FLEN/8, x13, x9, x10)

inst_2690:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:8007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8007*FLEN/8, x13, x9, x10)

inst_2691:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:8010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8010*FLEN/8, x13, x9, x10)

inst_2692:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:8013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8013*FLEN/8, x13, x9, x10)

inst_2693:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8016*FLEN/8, x13, x9, x10)

inst_2694:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8019*FLEN/8, x13, x9, x10)

inst_2695:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8022*FLEN/8, x13, x9, x10)

inst_2696:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:8025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8025*FLEN/8, x13, x9, x10)

inst_2697:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:8028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8028*FLEN/8, x13, x9, x10)

inst_2698:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:8031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8031*FLEN/8, x13, x9, x10)

inst_2699:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:8034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8034*FLEN/8, x13, x9, x10)

inst_2700:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8037*FLEN/8, x13, x9, x10)

inst_2701:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8040*FLEN/8, x13, x9, x10)

inst_2702:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8043*FLEN/8, x13, x9, x10)

inst_2703:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:8046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8046*FLEN/8, x13, x9, x10)

inst_2704:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8049*FLEN/8, x13, x9, x10)

inst_2705:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8052*FLEN/8, x13, x9, x10)

inst_2706:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8055*FLEN/8, x13, x9, x10)

inst_2707:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8058*FLEN/8, x13, x9, x10)

inst_2708:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8061*FLEN/8, x13, x9, x10)

inst_2709:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8064*FLEN/8, x13, x9, x10)

inst_2710:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8067*FLEN/8, x13, x9, x10)

inst_2711:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8070*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_21)

inst_2712:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:8073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8073*FLEN/8, x13, x9, x10)

inst_2713:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:8076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8076*FLEN/8, x13, x9, x10)

inst_2714:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:8079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8079*FLEN/8, x13, x9, x10)

inst_2715:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:8082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8082*FLEN/8, x13, x9, x10)

inst_2716:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:8085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8085*FLEN/8, x13, x9, x10)

inst_2717:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8088*FLEN/8, x13, x9, x10)

inst_2718:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8091*FLEN/8, x13, x9, x10)

inst_2719:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8094*FLEN/8, x13, x9, x10)

inst_2720:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:8097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8097*FLEN/8, x13, x9, x10)

inst_2721:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:8100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8100*FLEN/8, x13, x9, x10)

inst_2722:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:8103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8103*FLEN/8, x13, x9, x10)

inst_2723:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:8106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8106*FLEN/8, x13, x9, x10)

inst_2724:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8109*FLEN/8, x13, x9, x10)

inst_2725:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8112*FLEN/8, x13, x9, x10)

inst_2726:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8115*FLEN/8, x13, x9, x10)

inst_2727:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:8118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8118*FLEN/8, x13, x9, x10)

inst_2728:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8121*FLEN/8, x13, x9, x10)

inst_2729:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8124*FLEN/8, x13, x9, x10)

inst_2730:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8127*FLEN/8, x13, x9, x10)

inst_2731:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8130*FLEN/8, x13, x9, x10)

inst_2732:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8133*FLEN/8, x13, x9, x10)

inst_2733:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8136*FLEN/8, x13, x9, x10)

inst_2734:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8139*FLEN/8, x13, x9, x10)

inst_2735:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8142*FLEN/8, x13, x9, x10)

inst_2736:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:8145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8145*FLEN/8, x13, x9, x10)

inst_2737:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:8148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8148*FLEN/8, x13, x9, x10)

inst_2738:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:8151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8151*FLEN/8, x13, x9, x10)

inst_2739:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:8154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8154*FLEN/8, x13, x9, x10)

inst_2740:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:8157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8157*FLEN/8, x13, x9, x10)

inst_2741:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8160*FLEN/8, x13, x9, x10)

inst_2742:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8163*FLEN/8, x13, x9, x10)

inst_2743:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8166*FLEN/8, x13, x9, x10)

inst_2744:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:8169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8169*FLEN/8, x13, x9, x10)

inst_2745:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:8172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8172*FLEN/8, x13, x9, x10)

inst_2746:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:8175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8175*FLEN/8, x13, x9, x10)

inst_2747:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:8178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8178*FLEN/8, x13, x9, x10)

inst_2748:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8181*FLEN/8, x13, x9, x10)

inst_2749:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8184*FLEN/8, x13, x9, x10)

inst_2750:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8187*FLEN/8, x13, x9, x10)

inst_2751:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:8190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8190*FLEN/8, x13, x9, x10)

inst_2752:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8193*FLEN/8, x13, x9, x10)

inst_2753:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8196*FLEN/8, x13, x9, x10)

inst_2754:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8199*FLEN/8, x13, x9, x10)

inst_2755:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8202*FLEN/8, x13, x9, x10)

inst_2756:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8205*FLEN/8, x13, x9, x10)

inst_2757:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8208*FLEN/8, x13, x9, x10)

inst_2758:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8211*FLEN/8, x13, x9, x10)

inst_2759:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8214*FLEN/8, x13, x9, x10)

inst_2760:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:8217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8217*FLEN/8, x13, x9, x10)

inst_2761:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:8220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8220*FLEN/8, x13, x9, x10)

inst_2762:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:8223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8223*FLEN/8, x13, x9, x10)

inst_2763:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:8226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8226*FLEN/8, x13, x9, x10)

inst_2764:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:8229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8229*FLEN/8, x13, x9, x10)

inst_2765:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8232*FLEN/8, x13, x9, x10)

inst_2766:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8235*FLEN/8, x13, x9, x10)

inst_2767:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8238*FLEN/8, x13, x9, x10)

inst_2768:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:8241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8241*FLEN/8, x13, x9, x10)

inst_2769:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:8244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8244*FLEN/8, x13, x9, x10)

inst_2770:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:8247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8247*FLEN/8, x13, x9, x10)

inst_2771:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:8250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8250*FLEN/8, x13, x9, x10)

inst_2772:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8253*FLEN/8, x13, x9, x10)

inst_2773:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8256*FLEN/8, x13, x9, x10)

inst_2774:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8259*FLEN/8, x13, x9, x10)

inst_2775:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:8262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8262*FLEN/8, x13, x9, x10)

inst_2776:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8265*FLEN/8, x13, x9, x10)

inst_2777:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8268*FLEN/8, x13, x9, x10)

inst_2778:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8271*FLEN/8, x13, x9, x10)

inst_2779:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8274*FLEN/8, x13, x9, x10)

inst_2780:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8277*FLEN/8, x13, x9, x10)

inst_2781:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8280*FLEN/8, x13, x9, x10)

inst_2782:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8283*FLEN/8, x13, x9, x10)

inst_2783:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8286*FLEN/8, x13, x9, x10)

inst_2784:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:8289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8289*FLEN/8, x13, x9, x10)

inst_2785:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:8292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8292*FLEN/8, x13, x9, x10)

inst_2786:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:8295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8295*FLEN/8, x13, x9, x10)

inst_2787:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:8298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8298*FLEN/8, x13, x9, x10)

inst_2788:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:8301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8301*FLEN/8, x13, x9, x10)

inst_2789:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8304*FLEN/8, x13, x9, x10)

inst_2790:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8307*FLEN/8, x13, x9, x10)

inst_2791:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8310*FLEN/8, x13, x9, x10)

inst_2792:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:8313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8313*FLEN/8, x13, x9, x10)

inst_2793:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:8316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8316*FLEN/8, x13, x9, x10)

inst_2794:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:8319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8319*FLEN/8, x13, x9, x10)

inst_2795:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:8322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8322*FLEN/8, x13, x9, x10)

inst_2796:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8325*FLEN/8, x13, x9, x10)

inst_2797:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8328*FLEN/8, x13, x9, x10)

inst_2798:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8331*FLEN/8, x13, x9, x10)

inst_2799:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:8334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8334*FLEN/8, x13, x9, x10)

inst_2800:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8337*FLEN/8, x13, x9, x10)

inst_2801:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8340*FLEN/8, x13, x9, x10)

inst_2802:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8343*FLEN/8, x13, x9, x10)

inst_2803:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8346*FLEN/8, x13, x9, x10)

inst_2804:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8349*FLEN/8, x13, x9, x10)

inst_2805:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8352*FLEN/8, x13, x9, x10)

inst_2806:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8355*FLEN/8, x13, x9, x10)

inst_2807:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8358*FLEN/8, x13, x9, x10)

inst_2808:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:8361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8361*FLEN/8, x13, x9, x10)

inst_2809:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:8364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8364*FLEN/8, x13, x9, x10)

inst_2810:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:8367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8367*FLEN/8, x13, x9, x10)

inst_2811:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:8370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8370*FLEN/8, x13, x9, x10)

inst_2812:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:8373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8373*FLEN/8, x13, x9, x10)

inst_2813:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8376*FLEN/8, x13, x9, x10)

inst_2814:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8379*FLEN/8, x13, x9, x10)

inst_2815:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8382*FLEN/8, x13, x9, x10)

inst_2816:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:8385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8385*FLEN/8, x13, x9, x10)

inst_2817:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:8388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8388*FLEN/8, x13, x9, x10)

inst_2818:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:8391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8391*FLEN/8, x13, x9, x10)

inst_2819:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:8394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8394*FLEN/8, x13, x9, x10)

inst_2820:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8397*FLEN/8, x13, x9, x10)

inst_2821:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8400*FLEN/8, x13, x9, x10)

inst_2822:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8403*FLEN/8, x13, x9, x10)

inst_2823:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:8406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8406*FLEN/8, x13, x9, x10)

inst_2824:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8409*FLEN/8, x13, x9, x10)

inst_2825:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8412*FLEN/8, x13, x9, x10)

inst_2826:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8415*FLEN/8, x13, x9, x10)

inst_2827:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8418*FLEN/8, x13, x9, x10)

inst_2828:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8421*FLEN/8, x13, x9, x10)

inst_2829:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8424*FLEN/8, x13, x9, x10)

inst_2830:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8427*FLEN/8, x13, x9, x10)

inst_2831:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8430*FLEN/8, x13, x9, x10)

inst_2832:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:8433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8433*FLEN/8, x13, x9, x10)

inst_2833:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:8436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8436*FLEN/8, x13, x9, x10)

inst_2834:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:8439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8439*FLEN/8, x13, x9, x10)

inst_2835:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:8442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8442*FLEN/8, x13, x9, x10)

inst_2836:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:8445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8445*FLEN/8, x13, x9, x10)

inst_2837:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8448*FLEN/8, x13, x9, x10)

inst_2838:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8451*FLEN/8, x13, x9, x10)

inst_2839:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8454*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_22)

inst_2840:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:8457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8457*FLEN/8, x13, x9, x10)

inst_2841:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:8460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8460*FLEN/8, x13, x9, x10)

inst_2842:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:8463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8463*FLEN/8, x13, x9, x10)

inst_2843:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:8466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8466*FLEN/8, x13, x9, x10)

inst_2844:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8469*FLEN/8, x13, x9, x10)

inst_2845:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8472*FLEN/8, x13, x9, x10)

inst_2846:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8475*FLEN/8, x13, x9, x10)

inst_2847:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:8478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8478*FLEN/8, x13, x9, x10)

inst_2848:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8481*FLEN/8, x13, x9, x10)

inst_2849:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8484*FLEN/8, x13, x9, x10)

inst_2850:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8487*FLEN/8, x13, x9, x10)

inst_2851:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8490*FLEN/8, x13, x9, x10)

inst_2852:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8493*FLEN/8, x13, x9, x10)

inst_2853:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8496*FLEN/8, x13, x9, x10)

inst_2854:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8499*FLEN/8, x13, x9, x10)

inst_2855:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8502*FLEN/8, x13, x9, x10)

inst_2856:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:8505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8505*FLEN/8, x13, x9, x10)

inst_2857:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:8508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8508*FLEN/8, x13, x9, x10)

inst_2858:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:8511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8511*FLEN/8, x13, x9, x10)

inst_2859:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:8514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8514*FLEN/8, x13, x9, x10)

inst_2860:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:8517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8517*FLEN/8, x13, x9, x10)

inst_2861:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8520*FLEN/8, x13, x9, x10)

inst_2862:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8523*FLEN/8, x13, x9, x10)

inst_2863:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8526*FLEN/8, x13, x9, x10)

inst_2864:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:8529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8529*FLEN/8, x13, x9, x10)

inst_2865:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:8532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8532*FLEN/8, x13, x9, x10)

inst_2866:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:8535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8535*FLEN/8, x13, x9, x10)

inst_2867:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:8538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8538*FLEN/8, x13, x9, x10)

inst_2868:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8541*FLEN/8, x13, x9, x10)

inst_2869:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8544*FLEN/8, x13, x9, x10)

inst_2870:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8547*FLEN/8, x13, x9, x10)

inst_2871:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:8550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8550*FLEN/8, x13, x9, x10)

inst_2872:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8553*FLEN/8, x13, x9, x10)

inst_2873:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8556*FLEN/8, x13, x9, x10)

inst_2874:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8559*FLEN/8, x13, x9, x10)

inst_2875:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8562*FLEN/8, x13, x9, x10)

inst_2876:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8565*FLEN/8, x13, x9, x10)

inst_2877:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8568*FLEN/8, x13, x9, x10)

inst_2878:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8571*FLEN/8, x13, x9, x10)

inst_2879:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8574*FLEN/8, x13, x9, x10)

inst_2880:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:8577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8577*FLEN/8, x13, x9, x10)

inst_2881:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:8580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8580*FLEN/8, x13, x9, x10)

inst_2882:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:8583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8583*FLEN/8, x13, x9, x10)

inst_2883:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:8586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8586*FLEN/8, x13, x9, x10)

inst_2884:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:8589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8589*FLEN/8, x13, x9, x10)

inst_2885:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8592*FLEN/8, x13, x9, x10)

inst_2886:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8595*FLEN/8, x13, x9, x10)

inst_2887:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8598*FLEN/8, x13, x9, x10)

inst_2888:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:8601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8601*FLEN/8, x13, x9, x10)

inst_2889:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:8604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8604*FLEN/8, x13, x9, x10)

inst_2890:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:8607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8607*FLEN/8, x13, x9, x10)

inst_2891:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:8610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8610*FLEN/8, x13, x9, x10)

inst_2892:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8613*FLEN/8, x13, x9, x10)

inst_2893:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8616*FLEN/8, x13, x9, x10)

inst_2894:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8619*FLEN/8, x13, x9, x10)

inst_2895:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:8622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8622*FLEN/8, x13, x9, x10)

inst_2896:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8625*FLEN/8, x13, x9, x10)

inst_2897:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8628*FLEN/8, x13, x9, x10)

inst_2898:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8631*FLEN/8, x13, x9, x10)

inst_2899:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8634*FLEN/8, x13, x9, x10)

inst_2900:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8637*FLEN/8, x13, x9, x10)

inst_2901:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8640*FLEN/8, x13, x9, x10)

inst_2902:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8643*FLEN/8, x13, x9, x10)

inst_2903:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8646*FLEN/8, x13, x9, x10)

inst_2904:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:8649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8649*FLEN/8, x13, x9, x10)

inst_2905:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:8652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8652*FLEN/8, x13, x9, x10)

inst_2906:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:8655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8655*FLEN/8, x13, x9, x10)

inst_2907:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:8658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8658*FLEN/8, x13, x9, x10)

inst_2908:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:8661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8661*FLEN/8, x13, x9, x10)

inst_2909:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8664*FLEN/8, x13, x9, x10)

inst_2910:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8667*FLEN/8, x13, x9, x10)

inst_2911:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8670*FLEN/8, x13, x9, x10)

inst_2912:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:8673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8673*FLEN/8, x13, x9, x10)

inst_2913:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:8676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8676*FLEN/8, x13, x9, x10)

inst_2914:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:8679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8679*FLEN/8, x13, x9, x10)

inst_2915:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:8682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8682*FLEN/8, x13, x9, x10)

inst_2916:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8685*FLEN/8, x13, x9, x10)

inst_2917:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8688*FLEN/8, x13, x9, x10)

inst_2918:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8691*FLEN/8, x13, x9, x10)

inst_2919:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:8694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8694*FLEN/8, x13, x9, x10)

inst_2920:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8697*FLEN/8, x13, x9, x10)

inst_2921:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8700*FLEN/8, x13, x9, x10)

inst_2922:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8703*FLEN/8, x13, x9, x10)

inst_2923:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8706*FLEN/8, x13, x9, x10)

inst_2924:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8709*FLEN/8, x13, x9, x10)

inst_2925:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8712*FLEN/8, x13, x9, x10)

inst_2926:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8715*FLEN/8, x13, x9, x10)

inst_2927:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8718*FLEN/8, x13, x9, x10)

inst_2928:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:8721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8721*FLEN/8, x13, x9, x10)

inst_2929:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:8724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8724*FLEN/8, x13, x9, x10)

inst_2930:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:8727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8727*FLEN/8, x13, x9, x10)

inst_2931:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:8730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8730*FLEN/8, x13, x9, x10)

inst_2932:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:8733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8733*FLEN/8, x13, x9, x10)

inst_2933:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8736*FLEN/8, x13, x9, x10)

inst_2934:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8739*FLEN/8, x13, x9, x10)

inst_2935:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8742*FLEN/8, x13, x9, x10)

inst_2936:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:8745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8745*FLEN/8, x13, x9, x10)

inst_2937:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:8748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8748*FLEN/8, x13, x9, x10)

inst_2938:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:8751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8751*FLEN/8, x13, x9, x10)

inst_2939:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:8754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8754*FLEN/8, x13, x9, x10)

inst_2940:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8757*FLEN/8, x13, x9, x10)

inst_2941:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8760*FLEN/8, x13, x9, x10)

inst_2942:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8763*FLEN/8, x13, x9, x10)

inst_2943:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:8766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8766*FLEN/8, x13, x9, x10)

inst_2944:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8769*FLEN/8, x13, x9, x10)

inst_2945:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8772*FLEN/8, x13, x9, x10)

inst_2946:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8775*FLEN/8, x13, x9, x10)

inst_2947:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8778*FLEN/8, x13, x9, x10)

inst_2948:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8781*FLEN/8, x13, x9, x10)

inst_2949:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8784*FLEN/8, x13, x9, x10)

inst_2950:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8787*FLEN/8, x13, x9, x10)

inst_2951:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8790*FLEN/8, x13, x9, x10)

inst_2952:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:8793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8793*FLEN/8, x13, x9, x10)

inst_2953:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:8796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8796*FLEN/8, x13, x9, x10)

inst_2954:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:8799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8799*FLEN/8, x13, x9, x10)

inst_2955:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:8802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8802*FLEN/8, x13, x9, x10)

inst_2956:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:8805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8805*FLEN/8, x13, x9, x10)

inst_2957:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8808*FLEN/8, x13, x9, x10)

inst_2958:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8811*FLEN/8, x13, x9, x10)

inst_2959:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8814*FLEN/8, x13, x9, x10)

inst_2960:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:8817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8817*FLEN/8, x13, x9, x10)

inst_2961:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:8820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8820*FLEN/8, x13, x9, x10)

inst_2962:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:8823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8823*FLEN/8, x13, x9, x10)

inst_2963:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:8826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8826*FLEN/8, x13, x9, x10)

inst_2964:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8829*FLEN/8, x13, x9, x10)

inst_2965:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8832*FLEN/8, x13, x9, x10)

inst_2966:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8835*FLEN/8, x13, x9, x10)

inst_2967:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:8838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8838*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_23)

inst_2968:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8841*FLEN/8, x13, x9, x10)

inst_2969:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8844*FLEN/8, x13, x9, x10)

inst_2970:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8847*FLEN/8, x13, x9, x10)

inst_2971:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8850*FLEN/8, x13, x9, x10)

inst_2972:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8853*FLEN/8, x13, x9, x10)

inst_2973:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8856*FLEN/8, x13, x9, x10)

inst_2974:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8859*FLEN/8, x13, x9, x10)

inst_2975:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8862*FLEN/8, x13, x9, x10)

inst_2976:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:8865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8865*FLEN/8, x13, x9, x10)

inst_2977:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:8868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8868*FLEN/8, x13, x9, x10)

inst_2978:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:8871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8871*FLEN/8, x13, x9, x10)

inst_2979:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:8874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8874*FLEN/8, x13, x9, x10)

inst_2980:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:8877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8877*FLEN/8, x13, x9, x10)

inst_2981:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8880*FLEN/8, x13, x9, x10)

inst_2982:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8883*FLEN/8, x13, x9, x10)

inst_2983:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8886*FLEN/8, x13, x9, x10)

inst_2984:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:8889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8889*FLEN/8, x13, x9, x10)

inst_2985:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:8892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8892*FLEN/8, x13, x9, x10)

inst_2986:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:8895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8895*FLEN/8, x13, x9, x10)

inst_2987:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:8898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8898*FLEN/8, x13, x9, x10)

inst_2988:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8901*FLEN/8, x13, x9, x10)

inst_2989:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8904*FLEN/8, x13, x9, x10)

inst_2990:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8907*FLEN/8, x13, x9, x10)

inst_2991:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:8910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8910*FLEN/8, x13, x9, x10)

inst_2992:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8913*FLEN/8, x13, x9, x10)

inst_2993:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8916*FLEN/8, x13, x9, x10)

inst_2994:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8919*FLEN/8, x13, x9, x10)

inst_2995:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8922*FLEN/8, x13, x9, x10)

inst_2996:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8925*FLEN/8, x13, x9, x10)

inst_2997:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:8928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8928*FLEN/8, x13, x9, x10)

inst_2998:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:8931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8931*FLEN/8, x13, x9, x10)

inst_2999:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:8934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8934*FLEN/8, x13, x9, x10)

inst_3000:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:8937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8937*FLEN/8, x13, x9, x10)

inst_3001:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:8940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8940*FLEN/8, x13, x9, x10)

inst_3002:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:8943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8943*FLEN/8, x13, x9, x10)

inst_3003:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:8946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8946*FLEN/8, x13, x9, x10)

inst_3004:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:8949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8949*FLEN/8, x13, x9, x10)

inst_3005:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:8952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8952*FLEN/8, x13, x9, x10)

inst_3006:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:8955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8955*FLEN/8, x13, x9, x10)

inst_3007:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:8958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8958*FLEN/8, x13, x9, x10)

inst_3008:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:8961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8961*FLEN/8, x13, x9, x10)

inst_3009:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:8964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8964*FLEN/8, x13, x9, x10)

inst_3010:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:8967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8967*FLEN/8, x13, x9, x10)

inst_3011:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:8970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8970*FLEN/8, x13, x9, x10)

inst_3012:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:8973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8973*FLEN/8, x13, x9, x10)

inst_3013:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:8976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8976*FLEN/8, x13, x9, x10)

inst_3014:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:8979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8979*FLEN/8, x13, x9, x10)

inst_3015:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:8982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8982*FLEN/8, x13, x9, x10)

inst_3016:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:8985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8985*FLEN/8, x13, x9, x10)

inst_3017:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:8988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8988*FLEN/8, x13, x9, x10)

inst_3018:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:8991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8991*FLEN/8, x13, x9, x10)

inst_3019:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:8994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8994*FLEN/8, x13, x9, x10)

inst_3020:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:8997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 8997*FLEN/8, x13, x9, x10)

inst_3021:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9000*FLEN/8, x13, x9, x10)

inst_3022:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9003*FLEN/8, x13, x9, x10)

inst_3023:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9006*FLEN/8, x13, x9, x10)

inst_3024:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:9009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9009*FLEN/8, x13, x9, x10)

inst_3025:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:9012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9012*FLEN/8, x13, x9, x10)

inst_3026:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:9015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9015*FLEN/8, x13, x9, x10)

inst_3027:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:9018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9018*FLEN/8, x13, x9, x10)

inst_3028:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:9021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9021*FLEN/8, x13, x9, x10)

inst_3029:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9024*FLEN/8, x13, x9, x10)

inst_3030:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9027*FLEN/8, x13, x9, x10)

inst_3031:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9030*FLEN/8, x13, x9, x10)

inst_3032:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:9033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9033*FLEN/8, x13, x9, x10)

inst_3033:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:9036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9036*FLEN/8, x13, x9, x10)

inst_3034:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:9039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9039*FLEN/8, x13, x9, x10)

inst_3035:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:9042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9042*FLEN/8, x13, x9, x10)

inst_3036:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9045*FLEN/8, x13, x9, x10)

inst_3037:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9048*FLEN/8, x13, x9, x10)

inst_3038:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9051*FLEN/8, x13, x9, x10)

inst_3039:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:9054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9054*FLEN/8, x13, x9, x10)

inst_3040:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9057*FLEN/8, x13, x9, x10)

inst_3041:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9060*FLEN/8, x13, x9, x10)

inst_3042:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9063*FLEN/8, x13, x9, x10)

inst_3043:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9066*FLEN/8, x13, x9, x10)

inst_3044:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9069*FLEN/8, x13, x9, x10)

inst_3045:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9072*FLEN/8, x13, x9, x10)

inst_3046:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9075*FLEN/8, x13, x9, x10)

inst_3047:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9078*FLEN/8, x13, x9, x10)

inst_3048:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:9081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9081*FLEN/8, x13, x9, x10)

inst_3049:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:9084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9084*FLEN/8, x13, x9, x10)

inst_3050:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:9087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9087*FLEN/8, x13, x9, x10)

inst_3051:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:9090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9090*FLEN/8, x13, x9, x10)

inst_3052:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:9093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9093*FLEN/8, x13, x9, x10)

inst_3053:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9096*FLEN/8, x13, x9, x10)

inst_3054:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9099*FLEN/8, x13, x9, x10)

inst_3055:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9102*FLEN/8, x13, x9, x10)

inst_3056:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:9105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9105*FLEN/8, x13, x9, x10)

inst_3057:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:9108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9108*FLEN/8, x13, x9, x10)

inst_3058:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:9111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9111*FLEN/8, x13, x9, x10)

inst_3059:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:9114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9114*FLEN/8, x13, x9, x10)

inst_3060:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9117*FLEN/8, x13, x9, x10)

inst_3061:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9120*FLEN/8, x13, x9, x10)

inst_3062:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9123*FLEN/8, x13, x9, x10)

inst_3063:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:9126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9126*FLEN/8, x13, x9, x10)

inst_3064:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9129*FLEN/8, x13, x9, x10)

inst_3065:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9132*FLEN/8, x13, x9, x10)

inst_3066:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9135*FLEN/8, x13, x9, x10)

inst_3067:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9138*FLEN/8, x13, x9, x10)

inst_3068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9141*FLEN/8, x13, x9, x10)

inst_3069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9144*FLEN/8, x13, x9, x10)

inst_3070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9147*FLEN/8, x13, x9, x10)

inst_3071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9150*FLEN/8, x13, x9, x10)

inst_3072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:9153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9153*FLEN/8, x13, x9, x10)

inst_3073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:9156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9156*FLEN/8, x13, x9, x10)

inst_3074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:9159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9159*FLEN/8, x13, x9, x10)

inst_3075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:9162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9162*FLEN/8, x13, x9, x10)

inst_3076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:9165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9165*FLEN/8, x13, x9, x10)

inst_3077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9168*FLEN/8, x13, x9, x10)

inst_3078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9171*FLEN/8, x13, x9, x10)

inst_3079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9174*FLEN/8, x13, x9, x10)

inst_3080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:9177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9177*FLEN/8, x13, x9, x10)

inst_3081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:9180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9180*FLEN/8, x13, x9, x10)

inst_3082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:9183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9183*FLEN/8, x13, x9, x10)

inst_3083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:9186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9186*FLEN/8, x13, x9, x10)

inst_3084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9189*FLEN/8, x13, x9, x10)

inst_3085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9192*FLEN/8, x13, x9, x10)

inst_3086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9195*FLEN/8, x13, x9, x10)

inst_3087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:9198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9198*FLEN/8, x13, x9, x10)

inst_3088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9201*FLEN/8, x13, x9, x10)

inst_3089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9204*FLEN/8, x13, x9, x10)

inst_3090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9207*FLEN/8, x13, x9, x10)

inst_3091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9210*FLEN/8, x13, x9, x10)

inst_3092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9213*FLEN/8, x13, x9, x10)

inst_3093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9216*FLEN/8, x13, x9, x10)

inst_3094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9219*FLEN/8, x13, x9, x10)

inst_3095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9222*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_24)

inst_3096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:9225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9225*FLEN/8, x13, x9, x10)

inst_3097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:9228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9228*FLEN/8, x13, x9, x10)

inst_3098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:9231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9231*FLEN/8, x13, x9, x10)

inst_3099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:9234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9234*FLEN/8, x13, x9, x10)

inst_3100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:9237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9237*FLEN/8, x13, x9, x10)

inst_3101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9240*FLEN/8, x13, x9, x10)

inst_3102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9243*FLEN/8, x13, x9, x10)

inst_3103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9246*FLEN/8, x13, x9, x10)

inst_3104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:9249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9249*FLEN/8, x13, x9, x10)

inst_3105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:9252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9252*FLEN/8, x13, x9, x10)

inst_3106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:9255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9255*FLEN/8, x13, x9, x10)

inst_3107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:9258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9258*FLEN/8, x13, x9, x10)

inst_3108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9261*FLEN/8, x13, x9, x10)

inst_3109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9264*FLEN/8, x13, x9, x10)

inst_3110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9267*FLEN/8, x13, x9, x10)

inst_3111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:9270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9270*FLEN/8, x13, x9, x10)

inst_3112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9273*FLEN/8, x13, x9, x10)

inst_3113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9276*FLEN/8, x13, x9, x10)

inst_3114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9279*FLEN/8, x13, x9, x10)

inst_3115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9282*FLEN/8, x13, x9, x10)

inst_3116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9285*FLEN/8, x13, x9, x10)

inst_3117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9288*FLEN/8, x13, x9, x10)

inst_3118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9291*FLEN/8, x13, x9, x10)

inst_3119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9294*FLEN/8, x13, x9, x10)

inst_3120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:9297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9297*FLEN/8, x13, x9, x10)

inst_3121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:9300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9300*FLEN/8, x13, x9, x10)

inst_3122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:9303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9303*FLEN/8, x13, x9, x10)

inst_3123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:9306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9306*FLEN/8, x13, x9, x10)

inst_3124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:9309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9309*FLEN/8, x13, x9, x10)

inst_3125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9312*FLEN/8, x13, x9, x10)

inst_3126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9315*FLEN/8, x13, x9, x10)

inst_3127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9318*FLEN/8, x13, x9, x10)

inst_3128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:9321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9321*FLEN/8, x13, x9, x10)

inst_3129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:9324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9324*FLEN/8, x13, x9, x10)

inst_3130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:9327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9327*FLEN/8, x13, x9, x10)

inst_3131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:9330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9330*FLEN/8, x13, x9, x10)

inst_3132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9333*FLEN/8, x13, x9, x10)

inst_3133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9336*FLEN/8, x13, x9, x10)

inst_3134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9339*FLEN/8, x13, x9, x10)

inst_3135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:9342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9342*FLEN/8, x13, x9, x10)

inst_3136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9345*FLEN/8, x13, x9, x10)

inst_3137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9348*FLEN/8, x13, x9, x10)

inst_3138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9351*FLEN/8, x13, x9, x10)

inst_3139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9354*FLEN/8, x13, x9, x10)

inst_3140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9357*FLEN/8, x13, x9, x10)

inst_3141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9360*FLEN/8, x13, x9, x10)

inst_3142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9363*FLEN/8, x13, x9, x10)

inst_3143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9366*FLEN/8, x13, x9, x10)

inst_3144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:9369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9369*FLEN/8, x13, x9, x10)

inst_3145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:9372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9372*FLEN/8, x13, x9, x10)

inst_3146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:9375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9375*FLEN/8, x13, x9, x10)

inst_3147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:9378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9378*FLEN/8, x13, x9, x10)

inst_3148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:9381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9381*FLEN/8, x13, x9, x10)

inst_3149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9384*FLEN/8, x13, x9, x10)

inst_3150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9387*FLEN/8, x13, x9, x10)

inst_3151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9390*FLEN/8, x13, x9, x10)

inst_3152:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:9393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9393*FLEN/8, x13, x9, x10)

inst_3153:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:9396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9396*FLEN/8, x13, x9, x10)

inst_3154:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:9399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9399*FLEN/8, x13, x9, x10)

inst_3155:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:9402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9402*FLEN/8, x13, x9, x10)

inst_3156:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9405*FLEN/8, x13, x9, x10)

inst_3157:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9408*FLEN/8, x13, x9, x10)

inst_3158:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9411*FLEN/8, x13, x9, x10)

inst_3159:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:9414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9414*FLEN/8, x13, x9, x10)

inst_3160:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9417*FLEN/8, x13, x9, x10)

inst_3161:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9420*FLEN/8, x13, x9, x10)

inst_3162:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9423*FLEN/8, x13, x9, x10)

inst_3163:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9426*FLEN/8, x13, x9, x10)

inst_3164:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9429*FLEN/8, x13, x9, x10)

inst_3165:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9432*FLEN/8, x13, x9, x10)

inst_3166:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9435*FLEN/8, x13, x9, x10)

inst_3167:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9438*FLEN/8, x13, x9, x10)

inst_3168:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:9441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9441*FLEN/8, x13, x9, x10)

inst_3169:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:9444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9444*FLEN/8, x13, x9, x10)

inst_3170:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:9447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9447*FLEN/8, x13, x9, x10)

inst_3171:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:9450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9450*FLEN/8, x13, x9, x10)

inst_3172:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:9453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9453*FLEN/8, x13, x9, x10)

inst_3173:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9456*FLEN/8, x13, x9, x10)

inst_3174:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9459*FLEN/8, x13, x9, x10)

inst_3175:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9462*FLEN/8, x13, x9, x10)

inst_3176:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:9465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9465*FLEN/8, x13, x9, x10)

inst_3177:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:9468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9468*FLEN/8, x13, x9, x10)

inst_3178:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:9471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9471*FLEN/8, x13, x9, x10)

inst_3179:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:9474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9474*FLEN/8, x13, x9, x10)

inst_3180:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9477*FLEN/8, x13, x9, x10)

inst_3181:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9480*FLEN/8, x13, x9, x10)

inst_3182:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9483*FLEN/8, x13, x9, x10)

inst_3183:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:9486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9486*FLEN/8, x13, x9, x10)

inst_3184:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9489*FLEN/8, x13, x9, x10)

inst_3185:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9492*FLEN/8, x13, x9, x10)

inst_3186:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9495*FLEN/8, x13, x9, x10)

inst_3187:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9498*FLEN/8, x13, x9, x10)

inst_3188:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9501*FLEN/8, x13, x9, x10)

inst_3189:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9504*FLEN/8, x13, x9, x10)

inst_3190:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9507*FLEN/8, x13, x9, x10)

inst_3191:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9510*FLEN/8, x13, x9, x10)

inst_3192:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:9513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9513*FLEN/8, x13, x9, x10)

inst_3193:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:9516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9516*FLEN/8, x13, x9, x10)

inst_3194:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:9519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9519*FLEN/8, x13, x9, x10)

inst_3195:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:9522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9522*FLEN/8, x13, x9, x10)

inst_3196:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:9525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9525*FLEN/8, x13, x9, x10)

inst_3197:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9528*FLEN/8, x13, x9, x10)

inst_3198:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9531*FLEN/8, x13, x9, x10)

inst_3199:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9534*FLEN/8, x13, x9, x10)

inst_3200:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:9537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9537*FLEN/8, x13, x9, x10)

inst_3201:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:9540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9540*FLEN/8, x13, x9, x10)

inst_3202:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:9543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9543*FLEN/8, x13, x9, x10)

inst_3203:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:9546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9546*FLEN/8, x13, x9, x10)

inst_3204:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9549*FLEN/8, x13, x9, x10)

inst_3205:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9552*FLEN/8, x13, x9, x10)

inst_3206:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9555*FLEN/8, x13, x9, x10)

inst_3207:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:9558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9558*FLEN/8, x13, x9, x10)

inst_3208:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9561*FLEN/8, x13, x9, x10)

inst_3209:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9564*FLEN/8, x13, x9, x10)

inst_3210:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9567*FLEN/8, x13, x9, x10)

inst_3211:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9570*FLEN/8, x13, x9, x10)

inst_3212:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9573*FLEN/8, x13, x9, x10)

inst_3213:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9576*FLEN/8, x13, x9, x10)

inst_3214:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9579*FLEN/8, x13, x9, x10)

inst_3215:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9582*FLEN/8, x13, x9, x10)

inst_3216:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:9585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9585*FLEN/8, x13, x9, x10)

inst_3217:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:9588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9588*FLEN/8, x13, x9, x10)

inst_3218:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:9591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9591*FLEN/8, x13, x9, x10)

inst_3219:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:9594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9594*FLEN/8, x13, x9, x10)

inst_3220:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:9597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9597*FLEN/8, x13, x9, x10)

inst_3221:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9600*FLEN/8, x13, x9, x10)

inst_3222:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9603*FLEN/8, x13, x9, x10)

inst_3223:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9606*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_25)

inst_3224:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:9609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9609*FLEN/8, x13, x9, x10)

inst_3225:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:9612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9612*FLEN/8, x13, x9, x10)

inst_3226:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:9615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9615*FLEN/8, x13, x9, x10)

inst_3227:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:9618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9618*FLEN/8, x13, x9, x10)

inst_3228:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9621*FLEN/8, x13, x9, x10)

inst_3229:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9624*FLEN/8, x13, x9, x10)

inst_3230:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9627*FLEN/8, x13, x9, x10)

inst_3231:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:9630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9630*FLEN/8, x13, x9, x10)

inst_3232:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9633*FLEN/8, x13, x9, x10)

inst_3233:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9636*FLEN/8, x13, x9, x10)

inst_3234:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9639*FLEN/8, x13, x9, x10)

inst_3235:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9642*FLEN/8, x13, x9, x10)

inst_3236:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9645*FLEN/8, x13, x9, x10)

inst_3237:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9648*FLEN/8, x13, x9, x10)

inst_3238:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9651*FLEN/8, x13, x9, x10)

inst_3239:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9654*FLEN/8, x13, x9, x10)

inst_3240:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:9657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9657*FLEN/8, x13, x9, x10)

inst_3241:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:9660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9660*FLEN/8, x13, x9, x10)

inst_3242:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:9663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9663*FLEN/8, x13, x9, x10)

inst_3243:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:9666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9666*FLEN/8, x13, x9, x10)

inst_3244:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:9669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9669*FLEN/8, x13, x9, x10)

inst_3245:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9672*FLEN/8, x13, x9, x10)

inst_3246:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9675*FLEN/8, x13, x9, x10)

inst_3247:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9678*FLEN/8, x13, x9, x10)

inst_3248:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:9681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9681*FLEN/8, x13, x9, x10)

inst_3249:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:9684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9684*FLEN/8, x13, x9, x10)

inst_3250:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:9687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9687*FLEN/8, x13, x9, x10)

inst_3251:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:9690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9690*FLEN/8, x13, x9, x10)

inst_3252:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9693*FLEN/8, x13, x9, x10)

inst_3253:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9696*FLEN/8, x13, x9, x10)

inst_3254:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9699*FLEN/8, x13, x9, x10)

inst_3255:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:9702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9702*FLEN/8, x13, x9, x10)

inst_3256:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9705*FLEN/8, x13, x9, x10)

inst_3257:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9708*FLEN/8, x13, x9, x10)

inst_3258:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9711*FLEN/8, x13, x9, x10)

inst_3259:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9714*FLEN/8, x13, x9, x10)

inst_3260:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9717*FLEN/8, x13, x9, x10)

inst_3261:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9720*FLEN/8, x13, x9, x10)

inst_3262:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9723*FLEN/8, x13, x9, x10)

inst_3263:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9726*FLEN/8, x13, x9, x10)

inst_3264:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:9729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9729*FLEN/8, x13, x9, x10)

inst_3265:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:9732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9732*FLEN/8, x13, x9, x10)

inst_3266:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:9735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9735*FLEN/8, x13, x9, x10)

inst_3267:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:9738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9738*FLEN/8, x13, x9, x10)

inst_3268:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:9741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9741*FLEN/8, x13, x9, x10)

inst_3269:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9744*FLEN/8, x13, x9, x10)

inst_3270:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9747*FLEN/8, x13, x9, x10)

inst_3271:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9750*FLEN/8, x13, x9, x10)

inst_3272:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:9753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9753*FLEN/8, x13, x9, x10)

inst_3273:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:9756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9756*FLEN/8, x13, x9, x10)

inst_3274:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:9759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9759*FLEN/8, x13, x9, x10)

inst_3275:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:9762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9762*FLEN/8, x13, x9, x10)

inst_3276:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9765*FLEN/8, x13, x9, x10)

inst_3277:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9768*FLEN/8, x13, x9, x10)

inst_3278:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9771*FLEN/8, x13, x9, x10)

inst_3279:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:9774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9774*FLEN/8, x13, x9, x10)

inst_3280:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9777*FLEN/8, x13, x9, x10)

inst_3281:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9780*FLEN/8, x13, x9, x10)

inst_3282:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9783*FLEN/8, x13, x9, x10)

inst_3283:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9786*FLEN/8, x13, x9, x10)

inst_3284:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9789*FLEN/8, x13, x9, x10)

inst_3285:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9792*FLEN/8, x13, x9, x10)

inst_3286:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9795*FLEN/8, x13, x9, x10)

inst_3287:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9798*FLEN/8, x13, x9, x10)

inst_3288:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:9801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9801*FLEN/8, x13, x9, x10)

inst_3289:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:9804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9804*FLEN/8, x13, x9, x10)

inst_3290:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:9807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9807*FLEN/8, x13, x9, x10)

inst_3291:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:9810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9810*FLEN/8, x13, x9, x10)

inst_3292:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:9813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9813*FLEN/8, x13, x9, x10)

inst_3293:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9816*FLEN/8, x13, x9, x10)

inst_3294:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9819*FLEN/8, x13, x9, x10)

inst_3295:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9822*FLEN/8, x13, x9, x10)

inst_3296:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:9825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9825*FLEN/8, x13, x9, x10)

inst_3297:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:9828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9828*FLEN/8, x13, x9, x10)

inst_3298:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:9831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9831*FLEN/8, x13, x9, x10)

inst_3299:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:9834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9834*FLEN/8, x13, x9, x10)

inst_3300:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9837*FLEN/8, x13, x9, x10)

inst_3301:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9840*FLEN/8, x13, x9, x10)

inst_3302:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9843*FLEN/8, x13, x9, x10)

inst_3303:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:9846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9846*FLEN/8, x13, x9, x10)

inst_3304:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9849*FLEN/8, x13, x9, x10)

inst_3305:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9852*FLEN/8, x13, x9, x10)

inst_3306:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9855*FLEN/8, x13, x9, x10)

inst_3307:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9858*FLEN/8, x13, x9, x10)

inst_3308:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9861*FLEN/8, x13, x9, x10)

inst_3309:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9864*FLEN/8, x13, x9, x10)

inst_3310:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9867*FLEN/8, x13, x9, x10)

inst_3311:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9870*FLEN/8, x13, x9, x10)

inst_3312:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:9873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9873*FLEN/8, x13, x9, x10)

inst_3313:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:9876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9876*FLEN/8, x13, x9, x10)

inst_3314:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:9879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9879*FLEN/8, x13, x9, x10)

inst_3315:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:9882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9882*FLEN/8, x13, x9, x10)

inst_3316:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:9885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9885*FLEN/8, x13, x9, x10)

inst_3317:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9888*FLEN/8, x13, x9, x10)

inst_3318:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9891*FLEN/8, x13, x9, x10)

inst_3319:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9894*FLEN/8, x13, x9, x10)

inst_3320:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:9897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9897*FLEN/8, x13, x9, x10)

inst_3321:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:9900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9900*FLEN/8, x13, x9, x10)

inst_3322:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:9903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9903*FLEN/8, x13, x9, x10)

inst_3323:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:9906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9906*FLEN/8, x13, x9, x10)

inst_3324:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9909*FLEN/8, x13, x9, x10)

inst_3325:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9912*FLEN/8, x13, x9, x10)

inst_3326:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9915*FLEN/8, x13, x9, x10)

inst_3327:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:9918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9918*FLEN/8, x13, x9, x10)

inst_3328:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9921*FLEN/8, x13, x9, x10)

inst_3329:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9924*FLEN/8, x13, x9, x10)

inst_3330:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9927*FLEN/8, x13, x9, x10)

inst_3331:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:9930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9930*FLEN/8, x13, x9, x10)

inst_3332:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:9933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9933*FLEN/8, x13, x9, x10)

inst_3333:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:9936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9936*FLEN/8, x13, x9, x10)

inst_3334:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:9939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9939*FLEN/8, x13, x9, x10)

inst_3335:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:9942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9942*FLEN/8, x13, x9, x10)

inst_3336:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:9945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9945*FLEN/8, x13, x9, x10)

inst_3337:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:9948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9948*FLEN/8, x13, x9, x10)

inst_3338:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:9951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9951*FLEN/8, x13, x9, x10)

inst_3339:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:9954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9954*FLEN/8, x13, x9, x10)

inst_3340:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:9957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9957*FLEN/8, x13, x9, x10)

inst_3341:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:9960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9960*FLEN/8, x13, x9, x10)

inst_3342:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:9963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9963*FLEN/8, x13, x9, x10)

inst_3343:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:9966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9966*FLEN/8, x13, x9, x10)

inst_3344:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:9969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9969*FLEN/8, x13, x9, x10)

inst_3345:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:9972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9972*FLEN/8, x13, x9, x10)

inst_3346:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:9975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9975*FLEN/8, x13, x9, x10)

inst_3347:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:9978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9978*FLEN/8, x13, x9, x10)

inst_3348:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:9981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9981*FLEN/8, x13, x9, x10)

inst_3349:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:9984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9984*FLEN/8, x13, x9, x10)

inst_3350:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:9987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9987*FLEN/8, x13, x9, x10)

inst_3351:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:9990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9990*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_26)

inst_3352:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:9993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9993*FLEN/8, x13, x9, x10)

inst_3353:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:9996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9996*FLEN/8, x13, x9, x10)

inst_3354:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:9999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 9999*FLEN/8, x13, x9, x10)

inst_3355:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10002*FLEN/8, x13, x9, x10)

inst_3356:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10005*FLEN/8, x13, x9, x10)

inst_3357:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10008*FLEN/8, x13, x9, x10)

inst_3358:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10011*FLEN/8, x13, x9, x10)

inst_3359:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10014*FLEN/8, x13, x9, x10)

inst_3360:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:10017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10017*FLEN/8, x13, x9, x10)

inst_3361:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:10020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10020*FLEN/8, x13, x9, x10)

inst_3362:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:10023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10023*FLEN/8, x13, x9, x10)

inst_3363:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:10026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10026*FLEN/8, x13, x9, x10)

inst_3364:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:10029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10029*FLEN/8, x13, x9, x10)

inst_3365:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10032*FLEN/8, x13, x9, x10)

inst_3366:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10035*FLEN/8, x13, x9, x10)

inst_3367:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10038*FLEN/8, x13, x9, x10)

inst_3368:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:10041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10041*FLEN/8, x13, x9, x10)

inst_3369:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:10044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10044*FLEN/8, x13, x9, x10)

inst_3370:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:10047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10047*FLEN/8, x13, x9, x10)

inst_3371:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:10050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10050*FLEN/8, x13, x9, x10)

inst_3372:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10053*FLEN/8, x13, x9, x10)

inst_3373:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10056*FLEN/8, x13, x9, x10)

inst_3374:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10059*FLEN/8, x13, x9, x10)

inst_3375:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:10062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10062*FLEN/8, x13, x9, x10)

inst_3376:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10065*FLEN/8, x13, x9, x10)

inst_3377:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10068*FLEN/8, x13, x9, x10)

inst_3378:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10071*FLEN/8, x13, x9, x10)

inst_3379:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10074*FLEN/8, x13, x9, x10)

inst_3380:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10077*FLEN/8, x13, x9, x10)

inst_3381:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10080*FLEN/8, x13, x9, x10)

inst_3382:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10083*FLEN/8, x13, x9, x10)

inst_3383:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10086*FLEN/8, x13, x9, x10)

inst_3384:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:10089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10089*FLEN/8, x13, x9, x10)

inst_3385:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:10092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10092*FLEN/8, x13, x9, x10)

inst_3386:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:10095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10095*FLEN/8, x13, x9, x10)

inst_3387:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:10098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10098*FLEN/8, x13, x9, x10)

inst_3388:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:10101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10101*FLEN/8, x13, x9, x10)

inst_3389:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10104*FLEN/8, x13, x9, x10)

inst_3390:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10107*FLEN/8, x13, x9, x10)

inst_3391:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10110*FLEN/8, x13, x9, x10)

inst_3392:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:10113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10113*FLEN/8, x13, x9, x10)

inst_3393:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:10116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10116*FLEN/8, x13, x9, x10)

inst_3394:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:10119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10119*FLEN/8, x13, x9, x10)

inst_3395:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:10122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10122*FLEN/8, x13, x9, x10)

inst_3396:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10125*FLEN/8, x13, x9, x10)

inst_3397:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10128*FLEN/8, x13, x9, x10)

inst_3398:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10131*FLEN/8, x13, x9, x10)

inst_3399:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:10134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10134*FLEN/8, x13, x9, x10)

inst_3400:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10137*FLEN/8, x13, x9, x10)

inst_3401:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10140*FLEN/8, x13, x9, x10)

inst_3402:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10143*FLEN/8, x13, x9, x10)

inst_3403:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10146*FLEN/8, x13, x9, x10)

inst_3404:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10149*FLEN/8, x13, x9, x10)

inst_3405:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10152*FLEN/8, x13, x9, x10)

inst_3406:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10155*FLEN/8, x13, x9, x10)

inst_3407:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10158*FLEN/8, x13, x9, x10)

inst_3408:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:10161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10161*FLEN/8, x13, x9, x10)

inst_3409:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:10164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10164*FLEN/8, x13, x9, x10)

inst_3410:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:10167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10167*FLEN/8, x13, x9, x10)

inst_3411:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:10170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10170*FLEN/8, x13, x9, x10)

inst_3412:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:10173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10173*FLEN/8, x13, x9, x10)

inst_3413:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10176*FLEN/8, x13, x9, x10)

inst_3414:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10179*FLEN/8, x13, x9, x10)

inst_3415:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10182*FLEN/8, x13, x9, x10)

inst_3416:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:10185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10185*FLEN/8, x13, x9, x10)

inst_3417:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:10188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10188*FLEN/8, x13, x9, x10)

inst_3418:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:10191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10191*FLEN/8, x13, x9, x10)

inst_3419:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:10194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10194*FLEN/8, x13, x9, x10)

inst_3420:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10197*FLEN/8, x13, x9, x10)

inst_3421:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10200*FLEN/8, x13, x9, x10)

inst_3422:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10203*FLEN/8, x13, x9, x10)

inst_3423:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:10206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10206*FLEN/8, x13, x9, x10)

inst_3424:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10209*FLEN/8, x13, x9, x10)

inst_3425:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10212*FLEN/8, x13, x9, x10)

inst_3426:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10215*FLEN/8, x13, x9, x10)

inst_3427:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10218*FLEN/8, x13, x9, x10)

inst_3428:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10221*FLEN/8, x13, x9, x10)

inst_3429:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10224*FLEN/8, x13, x9, x10)

inst_3430:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10227*FLEN/8, x13, x9, x10)

inst_3431:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10230*FLEN/8, x13, x9, x10)

inst_3432:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:10233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10233*FLEN/8, x13, x9, x10)

inst_3433:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:10236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10236*FLEN/8, x13, x9, x10)

inst_3434:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:10239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10239*FLEN/8, x13, x9, x10)

inst_3435:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:10242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10242*FLEN/8, x13, x9, x10)

inst_3436:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:10245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10245*FLEN/8, x13, x9, x10)

inst_3437:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10248*FLEN/8, x13, x9, x10)

inst_3438:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10251*FLEN/8, x13, x9, x10)

inst_3439:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10254*FLEN/8, x13, x9, x10)

inst_3440:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:10257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10257*FLEN/8, x13, x9, x10)

inst_3441:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:10260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10260*FLEN/8, x13, x9, x10)

inst_3442:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:10263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10263*FLEN/8, x13, x9, x10)

inst_3443:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:10266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10266*FLEN/8, x13, x9, x10)

inst_3444:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10269*FLEN/8, x13, x9, x10)

inst_3445:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10272*FLEN/8, x13, x9, x10)

inst_3446:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10275*FLEN/8, x13, x9, x10)

inst_3447:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:10278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10278*FLEN/8, x13, x9, x10)

inst_3448:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10281*FLEN/8, x13, x9, x10)

inst_3449:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10284*FLEN/8, x13, x9, x10)

inst_3450:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10287*FLEN/8, x13, x9, x10)

inst_3451:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10290*FLEN/8, x13, x9, x10)

inst_3452:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10293*FLEN/8, x13, x9, x10)

inst_3453:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10296*FLEN/8, x13, x9, x10)

inst_3454:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10299*FLEN/8, x13, x9, x10)

inst_3455:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10302*FLEN/8, x13, x9, x10)

inst_3456:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:10305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10305*FLEN/8, x13, x9, x10)

inst_3457:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:10308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10308*FLEN/8, x13, x9, x10)

inst_3458:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:10311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10311*FLEN/8, x13, x9, x10)

inst_3459:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:10314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10314*FLEN/8, x13, x9, x10)

inst_3460:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:10317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10317*FLEN/8, x13, x9, x10)

inst_3461:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10320*FLEN/8, x13, x9, x10)

inst_3462:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10323*FLEN/8, x13, x9, x10)

inst_3463:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10326*FLEN/8, x13, x9, x10)

inst_3464:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:10329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10329*FLEN/8, x13, x9, x10)

inst_3465:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:10332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10332*FLEN/8, x13, x9, x10)

inst_3466:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:10335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10335*FLEN/8, x13, x9, x10)

inst_3467:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:10338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10338*FLEN/8, x13, x9, x10)

inst_3468:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10341*FLEN/8, x13, x9, x10)

inst_3469:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10344*FLEN/8, x13, x9, x10)

inst_3470:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10347*FLEN/8, x13, x9, x10)

inst_3471:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:10350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10350*FLEN/8, x13, x9, x10)

inst_3472:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10353*FLEN/8, x13, x9, x10)

inst_3473:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10356*FLEN/8, x13, x9, x10)

inst_3474:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10359*FLEN/8, x13, x9, x10)

inst_3475:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10362*FLEN/8, x13, x9, x10)

inst_3476:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10365*FLEN/8, x13, x9, x10)

inst_3477:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10368*FLEN/8, x13, x9, x10)

inst_3478:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10371*FLEN/8, x13, x9, x10)

inst_3479:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10374*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_27)

inst_3480:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:10377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10377*FLEN/8, x13, x9, x10)

inst_3481:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:10380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10380*FLEN/8, x13, x9, x10)

inst_3482:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:10383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10383*FLEN/8, x13, x9, x10)

inst_3483:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:10386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10386*FLEN/8, x13, x9, x10)

inst_3484:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:10389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10389*FLEN/8, x13, x9, x10)

inst_3485:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10392*FLEN/8, x13, x9, x10)

inst_3486:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10395*FLEN/8, x13, x9, x10)

inst_3487:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10398*FLEN/8, x13, x9, x10)

inst_3488:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:10401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10401*FLEN/8, x13, x9, x10)

inst_3489:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:10404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10404*FLEN/8, x13, x9, x10)

inst_3490:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:10407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10407*FLEN/8, x13, x9, x10)

inst_3491:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:10410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10410*FLEN/8, x13, x9, x10)

inst_3492:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10413*FLEN/8, x13, x9, x10)

inst_3493:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10416*FLEN/8, x13, x9, x10)

inst_3494:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10419*FLEN/8, x13, x9, x10)

inst_3495:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:10422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10422*FLEN/8, x13, x9, x10)

inst_3496:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10425*FLEN/8, x13, x9, x10)

inst_3497:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10428*FLEN/8, x13, x9, x10)

inst_3498:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10431*FLEN/8, x13, x9, x10)

inst_3499:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10434*FLEN/8, x13, x9, x10)

inst_3500:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10437*FLEN/8, x13, x9, x10)

inst_3501:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10440*FLEN/8, x13, x9, x10)

inst_3502:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10443*FLEN/8, x13, x9, x10)

inst_3503:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10446*FLEN/8, x13, x9, x10)

inst_3504:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:10449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10449*FLEN/8, x13, x9, x10)

inst_3505:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:10452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10452*FLEN/8, x13, x9, x10)

inst_3506:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:10455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10455*FLEN/8, x13, x9, x10)

inst_3507:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:10458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10458*FLEN/8, x13, x9, x10)

inst_3508:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:10461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10461*FLEN/8, x13, x9, x10)

inst_3509:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10464*FLEN/8, x13, x9, x10)

inst_3510:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10467*FLEN/8, x13, x9, x10)

inst_3511:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10470*FLEN/8, x13, x9, x10)

inst_3512:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:10473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10473*FLEN/8, x13, x9, x10)

inst_3513:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:10476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10476*FLEN/8, x13, x9, x10)

inst_3514:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:10479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10479*FLEN/8, x13, x9, x10)

inst_3515:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:10482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10482*FLEN/8, x13, x9, x10)

inst_3516:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10485*FLEN/8, x13, x9, x10)

inst_3517:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10488*FLEN/8, x13, x9, x10)

inst_3518:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10491*FLEN/8, x13, x9, x10)

inst_3519:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:10494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10494*FLEN/8, x13, x9, x10)

inst_3520:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10497*FLEN/8, x13, x9, x10)

inst_3521:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10500*FLEN/8, x13, x9, x10)

inst_3522:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10503*FLEN/8, x13, x9, x10)

inst_3523:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10506*FLEN/8, x13, x9, x10)

inst_3524:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10509*FLEN/8, x13, x9, x10)

inst_3525:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10512*FLEN/8, x13, x9, x10)

inst_3526:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10515*FLEN/8, x13, x9, x10)

inst_3527:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10518*FLEN/8, x13, x9, x10)

inst_3528:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:10521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10521*FLEN/8, x13, x9, x10)

inst_3529:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:10524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10524*FLEN/8, x13, x9, x10)

inst_3530:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:10527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10527*FLEN/8, x13, x9, x10)

inst_3531:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:10530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10530*FLEN/8, x13, x9, x10)

inst_3532:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:10533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10533*FLEN/8, x13, x9, x10)

inst_3533:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10536*FLEN/8, x13, x9, x10)

inst_3534:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10539*FLEN/8, x13, x9, x10)

inst_3535:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10542*FLEN/8, x13, x9, x10)

inst_3536:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:10545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10545*FLEN/8, x13, x9, x10)

inst_3537:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:10548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10548*FLEN/8, x13, x9, x10)

inst_3538:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:10551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10551*FLEN/8, x13, x9, x10)

inst_3539:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:10554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10554*FLEN/8, x13, x9, x10)

inst_3540:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10557*FLEN/8, x13, x9, x10)

inst_3541:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10560*FLEN/8, x13, x9, x10)

inst_3542:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10563*FLEN/8, x13, x9, x10)

inst_3543:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:10566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10566*FLEN/8, x13, x9, x10)

inst_3544:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10569*FLEN/8, x13, x9, x10)

inst_3545:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10572*FLEN/8, x13, x9, x10)

inst_3546:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10575*FLEN/8, x13, x9, x10)

inst_3547:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10578*FLEN/8, x13, x9, x10)

inst_3548:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10581*FLEN/8, x13, x9, x10)

inst_3549:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10584*FLEN/8, x13, x9, x10)

inst_3550:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10587*FLEN/8, x13, x9, x10)

inst_3551:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10590*FLEN/8, x13, x9, x10)

inst_3552:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:10593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10593*FLEN/8, x13, x9, x10)

inst_3553:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:10596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10596*FLEN/8, x13, x9, x10)

inst_3554:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:10599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10599*FLEN/8, x13, x9, x10)

inst_3555:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:10602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10602*FLEN/8, x13, x9, x10)

inst_3556:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:10605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10605*FLEN/8, x13, x9, x10)

inst_3557:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10608*FLEN/8, x13, x9, x10)

inst_3558:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10611*FLEN/8, x13, x9, x10)

inst_3559:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10614*FLEN/8, x13, x9, x10)

inst_3560:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:10617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10617*FLEN/8, x13, x9, x10)

inst_3561:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:10620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10620*FLEN/8, x13, x9, x10)

inst_3562:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:10623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10623*FLEN/8, x13, x9, x10)

inst_3563:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:10626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10626*FLEN/8, x13, x9, x10)

inst_3564:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10629*FLEN/8, x13, x9, x10)

inst_3565:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10632*FLEN/8, x13, x9, x10)

inst_3566:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10635*FLEN/8, x13, x9, x10)

inst_3567:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:10638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10638*FLEN/8, x13, x9, x10)

inst_3568:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10641*FLEN/8, x13, x9, x10)

inst_3569:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10644*FLEN/8, x13, x9, x10)

inst_3570:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10647*FLEN/8, x13, x9, x10)

inst_3571:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10650*FLEN/8, x13, x9, x10)

inst_3572:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10653*FLEN/8, x13, x9, x10)

inst_3573:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10656*FLEN/8, x13, x9, x10)

inst_3574:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10659*FLEN/8, x13, x9, x10)

inst_3575:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10662*FLEN/8, x13, x9, x10)

inst_3576:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:10665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10665*FLEN/8, x13, x9, x10)

inst_3577:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:10668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10668*FLEN/8, x13, x9, x10)

inst_3578:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:10671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10671*FLEN/8, x13, x9, x10)

inst_3579:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:10674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10674*FLEN/8, x13, x9, x10)

inst_3580:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:10677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10677*FLEN/8, x13, x9, x10)

inst_3581:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10680*FLEN/8, x13, x9, x10)

inst_3582:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10683*FLEN/8, x13, x9, x10)

inst_3583:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10686*FLEN/8, x13, x9, x10)

inst_3584:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:10689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10689*FLEN/8, x13, x9, x10)

inst_3585:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:10692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10692*FLEN/8, x13, x9, x10)

inst_3586:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:10695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10695*FLEN/8, x13, x9, x10)

inst_3587:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:10698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10698*FLEN/8, x13, x9, x10)

inst_3588:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10701*FLEN/8, x13, x9, x10)

inst_3589:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10704*FLEN/8, x13, x9, x10)

inst_3590:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10707*FLEN/8, x13, x9, x10)

inst_3591:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:10710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10710*FLEN/8, x13, x9, x10)

inst_3592:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10713*FLEN/8, x13, x9, x10)

inst_3593:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10716*FLEN/8, x13, x9, x10)

inst_3594:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10719*FLEN/8, x13, x9, x10)

inst_3595:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10722*FLEN/8, x13, x9, x10)

inst_3596:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10725*FLEN/8, x13, x9, x10)

inst_3597:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10728*FLEN/8, x13, x9, x10)

inst_3598:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10731*FLEN/8, x13, x9, x10)

inst_3599:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10734*FLEN/8, x13, x9, x10)

inst_3600:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:10737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10737*FLEN/8, x13, x9, x10)

inst_3601:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:10740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10740*FLEN/8, x13, x9, x10)

inst_3602:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:10743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10743*FLEN/8, x13, x9, x10)

inst_3603:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:10746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10746*FLEN/8, x13, x9, x10)

inst_3604:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:10749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10749*FLEN/8, x13, x9, x10)

inst_3605:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10752*FLEN/8, x13, x9, x10)

inst_3606:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10755*FLEN/8, x13, x9, x10)

inst_3607:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10758*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_28)

inst_3608:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:10761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10761*FLEN/8, x13, x9, x10)

inst_3609:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:10764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10764*FLEN/8, x13, x9, x10)

inst_3610:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:10767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10767*FLEN/8, x13, x9, x10)

inst_3611:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:10770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10770*FLEN/8, x13, x9, x10)

inst_3612:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10773*FLEN/8, x13, x9, x10)

inst_3613:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10776*FLEN/8, x13, x9, x10)

inst_3614:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10779*FLEN/8, x13, x9, x10)

inst_3615:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:10782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10782*FLEN/8, x13, x9, x10)

inst_3616:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10785*FLEN/8, x13, x9, x10)

inst_3617:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10788*FLEN/8, x13, x9, x10)

inst_3618:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10791*FLEN/8, x13, x9, x10)

inst_3619:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10794*FLEN/8, x13, x9, x10)

inst_3620:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10797*FLEN/8, x13, x9, x10)

inst_3621:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10800*FLEN/8, x13, x9, x10)

inst_3622:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10803*FLEN/8, x13, x9, x10)

inst_3623:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10806*FLEN/8, x13, x9, x10)

inst_3624:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:10809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10809*FLEN/8, x13, x9, x10)

inst_3625:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:10812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10812*FLEN/8, x13, x9, x10)

inst_3626:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:10815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10815*FLEN/8, x13, x9, x10)

inst_3627:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:10818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10818*FLEN/8, x13, x9, x10)

inst_3628:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:10821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10821*FLEN/8, x13, x9, x10)

inst_3629:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10824*FLEN/8, x13, x9, x10)

inst_3630:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10827*FLEN/8, x13, x9, x10)

inst_3631:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10830*FLEN/8, x13, x9, x10)

inst_3632:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:10833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10833*FLEN/8, x13, x9, x10)

inst_3633:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:10836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10836*FLEN/8, x13, x9, x10)

inst_3634:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:10839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10839*FLEN/8, x13, x9, x10)

inst_3635:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:10842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10842*FLEN/8, x13, x9, x10)

inst_3636:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10845*FLEN/8, x13, x9, x10)

inst_3637:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10848*FLEN/8, x13, x9, x10)

inst_3638:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10851*FLEN/8, x13, x9, x10)

inst_3639:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:10854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10854*FLEN/8, x13, x9, x10)

inst_3640:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10857*FLEN/8, x13, x9, x10)

inst_3641:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10860*FLEN/8, x13, x9, x10)

inst_3642:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10863*FLEN/8, x13, x9, x10)

inst_3643:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10866*FLEN/8, x13, x9, x10)

inst_3644:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10869*FLEN/8, x13, x9, x10)

inst_3645:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10872*FLEN/8, x13, x9, x10)

inst_3646:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10875*FLEN/8, x13, x9, x10)

inst_3647:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10878*FLEN/8, x13, x9, x10)

inst_3648:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:10881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10881*FLEN/8, x13, x9, x10)

inst_3649:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:10884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10884*FLEN/8, x13, x9, x10)

inst_3650:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:10887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10887*FLEN/8, x13, x9, x10)

inst_3651:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:10890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10890*FLEN/8, x13, x9, x10)

inst_3652:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:10893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10893*FLEN/8, x13, x9, x10)

inst_3653:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10896*FLEN/8, x13, x9, x10)

inst_3654:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10899*FLEN/8, x13, x9, x10)

inst_3655:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10902*FLEN/8, x13, x9, x10)

inst_3656:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:10905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10905*FLEN/8, x13, x9, x10)

inst_3657:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:10908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10908*FLEN/8, x13, x9, x10)

inst_3658:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:10911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10911*FLEN/8, x13, x9, x10)

inst_3659:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:10914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10914*FLEN/8, x13, x9, x10)

inst_3660:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10917*FLEN/8, x13, x9, x10)

inst_3661:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10920*FLEN/8, x13, x9, x10)

inst_3662:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10923*FLEN/8, x13, x9, x10)

inst_3663:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:10926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10926*FLEN/8, x13, x9, x10)

inst_3664:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:10929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10929*FLEN/8, x13, x9, x10)

inst_3665:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:10932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10932*FLEN/8, x13, x9, x10)

inst_3666:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:10935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10935*FLEN/8, x13, x9, x10)

inst_3667:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:10938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10938*FLEN/8, x13, x9, x10)

inst_3668:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:10941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10941*FLEN/8, x13, x9, x10)

inst_3669:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:10944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10944*FLEN/8, x13, x9, x10)

inst_3670:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:10947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10947*FLEN/8, x13, x9, x10)

inst_3671:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:10950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10950*FLEN/8, x13, x9, x10)

inst_3672:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:10953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10953*FLEN/8, x13, x9, x10)

inst_3673:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:10956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10956*FLEN/8, x13, x9, x10)

inst_3674:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:10959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10959*FLEN/8, x13, x9, x10)

inst_3675:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:10962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10962*FLEN/8, x13, x9, x10)

inst_3676:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:10965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10965*FLEN/8, x13, x9, x10)

inst_3677:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:10968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10968*FLEN/8, x13, x9, x10)

inst_3678:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:10971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10971*FLEN/8, x13, x9, x10)

inst_3679:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:10974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10974*FLEN/8, x13, x9, x10)

inst_3680:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:10977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10977*FLEN/8, x13, x9, x10)

inst_3681:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:10980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10980*FLEN/8, x13, x9, x10)

inst_3682:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:10983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10983*FLEN/8, x13, x9, x10)

inst_3683:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:10986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10986*FLEN/8, x13, x9, x10)

inst_3684:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:10989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10989*FLEN/8, x13, x9, x10)

inst_3685:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:10992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10992*FLEN/8, x13, x9, x10)

inst_3686:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:10995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10995*FLEN/8, x13, x9, x10)

inst_3687:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:10998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 10998*FLEN/8, x13, x9, x10)

inst_3688:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11001*FLEN/8, x13, x9, x10)

inst_3689:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11004*FLEN/8, x13, x9, x10)

inst_3690:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11007*FLEN/8, x13, x9, x10)

inst_3691:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11010*FLEN/8, x13, x9, x10)

inst_3692:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11013*FLEN/8, x13, x9, x10)

inst_3693:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11016*FLEN/8, x13, x9, x10)

inst_3694:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11019*FLEN/8, x13, x9, x10)

inst_3695:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11022*FLEN/8, x13, x9, x10)

inst_3696:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:11025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11025*FLEN/8, x13, x9, x10)

inst_3697:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:11028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11028*FLEN/8, x13, x9, x10)

inst_3698:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:11031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11031*FLEN/8, x13, x9, x10)

inst_3699:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:11034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11034*FLEN/8, x13, x9, x10)

inst_3700:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:11037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11037*FLEN/8, x13, x9, x10)

inst_3701:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11040*FLEN/8, x13, x9, x10)

inst_3702:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11043*FLEN/8, x13, x9, x10)

inst_3703:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11046*FLEN/8, x13, x9, x10)

inst_3704:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:11049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11049*FLEN/8, x13, x9, x10)

inst_3705:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:11052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11052*FLEN/8, x13, x9, x10)

inst_3706:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:11055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11055*FLEN/8, x13, x9, x10)

inst_3707:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:11058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11058*FLEN/8, x13, x9, x10)

inst_3708:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11061*FLEN/8, x13, x9, x10)

inst_3709:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11064*FLEN/8, x13, x9, x10)

inst_3710:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11067*FLEN/8, x13, x9, x10)

inst_3711:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:11070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11070*FLEN/8, x13, x9, x10)

inst_3712:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11073*FLEN/8, x13, x9, x10)

inst_3713:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11076*FLEN/8, x13, x9, x10)

inst_3714:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11079*FLEN/8, x13, x9, x10)

inst_3715:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11082*FLEN/8, x13, x9, x10)

inst_3716:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11085*FLEN/8, x13, x9, x10)

inst_3717:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11088*FLEN/8, x13, x9, x10)

inst_3718:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11091*FLEN/8, x13, x9, x10)

inst_3719:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11094*FLEN/8, x13, x9, x10)

inst_3720:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:11097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11097*FLEN/8, x13, x9, x10)

inst_3721:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:11100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11100*FLEN/8, x13, x9, x10)

inst_3722:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:11103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11103*FLEN/8, x13, x9, x10)

inst_3723:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:11106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11106*FLEN/8, x13, x9, x10)

inst_3724:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:11109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11109*FLEN/8, x13, x9, x10)

inst_3725:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11112*FLEN/8, x13, x9, x10)

inst_3726:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11115*FLEN/8, x13, x9, x10)

inst_3727:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11118*FLEN/8, x13, x9, x10)

inst_3728:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:11121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11121*FLEN/8, x13, x9, x10)

inst_3729:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:11124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11124*FLEN/8, x13, x9, x10)

inst_3730:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:11127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11127*FLEN/8, x13, x9, x10)

inst_3731:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:11130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11130*FLEN/8, x13, x9, x10)

inst_3732:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11133*FLEN/8, x13, x9, x10)

inst_3733:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11136*FLEN/8, x13, x9, x10)

inst_3734:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11139*FLEN/8, x13, x9, x10)

inst_3735:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:11142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11142*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_29)

inst_3736:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11145*FLEN/8, x13, x9, x10)

inst_3737:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11148*FLEN/8, x13, x9, x10)

inst_3738:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11151*FLEN/8, x13, x9, x10)

inst_3739:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11154*FLEN/8, x13, x9, x10)

inst_3740:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11157*FLEN/8, x13, x9, x10)

inst_3741:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11160*FLEN/8, x13, x9, x10)

inst_3742:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11163*FLEN/8, x13, x9, x10)

inst_3743:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11166*FLEN/8, x13, x9, x10)

inst_3744:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:11169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11169*FLEN/8, x13, x9, x10)

inst_3745:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:11172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11172*FLEN/8, x13, x9, x10)

inst_3746:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:11175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11175*FLEN/8, x13, x9, x10)

inst_3747:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:11178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11178*FLEN/8, x13, x9, x10)

inst_3748:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:11181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11181*FLEN/8, x13, x9, x10)

inst_3749:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11184*FLEN/8, x13, x9, x10)

inst_3750:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11187*FLEN/8, x13, x9, x10)

inst_3751:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11190*FLEN/8, x13, x9, x10)

inst_3752:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:11193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11193*FLEN/8, x13, x9, x10)

inst_3753:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:11196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11196*FLEN/8, x13, x9, x10)

inst_3754:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:11199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11199*FLEN/8, x13, x9, x10)

inst_3755:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:11202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11202*FLEN/8, x13, x9, x10)

inst_3756:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11205*FLEN/8, x13, x9, x10)

inst_3757:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11208*FLEN/8, x13, x9, x10)

inst_3758:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11211*FLEN/8, x13, x9, x10)

inst_3759:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:11214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11214*FLEN/8, x13, x9, x10)

inst_3760:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11217*FLEN/8, x13, x9, x10)

inst_3761:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11220*FLEN/8, x13, x9, x10)

inst_3762:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11223*FLEN/8, x13, x9, x10)

inst_3763:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11226*FLEN/8, x13, x9, x10)

inst_3764:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11229*FLEN/8, x13, x9, x10)

inst_3765:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11232*FLEN/8, x13, x9, x10)

inst_3766:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11235*FLEN/8, x13, x9, x10)

inst_3767:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11238*FLEN/8, x13, x9, x10)

inst_3768:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:11241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11241*FLEN/8, x13, x9, x10)

inst_3769:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:11244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11244*FLEN/8, x13, x9, x10)

inst_3770:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:11247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11247*FLEN/8, x13, x9, x10)

inst_3771:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:11250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11250*FLEN/8, x13, x9, x10)

inst_3772:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:11253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11253*FLEN/8, x13, x9, x10)

inst_3773:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11256*FLEN/8, x13, x9, x10)

inst_3774:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11259*FLEN/8, x13, x9, x10)

inst_3775:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11262*FLEN/8, x13, x9, x10)

inst_3776:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:11265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11265*FLEN/8, x13, x9, x10)

inst_3777:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:11268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11268*FLEN/8, x13, x9, x10)

inst_3778:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:11271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11271*FLEN/8, x13, x9, x10)

inst_3779:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:11274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11274*FLEN/8, x13, x9, x10)

inst_3780:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11277*FLEN/8, x13, x9, x10)

inst_3781:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11280*FLEN/8, x13, x9, x10)

inst_3782:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11283*FLEN/8, x13, x9, x10)

inst_3783:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:11286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11286*FLEN/8, x13, x9, x10)

inst_3784:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11289*FLEN/8, x13, x9, x10)

inst_3785:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11292*FLEN/8, x13, x9, x10)

inst_3786:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11295*FLEN/8, x13, x9, x10)

inst_3787:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11298*FLEN/8, x13, x9, x10)

inst_3788:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11301*FLEN/8, x13, x9, x10)

inst_3789:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11304*FLEN/8, x13, x9, x10)

inst_3790:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11307*FLEN/8, x13, x9, x10)

inst_3791:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11310*FLEN/8, x13, x9, x10)

inst_3792:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:11313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11313*FLEN/8, x13, x9, x10)

inst_3793:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:11316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11316*FLEN/8, x13, x9, x10)

inst_3794:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:11319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11319*FLEN/8, x13, x9, x10)

inst_3795:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11322*FLEN/8, x13, x9, x10)

inst_3796:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:11325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11325*FLEN/8, x13, x9, x10)

inst_3797:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11328*FLEN/8, x13, x9, x10)

inst_3798:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11331*FLEN/8, x13, x9, x10)

inst_3799:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11334*FLEN/8, x13, x9, x10)

inst_3800:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:11337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11337*FLEN/8, x13, x9, x10)

inst_3801:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:11340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11340*FLEN/8, x13, x9, x10)

inst_3802:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:11343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11343*FLEN/8, x13, x9, x10)

inst_3803:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:11346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11346*FLEN/8, x13, x9, x10)

inst_3804:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11349*FLEN/8, x13, x9, x10)

inst_3805:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11352*FLEN/8, x13, x9, x10)

inst_3806:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11355*FLEN/8, x13, x9, x10)

inst_3807:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:11358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11358*FLEN/8, x13, x9, x10)

inst_3808:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11361*FLEN/8, x13, x9, x10)

inst_3809:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11364*FLEN/8, x13, x9, x10)

inst_3810:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11367*FLEN/8, x13, x9, x10)

inst_3811:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11370*FLEN/8, x13, x9, x10)

inst_3812:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11373*FLEN/8, x13, x9, x10)

inst_3813:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11376*FLEN/8, x13, x9, x10)

inst_3814:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11379*FLEN/8, x13, x9, x10)

inst_3815:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11382*FLEN/8, x13, x9, x10)

inst_3816:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:11385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11385*FLEN/8, x13, x9, x10)

inst_3817:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:11388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11388*FLEN/8, x13, x9, x10)

inst_3818:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:11391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11391*FLEN/8, x13, x9, x10)

inst_3819:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11394*FLEN/8, x13, x9, x10)

inst_3820:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:11397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11397*FLEN/8, x13, x9, x10)

inst_3821:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11400*FLEN/8, x13, x9, x10)

inst_3822:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11403*FLEN/8, x13, x9, x10)

inst_3823:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11406*FLEN/8, x13, x9, x10)

inst_3824:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:11409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11409*FLEN/8, x13, x9, x10)

inst_3825:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:11412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11412*FLEN/8, x13, x9, x10)

inst_3826:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:11415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11415*FLEN/8, x13, x9, x10)

inst_3827:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:11418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11418*FLEN/8, x13, x9, x10)

inst_3828:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11421*FLEN/8, x13, x9, x10)

inst_3829:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11424*FLEN/8, x13, x9, x10)

inst_3830:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11427*FLEN/8, x13, x9, x10)

inst_3831:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:11430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11430*FLEN/8, x13, x9, x10)

inst_3832:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11433*FLEN/8, x13, x9, x10)

inst_3833:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11436*FLEN/8, x13, x9, x10)

inst_3834:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11439*FLEN/8, x13, x9, x10)

inst_3835:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11442*FLEN/8, x13, x9, x10)

inst_3836:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11445*FLEN/8, x13, x9, x10)

inst_3837:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11448*FLEN/8, x13, x9, x10)

inst_3838:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11451*FLEN/8, x13, x9, x10)

inst_3839:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11454*FLEN/8, x13, x9, x10)

inst_3840:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:11457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11457*FLEN/8, x13, x9, x10)

inst_3841:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:11460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11460*FLEN/8, x13, x9, x10)

inst_3842:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:11463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11463*FLEN/8, x13, x9, x10)

inst_3843:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11466*FLEN/8, x13, x9, x10)

inst_3844:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:11469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11469*FLEN/8, x13, x9, x10)

inst_3845:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11472*FLEN/8, x13, x9, x10)

inst_3846:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11475*FLEN/8, x13, x9, x10)

inst_3847:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11478*FLEN/8, x13, x9, x10)

inst_3848:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:11481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11481*FLEN/8, x13, x9, x10)

inst_3849:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:11484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11484*FLEN/8, x13, x9, x10)

inst_3850:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:11487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11487*FLEN/8, x13, x9, x10)

inst_3851:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:11490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11490*FLEN/8, x13, x9, x10)

inst_3852:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11493*FLEN/8, x13, x9, x10)

inst_3853:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11496*FLEN/8, x13, x9, x10)

inst_3854:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11499*FLEN/8, x13, x9, x10)

inst_3855:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:11502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11502*FLEN/8, x13, x9, x10)

inst_3856:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11505*FLEN/8, x13, x9, x10)

inst_3857:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11508*FLEN/8, x13, x9, x10)

inst_3858:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11511*FLEN/8, x13, x9, x10)

inst_3859:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11514*FLEN/8, x13, x9, x10)

inst_3860:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11517*FLEN/8, x13, x9, x10)

inst_3861:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11520*FLEN/8, x13, x9, x10)

inst_3862:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11523*FLEN/8, x13, x9, x10)

inst_3863:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11526*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_30)

inst_3864:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:11529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11529*FLEN/8, x13, x9, x10)

inst_3865:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:11532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11532*FLEN/8, x13, x9, x10)

inst_3866:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:11535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11535*FLEN/8, x13, x9, x10)

inst_3867:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11538*FLEN/8, x13, x9, x10)

inst_3868:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:11541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11541*FLEN/8, x13, x9, x10)

inst_3869:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11544*FLEN/8, x13, x9, x10)

inst_3870:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11547*FLEN/8, x13, x9, x10)

inst_3871:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11550*FLEN/8, x13, x9, x10)

inst_3872:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:11553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11553*FLEN/8, x13, x9, x10)

inst_3873:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:11556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11556*FLEN/8, x13, x9, x10)

inst_3874:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:11559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11559*FLEN/8, x13, x9, x10)

inst_3875:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:11562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11562*FLEN/8, x13, x9, x10)

inst_3876:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11565*FLEN/8, x13, x9, x10)

inst_3877:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11568*FLEN/8, x13, x9, x10)

inst_3878:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11571*FLEN/8, x13, x9, x10)

inst_3879:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:11574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11574*FLEN/8, x13, x9, x10)

inst_3880:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11577*FLEN/8, x13, x9, x10)

inst_3881:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11580*FLEN/8, x13, x9, x10)

inst_3882:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11583*FLEN/8, x13, x9, x10)

inst_3883:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11586*FLEN/8, x13, x9, x10)

inst_3884:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11589*FLEN/8, x13, x9, x10)

inst_3885:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11592*FLEN/8, x13, x9, x10)

inst_3886:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11595*FLEN/8, x13, x9, x10)

inst_3887:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11598*FLEN/8, x13, x9, x10)

inst_3888:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:11601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11601*FLEN/8, x13, x9, x10)

inst_3889:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:11604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11604*FLEN/8, x13, x9, x10)

inst_3890:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:11607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11607*FLEN/8, x13, x9, x10)

inst_3891:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:11610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11610*FLEN/8, x13, x9, x10)

inst_3892:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:11613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11613*FLEN/8, x13, x9, x10)

inst_3893:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11616*FLEN/8, x13, x9, x10)

inst_3894:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11619*FLEN/8, x13, x9, x10)

inst_3895:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11622*FLEN/8, x13, x9, x10)

inst_3896:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:11625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11625*FLEN/8, x13, x9, x10)

inst_3897:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:11628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11628*FLEN/8, x13, x9, x10)

inst_3898:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:11631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11631*FLEN/8, x13, x9, x10)

inst_3899:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:11634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11634*FLEN/8, x13, x9, x10)

inst_3900:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11637*FLEN/8, x13, x9, x10)

inst_3901:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11640*FLEN/8, x13, x9, x10)

inst_3902:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11643*FLEN/8, x13, x9, x10)

inst_3903:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:11646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11646*FLEN/8, x13, x9, x10)

inst_3904:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11649*FLEN/8, x13, x9, x10)

inst_3905:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11652*FLEN/8, x13, x9, x10)

inst_3906:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11655*FLEN/8, x13, x9, x10)

inst_3907:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11658*FLEN/8, x13, x9, x10)

inst_3908:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11661*FLEN/8, x13, x9, x10)

inst_3909:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11664*FLEN/8, x13, x9, x10)

inst_3910:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11667*FLEN/8, x13, x9, x10)

inst_3911:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11670*FLEN/8, x13, x9, x10)

inst_3912:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:11673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11673*FLEN/8, x13, x9, x10)

inst_3913:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:11676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11676*FLEN/8, x13, x9, x10)

inst_3914:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:11679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11679*FLEN/8, x13, x9, x10)

inst_3915:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:11682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11682*FLEN/8, x13, x9, x10)

inst_3916:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:11685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11685*FLEN/8, x13, x9, x10)

inst_3917:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11688*FLEN/8, x13, x9, x10)

inst_3918:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11691*FLEN/8, x13, x9, x10)

inst_3919:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11694*FLEN/8, x13, x9, x10)

inst_3920:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:11697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11697*FLEN/8, x13, x9, x10)

inst_3921:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:11700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11700*FLEN/8, x13, x9, x10)

inst_3922:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:11703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11703*FLEN/8, x13, x9, x10)

inst_3923:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:11706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11706*FLEN/8, x13, x9, x10)

inst_3924:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11709*FLEN/8, x13, x9, x10)

inst_3925:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11712*FLEN/8, x13, x9, x10)

inst_3926:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11715*FLEN/8, x13, x9, x10)

inst_3927:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:11718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11718*FLEN/8, x13, x9, x10)

inst_3928:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11721*FLEN/8, x13, x9, x10)

inst_3929:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11724*FLEN/8, x13, x9, x10)

inst_3930:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11727*FLEN/8, x13, x9, x10)

inst_3931:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11730*FLEN/8, x13, x9, x10)

inst_3932:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11733*FLEN/8, x13, x9, x10)

inst_3933:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11736*FLEN/8, x13, x9, x10)

inst_3934:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11739*FLEN/8, x13, x9, x10)

inst_3935:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11742*FLEN/8, x13, x9, x10)

inst_3936:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:11745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11745*FLEN/8, x13, x9, x10)

inst_3937:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:11748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11748*FLEN/8, x13, x9, x10)

inst_3938:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:11751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11751*FLEN/8, x13, x9, x10)

inst_3939:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:11754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11754*FLEN/8, x13, x9, x10)

inst_3940:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:11757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11757*FLEN/8, x13, x9, x10)

inst_3941:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11760*FLEN/8, x13, x9, x10)

inst_3942:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11763*FLEN/8, x13, x9, x10)

inst_3943:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11766*FLEN/8, x13, x9, x10)

inst_3944:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:11769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11769*FLEN/8, x13, x9, x10)

inst_3945:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:11772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11772*FLEN/8, x13, x9, x10)

inst_3946:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:11775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11775*FLEN/8, x13, x9, x10)

inst_3947:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:11778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11778*FLEN/8, x13, x9, x10)

inst_3948:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11781*FLEN/8, x13, x9, x10)

inst_3949:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11784*FLEN/8, x13, x9, x10)

inst_3950:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11787*FLEN/8, x13, x9, x10)

inst_3951:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:11790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11790*FLEN/8, x13, x9, x10)

inst_3952:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11793*FLEN/8, x13, x9, x10)

inst_3953:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11796*FLEN/8, x13, x9, x10)

inst_3954:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11799*FLEN/8, x13, x9, x10)

inst_3955:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11802*FLEN/8, x13, x9, x10)

inst_3956:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11805*FLEN/8, x13, x9, x10)

inst_3957:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11808*FLEN/8, x13, x9, x10)

inst_3958:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11811*FLEN/8, x13, x9, x10)

inst_3959:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11814*FLEN/8, x13, x9, x10)

inst_3960:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:11817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11817*FLEN/8, x13, x9, x10)

inst_3961:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:11820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11820*FLEN/8, x13, x9, x10)

inst_3962:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:11823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11823*FLEN/8, x13, x9, x10)

inst_3963:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:11826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11826*FLEN/8, x13, x9, x10)

inst_3964:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:11829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11829*FLEN/8, x13, x9, x10)

inst_3965:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11832*FLEN/8, x13, x9, x10)

inst_3966:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11835*FLEN/8, x13, x9, x10)

inst_3967:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11838*FLEN/8, x13, x9, x10)

inst_3968:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:11841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11841*FLEN/8, x13, x9, x10)

inst_3969:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:11844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11844*FLEN/8, x13, x9, x10)

inst_3970:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:11847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11847*FLEN/8, x13, x9, x10)

inst_3971:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:11850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11850*FLEN/8, x13, x9, x10)

inst_3972:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11853*FLEN/8, x13, x9, x10)

inst_3973:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11856*FLEN/8, x13, x9, x10)

inst_3974:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11859*FLEN/8, x13, x9, x10)

inst_3975:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:11862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11862*FLEN/8, x13, x9, x10)

inst_3976:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11865*FLEN/8, x13, x9, x10)

inst_3977:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11868*FLEN/8, x13, x9, x10)

inst_3978:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11871*FLEN/8, x13, x9, x10)

inst_3979:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11874*FLEN/8, x13, x9, x10)

inst_3980:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11877*FLEN/8, x13, x9, x10)

inst_3981:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11880*FLEN/8, x13, x9, x10)

inst_3982:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11883*FLEN/8, x13, x9, x10)

inst_3983:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11886*FLEN/8, x13, x9, x10)

inst_3984:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:11889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11889*FLEN/8, x13, x9, x10)

inst_3985:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:11892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11892*FLEN/8, x13, x9, x10)

inst_3986:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:11895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11895*FLEN/8, x13, x9, x10)

inst_3987:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11898*FLEN/8, x13, x9, x10)

inst_3988:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:11901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11901*FLEN/8, x13, x9, x10)

inst_3989:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11904*FLEN/8, x13, x9, x10)

inst_3990:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11907*FLEN/8, x13, x9, x10)

inst_3991:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11910*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_31)

inst_3992:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:11913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11913*FLEN/8, x13, x9, x10)

inst_3993:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:11916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11916*FLEN/8, x13, x9, x10)

inst_3994:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:11919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11919*FLEN/8, x13, x9, x10)

inst_3995:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:11922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11922*FLEN/8, x13, x9, x10)

inst_3996:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11925*FLEN/8, x13, x9, x10)

inst_3997:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:11928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11928*FLEN/8, x13, x9, x10)

inst_3998:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:11931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11931*FLEN/8, x13, x9, x10)

inst_3999:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:11934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11934*FLEN/8, x13, x9, x10)

inst_4000:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:11937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11937*FLEN/8, x13, x9, x10)

inst_4001:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:11940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11940*FLEN/8, x13, x9, x10)

inst_4002:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:11943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11943*FLEN/8, x13, x9, x10)

inst_4003:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:11946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11946*FLEN/8, x13, x9, x10)

inst_4004:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:11949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11949*FLEN/8, x13, x9, x10)

inst_4005:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:11952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11952*FLEN/8, x13, x9, x10)

inst_4006:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:11955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11955*FLEN/8, x13, x9, x10)

inst_4007:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:11958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11958*FLEN/8, x13, x9, x10)

inst_4008:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:11961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11961*FLEN/8, x13, x9, x10)

inst_4009:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:11964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11964*FLEN/8, x13, x9, x10)

inst_4010:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:11967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11967*FLEN/8, x13, x9, x10)

inst_4011:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:11970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11970*FLEN/8, x13, x9, x10)

inst_4012:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:11973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11973*FLEN/8, x13, x9, x10)

inst_4013:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:11976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11976*FLEN/8, x13, x9, x10)

inst_4014:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:11979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11979*FLEN/8, x13, x9, x10)

inst_4015:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:11982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11982*FLEN/8, x13, x9, x10)

inst_4016:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:11985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11985*FLEN/8, x13, x9, x10)

inst_4017:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:11988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11988*FLEN/8, x13, x9, x10)

inst_4018:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:11991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11991*FLEN/8, x13, x9, x10)

inst_4019:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:11994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11994*FLEN/8, x13, x9, x10)

inst_4020:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:11997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 11997*FLEN/8, x13, x9, x10)

inst_4021:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12000*FLEN/8, x13, x9, x10)

inst_4022:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12003*FLEN/8, x13, x9, x10)

inst_4023:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:12006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12006*FLEN/8, x13, x9, x10)

inst_4024:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12009*FLEN/8, x13, x9, x10)

inst_4025:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12012*FLEN/8, x13, x9, x10)

inst_4026:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12015*FLEN/8, x13, x9, x10)

inst_4027:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12018*FLEN/8, x13, x9, x10)

inst_4028:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12021*FLEN/8, x13, x9, x10)

inst_4029:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12024*FLEN/8, x13, x9, x10)

inst_4030:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12027*FLEN/8, x13, x9, x10)

inst_4031:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12030*FLEN/8, x13, x9, x10)

inst_4032:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:12033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12033*FLEN/8, x13, x9, x10)

inst_4033:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:12036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12036*FLEN/8, x13, x9, x10)

inst_4034:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:12039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12039*FLEN/8, x13, x9, x10)

inst_4035:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:12042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12042*FLEN/8, x13, x9, x10)

inst_4036:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:12045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12045*FLEN/8, x13, x9, x10)

inst_4037:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12048*FLEN/8, x13, x9, x10)

inst_4038:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12051*FLEN/8, x13, x9, x10)

inst_4039:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12054*FLEN/8, x13, x9, x10)

inst_4040:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:12057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12057*FLEN/8, x13, x9, x10)

inst_4041:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:12060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12060*FLEN/8, x13, x9, x10)

inst_4042:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:12063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12063*FLEN/8, x13, x9, x10)

inst_4043:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:12066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12066*FLEN/8, x13, x9, x10)

inst_4044:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12069*FLEN/8, x13, x9, x10)

inst_4045:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12072*FLEN/8, x13, x9, x10)

inst_4046:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12075*FLEN/8, x13, x9, x10)

inst_4047:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:12078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12078*FLEN/8, x13, x9, x10)

inst_4048:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12081*FLEN/8, x13, x9, x10)

inst_4049:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12084*FLEN/8, x13, x9, x10)

inst_4050:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12087*FLEN/8, x13, x9, x10)

inst_4051:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12090*FLEN/8, x13, x9, x10)

inst_4052:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12093*FLEN/8, x13, x9, x10)

inst_4053:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12096*FLEN/8, x13, x9, x10)

inst_4054:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12099*FLEN/8, x13, x9, x10)

inst_4055:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12102*FLEN/8, x13, x9, x10)

inst_4056:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:12105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12105*FLEN/8, x13, x9, x10)

inst_4057:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:12108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12108*FLEN/8, x13, x9, x10)

inst_4058:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:12111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12111*FLEN/8, x13, x9, x10)

inst_4059:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12114*FLEN/8, x13, x9, x10)

inst_4060:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:12117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12117*FLEN/8, x13, x9, x10)

inst_4061:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12120*FLEN/8, x13, x9, x10)

inst_4062:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12123*FLEN/8, x13, x9, x10)

inst_4063:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12126*FLEN/8, x13, x9, x10)

inst_4064:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:12129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12129*FLEN/8, x13, x9, x10)

inst_4065:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:12132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12132*FLEN/8, x13, x9, x10)

inst_4066:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:12135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12135*FLEN/8, x13, x9, x10)

inst_4067:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:12138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12138*FLEN/8, x13, x9, x10)

inst_4068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12141*FLEN/8, x13, x9, x10)

inst_4069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12144*FLEN/8, x13, x9, x10)

inst_4070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12147*FLEN/8, x13, x9, x10)

inst_4071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:12150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12150*FLEN/8, x13, x9, x10)

inst_4072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12153*FLEN/8, x13, x9, x10)

inst_4073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12156*FLEN/8, x13, x9, x10)

inst_4074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12159*FLEN/8, x13, x9, x10)

inst_4075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12162*FLEN/8, x13, x9, x10)

inst_4076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12165*FLEN/8, x13, x9, x10)

inst_4077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12168*FLEN/8, x13, x9, x10)

inst_4078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12171*FLEN/8, x13, x9, x10)

inst_4079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12174*FLEN/8, x13, x9, x10)

inst_4080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:12177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12177*FLEN/8, x13, x9, x10)

inst_4081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:12180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12180*FLEN/8, x13, x9, x10)

inst_4082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:12183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12183*FLEN/8, x13, x9, x10)

inst_4083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:12186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12186*FLEN/8, x13, x9, x10)

inst_4084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:12189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12189*FLEN/8, x13, x9, x10)

inst_4085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12192*FLEN/8, x13, x9, x10)

inst_4086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12195*FLEN/8, x13, x9, x10)

inst_4087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12198*FLEN/8, x13, x9, x10)

inst_4088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:12201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12201*FLEN/8, x13, x9, x10)

inst_4089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:12204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12204*FLEN/8, x13, x9, x10)

inst_4090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:12207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12207*FLEN/8, x13, x9, x10)

inst_4091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:12210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12210*FLEN/8, x13, x9, x10)

inst_4092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12213*FLEN/8, x13, x9, x10)

inst_4093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12216*FLEN/8, x13, x9, x10)

inst_4094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12219*FLEN/8, x13, x9, x10)

inst_4095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:12222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12222*FLEN/8, x13, x9, x10)

inst_4096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12225*FLEN/8, x13, x9, x10)

inst_4097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12228*FLEN/8, x13, x9, x10)

inst_4098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12231*FLEN/8, x13, x9, x10)

inst_4099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12234*FLEN/8, x13, x9, x10)

inst_4100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12237*FLEN/8, x13, x9, x10)

inst_4101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12240*FLEN/8, x13, x9, x10)

inst_4102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12243*FLEN/8, x13, x9, x10)

inst_4103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12246*FLEN/8, x13, x9, x10)

inst_4104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:12249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12249*FLEN/8, x13, x9, x10)

inst_4105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:12252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12252*FLEN/8, x13, x9, x10)

inst_4106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:12255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12255*FLEN/8, x13, x9, x10)

inst_4107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:12258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12258*FLEN/8, x13, x9, x10)

inst_4108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:12261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12261*FLEN/8, x13, x9, x10)

inst_4109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12264*FLEN/8, x13, x9, x10)

inst_4110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12267*FLEN/8, x13, x9, x10)

inst_4111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12270*FLEN/8, x13, x9, x10)

inst_4112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:12273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12273*FLEN/8, x13, x9, x10)

inst_4113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:12276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12276*FLEN/8, x13, x9, x10)

inst_4114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:12279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12279*FLEN/8, x13, x9, x10)

inst_4115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:12282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12282*FLEN/8, x13, x9, x10)

inst_4116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12285*FLEN/8, x13, x9, x10)

inst_4117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12288*FLEN/8, x13, x9, x10)

inst_4118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12291*FLEN/8, x13, x9, x10)

inst_4119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:12294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12294*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_32)

inst_4120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12297*FLEN/8, x13, x9, x10)

inst_4121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12300*FLEN/8, x13, x9, x10)

inst_4122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12303*FLEN/8, x13, x9, x10)

inst_4123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12306*FLEN/8, x13, x9, x10)

inst_4124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12309*FLEN/8, x13, x9, x10)

inst_4125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12312*FLEN/8, x13, x9, x10)

inst_4126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12315*FLEN/8, x13, x9, x10)

inst_4127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12318*FLEN/8, x13, x9, x10)

inst_4128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:12321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12321*FLEN/8, x13, x9, x10)

inst_4129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:12324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12324*FLEN/8, x13, x9, x10)

inst_4130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:12327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12327*FLEN/8, x13, x9, x10)

inst_4131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:12330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12330*FLEN/8, x13, x9, x10)

inst_4132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:12333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12333*FLEN/8, x13, x9, x10)

inst_4133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12336*FLEN/8, x13, x9, x10)

inst_4134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12339*FLEN/8, x13, x9, x10)

inst_4135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12342*FLEN/8, x13, x9, x10)

inst_4136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:12345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12345*FLEN/8, x13, x9, x10)

inst_4137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:12348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12348*FLEN/8, x13, x9, x10)

inst_4138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:12351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12351*FLEN/8, x13, x9, x10)

inst_4139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:12354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12354*FLEN/8, x13, x9, x10)

inst_4140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12357*FLEN/8, x13, x9, x10)

inst_4141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12360*FLEN/8, x13, x9, x10)

inst_4142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12363*FLEN/8, x13, x9, x10)

inst_4143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:12366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12366*FLEN/8, x13, x9, x10)

inst_4144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12369*FLEN/8, x13, x9, x10)

inst_4145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12372*FLEN/8, x13, x9, x10)

inst_4146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12375*FLEN/8, x13, x9, x10)

inst_4147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12378*FLEN/8, x13, x9, x10)

inst_4148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12381*FLEN/8, x13, x9, x10)

inst_4149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12384*FLEN/8, x13, x9, x10)

inst_4150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12387*FLEN/8, x13, x9, x10)

inst_4151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12390*FLEN/8, x13, x9, x10)

inst_4152:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:12393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12393*FLEN/8, x13, x9, x10)

inst_4153:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:12396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12396*FLEN/8, x13, x9, x10)

inst_4154:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:12399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12399*FLEN/8, x13, x9, x10)

inst_4155:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:12402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12402*FLEN/8, x13, x9, x10)

inst_4156:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:12405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12405*FLEN/8, x13, x9, x10)

inst_4157:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12408*FLEN/8, x13, x9, x10)

inst_4158:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12411*FLEN/8, x13, x9, x10)

inst_4159:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12414*FLEN/8, x13, x9, x10)

inst_4160:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:12417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12417*FLEN/8, x13, x9, x10)

inst_4161:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:12420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12420*FLEN/8, x13, x9, x10)

inst_4162:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:12423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12423*FLEN/8, x13, x9, x10)

inst_4163:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:12426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12426*FLEN/8, x13, x9, x10)

inst_4164:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12429*FLEN/8, x13, x9, x10)

inst_4165:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12432*FLEN/8, x13, x9, x10)

inst_4166:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12435*FLEN/8, x13, x9, x10)

inst_4167:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:12438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12438*FLEN/8, x13, x9, x10)

inst_4168:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12441*FLEN/8, x13, x9, x10)

inst_4169:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12444*FLEN/8, x13, x9, x10)

inst_4170:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12447*FLEN/8, x13, x9, x10)

inst_4171:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12450*FLEN/8, x13, x9, x10)

inst_4172:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12453*FLEN/8, x13, x9, x10)

inst_4173:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12456*FLEN/8, x13, x9, x10)

inst_4174:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12459*FLEN/8, x13, x9, x10)

inst_4175:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12462*FLEN/8, x13, x9, x10)

inst_4176:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:12465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12465*FLEN/8, x13, x9, x10)

inst_4177:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:12468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12468*FLEN/8, x13, x9, x10)

inst_4178:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:12471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12471*FLEN/8, x13, x9, x10)

inst_4179:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:12474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12474*FLEN/8, x13, x9, x10)

inst_4180:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:12477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12477*FLEN/8, x13, x9, x10)

inst_4181:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12480*FLEN/8, x13, x9, x10)

inst_4182:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12483*FLEN/8, x13, x9, x10)

inst_4183:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12486*FLEN/8, x13, x9, x10)

inst_4184:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:12489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12489*FLEN/8, x13, x9, x10)

inst_4185:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:12492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12492*FLEN/8, x13, x9, x10)

inst_4186:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:12495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12495*FLEN/8, x13, x9, x10)

inst_4187:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:12498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12498*FLEN/8, x13, x9, x10)

inst_4188:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12501*FLEN/8, x13, x9, x10)

inst_4189:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12504*FLEN/8, x13, x9, x10)

inst_4190:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12507*FLEN/8, x13, x9, x10)

inst_4191:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:12510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12510*FLEN/8, x13, x9, x10)

inst_4192:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12513*FLEN/8, x13, x9, x10)

inst_4193:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12516*FLEN/8, x13, x9, x10)

inst_4194:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12519*FLEN/8, x13, x9, x10)

inst_4195:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12522*FLEN/8, x13, x9, x10)

inst_4196:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12525*FLEN/8, x13, x9, x10)

inst_4197:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12528*FLEN/8, x13, x9, x10)

inst_4198:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12531*FLEN/8, x13, x9, x10)

inst_4199:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12534*FLEN/8, x13, x9, x10)

inst_4200:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:12537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12537*FLEN/8, x13, x9, x10)

inst_4201:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:12540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12540*FLEN/8, x13, x9, x10)

inst_4202:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:12543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12543*FLEN/8, x13, x9, x10)

inst_4203:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:12546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12546*FLEN/8, x13, x9, x10)

inst_4204:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:12549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12549*FLEN/8, x13, x9, x10)

inst_4205:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12552*FLEN/8, x13, x9, x10)

inst_4206:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12555*FLEN/8, x13, x9, x10)

inst_4207:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12558*FLEN/8, x13, x9, x10)

inst_4208:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:12561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12561*FLEN/8, x13, x9, x10)

inst_4209:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:12564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12564*FLEN/8, x13, x9, x10)

inst_4210:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:12567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12567*FLEN/8, x13, x9, x10)

inst_4211:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:12570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12570*FLEN/8, x13, x9, x10)

inst_4212:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12573*FLEN/8, x13, x9, x10)

inst_4213:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12576*FLEN/8, x13, x9, x10)

inst_4214:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12579*FLEN/8, x13, x9, x10)

inst_4215:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:12582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12582*FLEN/8, x13, x9, x10)

inst_4216:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12585*FLEN/8, x13, x9, x10)

inst_4217:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12588*FLEN/8, x13, x9, x10)

inst_4218:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12591*FLEN/8, x13, x9, x10)

inst_4219:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12594*FLEN/8, x13, x9, x10)

inst_4220:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12597*FLEN/8, x13, x9, x10)

inst_4221:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12600*FLEN/8, x13, x9, x10)

inst_4222:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12603*FLEN/8, x13, x9, x10)

inst_4223:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12606*FLEN/8, x13, x9, x10)

inst_4224:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:12609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12609*FLEN/8, x13, x9, x10)

inst_4225:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:12612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12612*FLEN/8, x13, x9, x10)

inst_4226:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:12615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12615*FLEN/8, x13, x9, x10)

inst_4227:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12618*FLEN/8, x13, x9, x10)

inst_4228:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:12621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12621*FLEN/8, x13, x9, x10)

inst_4229:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12624*FLEN/8, x13, x9, x10)

inst_4230:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12627*FLEN/8, x13, x9, x10)

inst_4231:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12630*FLEN/8, x13, x9, x10)

inst_4232:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:12633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12633*FLEN/8, x13, x9, x10)

inst_4233:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:12636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12636*FLEN/8, x13, x9, x10)

inst_4234:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:12639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12639*FLEN/8, x13, x9, x10)

inst_4235:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:12642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12642*FLEN/8, x13, x9, x10)

inst_4236:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12645*FLEN/8, x13, x9, x10)

inst_4237:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12648*FLEN/8, x13, x9, x10)

inst_4238:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12651*FLEN/8, x13, x9, x10)

inst_4239:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:12654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12654*FLEN/8, x13, x9, x10)

inst_4240:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12657*FLEN/8, x13, x9, x10)

inst_4241:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12660*FLEN/8, x13, x9, x10)

inst_4242:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12663*FLEN/8, x13, x9, x10)

inst_4243:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12666*FLEN/8, x13, x9, x10)

inst_4244:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12669*FLEN/8, x13, x9, x10)

inst_4245:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12672*FLEN/8, x13, x9, x10)

inst_4246:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12675*FLEN/8, x13, x9, x10)

inst_4247:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12678*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_33)

inst_4248:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:12681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12681*FLEN/8, x13, x9, x10)

inst_4249:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:12684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12684*FLEN/8, x13, x9, x10)

inst_4250:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:12687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12687*FLEN/8, x13, x9, x10)

inst_4251:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:12690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12690*FLEN/8, x13, x9, x10)

inst_4252:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:12693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12693*FLEN/8, x13, x9, x10)

inst_4253:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12696*FLEN/8, x13, x9, x10)

inst_4254:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12699*FLEN/8, x13, x9, x10)

inst_4255:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12702*FLEN/8, x13, x9, x10)

inst_4256:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:12705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12705*FLEN/8, x13, x9, x10)

inst_4257:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:12708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12708*FLEN/8, x13, x9, x10)

inst_4258:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:12711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12711*FLEN/8, x13, x9, x10)

inst_4259:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:12714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12714*FLEN/8, x13, x9, x10)

inst_4260:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12717*FLEN/8, x13, x9, x10)

inst_4261:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12720*FLEN/8, x13, x9, x10)

inst_4262:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12723*FLEN/8, x13, x9, x10)

inst_4263:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:12726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12726*FLEN/8, x13, x9, x10)

inst_4264:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12729*FLEN/8, x13, x9, x10)

inst_4265:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12732*FLEN/8, x13, x9, x10)

inst_4266:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12735*FLEN/8, x13, x9, x10)

inst_4267:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12738*FLEN/8, x13, x9, x10)

inst_4268:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12741*FLEN/8, x13, x9, x10)

inst_4269:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12744*FLEN/8, x13, x9, x10)

inst_4270:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12747*FLEN/8, x13, x9, x10)

inst_4271:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12750*FLEN/8, x13, x9, x10)

inst_4272:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:12753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12753*FLEN/8, x13, x9, x10)

inst_4273:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:12756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12756*FLEN/8, x13, x9, x10)

inst_4274:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:12759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12759*FLEN/8, x13, x9, x10)

inst_4275:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:12762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12762*FLEN/8, x13, x9, x10)

inst_4276:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:12765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12765*FLEN/8, x13, x9, x10)

inst_4277:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12768*FLEN/8, x13, x9, x10)

inst_4278:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12771*FLEN/8, x13, x9, x10)

inst_4279:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12774*FLEN/8, x13, x9, x10)

inst_4280:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:12777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12777*FLEN/8, x13, x9, x10)

inst_4281:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:12780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12780*FLEN/8, x13, x9, x10)

inst_4282:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:12783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12783*FLEN/8, x13, x9, x10)

inst_4283:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:12786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12786*FLEN/8, x13, x9, x10)

inst_4284:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12789*FLEN/8, x13, x9, x10)

inst_4285:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12792*FLEN/8, x13, x9, x10)

inst_4286:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12795*FLEN/8, x13, x9, x10)

inst_4287:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:12798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12798*FLEN/8, x13, x9, x10)

inst_4288:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12801*FLEN/8, x13, x9, x10)

inst_4289:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12804*FLEN/8, x13, x9, x10)

inst_4290:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12807*FLEN/8, x13, x9, x10)

inst_4291:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12810*FLEN/8, x13, x9, x10)

inst_4292:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12813*FLEN/8, x13, x9, x10)

inst_4293:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12816*FLEN/8, x13, x9, x10)

inst_4294:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12819*FLEN/8, x13, x9, x10)

inst_4295:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12822*FLEN/8, x13, x9, x10)

inst_4296:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:12825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12825*FLEN/8, x13, x9, x10)

inst_4297:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:12828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12828*FLEN/8, x13, x9, x10)

inst_4298:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:12831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12831*FLEN/8, x13, x9, x10)

inst_4299:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:12834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12834*FLEN/8, x13, x9, x10)

inst_4300:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:12837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12837*FLEN/8, x13, x9, x10)

inst_4301:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12840*FLEN/8, x13, x9, x10)

inst_4302:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12843*FLEN/8, x13, x9, x10)

inst_4303:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12846*FLEN/8, x13, x9, x10)

inst_4304:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:12849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12849*FLEN/8, x13, x9, x10)

inst_4305:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:12852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12852*FLEN/8, x13, x9, x10)

inst_4306:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:12855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12855*FLEN/8, x13, x9, x10)

inst_4307:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:12858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12858*FLEN/8, x13, x9, x10)

inst_4308:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12861*FLEN/8, x13, x9, x10)

inst_4309:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12864*FLEN/8, x13, x9, x10)

inst_4310:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12867*FLEN/8, x13, x9, x10)

inst_4311:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:12870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12870*FLEN/8, x13, x9, x10)

inst_4312:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12873*FLEN/8, x13, x9, x10)

inst_4313:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12876*FLEN/8, x13, x9, x10)

inst_4314:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12879*FLEN/8, x13, x9, x10)

inst_4315:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12882*FLEN/8, x13, x9, x10)

inst_4316:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12885*FLEN/8, x13, x9, x10)

inst_4317:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12888*FLEN/8, x13, x9, x10)

inst_4318:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12891*FLEN/8, x13, x9, x10)

inst_4319:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12894*FLEN/8, x13, x9, x10)

inst_4320:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:12897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12897*FLEN/8, x13, x9, x10)

inst_4321:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:12900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12900*FLEN/8, x13, x9, x10)

inst_4322:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:12903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12903*FLEN/8, x13, x9, x10)

inst_4323:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:12906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12906*FLEN/8, x13, x9, x10)

inst_4324:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:12909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12909*FLEN/8, x13, x9, x10)

inst_4325:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12912*FLEN/8, x13, x9, x10)

inst_4326:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12915*FLEN/8, x13, x9, x10)

inst_4327:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12918*FLEN/8, x13, x9, x10)

inst_4328:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:12921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12921*FLEN/8, x13, x9, x10)

inst_4329:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:12924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12924*FLEN/8, x13, x9, x10)

inst_4330:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:12927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12927*FLEN/8, x13, x9, x10)

inst_4331:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:12930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12930*FLEN/8, x13, x9, x10)

inst_4332:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:12933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12933*FLEN/8, x13, x9, x10)

inst_4333:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:12936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12936*FLEN/8, x13, x9, x10)

inst_4334:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:12939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12939*FLEN/8, x13, x9, x10)

inst_4335:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:12942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12942*FLEN/8, x13, x9, x10)

inst_4336:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:12945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12945*FLEN/8, x13, x9, x10)

inst_4337:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:12948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12948*FLEN/8, x13, x9, x10)

inst_4338:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:12951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12951*FLEN/8, x13, x9, x10)

inst_4339:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:12954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12954*FLEN/8, x13, x9, x10)

inst_4340:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:12957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12957*FLEN/8, x13, x9, x10)

inst_4341:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:12960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12960*FLEN/8, x13, x9, x10)

inst_4342:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:12963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12963*FLEN/8, x13, x9, x10)

inst_4343:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:12966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12966*FLEN/8, x13, x9, x10)

inst_4344:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:12969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12969*FLEN/8, x13, x9, x10)

inst_4345:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:12972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12972*FLEN/8, x13, x9, x10)

inst_4346:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:12975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12975*FLEN/8, x13, x9, x10)

inst_4347:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:12978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12978*FLEN/8, x13, x9, x10)

inst_4348:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:12981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12981*FLEN/8, x13, x9, x10)

inst_4349:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:12984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12984*FLEN/8, x13, x9, x10)

inst_4350:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:12987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12987*FLEN/8, x13, x9, x10)

inst_4351:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:12990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12990*FLEN/8, x13, x9, x10)

inst_4352:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:12993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12993*FLEN/8, x13, x9, x10)

inst_4353:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:12996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12996*FLEN/8, x13, x9, x10)

inst_4354:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:12999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 12999*FLEN/8, x13, x9, x10)

inst_4355:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:13002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13002*FLEN/8, x13, x9, x10)

inst_4356:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13005*FLEN/8, x13, x9, x10)

inst_4357:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13008*FLEN/8, x13, x9, x10)

inst_4358:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13011*FLEN/8, x13, x9, x10)

inst_4359:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:13014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13014*FLEN/8, x13, x9, x10)

inst_4360:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13017*FLEN/8, x13, x9, x10)

inst_4361:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13020*FLEN/8, x13, x9, x10)

inst_4362:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13023*FLEN/8, x13, x9, x10)

inst_4363:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13026*FLEN/8, x13, x9, x10)

inst_4364:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13029*FLEN/8, x13, x9, x10)

inst_4365:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13032*FLEN/8, x13, x9, x10)

inst_4366:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13035*FLEN/8, x13, x9, x10)

inst_4367:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13038*FLEN/8, x13, x9, x10)

inst_4368:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:13041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13041*FLEN/8, x13, x9, x10)

inst_4369:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13044*FLEN/8, x13, x9, x10)

inst_4370:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:13047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13047*FLEN/8, x13, x9, x10)

inst_4371:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13050*FLEN/8, x13, x9, x10)

inst_4372:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:13053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13053*FLEN/8, x13, x9, x10)

inst_4373:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13056*FLEN/8, x13, x9, x10)

inst_4374:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13059*FLEN/8, x13, x9, x10)

inst_4375:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13062*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_34)

inst_4376:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:13065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13065*FLEN/8, x13, x9, x10)

inst_4377:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13068*FLEN/8, x13, x9, x10)

inst_4378:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:13071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13071*FLEN/8, x13, x9, x10)

inst_4379:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13074*FLEN/8, x13, x9, x10)

inst_4380:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13077*FLEN/8, x13, x9, x10)

inst_4381:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13080*FLEN/8, x13, x9, x10)

inst_4382:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13083*FLEN/8, x13, x9, x10)

inst_4383:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13086*FLEN/8, x13, x9, x10)

inst_4384:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13089*FLEN/8, x13, x9, x10)

inst_4385:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13092*FLEN/8, x13, x9, x10)

inst_4386:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13095*FLEN/8, x13, x9, x10)

inst_4387:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13098*FLEN/8, x13, x9, x10)

inst_4388:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13101*FLEN/8, x13, x9, x10)

inst_4389:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13104*FLEN/8, x13, x9, x10)

inst_4390:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13107*FLEN/8, x13, x9, x10)

inst_4391:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13110*FLEN/8, x13, x9, x10)

inst_4392:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:13113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13113*FLEN/8, x13, x9, x10)

inst_4393:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13116*FLEN/8, x13, x9, x10)

inst_4394:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:13119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13119*FLEN/8, x13, x9, x10)

inst_4395:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13122*FLEN/8, x13, x9, x10)

inst_4396:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:13125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13125*FLEN/8, x13, x9, x10)

inst_4397:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13128*FLEN/8, x13, x9, x10)

inst_4398:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13131*FLEN/8, x13, x9, x10)

inst_4399:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13134*FLEN/8, x13, x9, x10)

inst_4400:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:13137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13137*FLEN/8, x13, x9, x10)

inst_4401:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13140*FLEN/8, x13, x9, x10)

inst_4402:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:13143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13143*FLEN/8, x13, x9, x10)

inst_4403:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13146*FLEN/8, x13, x9, x10)

inst_4404:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13149*FLEN/8, x13, x9, x10)

inst_4405:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13152*FLEN/8, x13, x9, x10)

inst_4406:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13155*FLEN/8, x13, x9, x10)

inst_4407:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13158*FLEN/8, x13, x9, x10)

inst_4408:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13161*FLEN/8, x13, x9, x10)

inst_4409:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13164*FLEN/8, x13, x9, x10)

inst_4410:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13167*FLEN/8, x13, x9, x10)

inst_4411:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13170*FLEN/8, x13, x9, x10)

inst_4412:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13173*FLEN/8, x13, x9, x10)

inst_4413:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13176*FLEN/8, x13, x9, x10)

inst_4414:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13179*FLEN/8, x13, x9, x10)

inst_4415:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13182*FLEN/8, x13, x9, x10)

inst_4416:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:13185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13185*FLEN/8, x13, x9, x10)

inst_4417:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13188*FLEN/8, x13, x9, x10)

inst_4418:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:13191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13191*FLEN/8, x13, x9, x10)

inst_4419:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13194*FLEN/8, x13, x9, x10)

inst_4420:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:13197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13197*FLEN/8, x13, x9, x10)

inst_4421:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13200*FLEN/8, x13, x9, x10)

inst_4422:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13203*FLEN/8, x13, x9, x10)

inst_4423:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13206*FLEN/8, x13, x9, x10)

inst_4424:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:13209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13209*FLEN/8, x13, x9, x10)

inst_4425:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13212*FLEN/8, x13, x9, x10)

inst_4426:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:13215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13215*FLEN/8, x13, x9, x10)

inst_4427:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13218*FLEN/8, x13, x9, x10)

inst_4428:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13221*FLEN/8, x13, x9, x10)

inst_4429:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13224*FLEN/8, x13, x9, x10)

inst_4430:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13227*FLEN/8, x13, x9, x10)

inst_4431:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13230*FLEN/8, x13, x9, x10)

inst_4432:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13233*FLEN/8, x13, x9, x10)

inst_4433:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13236*FLEN/8, x13, x9, x10)

inst_4434:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13239*FLEN/8, x13, x9, x10)

inst_4435:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13242*FLEN/8, x13, x9, x10)

inst_4436:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13245*FLEN/8, x13, x9, x10)

inst_4437:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13248*FLEN/8, x13, x9, x10)

inst_4438:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13251*FLEN/8, x13, x9, x10)

inst_4439:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13254*FLEN/8, x13, x9, x10)

inst_4440:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:13257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13257*FLEN/8, x13, x9, x10)

inst_4441:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13260*FLEN/8, x13, x9, x10)

inst_4442:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:13263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13263*FLEN/8, x13, x9, x10)

inst_4443:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13266*FLEN/8, x13, x9, x10)

inst_4444:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:13269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13269*FLEN/8, x13, x9, x10)

inst_4445:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13272*FLEN/8, x13, x9, x10)

inst_4446:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13275*FLEN/8, x13, x9, x10)

inst_4447:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13278*FLEN/8, x13, x9, x10)

inst_4448:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:13281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13281*FLEN/8, x13, x9, x10)

inst_4449:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13284*FLEN/8, x13, x9, x10)

inst_4450:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:13287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13287*FLEN/8, x13, x9, x10)

inst_4451:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13290*FLEN/8, x13, x9, x10)

inst_4452:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13293*FLEN/8, x13, x9, x10)

inst_4453:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13296*FLEN/8, x13, x9, x10)

inst_4454:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13299*FLEN/8, x13, x9, x10)

inst_4455:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13302*FLEN/8, x13, x9, x10)

inst_4456:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13305*FLEN/8, x13, x9, x10)

inst_4457:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13308*FLEN/8, x13, x9, x10)

inst_4458:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13311*FLEN/8, x13, x9, x10)

inst_4459:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13314*FLEN/8, x13, x9, x10)

inst_4460:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13317*FLEN/8, x13, x9, x10)

inst_4461:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13320*FLEN/8, x13, x9, x10)

inst_4462:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13323*FLEN/8, x13, x9, x10)

inst_4463:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13326*FLEN/8, x13, x9, x10)

inst_4464:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:13329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13329*FLEN/8, x13, x9, x10)

inst_4465:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:13332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13332*FLEN/8, x13, x9, x10)

inst_4466:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:13335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13335*FLEN/8, x13, x9, x10)

inst_4467:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:13338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13338*FLEN/8, x13, x9, x10)

inst_4468:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:13341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13341*FLEN/8, x13, x9, x10)

inst_4469:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13344*FLEN/8, x13, x9, x10)

inst_4470:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13347*FLEN/8, x13, x9, x10)

inst_4471:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13350*FLEN/8, x13, x9, x10)

inst_4472:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:13353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13353*FLEN/8, x13, x9, x10)

inst_4473:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:13356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13356*FLEN/8, x13, x9, x10)

inst_4474:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:13359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13359*FLEN/8, x13, x9, x10)

inst_4475:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:13362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13362*FLEN/8, x13, x9, x10)

inst_4476:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13365*FLEN/8, x13, x9, x10)

inst_4477:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13368*FLEN/8, x13, x9, x10)

inst_4478:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13371*FLEN/8, x13, x9, x10)

inst_4479:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:13374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13374*FLEN/8, x13, x9, x10)

inst_4480:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13377*FLEN/8, x13, x9, x10)

inst_4481:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13380*FLEN/8, x13, x9, x10)

inst_4482:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13383*FLEN/8, x13, x9, x10)

inst_4483:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13386*FLEN/8, x13, x9, x10)

inst_4484:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13389*FLEN/8, x13, x9, x10)

inst_4485:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13392*FLEN/8, x13, x9, x10)

inst_4486:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13395*FLEN/8, x13, x9, x10)

inst_4487:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13398*FLEN/8, x13, x9, x10)

inst_4488:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:13401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13401*FLEN/8, x13, x9, x10)

inst_4489:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:13404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13404*FLEN/8, x13, x9, x10)

inst_4490:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:13407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13407*FLEN/8, x13, x9, x10)

inst_4491:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:13410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13410*FLEN/8, x13, x9, x10)

inst_4492:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:13413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13413*FLEN/8, x13, x9, x10)

inst_4493:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13416*FLEN/8, x13, x9, x10)

inst_4494:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13419*FLEN/8, x13, x9, x10)

inst_4495:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13422*FLEN/8, x13, x9, x10)

inst_4496:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:13425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13425*FLEN/8, x13, x9, x10)

inst_4497:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:13428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13428*FLEN/8, x13, x9, x10)

inst_4498:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:13431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13431*FLEN/8, x13, x9, x10)

inst_4499:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:13434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13434*FLEN/8, x13, x9, x10)

inst_4500:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13437*FLEN/8, x13, x9, x10)

inst_4501:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13440*FLEN/8, x13, x9, x10)

inst_4502:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13443*FLEN/8, x13, x9, x10)

inst_4503:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:13446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13446*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_35)

inst_4504:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13449*FLEN/8, x13, x9, x10)

inst_4505:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13452*FLEN/8, x13, x9, x10)

inst_4506:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13455*FLEN/8, x13, x9, x10)

inst_4507:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13458*FLEN/8, x13, x9, x10)

inst_4508:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13461*FLEN/8, x13, x9, x10)

inst_4509:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13464*FLEN/8, x13, x9, x10)

inst_4510:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13467*FLEN/8, x13, x9, x10)

inst_4511:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13470*FLEN/8, x13, x9, x10)

inst_4512:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:13473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13473*FLEN/8, x13, x9, x10)

inst_4513:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:13476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13476*FLEN/8, x13, x9, x10)

inst_4514:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:13479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13479*FLEN/8, x13, x9, x10)

inst_4515:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:13482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13482*FLEN/8, x13, x9, x10)

inst_4516:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:13485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13485*FLEN/8, x13, x9, x10)

inst_4517:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13488*FLEN/8, x13, x9, x10)

inst_4518:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13491*FLEN/8, x13, x9, x10)

inst_4519:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13494*FLEN/8, x13, x9, x10)

inst_4520:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:13497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13497*FLEN/8, x13, x9, x10)

inst_4521:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:13500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13500*FLEN/8, x13, x9, x10)

inst_4522:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:13503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13503*FLEN/8, x13, x9, x10)

inst_4523:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:13506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13506*FLEN/8, x13, x9, x10)

inst_4524:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13509*FLEN/8, x13, x9, x10)

inst_4525:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13512*FLEN/8, x13, x9, x10)

inst_4526:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13515*FLEN/8, x13, x9, x10)

inst_4527:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:13518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13518*FLEN/8, x13, x9, x10)

inst_4528:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13521*FLEN/8, x13, x9, x10)

inst_4529:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13524*FLEN/8, x13, x9, x10)

inst_4530:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13527*FLEN/8, x13, x9, x10)

inst_4531:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13530*FLEN/8, x13, x9, x10)

inst_4532:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13533*FLEN/8, x13, x9, x10)

inst_4533:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13536*FLEN/8, x13, x9, x10)

inst_4534:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13539*FLEN/8, x13, x9, x10)

inst_4535:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13542*FLEN/8, x13, x9, x10)

inst_4536:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:13545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13545*FLEN/8, x13, x9, x10)

inst_4537:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:13548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13548*FLEN/8, x13, x9, x10)

inst_4538:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:13551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13551*FLEN/8, x13, x9, x10)

inst_4539:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:13554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13554*FLEN/8, x13, x9, x10)

inst_4540:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:13557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13557*FLEN/8, x13, x9, x10)

inst_4541:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13560*FLEN/8, x13, x9, x10)

inst_4542:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13563*FLEN/8, x13, x9, x10)

inst_4543:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13566*FLEN/8, x13, x9, x10)

inst_4544:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:13569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13569*FLEN/8, x13, x9, x10)

inst_4545:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:13572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13572*FLEN/8, x13, x9, x10)

inst_4546:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:13575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13575*FLEN/8, x13, x9, x10)

inst_4547:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:13578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13578*FLEN/8, x13, x9, x10)

inst_4548:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13581*FLEN/8, x13, x9, x10)

inst_4549:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13584*FLEN/8, x13, x9, x10)

inst_4550:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13587*FLEN/8, x13, x9, x10)

inst_4551:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:13590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13590*FLEN/8, x13, x9, x10)

inst_4552:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13593*FLEN/8, x13, x9, x10)

inst_4553:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13596*FLEN/8, x13, x9, x10)

inst_4554:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13599*FLEN/8, x13, x9, x10)

inst_4555:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13602*FLEN/8, x13, x9, x10)

inst_4556:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13605*FLEN/8, x13, x9, x10)

inst_4557:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13608*FLEN/8, x13, x9, x10)

inst_4558:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13611*FLEN/8, x13, x9, x10)

inst_4559:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13614*FLEN/8, x13, x9, x10)

inst_4560:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:13617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13617*FLEN/8, x13, x9, x10)

inst_4561:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13620*FLEN/8, x13, x9, x10)

inst_4562:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:13623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13623*FLEN/8, x13, x9, x10)

inst_4563:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13626*FLEN/8, x13, x9, x10)

inst_4564:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:13629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13629*FLEN/8, x13, x9, x10)

inst_4565:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13632*FLEN/8, x13, x9, x10)

inst_4566:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13635*FLEN/8, x13, x9, x10)

inst_4567:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13638*FLEN/8, x13, x9, x10)

inst_4568:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:13641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13641*FLEN/8, x13, x9, x10)

inst_4569:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13644*FLEN/8, x13, x9, x10)

inst_4570:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:13647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13647*FLEN/8, x13, x9, x10)

inst_4571:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13650*FLEN/8, x13, x9, x10)

inst_4572:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13653*FLEN/8, x13, x9, x10)

inst_4573:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13656*FLEN/8, x13, x9, x10)

inst_4574:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13659*FLEN/8, x13, x9, x10)

inst_4575:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13662*FLEN/8, x13, x9, x10)

inst_4576:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13665*FLEN/8, x13, x9, x10)

inst_4577:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13668*FLEN/8, x13, x9, x10)

inst_4578:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13671*FLEN/8, x13, x9, x10)

inst_4579:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13674*FLEN/8, x13, x9, x10)

inst_4580:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13677*FLEN/8, x13, x9, x10)

inst_4581:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13680*FLEN/8, x13, x9, x10)

inst_4582:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13683*FLEN/8, x13, x9, x10)

inst_4583:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13686*FLEN/8, x13, x9, x10)

inst_4584:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:13689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13689*FLEN/8, x13, x9, x10)

inst_4585:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13692*FLEN/8, x13, x9, x10)

inst_4586:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:13695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13695*FLEN/8, x13, x9, x10)

inst_4587:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13698*FLEN/8, x13, x9, x10)

inst_4588:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:13701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13701*FLEN/8, x13, x9, x10)

inst_4589:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13704*FLEN/8, x13, x9, x10)

inst_4590:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13707*FLEN/8, x13, x9, x10)

inst_4591:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13710*FLEN/8, x13, x9, x10)

inst_4592:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:13713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13713*FLEN/8, x13, x9, x10)

inst_4593:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13716*FLEN/8, x13, x9, x10)

inst_4594:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:13719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13719*FLEN/8, x13, x9, x10)

inst_4595:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13722*FLEN/8, x13, x9, x10)

inst_4596:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13725*FLEN/8, x13, x9, x10)

inst_4597:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13728*FLEN/8, x13, x9, x10)

inst_4598:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13731*FLEN/8, x13, x9, x10)

inst_4599:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13734*FLEN/8, x13, x9, x10)

inst_4600:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13737*FLEN/8, x13, x9, x10)

inst_4601:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13740*FLEN/8, x13, x9, x10)

inst_4602:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13743*FLEN/8, x13, x9, x10)

inst_4603:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13746*FLEN/8, x13, x9, x10)

inst_4604:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13749*FLEN/8, x13, x9, x10)

inst_4605:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13752*FLEN/8, x13, x9, x10)

inst_4606:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13755*FLEN/8, x13, x9, x10)

inst_4607:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13758*FLEN/8, x13, x9, x10)

inst_4608:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:13761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13761*FLEN/8, x13, x9, x10)

inst_4609:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:13764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13764*FLEN/8, x13, x9, x10)

inst_4610:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:13767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13767*FLEN/8, x13, x9, x10)

inst_4611:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:13770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13770*FLEN/8, x13, x9, x10)

inst_4612:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:13773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13773*FLEN/8, x13, x9, x10)

inst_4613:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13776*FLEN/8, x13, x9, x10)

inst_4614:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13779*FLEN/8, x13, x9, x10)

inst_4615:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13782*FLEN/8, x13, x9, x10)

inst_4616:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:13785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13785*FLEN/8, x13, x9, x10)

inst_4617:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:13788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13788*FLEN/8, x13, x9, x10)

inst_4618:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:13791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13791*FLEN/8, x13, x9, x10)

inst_4619:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:13794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13794*FLEN/8, x13, x9, x10)

inst_4620:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13797*FLEN/8, x13, x9, x10)

inst_4621:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13800*FLEN/8, x13, x9, x10)

inst_4622:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13803*FLEN/8, x13, x9, x10)

inst_4623:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:13806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13806*FLEN/8, x13, x9, x10)

inst_4624:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13809*FLEN/8, x13, x9, x10)

inst_4625:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13812*FLEN/8, x13, x9, x10)

inst_4626:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13815*FLEN/8, x13, x9, x10)

inst_4627:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13818*FLEN/8, x13, x9, x10)

inst_4628:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13821*FLEN/8, x13, x9, x10)

inst_4629:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13824*FLEN/8, x13, x9, x10)

inst_4630:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13827*FLEN/8, x13, x9, x10)

inst_4631:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13830*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_36)

inst_4632:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:13833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13833*FLEN/8, x13, x9, x10)

inst_4633:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:13836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13836*FLEN/8, x13, x9, x10)

inst_4634:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:13839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13839*FLEN/8, x13, x9, x10)

inst_4635:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:13842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13842*FLEN/8, x13, x9, x10)

inst_4636:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:13845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13845*FLEN/8, x13, x9, x10)

inst_4637:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13848*FLEN/8, x13, x9, x10)

inst_4638:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13851*FLEN/8, x13, x9, x10)

inst_4639:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13854*FLEN/8, x13, x9, x10)

inst_4640:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:13857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13857*FLEN/8, x13, x9, x10)

inst_4641:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:13860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13860*FLEN/8, x13, x9, x10)

inst_4642:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:13863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13863*FLEN/8, x13, x9, x10)

inst_4643:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:13866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13866*FLEN/8, x13, x9, x10)

inst_4644:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13869*FLEN/8, x13, x9, x10)

inst_4645:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13872*FLEN/8, x13, x9, x10)

inst_4646:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13875*FLEN/8, x13, x9, x10)

inst_4647:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:13878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13878*FLEN/8, x13, x9, x10)

inst_4648:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13881*FLEN/8, x13, x9, x10)

inst_4649:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13884*FLEN/8, x13, x9, x10)

inst_4650:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13887*FLEN/8, x13, x9, x10)

inst_4651:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13890*FLEN/8, x13, x9, x10)

inst_4652:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13893*FLEN/8, x13, x9, x10)

inst_4653:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13896*FLEN/8, x13, x9, x10)

inst_4654:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13899*FLEN/8, x13, x9, x10)

inst_4655:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13902*FLEN/8, x13, x9, x10)

inst_4656:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:13905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13905*FLEN/8, x13, x9, x10)

inst_4657:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:13908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13908*FLEN/8, x13, x9, x10)

inst_4658:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:13911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13911*FLEN/8, x13, x9, x10)

inst_4659:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:13914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13914*FLEN/8, x13, x9, x10)

inst_4660:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:13917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13917*FLEN/8, x13, x9, x10)

inst_4661:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13920*FLEN/8, x13, x9, x10)

inst_4662:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13923*FLEN/8, x13, x9, x10)

inst_4663:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13926*FLEN/8, x13, x9, x10)

inst_4664:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:13929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13929*FLEN/8, x13, x9, x10)

inst_4665:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:13932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13932*FLEN/8, x13, x9, x10)

inst_4666:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:13935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13935*FLEN/8, x13, x9, x10)

inst_4667:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:13938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13938*FLEN/8, x13, x9, x10)

inst_4668:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:13941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13941*FLEN/8, x13, x9, x10)

inst_4669:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:13944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13944*FLEN/8, x13, x9, x10)

inst_4670:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:13947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13947*FLEN/8, x13, x9, x10)

inst_4671:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:13950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13950*FLEN/8, x13, x9, x10)

inst_4672:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:13953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13953*FLEN/8, x13, x9, x10)

inst_4673:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:13956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13956*FLEN/8, x13, x9, x10)

inst_4674:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:13959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13959*FLEN/8, x13, x9, x10)

inst_4675:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:13962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13962*FLEN/8, x13, x9, x10)

inst_4676:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:13965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13965*FLEN/8, x13, x9, x10)

inst_4677:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:13968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13968*FLEN/8, x13, x9, x10)

inst_4678:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:13971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13971*FLEN/8, x13, x9, x10)

inst_4679:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:13974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13974*FLEN/8, x13, x9, x10)

inst_4680:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:13977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13977*FLEN/8, x13, x9, x10)

inst_4681:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:13980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13980*FLEN/8, x13, x9, x10)

inst_4682:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:13983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13983*FLEN/8, x13, x9, x10)

inst_4683:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:13986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13986*FLEN/8, x13, x9, x10)

inst_4684:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:13989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13989*FLEN/8, x13, x9, x10)

inst_4685:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:13992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13992*FLEN/8, x13, x9, x10)

inst_4686:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:13995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13995*FLEN/8, x13, x9, x10)

inst_4687:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:13998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 13998*FLEN/8, x13, x9, x10)

inst_4688:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:14001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14001*FLEN/8, x13, x9, x10)

inst_4689:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:14004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14004*FLEN/8, x13, x9, x10)

inst_4690:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:14007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14007*FLEN/8, x13, x9, x10)

inst_4691:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:14010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14010*FLEN/8, x13, x9, x10)

inst_4692:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14013*FLEN/8, x13, x9, x10)

inst_4693:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14016*FLEN/8, x13, x9, x10)

inst_4694:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14019*FLEN/8, x13, x9, x10)

inst_4695:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:14022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14022*FLEN/8, x13, x9, x10)

inst_4696:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14025*FLEN/8, x13, x9, x10)

inst_4697:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14028*FLEN/8, x13, x9, x10)

inst_4698:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14031*FLEN/8, x13, x9, x10)

inst_4699:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14034*FLEN/8, x13, x9, x10)

inst_4700:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14037*FLEN/8, x13, x9, x10)

inst_4701:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14040*FLEN/8, x13, x9, x10)

inst_4702:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14043*FLEN/8, x13, x9, x10)

inst_4703:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14046*FLEN/8, x13, x9, x10)

inst_4704:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:14049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14049*FLEN/8, x13, x9, x10)

inst_4705:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:14052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14052*FLEN/8, x13, x9, x10)

inst_4706:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:14055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14055*FLEN/8, x13, x9, x10)

inst_4707:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:14058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14058*FLEN/8, x13, x9, x10)

inst_4708:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:14061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14061*FLEN/8, x13, x9, x10)

inst_4709:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14064*FLEN/8, x13, x9, x10)

inst_4710:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14067*FLEN/8, x13, x9, x10)

inst_4711:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14070*FLEN/8, x13, x9, x10)

inst_4712:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:14073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14073*FLEN/8, x13, x9, x10)

inst_4713:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:14076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14076*FLEN/8, x13, x9, x10)

inst_4714:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:14079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14079*FLEN/8, x13, x9, x10)

inst_4715:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:14082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14082*FLEN/8, x13, x9, x10)

inst_4716:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14085*FLEN/8, x13, x9, x10)

inst_4717:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14088*FLEN/8, x13, x9, x10)

inst_4718:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14091*FLEN/8, x13, x9, x10)

inst_4719:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:14094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14094*FLEN/8, x13, x9, x10)

inst_4720:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14097*FLEN/8, x13, x9, x10)

inst_4721:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14100*FLEN/8, x13, x9, x10)

inst_4722:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14103*FLEN/8, x13, x9, x10)

inst_4723:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14106*FLEN/8, x13, x9, x10)

inst_4724:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14109*FLEN/8, x13, x9, x10)

inst_4725:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14112*FLEN/8, x13, x9, x10)

inst_4726:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14115*FLEN/8, x13, x9, x10)

inst_4727:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14118*FLEN/8, x13, x9, x10)

inst_4728:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:14121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14121*FLEN/8, x13, x9, x10)

inst_4729:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:14124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14124*FLEN/8, x13, x9, x10)

inst_4730:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:14127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14127*FLEN/8, x13, x9, x10)

inst_4731:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:14130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14130*FLEN/8, x13, x9, x10)

inst_4732:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:14133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14133*FLEN/8, x13, x9, x10)

inst_4733:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14136*FLEN/8, x13, x9, x10)

inst_4734:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14139*FLEN/8, x13, x9, x10)

inst_4735:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14142*FLEN/8, x13, x9, x10)

inst_4736:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:14145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14145*FLEN/8, x13, x9, x10)

inst_4737:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:14148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14148*FLEN/8, x13, x9, x10)

inst_4738:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:14151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14151*FLEN/8, x13, x9, x10)

inst_4739:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:14154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14154*FLEN/8, x13, x9, x10)

inst_4740:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14157*FLEN/8, x13, x9, x10)

inst_4741:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14160*FLEN/8, x13, x9, x10)

inst_4742:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14163*FLEN/8, x13, x9, x10)

inst_4743:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:14166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14166*FLEN/8, x13, x9, x10)

inst_4744:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14169*FLEN/8, x13, x9, x10)

inst_4745:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14172*FLEN/8, x13, x9, x10)

inst_4746:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14175*FLEN/8, x13, x9, x10)

inst_4747:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14178*FLEN/8, x13, x9, x10)

inst_4748:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14181*FLEN/8, x13, x9, x10)

inst_4749:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14184*FLEN/8, x13, x9, x10)

inst_4750:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14187*FLEN/8, x13, x9, x10)

inst_4751:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14190*FLEN/8, x13, x9, x10)

inst_4752:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:14193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14193*FLEN/8, x13, x9, x10)

inst_4753:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:14196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14196*FLEN/8, x13, x9, x10)

inst_4754:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:14199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14199*FLEN/8, x13, x9, x10)

inst_4755:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:14202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14202*FLEN/8, x13, x9, x10)

inst_4756:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:14205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14205*FLEN/8, x13, x9, x10)

inst_4757:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14208*FLEN/8, x13, x9, x10)

inst_4758:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14211*FLEN/8, x13, x9, x10)

inst_4759:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14214*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_37)

inst_4760:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:14217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14217*FLEN/8, x13, x9, x10)

inst_4761:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:14220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14220*FLEN/8, x13, x9, x10)

inst_4762:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:14223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14223*FLEN/8, x13, x9, x10)

inst_4763:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:14226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14226*FLEN/8, x13, x9, x10)

inst_4764:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14229*FLEN/8, x13, x9, x10)

inst_4765:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14232*FLEN/8, x13, x9, x10)

inst_4766:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14235*FLEN/8, x13, x9, x10)

inst_4767:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:14238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14238*FLEN/8, x13, x9, x10)

inst_4768:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14241*FLEN/8, x13, x9, x10)

inst_4769:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14244*FLEN/8, x13, x9, x10)

inst_4770:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14247*FLEN/8, x13, x9, x10)

inst_4771:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14250*FLEN/8, x13, x9, x10)

inst_4772:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14253*FLEN/8, x13, x9, x10)

inst_4773:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14256*FLEN/8, x13, x9, x10)

inst_4774:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14259*FLEN/8, x13, x9, x10)

inst_4775:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14262*FLEN/8, x13, x9, x10)

inst_4776:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:14265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14265*FLEN/8, x13, x9, x10)

inst_4777:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:14268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14268*FLEN/8, x13, x9, x10)

inst_4778:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:14271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14271*FLEN/8, x13, x9, x10)

inst_4779:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:14274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14274*FLEN/8, x13, x9, x10)

inst_4780:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:14277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14277*FLEN/8, x13, x9, x10)

inst_4781:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14280*FLEN/8, x13, x9, x10)

inst_4782:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14283*FLEN/8, x13, x9, x10)

inst_4783:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14286*FLEN/8, x13, x9, x10)

inst_4784:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:14289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14289*FLEN/8, x13, x9, x10)

inst_4785:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:14292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14292*FLEN/8, x13, x9, x10)

inst_4786:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:14295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14295*FLEN/8, x13, x9, x10)

inst_4787:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:14298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14298*FLEN/8, x13, x9, x10)

inst_4788:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14301*FLEN/8, x13, x9, x10)

inst_4789:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14304*FLEN/8, x13, x9, x10)

inst_4790:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14307*FLEN/8, x13, x9, x10)

inst_4791:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:14310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14310*FLEN/8, x13, x9, x10)

inst_4792:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14313*FLEN/8, x13, x9, x10)

inst_4793:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14316*FLEN/8, x13, x9, x10)

inst_4794:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14319*FLEN/8, x13, x9, x10)

inst_4795:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14322*FLEN/8, x13, x9, x10)

inst_4796:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14325*FLEN/8, x13, x9, x10)

inst_4797:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14328*FLEN/8, x13, x9, x10)

inst_4798:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14331*FLEN/8, x13, x9, x10)

inst_4799:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14334*FLEN/8, x13, x9, x10)

inst_4800:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:14337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14337*FLEN/8, x13, x9, x10)

inst_4801:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:14340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14340*FLEN/8, x13, x9, x10)

inst_4802:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:14343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14343*FLEN/8, x13, x9, x10)

inst_4803:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:14346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14346*FLEN/8, x13, x9, x10)

inst_4804:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:14349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14349*FLEN/8, x13, x9, x10)

inst_4805:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14352*FLEN/8, x13, x9, x10)

inst_4806:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14355*FLEN/8, x13, x9, x10)

inst_4807:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14358*FLEN/8, x13, x9, x10)

inst_4808:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:14361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14361*FLEN/8, x13, x9, x10)

inst_4809:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:14364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14364*FLEN/8, x13, x9, x10)

inst_4810:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:14367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14367*FLEN/8, x13, x9, x10)

inst_4811:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:14370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14370*FLEN/8, x13, x9, x10)

inst_4812:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14373*FLEN/8, x13, x9, x10)

inst_4813:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14376*FLEN/8, x13, x9, x10)

inst_4814:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14379*FLEN/8, x13, x9, x10)

inst_4815:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:14382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14382*FLEN/8, x13, x9, x10)

inst_4816:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14385*FLEN/8, x13, x9, x10)

inst_4817:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14388*FLEN/8, x13, x9, x10)

inst_4818:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14391*FLEN/8, x13, x9, x10)

inst_4819:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14394*FLEN/8, x13, x9, x10)

inst_4820:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14397*FLEN/8, x13, x9, x10)

inst_4821:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14400*FLEN/8, x13, x9, x10)

inst_4822:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14403*FLEN/8, x13, x9, x10)

inst_4823:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14406*FLEN/8, x13, x9, x10)

inst_4824:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:14409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14409*FLEN/8, x13, x9, x10)

inst_4825:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:14412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14412*FLEN/8, x13, x9, x10)

inst_4826:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:14415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14415*FLEN/8, x13, x9, x10)

inst_4827:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:14418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14418*FLEN/8, x13, x9, x10)

inst_4828:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:14421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14421*FLEN/8, x13, x9, x10)

inst_4829:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14424*FLEN/8, x13, x9, x10)

inst_4830:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14427*FLEN/8, x13, x9, x10)

inst_4831:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14430*FLEN/8, x13, x9, x10)

inst_4832:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:14433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14433*FLEN/8, x13, x9, x10)

inst_4833:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:14436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14436*FLEN/8, x13, x9, x10)

inst_4834:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:14439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14439*FLEN/8, x13, x9, x10)

inst_4835:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:14442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14442*FLEN/8, x13, x9, x10)

inst_4836:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14445*FLEN/8, x13, x9, x10)

inst_4837:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14448*FLEN/8, x13, x9, x10)

inst_4838:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14451*FLEN/8, x13, x9, x10)

inst_4839:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:14454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14454*FLEN/8, x13, x9, x10)

inst_4840:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14457*FLEN/8, x13, x9, x10)

inst_4841:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14460*FLEN/8, x13, x9, x10)

inst_4842:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14463*FLEN/8, x13, x9, x10)

inst_4843:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14466*FLEN/8, x13, x9, x10)

inst_4844:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14469*FLEN/8, x13, x9, x10)

inst_4845:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14472*FLEN/8, x13, x9, x10)

inst_4846:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14475*FLEN/8, x13, x9, x10)

inst_4847:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14478*FLEN/8, x13, x9, x10)

inst_4848:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:14481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14481*FLEN/8, x13, x9, x10)

inst_4849:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:14484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14484*FLEN/8, x13, x9, x10)

inst_4850:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:14487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14487*FLEN/8, x13, x9, x10)

inst_4851:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:14490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14490*FLEN/8, x13, x9, x10)

inst_4852:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:14493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14493*FLEN/8, x13, x9, x10)

inst_4853:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14496*FLEN/8, x13, x9, x10)

inst_4854:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14499*FLEN/8, x13, x9, x10)

inst_4855:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14502*FLEN/8, x13, x9, x10)

inst_4856:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:14505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14505*FLEN/8, x13, x9, x10)

inst_4857:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:14508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14508*FLEN/8, x13, x9, x10)

inst_4858:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:14511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14511*FLEN/8, x13, x9, x10)

inst_4859:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:14514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14514*FLEN/8, x13, x9, x10)

inst_4860:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14517*FLEN/8, x13, x9, x10)

inst_4861:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14520*FLEN/8, x13, x9, x10)

inst_4862:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14523*FLEN/8, x13, x9, x10)

inst_4863:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:14526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14526*FLEN/8, x13, x9, x10)

inst_4864:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14529*FLEN/8, x13, x9, x10)

inst_4865:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14532*FLEN/8, x13, x9, x10)

inst_4866:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14535*FLEN/8, x13, x9, x10)

inst_4867:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14538*FLEN/8, x13, x9, x10)

inst_4868:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14541*FLEN/8, x13, x9, x10)

inst_4869:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14544*FLEN/8, x13, x9, x10)

inst_4870:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14547*FLEN/8, x13, x9, x10)

inst_4871:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14550*FLEN/8, x13, x9, x10)

inst_4872:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:14553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14553*FLEN/8, x13, x9, x10)

inst_4873:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:14556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14556*FLEN/8, x13, x9, x10)

inst_4874:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:14559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14559*FLEN/8, x13, x9, x10)

inst_4875:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:14562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14562*FLEN/8, x13, x9, x10)

inst_4876:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:14565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14565*FLEN/8, x13, x9, x10)

inst_4877:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14568*FLEN/8, x13, x9, x10)

inst_4878:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14571*FLEN/8, x13, x9, x10)

inst_4879:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14574*FLEN/8, x13, x9, x10)

inst_4880:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:14577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14577*FLEN/8, x13, x9, x10)

inst_4881:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:14580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14580*FLEN/8, x13, x9, x10)

inst_4882:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:14583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14583*FLEN/8, x13, x9, x10)

inst_4883:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:14586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14586*FLEN/8, x13, x9, x10)

inst_4884:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14589*FLEN/8, x13, x9, x10)

inst_4885:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14592*FLEN/8, x13, x9, x10)

inst_4886:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14595*FLEN/8, x13, x9, x10)

inst_4887:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:14598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14598*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_38)

inst_4888:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14601*FLEN/8, x13, x9, x10)

inst_4889:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14604*FLEN/8, x13, x9, x10)

inst_4890:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14607*FLEN/8, x13, x9, x10)

inst_4891:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14610*FLEN/8, x13, x9, x10)

inst_4892:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14613*FLEN/8, x13, x9, x10)

inst_4893:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14616*FLEN/8, x13, x9, x10)

inst_4894:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14619*FLEN/8, x13, x9, x10)

inst_4895:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14622*FLEN/8, x13, x9, x10)

inst_4896:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:14625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14625*FLEN/8, x13, x9, x10)

inst_4897:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:14628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14628*FLEN/8, x13, x9, x10)

inst_4898:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:14631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14631*FLEN/8, x13, x9, x10)

inst_4899:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:14634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14634*FLEN/8, x13, x9, x10)

inst_4900:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:14637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14637*FLEN/8, x13, x9, x10)

inst_4901:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14640*FLEN/8, x13, x9, x10)

inst_4902:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14643*FLEN/8, x13, x9, x10)

inst_4903:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14646*FLEN/8, x13, x9, x10)

inst_4904:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:14649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14649*FLEN/8, x13, x9, x10)

inst_4905:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:14652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14652*FLEN/8, x13, x9, x10)

inst_4906:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:14655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14655*FLEN/8, x13, x9, x10)

inst_4907:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:14658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14658*FLEN/8, x13, x9, x10)

inst_4908:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14661*FLEN/8, x13, x9, x10)

inst_4909:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14664*FLEN/8, x13, x9, x10)

inst_4910:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14667*FLEN/8, x13, x9, x10)

inst_4911:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:14670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14670*FLEN/8, x13, x9, x10)

inst_4912:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14673*FLEN/8, x13, x9, x10)

inst_4913:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14676*FLEN/8, x13, x9, x10)

inst_4914:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14679*FLEN/8, x13, x9, x10)

inst_4915:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14682*FLEN/8, x13, x9, x10)

inst_4916:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14685*FLEN/8, x13, x9, x10)

inst_4917:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14688*FLEN/8, x13, x9, x10)

inst_4918:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14691*FLEN/8, x13, x9, x10)

inst_4919:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14694*FLEN/8, x13, x9, x10)

inst_4920:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:14697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14697*FLEN/8, x13, x9, x10)

inst_4921:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:14700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14700*FLEN/8, x13, x9, x10)

inst_4922:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:14703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14703*FLEN/8, x13, x9, x10)

inst_4923:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:14706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14706*FLEN/8, x13, x9, x10)

inst_4924:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:14709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14709*FLEN/8, x13, x9, x10)

inst_4925:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14712*FLEN/8, x13, x9, x10)

inst_4926:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14715*FLEN/8, x13, x9, x10)

inst_4927:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14718*FLEN/8, x13, x9, x10)

inst_4928:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:14721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14721*FLEN/8, x13, x9, x10)

inst_4929:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:14724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14724*FLEN/8, x13, x9, x10)

inst_4930:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:14727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14727*FLEN/8, x13, x9, x10)

inst_4931:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:14730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14730*FLEN/8, x13, x9, x10)

inst_4932:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14733*FLEN/8, x13, x9, x10)

inst_4933:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14736*FLEN/8, x13, x9, x10)

inst_4934:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14739*FLEN/8, x13, x9, x10)

inst_4935:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:14742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14742*FLEN/8, x13, x9, x10)

inst_4936:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14745*FLEN/8, x13, x9, x10)

inst_4937:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14748*FLEN/8, x13, x9, x10)

inst_4938:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14751*FLEN/8, x13, x9, x10)

inst_4939:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14754*FLEN/8, x13, x9, x10)

inst_4940:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14757*FLEN/8, x13, x9, x10)

inst_4941:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14760*FLEN/8, x13, x9, x10)

inst_4942:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14763*FLEN/8, x13, x9, x10)

inst_4943:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14766*FLEN/8, x13, x9, x10)

inst_4944:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:14769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14769*FLEN/8, x13, x9, x10)

inst_4945:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:14772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14772*FLEN/8, x13, x9, x10)

inst_4946:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:14775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14775*FLEN/8, x13, x9, x10)

inst_4947:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:14778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14778*FLEN/8, x13, x9, x10)

inst_4948:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:14781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14781*FLEN/8, x13, x9, x10)

inst_4949:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14784*FLEN/8, x13, x9, x10)

inst_4950:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14787*FLEN/8, x13, x9, x10)

inst_4951:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14790*FLEN/8, x13, x9, x10)

inst_4952:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:14793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14793*FLEN/8, x13, x9, x10)

inst_4953:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:14796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14796*FLEN/8, x13, x9, x10)

inst_4954:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:14799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14799*FLEN/8, x13, x9, x10)

inst_4955:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:14802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14802*FLEN/8, x13, x9, x10)

inst_4956:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14805*FLEN/8, x13, x9, x10)

inst_4957:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14808*FLEN/8, x13, x9, x10)

inst_4958:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14811*FLEN/8, x13, x9, x10)

inst_4959:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:14814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14814*FLEN/8, x13, x9, x10)

inst_4960:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14817*FLEN/8, x13, x9, x10)

inst_4961:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14820*FLEN/8, x13, x9, x10)

inst_4962:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14823*FLEN/8, x13, x9, x10)

inst_4963:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14826*FLEN/8, x13, x9, x10)

inst_4964:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14829*FLEN/8, x13, x9, x10)

inst_4965:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14832*FLEN/8, x13, x9, x10)

inst_4966:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14835*FLEN/8, x13, x9, x10)

inst_4967:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14838*FLEN/8, x13, x9, x10)

inst_4968:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:14841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14841*FLEN/8, x13, x9, x10)

inst_4969:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:14844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14844*FLEN/8, x13, x9, x10)

inst_4970:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:14847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14847*FLEN/8, x13, x9, x10)

inst_4971:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:14850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14850*FLEN/8, x13, x9, x10)

inst_4972:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:14853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14853*FLEN/8, x13, x9, x10)

inst_4973:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14856*FLEN/8, x13, x9, x10)

inst_4974:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14859*FLEN/8, x13, x9, x10)

inst_4975:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14862*FLEN/8, x13, x9, x10)

inst_4976:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:14865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14865*FLEN/8, x13, x9, x10)

inst_4977:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:14868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14868*FLEN/8, x13, x9, x10)

inst_4978:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:14871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14871*FLEN/8, x13, x9, x10)

inst_4979:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:14874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14874*FLEN/8, x13, x9, x10)

inst_4980:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14877*FLEN/8, x13, x9, x10)

inst_4981:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14880*FLEN/8, x13, x9, x10)

inst_4982:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14883*FLEN/8, x13, x9, x10)

inst_4983:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:14886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14886*FLEN/8, x13, x9, x10)

inst_4984:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14889*FLEN/8, x13, x9, x10)

inst_4985:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14892*FLEN/8, x13, x9, x10)

inst_4986:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14895*FLEN/8, x13, x9, x10)

inst_4987:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14898*FLEN/8, x13, x9, x10)

inst_4988:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14901*FLEN/8, x13, x9, x10)

inst_4989:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14904*FLEN/8, x13, x9, x10)

inst_4990:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14907*FLEN/8, x13, x9, x10)

inst_4991:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14910*FLEN/8, x13, x9, x10)

inst_4992:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:14913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14913*FLEN/8, x13, x9, x10)

inst_4993:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:14916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14916*FLEN/8, x13, x9, x10)

inst_4994:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:14919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14919*FLEN/8, x13, x9, x10)

inst_4995:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:14922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14922*FLEN/8, x13, x9, x10)

inst_4996:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:14925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14925*FLEN/8, x13, x9, x10)

inst_4997:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:14928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14928*FLEN/8, x13, x9, x10)

inst_4998:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:14931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14931*FLEN/8, x13, x9, x10)

inst_4999:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:14934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14934*FLEN/8, x13, x9, x10)

inst_5000:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:14937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14937*FLEN/8, x13, x9, x10)

inst_5001:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:14940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14940*FLEN/8, x13, x9, x10)

inst_5002:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:14943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14943*FLEN/8, x13, x9, x10)

inst_5003:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:14946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14946*FLEN/8, x13, x9, x10)

inst_5004:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:14949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14949*FLEN/8, x13, x9, x10)

inst_5005:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:14952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14952*FLEN/8, x13, x9, x10)

inst_5006:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:14955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14955*FLEN/8, x13, x9, x10)

inst_5007:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:14958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14958*FLEN/8, x13, x9, x10)

inst_5008:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:14961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14961*FLEN/8, x13, x9, x10)

inst_5009:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:14964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14964*FLEN/8, x13, x9, x10)

inst_5010:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:14967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14967*FLEN/8, x13, x9, x10)

inst_5011:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:14970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14970*FLEN/8, x13, x9, x10)

inst_5012:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:14973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14973*FLEN/8, x13, x9, x10)

inst_5013:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:14976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14976*FLEN/8, x13, x9, x10)

inst_5014:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:14979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14979*FLEN/8, x13, x9, x10)

inst_5015:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:14982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14982*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_39)

inst_5016:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:14985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14985*FLEN/8, x13, x9, x10)

inst_5017:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:14988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14988*FLEN/8, x13, x9, x10)

inst_5018:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:14991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14991*FLEN/8, x13, x9, x10)

inst_5019:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:14994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14994*FLEN/8, x13, x9, x10)

inst_5020:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:14997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 14997*FLEN/8, x13, x9, x10)

inst_5021:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15000*FLEN/8, x13, x9, x10)

inst_5022:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15003*FLEN/8, x13, x9, x10)

inst_5023:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15006*FLEN/8, x13, x9, x10)

inst_5024:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:15009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15009*FLEN/8, x13, x9, x10)

inst_5025:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:15012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15012*FLEN/8, x13, x9, x10)

inst_5026:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:15015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15015*FLEN/8, x13, x9, x10)

inst_5027:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:15018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15018*FLEN/8, x13, x9, x10)

inst_5028:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15021*FLEN/8, x13, x9, x10)

inst_5029:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15024*FLEN/8, x13, x9, x10)

inst_5030:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15027*FLEN/8, x13, x9, x10)

inst_5031:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:15030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15030*FLEN/8, x13, x9, x10)

inst_5032:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15033*FLEN/8, x13, x9, x10)

inst_5033:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15036*FLEN/8, x13, x9, x10)

inst_5034:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15039*FLEN/8, x13, x9, x10)

inst_5035:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15042*FLEN/8, x13, x9, x10)

inst_5036:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15045*FLEN/8, x13, x9, x10)

inst_5037:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15048*FLEN/8, x13, x9, x10)

inst_5038:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15051*FLEN/8, x13, x9, x10)

inst_5039:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15054*FLEN/8, x13, x9, x10)

inst_5040:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:15057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15057*FLEN/8, x13, x9, x10)

inst_5041:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:15060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15060*FLEN/8, x13, x9, x10)

inst_5042:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:15063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15063*FLEN/8, x13, x9, x10)

inst_5043:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:15066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15066*FLEN/8, x13, x9, x10)

inst_5044:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:15069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15069*FLEN/8, x13, x9, x10)

inst_5045:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15072*FLEN/8, x13, x9, x10)

inst_5046:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15075*FLEN/8, x13, x9, x10)

inst_5047:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15078*FLEN/8, x13, x9, x10)

inst_5048:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:15081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15081*FLEN/8, x13, x9, x10)

inst_5049:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:15084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15084*FLEN/8, x13, x9, x10)

inst_5050:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:15087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15087*FLEN/8, x13, x9, x10)

inst_5051:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:15090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15090*FLEN/8, x13, x9, x10)

inst_5052:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15093*FLEN/8, x13, x9, x10)

inst_5053:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15096*FLEN/8, x13, x9, x10)

inst_5054:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15099*FLEN/8, x13, x9, x10)

inst_5055:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:15102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15102*FLEN/8, x13, x9, x10)

inst_5056:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15105*FLEN/8, x13, x9, x10)

inst_5057:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15108*FLEN/8, x13, x9, x10)

inst_5058:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15111*FLEN/8, x13, x9, x10)

inst_5059:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15114*FLEN/8, x13, x9, x10)

inst_5060:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15117*FLEN/8, x13, x9, x10)

inst_5061:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15120*FLEN/8, x13, x9, x10)

inst_5062:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15123*FLEN/8, x13, x9, x10)

inst_5063:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15126*FLEN/8, x13, x9, x10)

inst_5064:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:15129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15129*FLEN/8, x13, x9, x10)

inst_5065:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:15132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15132*FLEN/8, x13, x9, x10)

inst_5066:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:15135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15135*FLEN/8, x13, x9, x10)

inst_5067:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:15138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15138*FLEN/8, x13, x9, x10)

inst_5068:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:15141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15141*FLEN/8, x13, x9, x10)

inst_5069:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15144*FLEN/8, x13, x9, x10)

inst_5070:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15147*FLEN/8, x13, x9, x10)

inst_5071:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15150*FLEN/8, x13, x9, x10)

inst_5072:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:15153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15153*FLEN/8, x13, x9, x10)

inst_5073:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:15156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15156*FLEN/8, x13, x9, x10)

inst_5074:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:15159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15159*FLEN/8, x13, x9, x10)

inst_5075:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:15162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15162*FLEN/8, x13, x9, x10)

inst_5076:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15165*FLEN/8, x13, x9, x10)

inst_5077:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15168*FLEN/8, x13, x9, x10)

inst_5078:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15171*FLEN/8, x13, x9, x10)

inst_5079:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:15174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15174*FLEN/8, x13, x9, x10)

inst_5080:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15177*FLEN/8, x13, x9, x10)

inst_5081:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15180*FLEN/8, x13, x9, x10)

inst_5082:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15183*FLEN/8, x13, x9, x10)

inst_5083:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15186*FLEN/8, x13, x9, x10)

inst_5084:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15189*FLEN/8, x13, x9, x10)

inst_5085:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15192*FLEN/8, x13, x9, x10)

inst_5086:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15195*FLEN/8, x13, x9, x10)

inst_5087:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15198*FLEN/8, x13, x9, x10)

inst_5088:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:15201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15201*FLEN/8, x13, x9, x10)

inst_5089:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:15204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15204*FLEN/8, x13, x9, x10)

inst_5090:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:15207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15207*FLEN/8, x13, x9, x10)

inst_5091:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:15210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15210*FLEN/8, x13, x9, x10)

inst_5092:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:15213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15213*FLEN/8, x13, x9, x10)

inst_5093:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15216*FLEN/8, x13, x9, x10)

inst_5094:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15219*FLEN/8, x13, x9, x10)

inst_5095:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15222*FLEN/8, x13, x9, x10)

inst_5096:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:15225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15225*FLEN/8, x13, x9, x10)

inst_5097:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:15228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15228*FLEN/8, x13, x9, x10)

inst_5098:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:15231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15231*FLEN/8, x13, x9, x10)

inst_5099:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:15234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15234*FLEN/8, x13, x9, x10)

inst_5100:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15237*FLEN/8, x13, x9, x10)

inst_5101:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15240*FLEN/8, x13, x9, x10)

inst_5102:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15243*FLEN/8, x13, x9, x10)

inst_5103:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:15246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15246*FLEN/8, x13, x9, x10)

inst_5104:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15249*FLEN/8, x13, x9, x10)

inst_5105:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15252*FLEN/8, x13, x9, x10)

inst_5106:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15255*FLEN/8, x13, x9, x10)

inst_5107:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15258*FLEN/8, x13, x9, x10)

inst_5108:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15261*FLEN/8, x13, x9, x10)

inst_5109:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15264*FLEN/8, x13, x9, x10)

inst_5110:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15267*FLEN/8, x13, x9, x10)

inst_5111:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15270*FLEN/8, x13, x9, x10)

inst_5112:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:15273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15273*FLEN/8, x13, x9, x10)

inst_5113:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:15276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15276*FLEN/8, x13, x9, x10)

inst_5114:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:15279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15279*FLEN/8, x13, x9, x10)

inst_5115:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:15282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15282*FLEN/8, x13, x9, x10)

inst_5116:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:15285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15285*FLEN/8, x13, x9, x10)

inst_5117:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15288*FLEN/8, x13, x9, x10)

inst_5118:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15291*FLEN/8, x13, x9, x10)

inst_5119:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15294*FLEN/8, x13, x9, x10)

inst_5120:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:15297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15297*FLEN/8, x13, x9, x10)

inst_5121:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:15300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15300*FLEN/8, x13, x9, x10)

inst_5122:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:15303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15303*FLEN/8, x13, x9, x10)

inst_5123:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:15306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15306*FLEN/8, x13, x9, x10)

inst_5124:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15309*FLEN/8, x13, x9, x10)

inst_5125:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15312*FLEN/8, x13, x9, x10)

inst_5126:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15315*FLEN/8, x13, x9, x10)

inst_5127:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:15318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15318*FLEN/8, x13, x9, x10)

inst_5128:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15321*FLEN/8, x13, x9, x10)

inst_5129:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15324*FLEN/8, x13, x9, x10)

inst_5130:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15327*FLEN/8, x13, x9, x10)

inst_5131:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15330*FLEN/8, x13, x9, x10)

inst_5132:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15333*FLEN/8, x13, x9, x10)

inst_5133:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15336*FLEN/8, x13, x9, x10)

inst_5134:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15339*FLEN/8, x13, x9, x10)

inst_5135:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15342*FLEN/8, x13, x9, x10)

inst_5136:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:15345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15345*FLEN/8, x13, x9, x10)

inst_5137:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:15348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15348*FLEN/8, x13, x9, x10)

inst_5138:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:15351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15351*FLEN/8, x13, x9, x10)

inst_5139:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:15354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15354*FLEN/8, x13, x9, x10)

inst_5140:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:15357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15357*FLEN/8, x13, x9, x10)

inst_5141:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15360*FLEN/8, x13, x9, x10)

inst_5142:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15363*FLEN/8, x13, x9, x10)

inst_5143:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15366*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_40)

inst_5144:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:15369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15369*FLEN/8, x13, x9, x10)

inst_5145:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:15372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15372*FLEN/8, x13, x9, x10)

inst_5146:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:15375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15375*FLEN/8, x13, x9, x10)

inst_5147:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:15378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15378*FLEN/8, x13, x9, x10)

inst_5148:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15381*FLEN/8, x13, x9, x10)

inst_5149:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15384*FLEN/8, x13, x9, x10)

inst_5150:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15387*FLEN/8, x13, x9, x10)

inst_5151:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:15390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15390*FLEN/8, x13, x9, x10)

inst_5152:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15393*FLEN/8, x13, x9, x10)

inst_5153:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15396*FLEN/8, x13, x9, x10)

inst_5154:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15399*FLEN/8, x13, x9, x10)

inst_5155:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15402*FLEN/8, x13, x9, x10)

inst_5156:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15405*FLEN/8, x13, x9, x10)

inst_5157:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15408*FLEN/8, x13, x9, x10)

inst_5158:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15411*FLEN/8, x13, x9, x10)

inst_5159:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15414*FLEN/8, x13, x9, x10)

inst_5160:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:15417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15417*FLEN/8, x13, x9, x10)

inst_5161:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:15420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15420*FLEN/8, x13, x9, x10)

inst_5162:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:15423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15423*FLEN/8, x13, x9, x10)

inst_5163:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:15426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15426*FLEN/8, x13, x9, x10)

inst_5164:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:15429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15429*FLEN/8, x13, x9, x10)

inst_5165:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15432*FLEN/8, x13, x9, x10)

inst_5166:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15435*FLEN/8, x13, x9, x10)

inst_5167:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15438*FLEN/8, x13, x9, x10)

inst_5168:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:15441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15441*FLEN/8, x13, x9, x10)

inst_5169:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:15444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15444*FLEN/8, x13, x9, x10)

inst_5170:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:15447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15447*FLEN/8, x13, x9, x10)

inst_5171:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:15450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15450*FLEN/8, x13, x9, x10)

inst_5172:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15453*FLEN/8, x13, x9, x10)

inst_5173:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15456*FLEN/8, x13, x9, x10)

inst_5174:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15459*FLEN/8, x13, x9, x10)

inst_5175:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:15462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15462*FLEN/8, x13, x9, x10)

inst_5176:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15465*FLEN/8, x13, x9, x10)

inst_5177:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15468*FLEN/8, x13, x9, x10)

inst_5178:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15471*FLEN/8, x13, x9, x10)

inst_5179:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15474*FLEN/8, x13, x9, x10)

inst_5180:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15477*FLEN/8, x13, x9, x10)

inst_5181:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15480*FLEN/8, x13, x9, x10)

inst_5182:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15483*FLEN/8, x13, x9, x10)

inst_5183:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15486*FLEN/8, x13, x9, x10)

inst_5184:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:15489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15489*FLEN/8, x13, x9, x10)

inst_5185:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:15492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15492*FLEN/8, x13, x9, x10)

inst_5186:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:15495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15495*FLEN/8, x13, x9, x10)

inst_5187:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:15498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15498*FLEN/8, x13, x9, x10)

inst_5188:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:15501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15501*FLEN/8, x13, x9, x10)

inst_5189:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15504*FLEN/8, x13, x9, x10)

inst_5190:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15507*FLEN/8, x13, x9, x10)

inst_5191:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15510*FLEN/8, x13, x9, x10)

inst_5192:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:15513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15513*FLEN/8, x13, x9, x10)

inst_5193:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:15516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15516*FLEN/8, x13, x9, x10)

inst_5194:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:15519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15519*FLEN/8, x13, x9, x10)

inst_5195:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:15522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15522*FLEN/8, x13, x9, x10)

inst_5196:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15525*FLEN/8, x13, x9, x10)

inst_5197:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15528*FLEN/8, x13, x9, x10)

inst_5198:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15531*FLEN/8, x13, x9, x10)

inst_5199:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:15534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15534*FLEN/8, x13, x9, x10)

inst_5200:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15537*FLEN/8, x13, x9, x10)

inst_5201:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15540*FLEN/8, x13, x9, x10)

inst_5202:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15543*FLEN/8, x13, x9, x10)

inst_5203:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15546*FLEN/8, x13, x9, x10)

inst_5204:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15549*FLEN/8, x13, x9, x10)

inst_5205:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15552*FLEN/8, x13, x9, x10)

inst_5206:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15555*FLEN/8, x13, x9, x10)

inst_5207:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15558*FLEN/8, x13, x9, x10)

inst_5208:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:15561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15561*FLEN/8, x13, x9, x10)

inst_5209:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:15564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15564*FLEN/8, x13, x9, x10)

inst_5210:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:15567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15567*FLEN/8, x13, x9, x10)

inst_5211:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:15570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15570*FLEN/8, x13, x9, x10)

inst_5212:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:15573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15573*FLEN/8, x13, x9, x10)

inst_5213:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15576*FLEN/8, x13, x9, x10)

inst_5214:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15579*FLEN/8, x13, x9, x10)

inst_5215:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15582*FLEN/8, x13, x9, x10)

inst_5216:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:15585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15585*FLEN/8, x13, x9, x10)

inst_5217:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:15588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15588*FLEN/8, x13, x9, x10)

inst_5218:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:15591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15591*FLEN/8, x13, x9, x10)

inst_5219:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:15594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15594*FLEN/8, x13, x9, x10)

inst_5220:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15597*FLEN/8, x13, x9, x10)

inst_5221:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15600*FLEN/8, x13, x9, x10)

inst_5222:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15603*FLEN/8, x13, x9, x10)

inst_5223:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:15606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15606*FLEN/8, x13, x9, x10)

inst_5224:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15609*FLEN/8, x13, x9, x10)

inst_5225:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15612*FLEN/8, x13, x9, x10)

inst_5226:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15615*FLEN/8, x13, x9, x10)

inst_5227:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15618*FLEN/8, x13, x9, x10)

inst_5228:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15621*FLEN/8, x13, x9, x10)

inst_5229:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15624*FLEN/8, x13, x9, x10)

inst_5230:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15627*FLEN/8, x13, x9, x10)

inst_5231:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15630*FLEN/8, x13, x9, x10)

inst_5232:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:15633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15633*FLEN/8, x13, x9, x10)

inst_5233:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:15636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15636*FLEN/8, x13, x9, x10)

inst_5234:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:15639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15639*FLEN/8, x13, x9, x10)

inst_5235:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:15642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15642*FLEN/8, x13, x9, x10)

inst_5236:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:15645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15645*FLEN/8, x13, x9, x10)

inst_5237:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15648*FLEN/8, x13, x9, x10)

inst_5238:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15651*FLEN/8, x13, x9, x10)

inst_5239:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15654*FLEN/8, x13, x9, x10)

inst_5240:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:15657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15657*FLEN/8, x13, x9, x10)

inst_5241:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:15660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15660*FLEN/8, x13, x9, x10)

inst_5242:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:15663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15663*FLEN/8, x13, x9, x10)

inst_5243:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:15666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15666*FLEN/8, x13, x9, x10)

inst_5244:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15669*FLEN/8, x13, x9, x10)

inst_5245:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15672*FLEN/8, x13, x9, x10)

inst_5246:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15675*FLEN/8, x13, x9, x10)

inst_5247:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:15678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15678*FLEN/8, x13, x9, x10)

inst_5248:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15681*FLEN/8, x13, x9, x10)

inst_5249:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15684*FLEN/8, x13, x9, x10)

inst_5250:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15687*FLEN/8, x13, x9, x10)

inst_5251:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15690*FLEN/8, x13, x9, x10)

inst_5252:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15693*FLEN/8, x13, x9, x10)

inst_5253:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15696*FLEN/8, x13, x9, x10)

inst_5254:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15699*FLEN/8, x13, x9, x10)

inst_5255:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15702*FLEN/8, x13, x9, x10)

inst_5256:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:15705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15705*FLEN/8, x13, x9, x10)

inst_5257:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:15708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15708*FLEN/8, x13, x9, x10)

inst_5258:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:15711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15711*FLEN/8, x13, x9, x10)

inst_5259:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:15714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15714*FLEN/8, x13, x9, x10)

inst_5260:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:15717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15717*FLEN/8, x13, x9, x10)

inst_5261:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15720*FLEN/8, x13, x9, x10)

inst_5262:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15723*FLEN/8, x13, x9, x10)

inst_5263:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15726*FLEN/8, x13, x9, x10)

inst_5264:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:15729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15729*FLEN/8, x13, x9, x10)

inst_5265:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:15732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15732*FLEN/8, x13, x9, x10)

inst_5266:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:15735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15735*FLEN/8, x13, x9, x10)

inst_5267:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:15738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15738*FLEN/8, x13, x9, x10)

inst_5268:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15741*FLEN/8, x13, x9, x10)

inst_5269:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15744*FLEN/8, x13, x9, x10)

inst_5270:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15747*FLEN/8, x13, x9, x10)

inst_5271:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:15750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15750*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_41)

inst_5272:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15753*FLEN/8, x13, x9, x10)

inst_5273:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15756*FLEN/8, x13, x9, x10)

inst_5274:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15759*FLEN/8, x13, x9, x10)

inst_5275:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15762*FLEN/8, x13, x9, x10)

inst_5276:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15765*FLEN/8, x13, x9, x10)

inst_5277:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15768*FLEN/8, x13, x9, x10)

inst_5278:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15771*FLEN/8, x13, x9, x10)

inst_5279:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15774*FLEN/8, x13, x9, x10)

inst_5280:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:15777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15777*FLEN/8, x13, x9, x10)

inst_5281:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:15780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15780*FLEN/8, x13, x9, x10)

inst_5282:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:15783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15783*FLEN/8, x13, x9, x10)

inst_5283:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:15786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15786*FLEN/8, x13, x9, x10)

inst_5284:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:15789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15789*FLEN/8, x13, x9, x10)

inst_5285:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15792*FLEN/8, x13, x9, x10)

inst_5286:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15795*FLEN/8, x13, x9, x10)

inst_5287:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15798*FLEN/8, x13, x9, x10)

inst_5288:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:15801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15801*FLEN/8, x13, x9, x10)

inst_5289:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:15804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15804*FLEN/8, x13, x9, x10)

inst_5290:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:15807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15807*FLEN/8, x13, x9, x10)

inst_5291:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:15810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15810*FLEN/8, x13, x9, x10)

inst_5292:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15813*FLEN/8, x13, x9, x10)

inst_5293:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15816*FLEN/8, x13, x9, x10)

inst_5294:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15819*FLEN/8, x13, x9, x10)

inst_5295:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:15822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15822*FLEN/8, x13, x9, x10)

inst_5296:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15825*FLEN/8, x13, x9, x10)

inst_5297:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15828*FLEN/8, x13, x9, x10)

inst_5298:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15831*FLEN/8, x13, x9, x10)

inst_5299:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15834*FLEN/8, x13, x9, x10)

inst_5300:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15837*FLEN/8, x13, x9, x10)

inst_5301:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15840*FLEN/8, x13, x9, x10)

inst_5302:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15843*FLEN/8, x13, x9, x10)

inst_5303:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15846*FLEN/8, x13, x9, x10)

inst_5304:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:15849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15849*FLEN/8, x13, x9, x10)

inst_5305:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:15852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15852*FLEN/8, x13, x9, x10)

inst_5306:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:15855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15855*FLEN/8, x13, x9, x10)

inst_5307:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:15858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15858*FLEN/8, x13, x9, x10)

inst_5308:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:15861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15861*FLEN/8, x13, x9, x10)

inst_5309:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15864*FLEN/8, x13, x9, x10)

inst_5310:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15867*FLEN/8, x13, x9, x10)

inst_5311:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15870*FLEN/8, x13, x9, x10)

inst_5312:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:15873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15873*FLEN/8, x13, x9, x10)

inst_5313:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:15876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15876*FLEN/8, x13, x9, x10)

inst_5314:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:15879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15879*FLEN/8, x13, x9, x10)

inst_5315:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:15882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15882*FLEN/8, x13, x9, x10)

inst_5316:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15885*FLEN/8, x13, x9, x10)

inst_5317:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15888*FLEN/8, x13, x9, x10)

inst_5318:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15891*FLEN/8, x13, x9, x10)

inst_5319:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:15894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15894*FLEN/8, x13, x9, x10)

inst_5320:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15897*FLEN/8, x13, x9, x10)

inst_5321:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15900*FLEN/8, x13, x9, x10)

inst_5322:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15903*FLEN/8, x13, x9, x10)

inst_5323:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15906*FLEN/8, x13, x9, x10)

inst_5324:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15909*FLEN/8, x13, x9, x10)

inst_5325:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15912*FLEN/8, x13, x9, x10)

inst_5326:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15915*FLEN/8, x13, x9, x10)

inst_5327:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15918*FLEN/8, x13, x9, x10)

inst_5328:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:15921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15921*FLEN/8, x13, x9, x10)

inst_5329:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:15924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15924*FLEN/8, x13, x9, x10)

inst_5330:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:15927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15927*FLEN/8, x13, x9, x10)

inst_5331:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:15930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15930*FLEN/8, x13, x9, x10)

inst_5332:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:15933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15933*FLEN/8, x13, x9, x10)

inst_5333:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:15936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15936*FLEN/8, x13, x9, x10)

inst_5334:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:15939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15939*FLEN/8, x13, x9, x10)

inst_5335:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:15942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15942*FLEN/8, x13, x9, x10)

inst_5336:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:15945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15945*FLEN/8, x13, x9, x10)

inst_5337:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:15948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15948*FLEN/8, x13, x9, x10)

inst_5338:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:15951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15951*FLEN/8, x13, x9, x10)

inst_5339:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:15954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15954*FLEN/8, x13, x9, x10)

inst_5340:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:15957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15957*FLEN/8, x13, x9, x10)

inst_5341:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:15960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15960*FLEN/8, x13, x9, x10)

inst_5342:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:15963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15963*FLEN/8, x13, x9, x10)

inst_5343:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:15966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15966*FLEN/8, x13, x9, x10)

inst_5344:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:15969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15969*FLEN/8, x13, x9, x10)

inst_5345:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:15972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15972*FLEN/8, x13, x9, x10)

inst_5346:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:15975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15975*FLEN/8, x13, x9, x10)

inst_5347:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:15978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15978*FLEN/8, x13, x9, x10)

inst_5348:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:15981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15981*FLEN/8, x13, x9, x10)

inst_5349:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:15984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15984*FLEN/8, x13, x9, x10)

inst_5350:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:15987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15987*FLEN/8, x13, x9, x10)

inst_5351:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:15990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15990*FLEN/8, x13, x9, x10)

inst_5352:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:15993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15993*FLEN/8, x13, x9, x10)

inst_5353:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:15996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15996*FLEN/8, x13, x9, x10)

inst_5354:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:15999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 15999*FLEN/8, x13, x9, x10)

inst_5355:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:16002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16002*FLEN/8, x13, x9, x10)

inst_5356:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:16005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16005*FLEN/8, x13, x9, x10)

inst_5357:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16008*FLEN/8, x13, x9, x10)

inst_5358:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16011*FLEN/8, x13, x9, x10)

inst_5359:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16014*FLEN/8, x13, x9, x10)

inst_5360:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:16017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16017*FLEN/8, x13, x9, x10)

inst_5361:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:16020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16020*FLEN/8, x13, x9, x10)

inst_5362:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:16023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16023*FLEN/8, x13, x9, x10)

inst_5363:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:16026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16026*FLEN/8, x13, x9, x10)

inst_5364:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16029*FLEN/8, x13, x9, x10)

inst_5365:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16032*FLEN/8, x13, x9, x10)

inst_5366:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16035*FLEN/8, x13, x9, x10)

inst_5367:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:16038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16038*FLEN/8, x13, x9, x10)

inst_5368:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16041*FLEN/8, x13, x9, x10)

inst_5369:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16044*FLEN/8, x13, x9, x10)

inst_5370:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16047*FLEN/8, x13, x9, x10)

inst_5371:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16050*FLEN/8, x13, x9, x10)

inst_5372:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16053*FLEN/8, x13, x9, x10)

inst_5373:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16056*FLEN/8, x13, x9, x10)

inst_5374:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16059*FLEN/8, x13, x9, x10)

inst_5375:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16062*FLEN/8, x13, x9, x10)

inst_5376:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:16065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16065*FLEN/8, x13, x9, x10)

inst_5377:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:16068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16068*FLEN/8, x13, x9, x10)

inst_5378:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:16071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16071*FLEN/8, x13, x9, x10)

inst_5379:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:16074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16074*FLEN/8, x13, x9, x10)

inst_5380:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:16077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16077*FLEN/8, x13, x9, x10)

inst_5381:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16080*FLEN/8, x13, x9, x10)

inst_5382:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16083*FLEN/8, x13, x9, x10)

inst_5383:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16086*FLEN/8, x13, x9, x10)

inst_5384:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:16089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16089*FLEN/8, x13, x9, x10)

inst_5385:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:16092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16092*FLEN/8, x13, x9, x10)

inst_5386:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:16095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16095*FLEN/8, x13, x9, x10)

inst_5387:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:16098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16098*FLEN/8, x13, x9, x10)

inst_5388:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16101*FLEN/8, x13, x9, x10)

inst_5389:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16104*FLEN/8, x13, x9, x10)

inst_5390:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16107*FLEN/8, x13, x9, x10)

inst_5391:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:16110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16110*FLEN/8, x13, x9, x10)

inst_5392:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16113*FLEN/8, x13, x9, x10)

inst_5393:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16116*FLEN/8, x13, x9, x10)

inst_5394:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16119*FLEN/8, x13, x9, x10)

inst_5395:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16122*FLEN/8, x13, x9, x10)

inst_5396:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16125*FLEN/8, x13, x9, x10)

inst_5397:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16128*FLEN/8, x13, x9, x10)

inst_5398:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16131*FLEN/8, x13, x9, x10)

inst_5399:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16134*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_42)

inst_5400:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:16137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16137*FLEN/8, x13, x9, x10)

inst_5401:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:16140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16140*FLEN/8, x13, x9, x10)

inst_5402:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:16143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16143*FLEN/8, x13, x9, x10)

inst_5403:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:16146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16146*FLEN/8, x13, x9, x10)

inst_5404:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:16149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16149*FLEN/8, x13, x9, x10)

inst_5405:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16152*FLEN/8, x13, x9, x10)

inst_5406:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16155*FLEN/8, x13, x9, x10)

inst_5407:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16158*FLEN/8, x13, x9, x10)

inst_5408:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:16161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16161*FLEN/8, x13, x9, x10)

inst_5409:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:16164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16164*FLEN/8, x13, x9, x10)

inst_5410:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:16167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16167*FLEN/8, x13, x9, x10)

inst_5411:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:16170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16170*FLEN/8, x13, x9, x10)

inst_5412:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16173*FLEN/8, x13, x9, x10)

inst_5413:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16176*FLEN/8, x13, x9, x10)

inst_5414:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16179*FLEN/8, x13, x9, x10)

inst_5415:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:16182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16182*FLEN/8, x13, x9, x10)

inst_5416:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16185*FLEN/8, x13, x9, x10)

inst_5417:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16188*FLEN/8, x13, x9, x10)

inst_5418:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16191*FLEN/8, x13, x9, x10)

inst_5419:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16194*FLEN/8, x13, x9, x10)

inst_5420:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16197*FLEN/8, x13, x9, x10)

inst_5421:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16200*FLEN/8, x13, x9, x10)

inst_5422:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16203*FLEN/8, x13, x9, x10)

inst_5423:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16206*FLEN/8, x13, x9, x10)

inst_5424:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:16209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16209*FLEN/8, x13, x9, x10)

inst_5425:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:16212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16212*FLEN/8, x13, x9, x10)

inst_5426:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:16215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16215*FLEN/8, x13, x9, x10)

inst_5427:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:16218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16218*FLEN/8, x13, x9, x10)

inst_5428:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:16221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16221*FLEN/8, x13, x9, x10)

inst_5429:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16224*FLEN/8, x13, x9, x10)

inst_5430:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16227*FLEN/8, x13, x9, x10)

inst_5431:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16230*FLEN/8, x13, x9, x10)

inst_5432:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:16233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16233*FLEN/8, x13, x9, x10)

inst_5433:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:16236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16236*FLEN/8, x13, x9, x10)

inst_5434:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:16239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16239*FLEN/8, x13, x9, x10)

inst_5435:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:16242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16242*FLEN/8, x13, x9, x10)

inst_5436:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16245*FLEN/8, x13, x9, x10)

inst_5437:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16248*FLEN/8, x13, x9, x10)

inst_5438:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16251*FLEN/8, x13, x9, x10)

inst_5439:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:16254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16254*FLEN/8, x13, x9, x10)

inst_5440:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16257*FLEN/8, x13, x9, x10)

inst_5441:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16260*FLEN/8, x13, x9, x10)

inst_5442:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16263*FLEN/8, x13, x9, x10)

inst_5443:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16266*FLEN/8, x13, x9, x10)

inst_5444:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16269*FLEN/8, x13, x9, x10)

inst_5445:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16272*FLEN/8, x13, x9, x10)

inst_5446:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16275*FLEN/8, x13, x9, x10)

inst_5447:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16278*FLEN/8, x13, x9, x10)

inst_5448:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:16281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16281*FLEN/8, x13, x9, x10)

inst_5449:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:16284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16284*FLEN/8, x13, x9, x10)

inst_5450:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:16287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16287*FLEN/8, x13, x9, x10)

inst_5451:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:16290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16290*FLEN/8, x13, x9, x10)

inst_5452:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:16293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16293*FLEN/8, x13, x9, x10)

inst_5453:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16296*FLEN/8, x13, x9, x10)

inst_5454:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16299*FLEN/8, x13, x9, x10)

inst_5455:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16302*FLEN/8, x13, x9, x10)

inst_5456:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:16305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16305*FLEN/8, x13, x9, x10)

inst_5457:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:16308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16308*FLEN/8, x13, x9, x10)

inst_5458:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:16311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16311*FLEN/8, x13, x9, x10)

inst_5459:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:16314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16314*FLEN/8, x13, x9, x10)

inst_5460:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16317*FLEN/8, x13, x9, x10)

inst_5461:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16320*FLEN/8, x13, x9, x10)

inst_5462:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16323*FLEN/8, x13, x9, x10)

inst_5463:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:16326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16326*FLEN/8, x13, x9, x10)

inst_5464:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16329*FLEN/8, x13, x9, x10)

inst_5465:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16332*FLEN/8, x13, x9, x10)

inst_5466:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16335*FLEN/8, x13, x9, x10)

inst_5467:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16338*FLEN/8, x13, x9, x10)

inst_5468:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16341*FLEN/8, x13, x9, x10)

inst_5469:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16344*FLEN/8, x13, x9, x10)

inst_5470:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16347*FLEN/8, x13, x9, x10)

inst_5471:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16350*FLEN/8, x13, x9, x10)

inst_5472:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:16353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16353*FLEN/8, x13, x9, x10)

inst_5473:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:16356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16356*FLEN/8, x13, x9, x10)

inst_5474:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:16359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16359*FLEN/8, x13, x9, x10)

inst_5475:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:16362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16362*FLEN/8, x13, x9, x10)

inst_5476:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:16365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16365*FLEN/8, x13, x9, x10)

inst_5477:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16368*FLEN/8, x13, x9, x10)

inst_5478:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16371*FLEN/8, x13, x9, x10)

inst_5479:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16374*FLEN/8, x13, x9, x10)

inst_5480:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:16377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16377*FLEN/8, x13, x9, x10)

inst_5481:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:16380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16380*FLEN/8, x13, x9, x10)

inst_5482:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:16383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16383*FLEN/8, x13, x9, x10)

inst_5483:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:16386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16386*FLEN/8, x13, x9, x10)

inst_5484:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16389*FLEN/8, x13, x9, x10)

inst_5485:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16392*FLEN/8, x13, x9, x10)

inst_5486:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16395*FLEN/8, x13, x9, x10)

inst_5487:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:16398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16398*FLEN/8, x13, x9, x10)

inst_5488:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16401*FLEN/8, x13, x9, x10)

inst_5489:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16404*FLEN/8, x13, x9, x10)

inst_5490:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16407*FLEN/8, x13, x9, x10)

inst_5491:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16410*FLEN/8, x13, x9, x10)

inst_5492:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16413*FLEN/8, x13, x9, x10)

inst_5493:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16416*FLEN/8, x13, x9, x10)

inst_5494:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16419*FLEN/8, x13, x9, x10)

inst_5495:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16422*FLEN/8, x13, x9, x10)

inst_5496:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:16425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16425*FLEN/8, x13, x9, x10)

inst_5497:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:16428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16428*FLEN/8, x13, x9, x10)

inst_5498:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:16431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16431*FLEN/8, x13, x9, x10)

inst_5499:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:16434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16434*FLEN/8, x13, x9, x10)

inst_5500:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:16437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16437*FLEN/8, x13, x9, x10)

inst_5501:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16440*FLEN/8, x13, x9, x10)

inst_5502:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16443*FLEN/8, x13, x9, x10)

inst_5503:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16446*FLEN/8, x13, x9, x10)

inst_5504:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:16449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16449*FLEN/8, x13, x9, x10)

inst_5505:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:16452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16452*FLEN/8, x13, x9, x10)

inst_5506:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:16455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16455*FLEN/8, x13, x9, x10)

inst_5507:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:16458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16458*FLEN/8, x13, x9, x10)

inst_5508:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16461*FLEN/8, x13, x9, x10)

inst_5509:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16464*FLEN/8, x13, x9, x10)

inst_5510:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16467*FLEN/8, x13, x9, x10)

inst_5511:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:16470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16470*FLEN/8, x13, x9, x10)

inst_5512:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16473*FLEN/8, x13, x9, x10)

inst_5513:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16476*FLEN/8, x13, x9, x10)

inst_5514:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16479*FLEN/8, x13, x9, x10)

inst_5515:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16482*FLEN/8, x13, x9, x10)

inst_5516:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16485*FLEN/8, x13, x9, x10)

inst_5517:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16488*FLEN/8, x13, x9, x10)

inst_5518:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16491*FLEN/8, x13, x9, x10)

inst_5519:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16494*FLEN/8, x13, x9, x10)

inst_5520:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:16497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16497*FLEN/8, x13, x9, x10)

inst_5521:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:16500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16500*FLEN/8, x13, x9, x10)

inst_5522:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:16503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16503*FLEN/8, x13, x9, x10)

inst_5523:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:16506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16506*FLEN/8, x13, x9, x10)

inst_5524:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:16509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16509*FLEN/8, x13, x9, x10)

inst_5525:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16512*FLEN/8, x13, x9, x10)

inst_5526:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16515*FLEN/8, x13, x9, x10)

inst_5527:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16518*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_43)

inst_5528:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:16521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16521*FLEN/8, x13, x9, x10)

inst_5529:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:16524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16524*FLEN/8, x13, x9, x10)

inst_5530:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:16527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16527*FLEN/8, x13, x9, x10)

inst_5531:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:16530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16530*FLEN/8, x13, x9, x10)

inst_5532:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16533*FLEN/8, x13, x9, x10)

inst_5533:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16536*FLEN/8, x13, x9, x10)

inst_5534:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16539*FLEN/8, x13, x9, x10)

inst_5535:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:16542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16542*FLEN/8, x13, x9, x10)

inst_5536:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16545*FLEN/8, x13, x9, x10)

inst_5537:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16548*FLEN/8, x13, x9, x10)

inst_5538:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16551*FLEN/8, x13, x9, x10)

inst_5539:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16554*FLEN/8, x13, x9, x10)

inst_5540:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16557*FLEN/8, x13, x9, x10)

inst_5541:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16560*FLEN/8, x13, x9, x10)

inst_5542:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16563*FLEN/8, x13, x9, x10)

inst_5543:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16566*FLEN/8, x13, x9, x10)

inst_5544:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:16569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16569*FLEN/8, x13, x9, x10)

inst_5545:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:16572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16572*FLEN/8, x13, x9, x10)

inst_5546:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:16575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16575*FLEN/8, x13, x9, x10)

inst_5547:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:16578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16578*FLEN/8, x13, x9, x10)

inst_5548:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:16581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16581*FLEN/8, x13, x9, x10)

inst_5549:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16584*FLEN/8, x13, x9, x10)

inst_5550:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16587*FLEN/8, x13, x9, x10)

inst_5551:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16590*FLEN/8, x13, x9, x10)

inst_5552:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:16593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16593*FLEN/8, x13, x9, x10)

inst_5553:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:16596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16596*FLEN/8, x13, x9, x10)

inst_5554:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:16599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16599*FLEN/8, x13, x9, x10)

inst_5555:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:16602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16602*FLEN/8, x13, x9, x10)

inst_5556:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16605*FLEN/8, x13, x9, x10)

inst_5557:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16608*FLEN/8, x13, x9, x10)

inst_5558:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16611*FLEN/8, x13, x9, x10)

inst_5559:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:16614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16614*FLEN/8, x13, x9, x10)

inst_5560:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16617*FLEN/8, x13, x9, x10)

inst_5561:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16620*FLEN/8, x13, x9, x10)

inst_5562:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16623*FLEN/8, x13, x9, x10)

inst_5563:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16626*FLEN/8, x13, x9, x10)

inst_5564:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16629*FLEN/8, x13, x9, x10)

inst_5565:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16632*FLEN/8, x13, x9, x10)

inst_5566:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16635*FLEN/8, x13, x9, x10)

inst_5567:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16638*FLEN/8, x13, x9, x10)

inst_5568:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:16641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16641*FLEN/8, x13, x9, x10)

inst_5569:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:16644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16644*FLEN/8, x13, x9, x10)

inst_5570:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:16647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16647*FLEN/8, x13, x9, x10)

inst_5571:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:16650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16650*FLEN/8, x13, x9, x10)

inst_5572:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:16653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16653*FLEN/8, x13, x9, x10)

inst_5573:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16656*FLEN/8, x13, x9, x10)

inst_5574:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16659*FLEN/8, x13, x9, x10)

inst_5575:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16662*FLEN/8, x13, x9, x10)

inst_5576:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:16665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16665*FLEN/8, x13, x9, x10)

inst_5577:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:16668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16668*FLEN/8, x13, x9, x10)

inst_5578:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:16671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16671*FLEN/8, x13, x9, x10)

inst_5579:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:16674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16674*FLEN/8, x13, x9, x10)

inst_5580:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16677*FLEN/8, x13, x9, x10)

inst_5581:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16680*FLEN/8, x13, x9, x10)

inst_5582:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16683*FLEN/8, x13, x9, x10)

inst_5583:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:16686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16686*FLEN/8, x13, x9, x10)

inst_5584:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16689*FLEN/8, x13, x9, x10)

inst_5585:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16692*FLEN/8, x13, x9, x10)

inst_5586:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16695*FLEN/8, x13, x9, x10)

inst_5587:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16698*FLEN/8, x13, x9, x10)

inst_5588:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16701*FLEN/8, x13, x9, x10)

inst_5589:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16704*FLEN/8, x13, x9, x10)

inst_5590:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16707*FLEN/8, x13, x9, x10)

inst_5591:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16710*FLEN/8, x13, x9, x10)

inst_5592:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:16713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16713*FLEN/8, x13, x9, x10)

inst_5593:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:16716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16716*FLEN/8, x13, x9, x10)

inst_5594:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:16719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16719*FLEN/8, x13, x9, x10)

inst_5595:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:16722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16722*FLEN/8, x13, x9, x10)

inst_5596:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:16725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16725*FLEN/8, x13, x9, x10)

inst_5597:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16728*FLEN/8, x13, x9, x10)

inst_5598:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16731*FLEN/8, x13, x9, x10)

inst_5599:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16734*FLEN/8, x13, x9, x10)

inst_5600:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:16737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16737*FLEN/8, x13, x9, x10)

inst_5601:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:16740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16740*FLEN/8, x13, x9, x10)

inst_5602:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:16743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16743*FLEN/8, x13, x9, x10)

inst_5603:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:16746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16746*FLEN/8, x13, x9, x10)

inst_5604:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16749*FLEN/8, x13, x9, x10)

inst_5605:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16752*FLEN/8, x13, x9, x10)

inst_5606:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16755*FLEN/8, x13, x9, x10)

inst_5607:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:16758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16758*FLEN/8, x13, x9, x10)

inst_5608:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16761*FLEN/8, x13, x9, x10)

inst_5609:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16764*FLEN/8, x13, x9, x10)

inst_5610:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16767*FLEN/8, x13, x9, x10)

inst_5611:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16770*FLEN/8, x13, x9, x10)

inst_5612:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16773*FLEN/8, x13, x9, x10)

inst_5613:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16776*FLEN/8, x13, x9, x10)

inst_5614:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16779*FLEN/8, x13, x9, x10)

inst_5615:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16782*FLEN/8, x13, x9, x10)

inst_5616:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:16785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16785*FLEN/8, x13, x9, x10)

inst_5617:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:16788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16788*FLEN/8, x13, x9, x10)

inst_5618:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:16791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16791*FLEN/8, x13, x9, x10)

inst_5619:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:16794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16794*FLEN/8, x13, x9, x10)

inst_5620:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:16797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16797*FLEN/8, x13, x9, x10)

inst_5621:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16800*FLEN/8, x13, x9, x10)

inst_5622:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16803*FLEN/8, x13, x9, x10)

inst_5623:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16806*FLEN/8, x13, x9, x10)

inst_5624:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:16809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16809*FLEN/8, x13, x9, x10)

inst_5625:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:16812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16812*FLEN/8, x13, x9, x10)

inst_5626:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:16815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16815*FLEN/8, x13, x9, x10)

inst_5627:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:16818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16818*FLEN/8, x13, x9, x10)

inst_5628:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16821*FLEN/8, x13, x9, x10)

inst_5629:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16824*FLEN/8, x13, x9, x10)

inst_5630:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16827*FLEN/8, x13, x9, x10)

inst_5631:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:16830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16830*FLEN/8, x13, x9, x10)

inst_5632:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16833*FLEN/8, x13, x9, x10)

inst_5633:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16836*FLEN/8, x13, x9, x10)

inst_5634:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16839*FLEN/8, x13, x9, x10)

inst_5635:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16842*FLEN/8, x13, x9, x10)

inst_5636:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16845*FLEN/8, x13, x9, x10)

inst_5637:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16848*FLEN/8, x13, x9, x10)

inst_5638:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16851*FLEN/8, x13, x9, x10)

inst_5639:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16854*FLEN/8, x13, x9, x10)

inst_5640:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:16857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16857*FLEN/8, x13, x9, x10)

inst_5641:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:16860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16860*FLEN/8, x13, x9, x10)

inst_5642:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:16863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16863*FLEN/8, x13, x9, x10)

inst_5643:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:16866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16866*FLEN/8, x13, x9, x10)

inst_5644:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:16869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16869*FLEN/8, x13, x9, x10)

inst_5645:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16872*FLEN/8, x13, x9, x10)

inst_5646:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16875*FLEN/8, x13, x9, x10)

inst_5647:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16878*FLEN/8, x13, x9, x10)

inst_5648:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:16881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16881*FLEN/8, x13, x9, x10)

inst_5649:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:16884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16884*FLEN/8, x13, x9, x10)

inst_5650:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:16887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16887*FLEN/8, x13, x9, x10)

inst_5651:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:16890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16890*FLEN/8, x13, x9, x10)

inst_5652:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16893*FLEN/8, x13, x9, x10)

inst_5653:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16896*FLEN/8, x13, x9, x10)

inst_5654:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16899*FLEN/8, x13, x9, x10)

inst_5655:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:16902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16902*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_44)

inst_5656:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16905*FLEN/8, x13, x9, x10)

inst_5657:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16908*FLEN/8, x13, x9, x10)

inst_5658:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16911*FLEN/8, x13, x9, x10)

inst_5659:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16914*FLEN/8, x13, x9, x10)

inst_5660:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16917*FLEN/8, x13, x9, x10)

inst_5661:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16920*FLEN/8, x13, x9, x10)

inst_5662:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16923*FLEN/8, x13, x9, x10)

inst_5663:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16926*FLEN/8, x13, x9, x10)

inst_5664:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:16929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16929*FLEN/8, x13, x9, x10)

inst_5665:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:16932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16932*FLEN/8, x13, x9, x10)

inst_5666:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:16935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16935*FLEN/8, x13, x9, x10)

inst_5667:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:16938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16938*FLEN/8, x13, x9, x10)

inst_5668:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:16941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16941*FLEN/8, x13, x9, x10)

inst_5669:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:16944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16944*FLEN/8, x13, x9, x10)

inst_5670:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:16947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16947*FLEN/8, x13, x9, x10)

inst_5671:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:16950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16950*FLEN/8, x13, x9, x10)

inst_5672:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:16953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16953*FLEN/8, x13, x9, x10)

inst_5673:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:16956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16956*FLEN/8, x13, x9, x10)

inst_5674:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:16959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16959*FLEN/8, x13, x9, x10)

inst_5675:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:16962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16962*FLEN/8, x13, x9, x10)

inst_5676:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:16965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16965*FLEN/8, x13, x9, x10)

inst_5677:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:16968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16968*FLEN/8, x13, x9, x10)

inst_5678:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:16971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16971*FLEN/8, x13, x9, x10)

inst_5679:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:16974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16974*FLEN/8, x13, x9, x10)

inst_5680:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:16977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16977*FLEN/8, x13, x9, x10)

inst_5681:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:16980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16980*FLEN/8, x13, x9, x10)

inst_5682:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:16983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16983*FLEN/8, x13, x9, x10)

inst_5683:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:16986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16986*FLEN/8, x13, x9, x10)

inst_5684:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:16989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16989*FLEN/8, x13, x9, x10)

inst_5685:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:16992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16992*FLEN/8, x13, x9, x10)

inst_5686:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:16995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16995*FLEN/8, x13, x9, x10)

inst_5687:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:16998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 16998*FLEN/8, x13, x9, x10)

inst_5688:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:17001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17001*FLEN/8, x13, x9, x10)

inst_5689:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:17004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17004*FLEN/8, x13, x9, x10)

inst_5690:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:17007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17007*FLEN/8, x13, x9, x10)

inst_5691:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:17010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17010*FLEN/8, x13, x9, x10)

inst_5692:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:17013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17013*FLEN/8, x13, x9, x10)

inst_5693:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17016*FLEN/8, x13, x9, x10)

inst_5694:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17019*FLEN/8, x13, x9, x10)

inst_5695:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17022*FLEN/8, x13, x9, x10)

inst_5696:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:17025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17025*FLEN/8, x13, x9, x10)

inst_5697:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:17028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17028*FLEN/8, x13, x9, x10)

inst_5698:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:17031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17031*FLEN/8, x13, x9, x10)

inst_5699:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:17034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17034*FLEN/8, x13, x9, x10)

inst_5700:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17037*FLEN/8, x13, x9, x10)

inst_5701:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17040*FLEN/8, x13, x9, x10)

inst_5702:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17043*FLEN/8, x13, x9, x10)

inst_5703:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:17046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17046*FLEN/8, x13, x9, x10)

inst_5704:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17049*FLEN/8, x13, x9, x10)

inst_5705:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17052*FLEN/8, x13, x9, x10)

inst_5706:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17055*FLEN/8, x13, x9, x10)

inst_5707:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17058*FLEN/8, x13, x9, x10)

inst_5708:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17061*FLEN/8, x13, x9, x10)

inst_5709:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17064*FLEN/8, x13, x9, x10)

inst_5710:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17067*FLEN/8, x13, x9, x10)

inst_5711:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17070*FLEN/8, x13, x9, x10)

inst_5712:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:17073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17073*FLEN/8, x13, x9, x10)

inst_5713:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:17076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17076*FLEN/8, x13, x9, x10)

inst_5714:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:17079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17079*FLEN/8, x13, x9, x10)

inst_5715:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:17082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17082*FLEN/8, x13, x9, x10)

inst_5716:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:17085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17085*FLEN/8, x13, x9, x10)

inst_5717:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17088*FLEN/8, x13, x9, x10)

inst_5718:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17091*FLEN/8, x13, x9, x10)

inst_5719:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17094*FLEN/8, x13, x9, x10)

inst_5720:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:17097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17097*FLEN/8, x13, x9, x10)

inst_5721:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:17100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17100*FLEN/8, x13, x9, x10)

inst_5722:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:17103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17103*FLEN/8, x13, x9, x10)

inst_5723:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:17106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17106*FLEN/8, x13, x9, x10)

inst_5724:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17109*FLEN/8, x13, x9, x10)

inst_5725:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17112*FLEN/8, x13, x9, x10)

inst_5726:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17115*FLEN/8, x13, x9, x10)

inst_5727:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:17118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17118*FLEN/8, x13, x9, x10)

inst_5728:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17121*FLEN/8, x13, x9, x10)

inst_5729:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17124*FLEN/8, x13, x9, x10)

inst_5730:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17127*FLEN/8, x13, x9, x10)

inst_5731:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17130*FLEN/8, x13, x9, x10)

inst_5732:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17133*FLEN/8, x13, x9, x10)

inst_5733:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17136*FLEN/8, x13, x9, x10)

inst_5734:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17139*FLEN/8, x13, x9, x10)

inst_5735:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17142*FLEN/8, x13, x9, x10)

inst_5736:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:17145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17145*FLEN/8, x13, x9, x10)

inst_5737:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:17148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17148*FLEN/8, x13, x9, x10)

inst_5738:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:17151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17151*FLEN/8, x13, x9, x10)

inst_5739:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:17154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17154*FLEN/8, x13, x9, x10)

inst_5740:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:17157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17157*FLEN/8, x13, x9, x10)

inst_5741:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17160*FLEN/8, x13, x9, x10)

inst_5742:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17163*FLEN/8, x13, x9, x10)

inst_5743:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17166*FLEN/8, x13, x9, x10)

inst_5744:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:17169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17169*FLEN/8, x13, x9, x10)

inst_5745:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:17172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17172*FLEN/8, x13, x9, x10)

inst_5746:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:17175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17175*FLEN/8, x13, x9, x10)

inst_5747:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:17178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17178*FLEN/8, x13, x9, x10)

inst_5748:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17181*FLEN/8, x13, x9, x10)

inst_5749:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17184*FLEN/8, x13, x9, x10)

inst_5750:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17187*FLEN/8, x13, x9, x10)

inst_5751:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:17190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17190*FLEN/8, x13, x9, x10)

inst_5752:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17193*FLEN/8, x13, x9, x10)

inst_5753:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17196*FLEN/8, x13, x9, x10)

inst_5754:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17199*FLEN/8, x13, x9, x10)

inst_5755:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17202*FLEN/8, x13, x9, x10)

inst_5756:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17205*FLEN/8, x13, x9, x10)

inst_5757:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17208*FLEN/8, x13, x9, x10)

inst_5758:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17211*FLEN/8, x13, x9, x10)

inst_5759:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80800000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17214*FLEN/8, x13, x9, x10)

inst_5760:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:17217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17217*FLEN/8, x13, x9, x10)

inst_5761:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:17220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17220*FLEN/8, x13, x9, x10)

inst_5762:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:17223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17223*FLEN/8, x13, x9, x10)

inst_5763:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:17226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17226*FLEN/8, x13, x9, x10)

inst_5764:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:17229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17229*FLEN/8, x13, x9, x10)

inst_5765:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17232*FLEN/8, x13, x9, x10)

inst_5766:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17235*FLEN/8, x13, x9, x10)

inst_5767:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17238*FLEN/8, x13, x9, x10)

inst_5768:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:17241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17241*FLEN/8, x13, x9, x10)

inst_5769:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:17244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17244*FLEN/8, x13, x9, x10)

inst_5770:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:17247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17247*FLEN/8, x13, x9, x10)

inst_5771:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:17250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17250*FLEN/8, x13, x9, x10)

inst_5772:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17253*FLEN/8, x13, x9, x10)

inst_5773:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17256*FLEN/8, x13, x9, x10)

inst_5774:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17259*FLEN/8, x13, x9, x10)

inst_5775:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:17262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17262*FLEN/8, x13, x9, x10)

inst_5776:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17265*FLEN/8, x13, x9, x10)

inst_5777:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17268*FLEN/8, x13, x9, x10)

inst_5778:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17271*FLEN/8, x13, x9, x10)

inst_5779:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17274*FLEN/8, x13, x9, x10)

inst_5780:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17277*FLEN/8, x13, x9, x10)

inst_5781:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17280*FLEN/8, x13, x9, x10)

inst_5782:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17283*FLEN/8, x13, x9, x10)

inst_5783:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17286*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_45)

inst_5784:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:17289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17289*FLEN/8, x13, x9, x10)

inst_5785:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:17292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17292*FLEN/8, x13, x9, x10)

inst_5786:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:17295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17295*FLEN/8, x13, x9, x10)

inst_5787:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:17298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17298*FLEN/8, x13, x9, x10)

inst_5788:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:17301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17301*FLEN/8, x13, x9, x10)

inst_5789:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17304*FLEN/8, x13, x9, x10)

inst_5790:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17307*FLEN/8, x13, x9, x10)

inst_5791:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17310*FLEN/8, x13, x9, x10)

inst_5792:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:17313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17313*FLEN/8, x13, x9, x10)

inst_5793:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:17316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17316*FLEN/8, x13, x9, x10)

inst_5794:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:17319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17319*FLEN/8, x13, x9, x10)

inst_5795:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:17322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17322*FLEN/8, x13, x9, x10)

inst_5796:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17325*FLEN/8, x13, x9, x10)

inst_5797:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17328*FLEN/8, x13, x9, x10)

inst_5798:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17331*FLEN/8, x13, x9, x10)

inst_5799:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:17334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17334*FLEN/8, x13, x9, x10)

inst_5800:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17337*FLEN/8, x13, x9, x10)

inst_5801:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17340*FLEN/8, x13, x9, x10)

inst_5802:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17343*FLEN/8, x13, x9, x10)

inst_5803:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17346*FLEN/8, x13, x9, x10)

inst_5804:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17349*FLEN/8, x13, x9, x10)

inst_5805:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17352*FLEN/8, x13, x9, x10)

inst_5806:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17355*FLEN/8, x13, x9, x10)

inst_5807:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17358*FLEN/8, x13, x9, x10)

inst_5808:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:17361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17361*FLEN/8, x13, x9, x10)

inst_5809:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:17364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17364*FLEN/8, x13, x9, x10)

inst_5810:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:17367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17367*FLEN/8, x13, x9, x10)

inst_5811:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:17370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17370*FLEN/8, x13, x9, x10)

inst_5812:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:17373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17373*FLEN/8, x13, x9, x10)

inst_5813:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17376*FLEN/8, x13, x9, x10)

inst_5814:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17379*FLEN/8, x13, x9, x10)

inst_5815:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17382*FLEN/8, x13, x9, x10)

inst_5816:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:17385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17385*FLEN/8, x13, x9, x10)

inst_5817:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:17388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17388*FLEN/8, x13, x9, x10)

inst_5818:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:17391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17391*FLEN/8, x13, x9, x10)

inst_5819:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:17394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17394*FLEN/8, x13, x9, x10)

inst_5820:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17397*FLEN/8, x13, x9, x10)

inst_5821:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17400*FLEN/8, x13, x9, x10)

inst_5822:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17403*FLEN/8, x13, x9, x10)

inst_5823:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:17406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17406*FLEN/8, x13, x9, x10)

inst_5824:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17409*FLEN/8, x13, x9, x10)

inst_5825:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17412*FLEN/8, x13, x9, x10)

inst_5826:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17415*FLEN/8, x13, x9, x10)

inst_5827:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17418*FLEN/8, x13, x9, x10)

inst_5828:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17421*FLEN/8, x13, x9, x10)

inst_5829:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17424*FLEN/8, x13, x9, x10)

inst_5830:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17427*FLEN/8, x13, x9, x10)

inst_5831:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17430*FLEN/8, x13, x9, x10)

inst_5832:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:17433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17433*FLEN/8, x13, x9, x10)

inst_5833:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:17436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17436*FLEN/8, x13, x9, x10)

inst_5834:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:17439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17439*FLEN/8, x13, x9, x10)

inst_5835:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:17442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17442*FLEN/8, x13, x9, x10)

inst_5836:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:17445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17445*FLEN/8, x13, x9, x10)

inst_5837:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17448*FLEN/8, x13, x9, x10)

inst_5838:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17451*FLEN/8, x13, x9, x10)

inst_5839:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17454*FLEN/8, x13, x9, x10)

inst_5840:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:17457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17457*FLEN/8, x13, x9, x10)

inst_5841:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:17460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17460*FLEN/8, x13, x9, x10)

inst_5842:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:17463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17463*FLEN/8, x13, x9, x10)

inst_5843:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:17466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17466*FLEN/8, x13, x9, x10)

inst_5844:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17469*FLEN/8, x13, x9, x10)

inst_5845:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17472*FLEN/8, x13, x9, x10)

inst_5846:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17475*FLEN/8, x13, x9, x10)

inst_5847:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:17478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17478*FLEN/8, x13, x9, x10)

inst_5848:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17481*FLEN/8, x13, x9, x10)

inst_5849:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17484*FLEN/8, x13, x9, x10)

inst_5850:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17487*FLEN/8, x13, x9, x10)

inst_5851:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17490*FLEN/8, x13, x9, x10)

inst_5852:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17493*FLEN/8, x13, x9, x10)

inst_5853:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17496*FLEN/8, x13, x9, x10)

inst_5854:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17499*FLEN/8, x13, x9, x10)

inst_5855:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17502*FLEN/8, x13, x9, x10)

inst_5856:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:17505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17505*FLEN/8, x13, x9, x10)

inst_5857:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:17508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17508*FLEN/8, x13, x9, x10)

inst_5858:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:17511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17511*FLEN/8, x13, x9, x10)

inst_5859:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:17514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17514*FLEN/8, x13, x9, x10)

inst_5860:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:17517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17517*FLEN/8, x13, x9, x10)

inst_5861:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17520*FLEN/8, x13, x9, x10)

inst_5862:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17523*FLEN/8, x13, x9, x10)

inst_5863:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17526*FLEN/8, x13, x9, x10)

inst_5864:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:17529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17529*FLEN/8, x13, x9, x10)

inst_5865:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:17532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17532*FLEN/8, x13, x9, x10)

inst_5866:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:17535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17535*FLEN/8, x13, x9, x10)

inst_5867:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:17538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17538*FLEN/8, x13, x9, x10)

inst_5868:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17541*FLEN/8, x13, x9, x10)

inst_5869:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17544*FLEN/8, x13, x9, x10)

inst_5870:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17547*FLEN/8, x13, x9, x10)

inst_5871:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:17550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17550*FLEN/8, x13, x9, x10)

inst_5872:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17553*FLEN/8, x13, x9, x10)

inst_5873:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17556*FLEN/8, x13, x9, x10)

inst_5874:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17559*FLEN/8, x13, x9, x10)

inst_5875:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17562*FLEN/8, x13, x9, x10)

inst_5876:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17565*FLEN/8, x13, x9, x10)

inst_5877:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17568*FLEN/8, x13, x9, x10)

inst_5878:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17571*FLEN/8, x13, x9, x10)

inst_5879:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17574*FLEN/8, x13, x9, x10)

inst_5880:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:17577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17577*FLEN/8, x13, x9, x10)

inst_5881:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:17580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17580*FLEN/8, x13, x9, x10)

inst_5882:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:17583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17583*FLEN/8, x13, x9, x10)

inst_5883:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:17586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17586*FLEN/8, x13, x9, x10)

inst_5884:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:17589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17589*FLEN/8, x13, x9, x10)

inst_5885:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17592*FLEN/8, x13, x9, x10)

inst_5886:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17595*FLEN/8, x13, x9, x10)

inst_5887:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17598*FLEN/8, x13, x9, x10)

inst_5888:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:17601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17601*FLEN/8, x13, x9, x10)

inst_5889:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:17604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17604*FLEN/8, x13, x9, x10)

inst_5890:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:17607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17607*FLEN/8, x13, x9, x10)

inst_5891:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:17610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17610*FLEN/8, x13, x9, x10)

inst_5892:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17613*FLEN/8, x13, x9, x10)

inst_5893:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17616*FLEN/8, x13, x9, x10)

inst_5894:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17619*FLEN/8, x13, x9, x10)

inst_5895:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:17622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17622*FLEN/8, x13, x9, x10)

inst_5896:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17625*FLEN/8, x13, x9, x10)

inst_5897:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17628*FLEN/8, x13, x9, x10)

inst_5898:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17631*FLEN/8, x13, x9, x10)

inst_5899:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17634*FLEN/8, x13, x9, x10)

inst_5900:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17637*FLEN/8, x13, x9, x10)

inst_5901:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17640*FLEN/8, x13, x9, x10)

inst_5902:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17643*FLEN/8, x13, x9, x10)

inst_5903:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17646*FLEN/8, x13, x9, x10)

inst_5904:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:17649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17649*FLEN/8, x13, x9, x10)

inst_5905:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:17652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17652*FLEN/8, x13, x9, x10)

inst_5906:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:17655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17655*FLEN/8, x13, x9, x10)

inst_5907:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:17658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17658*FLEN/8, x13, x9, x10)

inst_5908:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:17661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17661*FLEN/8, x13, x9, x10)

inst_5909:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17664*FLEN/8, x13, x9, x10)

inst_5910:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17667*FLEN/8, x13, x9, x10)

inst_5911:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17670*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_46)

inst_5912:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:17673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17673*FLEN/8, x13, x9, x10)

inst_5913:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:17676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17676*FLEN/8, x13, x9, x10)

inst_5914:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:17679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17679*FLEN/8, x13, x9, x10)

inst_5915:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:17682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17682*FLEN/8, x13, x9, x10)

inst_5916:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17685*FLEN/8, x13, x9, x10)

inst_5917:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17688*FLEN/8, x13, x9, x10)

inst_5918:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17691*FLEN/8, x13, x9, x10)

inst_5919:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:17694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17694*FLEN/8, x13, x9, x10)

inst_5920:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17697*FLEN/8, x13, x9, x10)

inst_5921:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17700*FLEN/8, x13, x9, x10)

inst_5922:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17703*FLEN/8, x13, x9, x10)

inst_5923:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17706*FLEN/8, x13, x9, x10)

inst_5924:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17709*FLEN/8, x13, x9, x10)

inst_5925:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17712*FLEN/8, x13, x9, x10)

inst_5926:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17715*FLEN/8, x13, x9, x10)

inst_5927:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17718*FLEN/8, x13, x9, x10)

inst_5928:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:17721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17721*FLEN/8, x13, x9, x10)

inst_5929:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:17724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17724*FLEN/8, x13, x9, x10)

inst_5930:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:17727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17727*FLEN/8, x13, x9, x10)

inst_5931:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:17730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17730*FLEN/8, x13, x9, x10)

inst_5932:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:17733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17733*FLEN/8, x13, x9, x10)

inst_5933:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17736*FLEN/8, x13, x9, x10)

inst_5934:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17739*FLEN/8, x13, x9, x10)

inst_5935:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17742*FLEN/8, x13, x9, x10)

inst_5936:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:17745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17745*FLEN/8, x13, x9, x10)

inst_5937:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:17748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17748*FLEN/8, x13, x9, x10)

inst_5938:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:17751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17751*FLEN/8, x13, x9, x10)

inst_5939:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:17754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17754*FLEN/8, x13, x9, x10)

inst_5940:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17757*FLEN/8, x13, x9, x10)

inst_5941:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17760*FLEN/8, x13, x9, x10)

inst_5942:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17763*FLEN/8, x13, x9, x10)

inst_5943:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:17766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17766*FLEN/8, x13, x9, x10)

inst_5944:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17769*FLEN/8, x13, x9, x10)

inst_5945:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17772*FLEN/8, x13, x9, x10)

inst_5946:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17775*FLEN/8, x13, x9, x10)

inst_5947:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17778*FLEN/8, x13, x9, x10)

inst_5948:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17781*FLEN/8, x13, x9, x10)

inst_5949:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17784*FLEN/8, x13, x9, x10)

inst_5950:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17787*FLEN/8, x13, x9, x10)

inst_5951:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17790*FLEN/8, x13, x9, x10)

inst_5952:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:17793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17793*FLEN/8, x13, x9, x10)

inst_5953:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:17796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17796*FLEN/8, x13, x9, x10)

inst_5954:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:17799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17799*FLEN/8, x13, x9, x10)

inst_5955:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:17802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17802*FLEN/8, x13, x9, x10)

inst_5956:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:17805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17805*FLEN/8, x13, x9, x10)

inst_5957:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17808*FLEN/8, x13, x9, x10)

inst_5958:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17811*FLEN/8, x13, x9, x10)

inst_5959:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17814*FLEN/8, x13, x9, x10)

inst_5960:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:17817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17817*FLEN/8, x13, x9, x10)

inst_5961:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:17820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17820*FLEN/8, x13, x9, x10)

inst_5962:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:17823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17823*FLEN/8, x13, x9, x10)

inst_5963:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:17826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17826*FLEN/8, x13, x9, x10)

inst_5964:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17829*FLEN/8, x13, x9, x10)

inst_5965:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17832*FLEN/8, x13, x9, x10)

inst_5966:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17835*FLEN/8, x13, x9, x10)

inst_5967:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:17838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17838*FLEN/8, x13, x9, x10)

inst_5968:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17841*FLEN/8, x13, x9, x10)

inst_5969:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17844*FLEN/8, x13, x9, x10)

inst_5970:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17847*FLEN/8, x13, x9, x10)

inst_5971:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17850*FLEN/8, x13, x9, x10)

inst_5972:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17853*FLEN/8, x13, x9, x10)

inst_5973:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17856*FLEN/8, x13, x9, x10)

inst_5974:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17859*FLEN/8, x13, x9, x10)

inst_5975:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17862*FLEN/8, x13, x9, x10)

inst_5976:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:17865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17865*FLEN/8, x13, x9, x10)

inst_5977:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:17868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17868*FLEN/8, x13, x9, x10)

inst_5978:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:17871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17871*FLEN/8, x13, x9, x10)

inst_5979:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:17874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17874*FLEN/8, x13, x9, x10)

inst_5980:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:17877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17877*FLEN/8, x13, x9, x10)

inst_5981:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17880*FLEN/8, x13, x9, x10)

inst_5982:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17883*FLEN/8, x13, x9, x10)

inst_5983:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17886*FLEN/8, x13, x9, x10)

inst_5984:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:17889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17889*FLEN/8, x13, x9, x10)

inst_5985:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:17892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17892*FLEN/8, x13, x9, x10)

inst_5986:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:17895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17895*FLEN/8, x13, x9, x10)

inst_5987:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:17898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17898*FLEN/8, x13, x9, x10)

inst_5988:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17901*FLEN/8, x13, x9, x10)

inst_5989:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17904*FLEN/8, x13, x9, x10)

inst_5990:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17907*FLEN/8, x13, x9, x10)

inst_5991:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:17910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17910*FLEN/8, x13, x9, x10)

inst_5992:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17913*FLEN/8, x13, x9, x10)

inst_5993:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17916*FLEN/8, x13, x9, x10)

inst_5994:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17919*FLEN/8, x13, x9, x10)

inst_5995:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17922*FLEN/8, x13, x9, x10)

inst_5996:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17925*FLEN/8, x13, x9, x10)

inst_5997:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:17928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17928*FLEN/8, x13, x9, x10)

inst_5998:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:17931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17931*FLEN/8, x13, x9, x10)

inst_5999:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:17934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17934*FLEN/8, x13, x9, x10)

inst_6000:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:17937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17937*FLEN/8, x13, x9, x10)

inst_6001:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:17940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17940*FLEN/8, x13, x9, x10)

inst_6002:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:17943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17943*FLEN/8, x13, x9, x10)

inst_6003:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:17946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17946*FLEN/8, x13, x9, x10)

inst_6004:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:17949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17949*FLEN/8, x13, x9, x10)

inst_6005:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:17952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17952*FLEN/8, x13, x9, x10)

inst_6006:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:17955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17955*FLEN/8, x13, x9, x10)

inst_6007:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:17958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17958*FLEN/8, x13, x9, x10)

inst_6008:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:17961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17961*FLEN/8, x13, x9, x10)

inst_6009:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:17964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17964*FLEN/8, x13, x9, x10)

inst_6010:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:17967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17967*FLEN/8, x13, x9, x10)

inst_6011:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:17970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17970*FLEN/8, x13, x9, x10)

inst_6012:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:17973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17973*FLEN/8, x13, x9, x10)

inst_6013:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:17976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17976*FLEN/8, x13, x9, x10)

inst_6014:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:17979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17979*FLEN/8, x13, x9, x10)

inst_6015:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:17982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17982*FLEN/8, x13, x9, x10)

inst_6016:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:17985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17985*FLEN/8, x13, x9, x10)

inst_6017:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:17988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17988*FLEN/8, x13, x9, x10)

inst_6018:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:17991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17991*FLEN/8, x13, x9, x10)

inst_6019:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:17994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17994*FLEN/8, x13, x9, x10)

inst_6020:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:17997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 17997*FLEN/8, x13, x9, x10)

inst_6021:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18000*FLEN/8, x13, x9, x10)

inst_6022:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18003*FLEN/8, x13, x9, x10)

inst_6023:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18006*FLEN/8, x13, x9, x10)

inst_6024:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:18009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18009*FLEN/8, x13, x9, x10)

inst_6025:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:18012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18012*FLEN/8, x13, x9, x10)

inst_6026:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:18015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18015*FLEN/8, x13, x9, x10)

inst_6027:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:18018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18018*FLEN/8, x13, x9, x10)

inst_6028:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:18021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18021*FLEN/8, x13, x9, x10)

inst_6029:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18024*FLEN/8, x13, x9, x10)

inst_6030:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18027*FLEN/8, x13, x9, x10)

inst_6031:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18030*FLEN/8, x13, x9, x10)

inst_6032:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:18033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18033*FLEN/8, x13, x9, x10)

inst_6033:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:18036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18036*FLEN/8, x13, x9, x10)

inst_6034:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:18039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18039*FLEN/8, x13, x9, x10)

inst_6035:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:18042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18042*FLEN/8, x13, x9, x10)

inst_6036:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18045*FLEN/8, x13, x9, x10)

inst_6037:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18048*FLEN/8, x13, x9, x10)

inst_6038:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18051*FLEN/8, x13, x9, x10)

inst_6039:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:18054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18054*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_47)

inst_6040:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18057*FLEN/8, x13, x9, x10)

inst_6041:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18060*FLEN/8, x13, x9, x10)

inst_6042:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18063*FLEN/8, x13, x9, x10)

inst_6043:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18066*FLEN/8, x13, x9, x10)

inst_6044:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18069*FLEN/8, x13, x9, x10)

inst_6045:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18072*FLEN/8, x13, x9, x10)

inst_6046:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18075*FLEN/8, x13, x9, x10)

inst_6047:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18078*FLEN/8, x13, x9, x10)

inst_6048:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:18081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18081*FLEN/8, x13, x9, x10)

inst_6049:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:18084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18084*FLEN/8, x13, x9, x10)

inst_6050:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:18087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18087*FLEN/8, x13, x9, x10)

inst_6051:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:18090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18090*FLEN/8, x13, x9, x10)

inst_6052:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:18093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18093*FLEN/8, x13, x9, x10)

inst_6053:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18096*FLEN/8, x13, x9, x10)

inst_6054:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18099*FLEN/8, x13, x9, x10)

inst_6055:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18102*FLEN/8, x13, x9, x10)

inst_6056:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:18105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18105*FLEN/8, x13, x9, x10)

inst_6057:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:18108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18108*FLEN/8, x13, x9, x10)

inst_6058:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:18111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18111*FLEN/8, x13, x9, x10)

inst_6059:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:18114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18114*FLEN/8, x13, x9, x10)

inst_6060:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18117*FLEN/8, x13, x9, x10)

inst_6061:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18120*FLEN/8, x13, x9, x10)

inst_6062:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18123*FLEN/8, x13, x9, x10)

inst_6063:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:18126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18126*FLEN/8, x13, x9, x10)

inst_6064:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18129*FLEN/8, x13, x9, x10)

inst_6065:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18132*FLEN/8, x13, x9, x10)

inst_6066:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18135*FLEN/8, x13, x9, x10)

inst_6067:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18138*FLEN/8, x13, x9, x10)

inst_6068:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18141*FLEN/8, x13, x9, x10)

inst_6069:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18144*FLEN/8, x13, x9, x10)

inst_6070:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18147*FLEN/8, x13, x9, x10)

inst_6071:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18150*FLEN/8, x13, x9, x10)

inst_6072:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:18153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18153*FLEN/8, x13, x9, x10)

inst_6073:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:18156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18156*FLEN/8, x13, x9, x10)

inst_6074:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:18159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18159*FLEN/8, x13, x9, x10)

inst_6075:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:18162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18162*FLEN/8, x13, x9, x10)

inst_6076:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:18165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18165*FLEN/8, x13, x9, x10)

inst_6077:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18168*FLEN/8, x13, x9, x10)

inst_6078:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18171*FLEN/8, x13, x9, x10)

inst_6079:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18174*FLEN/8, x13, x9, x10)

inst_6080:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:18177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18177*FLEN/8, x13, x9, x10)

inst_6081:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:18180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18180*FLEN/8, x13, x9, x10)

inst_6082:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:18183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18183*FLEN/8, x13, x9, x10)

inst_6083:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:18186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18186*FLEN/8, x13, x9, x10)

inst_6084:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18189*FLEN/8, x13, x9, x10)

inst_6085:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18192*FLEN/8, x13, x9, x10)

inst_6086:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18195*FLEN/8, x13, x9, x10)

inst_6087:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:18198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18198*FLEN/8, x13, x9, x10)

inst_6088:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18201*FLEN/8, x13, x9, x10)

inst_6089:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18204*FLEN/8, x13, x9, x10)

inst_6090:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18207*FLEN/8, x13, x9, x10)

inst_6091:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18210*FLEN/8, x13, x9, x10)

inst_6092:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18213*FLEN/8, x13, x9, x10)

inst_6093:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18216*FLEN/8, x13, x9, x10)

inst_6094:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18219*FLEN/8, x13, x9, x10)

inst_6095:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18222*FLEN/8, x13, x9, x10)

inst_6096:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:18225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18225*FLEN/8, x13, x9, x10)

inst_6097:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:18228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18228*FLEN/8, x13, x9, x10)

inst_6098:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:18231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18231*FLEN/8, x13, x9, x10)

inst_6099:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18234*FLEN/8, x13, x9, x10)

inst_6100:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:18237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18237*FLEN/8, x13, x9, x10)

inst_6101:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18240*FLEN/8, x13, x9, x10)

inst_6102:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18243*FLEN/8, x13, x9, x10)

inst_6103:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18246*FLEN/8, x13, x9, x10)

inst_6104:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:18249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18249*FLEN/8, x13, x9, x10)

inst_6105:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:18252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18252*FLEN/8, x13, x9, x10)

inst_6106:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:18255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18255*FLEN/8, x13, x9, x10)

inst_6107:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:18258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18258*FLEN/8, x13, x9, x10)

inst_6108:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18261*FLEN/8, x13, x9, x10)

inst_6109:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18264*FLEN/8, x13, x9, x10)

inst_6110:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18267*FLEN/8, x13, x9, x10)

inst_6111:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:18270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18270*FLEN/8, x13, x9, x10)

inst_6112:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18273*FLEN/8, x13, x9, x10)

inst_6113:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18276*FLEN/8, x13, x9, x10)

inst_6114:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18279*FLEN/8, x13, x9, x10)

inst_6115:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18282*FLEN/8, x13, x9, x10)

inst_6116:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18285*FLEN/8, x13, x9, x10)

inst_6117:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18288*FLEN/8, x13, x9, x10)

inst_6118:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18291*FLEN/8, x13, x9, x10)

inst_6119:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18294*FLEN/8, x13, x9, x10)

inst_6120:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:18297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18297*FLEN/8, x13, x9, x10)

inst_6121:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:18300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18300*FLEN/8, x13, x9, x10)

inst_6122:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:18303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18303*FLEN/8, x13, x9, x10)

inst_6123:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18306*FLEN/8, x13, x9, x10)

inst_6124:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:18309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18309*FLEN/8, x13, x9, x10)

inst_6125:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18312*FLEN/8, x13, x9, x10)

inst_6126:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18315*FLEN/8, x13, x9, x10)

inst_6127:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18318*FLEN/8, x13, x9, x10)

inst_6128:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:18321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18321*FLEN/8, x13, x9, x10)

inst_6129:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:18324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18324*FLEN/8, x13, x9, x10)

inst_6130:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:18327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18327*FLEN/8, x13, x9, x10)

inst_6131:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:18330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18330*FLEN/8, x13, x9, x10)

inst_6132:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18333*FLEN/8, x13, x9, x10)

inst_6133:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18336*FLEN/8, x13, x9, x10)

inst_6134:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18339*FLEN/8, x13, x9, x10)

inst_6135:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:18342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18342*FLEN/8, x13, x9, x10)

inst_6136:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18345*FLEN/8, x13, x9, x10)

inst_6137:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18348*FLEN/8, x13, x9, x10)

inst_6138:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18351*FLEN/8, x13, x9, x10)

inst_6139:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18354*FLEN/8, x13, x9, x10)

inst_6140:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18357*FLEN/8, x13, x9, x10)

inst_6141:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18360*FLEN/8, x13, x9, x10)

inst_6142:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18363*FLEN/8, x13, x9, x10)

inst_6143:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18366*FLEN/8, x13, x9, x10)

inst_6144:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:18369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18369*FLEN/8, x13, x9, x10)

inst_6145:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:18372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18372*FLEN/8, x13, x9, x10)

inst_6146:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:18375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18375*FLEN/8, x13, x9, x10)

inst_6147:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18378*FLEN/8, x13, x9, x10)

inst_6148:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:18381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18381*FLEN/8, x13, x9, x10)

inst_6149:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18384*FLEN/8, x13, x9, x10)

inst_6150:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18387*FLEN/8, x13, x9, x10)

inst_6151:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18390*FLEN/8, x13, x9, x10)

inst_6152:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:18393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18393*FLEN/8, x13, x9, x10)

inst_6153:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:18396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18396*FLEN/8, x13, x9, x10)

inst_6154:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:18399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18399*FLEN/8, x13, x9, x10)

inst_6155:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:18402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18402*FLEN/8, x13, x9, x10)

inst_6156:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18405*FLEN/8, x13, x9, x10)

inst_6157:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18408*FLEN/8, x13, x9, x10)

inst_6158:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18411*FLEN/8, x13, x9, x10)

inst_6159:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:18414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18414*FLEN/8, x13, x9, x10)

inst_6160:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18417*FLEN/8, x13, x9, x10)

inst_6161:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18420*FLEN/8, x13, x9, x10)

inst_6162:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18423*FLEN/8, x13, x9, x10)

inst_6163:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18426*FLEN/8, x13, x9, x10)

inst_6164:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18429*FLEN/8, x13, x9, x10)

inst_6165:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18432*FLEN/8, x13, x9, x10)

inst_6166:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18435*FLEN/8, x13, x9, x10)

inst_6167:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18438*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_48)

inst_6168:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:18441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18441*FLEN/8, x13, x9, x10)

inst_6169:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:18444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18444*FLEN/8, x13, x9, x10)

inst_6170:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:18447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18447*FLEN/8, x13, x9, x10)

inst_6171:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18450*FLEN/8, x13, x9, x10)

inst_6172:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:18453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18453*FLEN/8, x13, x9, x10)

inst_6173:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18456*FLEN/8, x13, x9, x10)

inst_6174:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18459*FLEN/8, x13, x9, x10)

inst_6175:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18462*FLEN/8, x13, x9, x10)

inst_6176:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:18465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18465*FLEN/8, x13, x9, x10)

inst_6177:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:18468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18468*FLEN/8, x13, x9, x10)

inst_6178:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:18471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18471*FLEN/8, x13, x9, x10)

inst_6179:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:18474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18474*FLEN/8, x13, x9, x10)

inst_6180:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18477*FLEN/8, x13, x9, x10)

inst_6181:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18480*FLEN/8, x13, x9, x10)

inst_6182:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18483*FLEN/8, x13, x9, x10)

inst_6183:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:18486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18486*FLEN/8, x13, x9, x10)

inst_6184:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18489*FLEN/8, x13, x9, x10)

inst_6185:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18492*FLEN/8, x13, x9, x10)

inst_6186:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18495*FLEN/8, x13, x9, x10)

inst_6187:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18498*FLEN/8, x13, x9, x10)

inst_6188:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18501*FLEN/8, x13, x9, x10)

inst_6189:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18504*FLEN/8, x13, x9, x10)

inst_6190:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18507*FLEN/8, x13, x9, x10)

inst_6191:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18510*FLEN/8, x13, x9, x10)

inst_6192:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:18513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18513*FLEN/8, x13, x9, x10)

inst_6193:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:18516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18516*FLEN/8, x13, x9, x10)

inst_6194:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:18519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18519*FLEN/8, x13, x9, x10)

inst_6195:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:18522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18522*FLEN/8, x13, x9, x10)

inst_6196:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:18525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18525*FLEN/8, x13, x9, x10)

inst_6197:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18528*FLEN/8, x13, x9, x10)

inst_6198:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18531*FLEN/8, x13, x9, x10)

inst_6199:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18534*FLEN/8, x13, x9, x10)

inst_6200:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:18537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18537*FLEN/8, x13, x9, x10)

inst_6201:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:18540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18540*FLEN/8, x13, x9, x10)

inst_6202:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:18543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18543*FLEN/8, x13, x9, x10)

inst_6203:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:18546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18546*FLEN/8, x13, x9, x10)

inst_6204:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18549*FLEN/8, x13, x9, x10)

inst_6205:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18552*FLEN/8, x13, x9, x10)

inst_6206:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18555*FLEN/8, x13, x9, x10)

inst_6207:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:18558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18558*FLEN/8, x13, x9, x10)

inst_6208:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18561*FLEN/8, x13, x9, x10)

inst_6209:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18564*FLEN/8, x13, x9, x10)

inst_6210:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18567*FLEN/8, x13, x9, x10)

inst_6211:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18570*FLEN/8, x13, x9, x10)

inst_6212:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18573*FLEN/8, x13, x9, x10)

inst_6213:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18576*FLEN/8, x13, x9, x10)

inst_6214:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18579*FLEN/8, x13, x9, x10)

inst_6215:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18582*FLEN/8, x13, x9, x10)

inst_6216:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:18585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18585*FLEN/8, x13, x9, x10)

inst_6217:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:18588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18588*FLEN/8, x13, x9, x10)

inst_6218:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:18591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18591*FLEN/8, x13, x9, x10)

inst_6219:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:18594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18594*FLEN/8, x13, x9, x10)

inst_6220:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:18597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18597*FLEN/8, x13, x9, x10)

inst_6221:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18600*FLEN/8, x13, x9, x10)

inst_6222:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18603*FLEN/8, x13, x9, x10)

inst_6223:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18606*FLEN/8, x13, x9, x10)

inst_6224:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:18609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18609*FLEN/8, x13, x9, x10)

inst_6225:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:18612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18612*FLEN/8, x13, x9, x10)

inst_6226:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:18615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18615*FLEN/8, x13, x9, x10)

inst_6227:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:18618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18618*FLEN/8, x13, x9, x10)

inst_6228:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18621*FLEN/8, x13, x9, x10)

inst_6229:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18624*FLEN/8, x13, x9, x10)

inst_6230:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18627*FLEN/8, x13, x9, x10)

inst_6231:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:18630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18630*FLEN/8, x13, x9, x10)

inst_6232:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18633*FLEN/8, x13, x9, x10)

inst_6233:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18636*FLEN/8, x13, x9, x10)

inst_6234:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18639*FLEN/8, x13, x9, x10)

inst_6235:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18642*FLEN/8, x13, x9, x10)

inst_6236:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18645*FLEN/8, x13, x9, x10)

inst_6237:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18648*FLEN/8, x13, x9, x10)

inst_6238:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18651*FLEN/8, x13, x9, x10)

inst_6239:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18654*FLEN/8, x13, x9, x10)

inst_6240:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:18657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18657*FLEN/8, x13, x9, x10)

inst_6241:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:18660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18660*FLEN/8, x13, x9, x10)

inst_6242:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:18663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18663*FLEN/8, x13, x9, x10)

inst_6243:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:18666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18666*FLEN/8, x13, x9, x10)

inst_6244:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:18669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18669*FLEN/8, x13, x9, x10)

inst_6245:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18672*FLEN/8, x13, x9, x10)

inst_6246:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18675*FLEN/8, x13, x9, x10)

inst_6247:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18678*FLEN/8, x13, x9, x10)

inst_6248:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:18681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18681*FLEN/8, x13, x9, x10)

inst_6249:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:18684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18684*FLEN/8, x13, x9, x10)

inst_6250:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:18687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18687*FLEN/8, x13, x9, x10)

inst_6251:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:18690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18690*FLEN/8, x13, x9, x10)

inst_6252:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18693*FLEN/8, x13, x9, x10)

inst_6253:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18696*FLEN/8, x13, x9, x10)

inst_6254:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18699*FLEN/8, x13, x9, x10)

inst_6255:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:18702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18702*FLEN/8, x13, x9, x10)

inst_6256:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18705*FLEN/8, x13, x9, x10)

inst_6257:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18708*FLEN/8, x13, x9, x10)

inst_6258:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18711*FLEN/8, x13, x9, x10)

inst_6259:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18714*FLEN/8, x13, x9, x10)

inst_6260:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18717*FLEN/8, x13, x9, x10)

inst_6261:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18720*FLEN/8, x13, x9, x10)

inst_6262:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18723*FLEN/8, x13, x9, x10)

inst_6263:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18726*FLEN/8, x13, x9, x10)

inst_6264:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:18729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18729*FLEN/8, x13, x9, x10)

inst_6265:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:18732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18732*FLEN/8, x13, x9, x10)

inst_6266:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:18735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18735*FLEN/8, x13, x9, x10)

inst_6267:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:18738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18738*FLEN/8, x13, x9, x10)

inst_6268:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:18741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18741*FLEN/8, x13, x9, x10)

inst_6269:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18744*FLEN/8, x13, x9, x10)

inst_6270:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18747*FLEN/8, x13, x9, x10)

inst_6271:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18750*FLEN/8, x13, x9, x10)

inst_6272:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:18753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18753*FLEN/8, x13, x9, x10)

inst_6273:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:18756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18756*FLEN/8, x13, x9, x10)

inst_6274:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:18759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18759*FLEN/8, x13, x9, x10)

inst_6275:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:18762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18762*FLEN/8, x13, x9, x10)

inst_6276:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18765*FLEN/8, x13, x9, x10)

inst_6277:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18768*FLEN/8, x13, x9, x10)

inst_6278:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18771*FLEN/8, x13, x9, x10)

inst_6279:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:18774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18774*FLEN/8, x13, x9, x10)

inst_6280:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18777*FLEN/8, x13, x9, x10)

inst_6281:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18780*FLEN/8, x13, x9, x10)

inst_6282:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18783*FLEN/8, x13, x9, x10)

inst_6283:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18786*FLEN/8, x13, x9, x10)

inst_6284:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18789*FLEN/8, x13, x9, x10)

inst_6285:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18792*FLEN/8, x13, x9, x10)

inst_6286:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18795*FLEN/8, x13, x9, x10)

inst_6287:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18798*FLEN/8, x13, x9, x10)

inst_6288:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:18801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18801*FLEN/8, x13, x9, x10)

inst_6289:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:18804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18804*FLEN/8, x13, x9, x10)

inst_6290:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:18807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18807*FLEN/8, x13, x9, x10)

inst_6291:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18810*FLEN/8, x13, x9, x10)

inst_6292:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:18813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18813*FLEN/8, x13, x9, x10)

inst_6293:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18816*FLEN/8, x13, x9, x10)

inst_6294:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18819*FLEN/8, x13, x9, x10)

inst_6295:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18822*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_49)

inst_6296:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:18825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18825*FLEN/8, x13, x9, x10)

inst_6297:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:18828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18828*FLEN/8, x13, x9, x10)

inst_6298:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:18831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18831*FLEN/8, x13, x9, x10)

inst_6299:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:18834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18834*FLEN/8, x13, x9, x10)

inst_6300:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18837*FLEN/8, x13, x9, x10)

inst_6301:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18840*FLEN/8, x13, x9, x10)

inst_6302:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18843*FLEN/8, x13, x9, x10)

inst_6303:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:18846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18846*FLEN/8, x13, x9, x10)

inst_6304:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18849*FLEN/8, x13, x9, x10)

inst_6305:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18852*FLEN/8, x13, x9, x10)

inst_6306:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18855*FLEN/8, x13, x9, x10)

inst_6307:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18858*FLEN/8, x13, x9, x10)

inst_6308:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18861*FLEN/8, x13, x9, x10)

inst_6309:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18864*FLEN/8, x13, x9, x10)

inst_6310:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18867*FLEN/8, x13, x9, x10)

inst_6311:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18870*FLEN/8, x13, x9, x10)

inst_6312:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:18873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18873*FLEN/8, x13, x9, x10)

inst_6313:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:18876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18876*FLEN/8, x13, x9, x10)

inst_6314:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:18879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18879*FLEN/8, x13, x9, x10)

inst_6315:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:18882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18882*FLEN/8, x13, x9, x10)

inst_6316:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:18885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18885*FLEN/8, x13, x9, x10)

inst_6317:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18888*FLEN/8, x13, x9, x10)

inst_6318:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18891*FLEN/8, x13, x9, x10)

inst_6319:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18894*FLEN/8, x13, x9, x10)

inst_6320:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:18897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18897*FLEN/8, x13, x9, x10)

inst_6321:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:18900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18900*FLEN/8, x13, x9, x10)

inst_6322:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:18903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18903*FLEN/8, x13, x9, x10)

inst_6323:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:18906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18906*FLEN/8, x13, x9, x10)

inst_6324:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18909*FLEN/8, x13, x9, x10)

inst_6325:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18912*FLEN/8, x13, x9, x10)

inst_6326:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18915*FLEN/8, x13, x9, x10)

inst_6327:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:18918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18918*FLEN/8, x13, x9, x10)

inst_6328:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18921*FLEN/8, x13, x9, x10)

inst_6329:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18924*FLEN/8, x13, x9, x10)

inst_6330:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18927*FLEN/8, x13, x9, x10)

inst_6331:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:18930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18930*FLEN/8, x13, x9, x10)

inst_6332:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:18933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18933*FLEN/8, x13, x9, x10)

inst_6333:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:18936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18936*FLEN/8, x13, x9, x10)

inst_6334:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:18939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18939*FLEN/8, x13, x9, x10)

inst_6335:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x800001; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:18942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18942*FLEN/8, x13, x9, x10)

inst_6336:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:18945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18945*FLEN/8, x13, x9, x10)

inst_6337:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:18948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18948*FLEN/8, x13, x9, x10)

inst_6338:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:18951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18951*FLEN/8, x13, x9, x10)

inst_6339:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:18954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18954*FLEN/8, x13, x9, x10)

inst_6340:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:18957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18957*FLEN/8, x13, x9, x10)

inst_6341:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:18960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18960*FLEN/8, x13, x9, x10)

inst_6342:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:18963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18963*FLEN/8, x13, x9, x10)

inst_6343:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:18966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18966*FLEN/8, x13, x9, x10)

inst_6344:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:18969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18969*FLEN/8, x13, x9, x10)

inst_6345:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:18972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18972*FLEN/8, x13, x9, x10)

inst_6346:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:18975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18975*FLEN/8, x13, x9, x10)

inst_6347:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:18978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18978*FLEN/8, x13, x9, x10)

inst_6348:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:18981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18981*FLEN/8, x13, x9, x10)

inst_6349:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:18984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18984*FLEN/8, x13, x9, x10)

inst_6350:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:18987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18987*FLEN/8, x13, x9, x10)

inst_6351:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:18990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18990*FLEN/8, x13, x9, x10)

inst_6352:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:18993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18993*FLEN/8, x13, x9, x10)

inst_6353:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:18996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18996*FLEN/8, x13, x9, x10)

inst_6354:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:18999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 18999*FLEN/8, x13, x9, x10)

inst_6355:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19002*FLEN/8, x13, x9, x10)

inst_6356:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19005*FLEN/8, x13, x9, x10)

inst_6357:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19008*FLEN/8, x13, x9, x10)

inst_6358:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19011*FLEN/8, x13, x9, x10)

inst_6359:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19014*FLEN/8, x13, x9, x10)

inst_6360:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:19017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19017*FLEN/8, x13, x9, x10)

inst_6361:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:19020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19020*FLEN/8, x13, x9, x10)

inst_6362:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:19023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19023*FLEN/8, x13, x9, x10)

inst_6363:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:19026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19026*FLEN/8, x13, x9, x10)

inst_6364:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:19029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19029*FLEN/8, x13, x9, x10)

inst_6365:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19032*FLEN/8, x13, x9, x10)

inst_6366:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19035*FLEN/8, x13, x9, x10)

inst_6367:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19038*FLEN/8, x13, x9, x10)

inst_6368:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:19041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19041*FLEN/8, x13, x9, x10)

inst_6369:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:19044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19044*FLEN/8, x13, x9, x10)

inst_6370:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:19047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19047*FLEN/8, x13, x9, x10)

inst_6371:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:19050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19050*FLEN/8, x13, x9, x10)

inst_6372:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19053*FLEN/8, x13, x9, x10)

inst_6373:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19056*FLEN/8, x13, x9, x10)

inst_6374:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19059*FLEN/8, x13, x9, x10)

inst_6375:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:19062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19062*FLEN/8, x13, x9, x10)

inst_6376:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19065*FLEN/8, x13, x9, x10)

inst_6377:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19068*FLEN/8, x13, x9, x10)

inst_6378:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19071*FLEN/8, x13, x9, x10)

inst_6379:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19074*FLEN/8, x13, x9, x10)

inst_6380:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19077*FLEN/8, x13, x9, x10)

inst_6381:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19080*FLEN/8, x13, x9, x10)

inst_6382:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19083*FLEN/8, x13, x9, x10)

inst_6383:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19086*FLEN/8, x13, x9, x10)

inst_6384:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:19089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19089*FLEN/8, x13, x9, x10)

inst_6385:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:19092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19092*FLEN/8, x13, x9, x10)

inst_6386:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:19095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19095*FLEN/8, x13, x9, x10)

inst_6387:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:19098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19098*FLEN/8, x13, x9, x10)

inst_6388:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:19101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19101*FLEN/8, x13, x9, x10)

inst_6389:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19104*FLEN/8, x13, x9, x10)

inst_6390:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19107*FLEN/8, x13, x9, x10)

inst_6391:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19110*FLEN/8, x13, x9, x10)

inst_6392:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:19113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19113*FLEN/8, x13, x9, x10)

inst_6393:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:19116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19116*FLEN/8, x13, x9, x10)

inst_6394:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:19119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19119*FLEN/8, x13, x9, x10)

inst_6395:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:19122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19122*FLEN/8, x13, x9, x10)

inst_6396:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19125*FLEN/8, x13, x9, x10)

inst_6397:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19128*FLEN/8, x13, x9, x10)

inst_6398:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19131*FLEN/8, x13, x9, x10)

inst_6399:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:19134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19134*FLEN/8, x13, x9, x10)

inst_6400:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19137*FLEN/8, x13, x9, x10)

inst_6401:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19140*FLEN/8, x13, x9, x10)

inst_6402:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19143*FLEN/8, x13, x9, x10)

inst_6403:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19146*FLEN/8, x13, x9, x10)

inst_6404:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19149*FLEN/8, x13, x9, x10)

inst_6405:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19152*FLEN/8, x13, x9, x10)

inst_6406:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19155*FLEN/8, x13, x9, x10)

inst_6407:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19158*FLEN/8, x13, x9, x10)

inst_6408:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:19161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19161*FLEN/8, x13, x9, x10)

inst_6409:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:19164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19164*FLEN/8, x13, x9, x10)

inst_6410:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:19167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19167*FLEN/8, x13, x9, x10)

inst_6411:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:19170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19170*FLEN/8, x13, x9, x10)

inst_6412:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:19173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19173*FLEN/8, x13, x9, x10)

inst_6413:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19176*FLEN/8, x13, x9, x10)

inst_6414:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19179*FLEN/8, x13, x9, x10)

inst_6415:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19182*FLEN/8, x13, x9, x10)

inst_6416:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:19185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19185*FLEN/8, x13, x9, x10)

inst_6417:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:19188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19188*FLEN/8, x13, x9, x10)

inst_6418:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:19191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19191*FLEN/8, x13, x9, x10)

inst_6419:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:19194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19194*FLEN/8, x13, x9, x10)

inst_6420:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19197*FLEN/8, x13, x9, x10)

inst_6421:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19200*FLEN/8, x13, x9, x10)

inst_6422:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19203*FLEN/8, x13, x9, x10)

inst_6423:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:19206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19206*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_50)

inst_6424:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19209*FLEN/8, x13, x9, x10)

inst_6425:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19212*FLEN/8, x13, x9, x10)

inst_6426:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19215*FLEN/8, x13, x9, x10)

inst_6427:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19218*FLEN/8, x13, x9, x10)

inst_6428:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19221*FLEN/8, x13, x9, x10)

inst_6429:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19224*FLEN/8, x13, x9, x10)

inst_6430:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19227*FLEN/8, x13, x9, x10)

inst_6431:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19230*FLEN/8, x13, x9, x10)

inst_6432:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:19233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19233*FLEN/8, x13, x9, x10)

inst_6433:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:19236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19236*FLEN/8, x13, x9, x10)

inst_6434:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:19239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19239*FLEN/8, x13, x9, x10)

inst_6435:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:19242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19242*FLEN/8, x13, x9, x10)

inst_6436:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:19245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19245*FLEN/8, x13, x9, x10)

inst_6437:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19248*FLEN/8, x13, x9, x10)

inst_6438:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19251*FLEN/8, x13, x9, x10)

inst_6439:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19254*FLEN/8, x13, x9, x10)

inst_6440:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:19257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19257*FLEN/8, x13, x9, x10)

inst_6441:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:19260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19260*FLEN/8, x13, x9, x10)

inst_6442:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:19263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19263*FLEN/8, x13, x9, x10)

inst_6443:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:19266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19266*FLEN/8, x13, x9, x10)

inst_6444:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19269*FLEN/8, x13, x9, x10)

inst_6445:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19272*FLEN/8, x13, x9, x10)

inst_6446:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19275*FLEN/8, x13, x9, x10)

inst_6447:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:19278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19278*FLEN/8, x13, x9, x10)

inst_6448:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19281*FLEN/8, x13, x9, x10)

inst_6449:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19284*FLEN/8, x13, x9, x10)

inst_6450:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19287*FLEN/8, x13, x9, x10)

inst_6451:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19290*FLEN/8, x13, x9, x10)

inst_6452:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19293*FLEN/8, x13, x9, x10)

inst_6453:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19296*FLEN/8, x13, x9, x10)

inst_6454:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19299*FLEN/8, x13, x9, x10)

inst_6455:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19302*FLEN/8, x13, x9, x10)

inst_6456:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:19305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19305*FLEN/8, x13, x9, x10)

inst_6457:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:19308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19308*FLEN/8, x13, x9, x10)

inst_6458:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:19311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19311*FLEN/8, x13, x9, x10)

inst_6459:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:19314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19314*FLEN/8, x13, x9, x10)

inst_6460:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:19317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19317*FLEN/8, x13, x9, x10)

inst_6461:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19320*FLEN/8, x13, x9, x10)

inst_6462:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19323*FLEN/8, x13, x9, x10)

inst_6463:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19326*FLEN/8, x13, x9, x10)

inst_6464:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:19329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19329*FLEN/8, x13, x9, x10)

inst_6465:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:19332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19332*FLEN/8, x13, x9, x10)

inst_6466:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:19335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19335*FLEN/8, x13, x9, x10)

inst_6467:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:19338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19338*FLEN/8, x13, x9, x10)

inst_6468:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19341*FLEN/8, x13, x9, x10)

inst_6469:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19344*FLEN/8, x13, x9, x10)

inst_6470:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19347*FLEN/8, x13, x9, x10)

inst_6471:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:19350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19350*FLEN/8, x13, x9, x10)

inst_6472:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19353*FLEN/8, x13, x9, x10)

inst_6473:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19356*FLEN/8, x13, x9, x10)

inst_6474:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19359*FLEN/8, x13, x9, x10)

inst_6475:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19362*FLEN/8, x13, x9, x10)

inst_6476:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19365*FLEN/8, x13, x9, x10)

inst_6477:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19368*FLEN/8, x13, x9, x10)

inst_6478:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19371*FLEN/8, x13, x9, x10)

inst_6479:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19374*FLEN/8, x13, x9, x10)

inst_6480:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:19377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19377*FLEN/8, x13, x9, x10)

inst_6481:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:19380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19380*FLEN/8, x13, x9, x10)

inst_6482:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:19383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19383*FLEN/8, x13, x9, x10)

inst_6483:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:19386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19386*FLEN/8, x13, x9, x10)

inst_6484:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:19389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19389*FLEN/8, x13, x9, x10)

inst_6485:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19392*FLEN/8, x13, x9, x10)

inst_6486:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19395*FLEN/8, x13, x9, x10)

inst_6487:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19398*FLEN/8, x13, x9, x10)

inst_6488:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:19401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19401*FLEN/8, x13, x9, x10)

inst_6489:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:19404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19404*FLEN/8, x13, x9, x10)

inst_6490:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:19407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19407*FLEN/8, x13, x9, x10)

inst_6491:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:19410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19410*FLEN/8, x13, x9, x10)

inst_6492:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19413*FLEN/8, x13, x9, x10)

inst_6493:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19416*FLEN/8, x13, x9, x10)

inst_6494:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19419*FLEN/8, x13, x9, x10)

inst_6495:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:19422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19422*FLEN/8, x13, x9, x10)

inst_6496:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19425*FLEN/8, x13, x9, x10)

inst_6497:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19428*FLEN/8, x13, x9, x10)

inst_6498:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19431*FLEN/8, x13, x9, x10)

inst_6499:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19434*FLEN/8, x13, x9, x10)

inst_6500:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19437*FLEN/8, x13, x9, x10)

inst_6501:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19440*FLEN/8, x13, x9, x10)

inst_6502:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19443*FLEN/8, x13, x9, x10)

inst_6503:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19446*FLEN/8, x13, x9, x10)

inst_6504:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:19449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19449*FLEN/8, x13, x9, x10)

inst_6505:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:19452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19452*FLEN/8, x13, x9, x10)

inst_6506:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:19455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19455*FLEN/8, x13, x9, x10)

inst_6507:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:19458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19458*FLEN/8, x13, x9, x10)

inst_6508:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:19461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19461*FLEN/8, x13, x9, x10)

inst_6509:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19464*FLEN/8, x13, x9, x10)

inst_6510:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19467*FLEN/8, x13, x9, x10)

inst_6511:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19470*FLEN/8, x13, x9, x10)

inst_6512:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:19473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19473*FLEN/8, x13, x9, x10)

inst_6513:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:19476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19476*FLEN/8, x13, x9, x10)

inst_6514:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:19479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19479*FLEN/8, x13, x9, x10)

inst_6515:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:19482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19482*FLEN/8, x13, x9, x10)

inst_6516:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19485*FLEN/8, x13, x9, x10)

inst_6517:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19488*FLEN/8, x13, x9, x10)

inst_6518:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19491*FLEN/8, x13, x9, x10)

inst_6519:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:19494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19494*FLEN/8, x13, x9, x10)

inst_6520:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19497*FLEN/8, x13, x9, x10)

inst_6521:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19500*FLEN/8, x13, x9, x10)

inst_6522:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19503*FLEN/8, x13, x9, x10)

inst_6523:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19506*FLEN/8, x13, x9, x10)

inst_6524:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19509*FLEN/8, x13, x9, x10)

inst_6525:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19512*FLEN/8, x13, x9, x10)

inst_6526:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19515*FLEN/8, x13, x9, x10)

inst_6527:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19518*FLEN/8, x13, x9, x10)

inst_6528:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:19521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19521*FLEN/8, x13, x9, x10)

inst_6529:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:19524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19524*FLEN/8, x13, x9, x10)

inst_6530:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:19527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19527*FLEN/8, x13, x9, x10)

inst_6531:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:19530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19530*FLEN/8, x13, x9, x10)

inst_6532:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:19533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19533*FLEN/8, x13, x9, x10)

inst_6533:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19536*FLEN/8, x13, x9, x10)

inst_6534:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19539*FLEN/8, x13, x9, x10)

inst_6535:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19542*FLEN/8, x13, x9, x10)

inst_6536:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:19545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19545*FLEN/8, x13, x9, x10)

inst_6537:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:19548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19548*FLEN/8, x13, x9, x10)

inst_6538:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:19551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19551*FLEN/8, x13, x9, x10)

inst_6539:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:19554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19554*FLEN/8, x13, x9, x10)

inst_6540:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19557*FLEN/8, x13, x9, x10)

inst_6541:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19560*FLEN/8, x13, x9, x10)

inst_6542:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19563*FLEN/8, x13, x9, x10)

inst_6543:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:19566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19566*FLEN/8, x13, x9, x10)

inst_6544:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19569*FLEN/8, x13, x9, x10)

inst_6545:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19572*FLEN/8, x13, x9, x10)

inst_6546:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19575*FLEN/8, x13, x9, x10)

inst_6547:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19578*FLEN/8, x13, x9, x10)

inst_6548:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19581*FLEN/8, x13, x9, x10)

inst_6549:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19584*FLEN/8, x13, x9, x10)

inst_6550:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19587*FLEN/8, x13, x9, x10)

inst_6551:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19590*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_51)

inst_6552:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:19593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19593*FLEN/8, x13, x9, x10)

inst_6553:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:19596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19596*FLEN/8, x13, x9, x10)

inst_6554:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:19599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19599*FLEN/8, x13, x9, x10)

inst_6555:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:19602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19602*FLEN/8, x13, x9, x10)

inst_6556:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:19605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19605*FLEN/8, x13, x9, x10)

inst_6557:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19608*FLEN/8, x13, x9, x10)

inst_6558:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19611*FLEN/8, x13, x9, x10)

inst_6559:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19614*FLEN/8, x13, x9, x10)

inst_6560:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:19617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19617*FLEN/8, x13, x9, x10)

inst_6561:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:19620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19620*FLEN/8, x13, x9, x10)

inst_6562:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:19623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19623*FLEN/8, x13, x9, x10)

inst_6563:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:19626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19626*FLEN/8, x13, x9, x10)

inst_6564:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19629*FLEN/8, x13, x9, x10)

inst_6565:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19632*FLEN/8, x13, x9, x10)

inst_6566:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19635*FLEN/8, x13, x9, x10)

inst_6567:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:19638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19638*FLEN/8, x13, x9, x10)

inst_6568:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19641*FLEN/8, x13, x9, x10)

inst_6569:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19644*FLEN/8, x13, x9, x10)

inst_6570:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19647*FLEN/8, x13, x9, x10)

inst_6571:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19650*FLEN/8, x13, x9, x10)

inst_6572:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19653*FLEN/8, x13, x9, x10)

inst_6573:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19656*FLEN/8, x13, x9, x10)

inst_6574:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19659*FLEN/8, x13, x9, x10)

inst_6575:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19662*FLEN/8, x13, x9, x10)

inst_6576:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:19665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19665*FLEN/8, x13, x9, x10)

inst_6577:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:19668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19668*FLEN/8, x13, x9, x10)

inst_6578:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:19671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19671*FLEN/8, x13, x9, x10)

inst_6579:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:19674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19674*FLEN/8, x13, x9, x10)

inst_6580:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:19677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19677*FLEN/8, x13, x9, x10)

inst_6581:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19680*FLEN/8, x13, x9, x10)

inst_6582:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19683*FLEN/8, x13, x9, x10)

inst_6583:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19686*FLEN/8, x13, x9, x10)

inst_6584:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:19689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19689*FLEN/8, x13, x9, x10)

inst_6585:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:19692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19692*FLEN/8, x13, x9, x10)

inst_6586:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:19695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19695*FLEN/8, x13, x9, x10)

inst_6587:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:19698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19698*FLEN/8, x13, x9, x10)

inst_6588:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19701*FLEN/8, x13, x9, x10)

inst_6589:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19704*FLEN/8, x13, x9, x10)

inst_6590:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19707*FLEN/8, x13, x9, x10)

inst_6591:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:19710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19710*FLEN/8, x13, x9, x10)

inst_6592:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19713*FLEN/8, x13, x9, x10)

inst_6593:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19716*FLEN/8, x13, x9, x10)

inst_6594:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19719*FLEN/8, x13, x9, x10)

inst_6595:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19722*FLEN/8, x13, x9, x10)

inst_6596:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19725*FLEN/8, x13, x9, x10)

inst_6597:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19728*FLEN/8, x13, x9, x10)

inst_6598:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19731*FLEN/8, x13, x9, x10)

inst_6599:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19734*FLEN/8, x13, x9, x10)

inst_6600:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:19737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19737*FLEN/8, x13, x9, x10)

inst_6601:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:19740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19740*FLEN/8, x13, x9, x10)

inst_6602:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:19743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19743*FLEN/8, x13, x9, x10)

inst_6603:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:19746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19746*FLEN/8, x13, x9, x10)

inst_6604:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:19749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19749*FLEN/8, x13, x9, x10)

inst_6605:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19752*FLEN/8, x13, x9, x10)

inst_6606:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19755*FLEN/8, x13, x9, x10)

inst_6607:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19758*FLEN/8, x13, x9, x10)

inst_6608:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:19761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19761*FLEN/8, x13, x9, x10)

inst_6609:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:19764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19764*FLEN/8, x13, x9, x10)

inst_6610:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:19767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19767*FLEN/8, x13, x9, x10)

inst_6611:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:19770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19770*FLEN/8, x13, x9, x10)

inst_6612:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19773*FLEN/8, x13, x9, x10)

inst_6613:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19776*FLEN/8, x13, x9, x10)

inst_6614:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19779*FLEN/8, x13, x9, x10)

inst_6615:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:19782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19782*FLEN/8, x13, x9, x10)

inst_6616:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19785*FLEN/8, x13, x9, x10)

inst_6617:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19788*FLEN/8, x13, x9, x10)

inst_6618:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19791*FLEN/8, x13, x9, x10)

inst_6619:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19794*FLEN/8, x13, x9, x10)

inst_6620:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19797*FLEN/8, x13, x9, x10)

inst_6621:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19800*FLEN/8, x13, x9, x10)

inst_6622:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19803*FLEN/8, x13, x9, x10)

inst_6623:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19806*FLEN/8, x13, x9, x10)

inst_6624:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:19809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19809*FLEN/8, x13, x9, x10)

inst_6625:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:19812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19812*FLEN/8, x13, x9, x10)

inst_6626:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:19815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19815*FLEN/8, x13, x9, x10)

inst_6627:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:19818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19818*FLEN/8, x13, x9, x10)

inst_6628:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:19821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19821*FLEN/8, x13, x9, x10)

inst_6629:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19824*FLEN/8, x13, x9, x10)

inst_6630:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19827*FLEN/8, x13, x9, x10)

inst_6631:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19830*FLEN/8, x13, x9, x10)

inst_6632:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:19833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19833*FLEN/8, x13, x9, x10)

inst_6633:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:19836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19836*FLEN/8, x13, x9, x10)

inst_6634:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:19839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19839*FLEN/8, x13, x9, x10)

inst_6635:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:19842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19842*FLEN/8, x13, x9, x10)

inst_6636:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19845*FLEN/8, x13, x9, x10)

inst_6637:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19848*FLEN/8, x13, x9, x10)

inst_6638:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19851*FLEN/8, x13, x9, x10)

inst_6639:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:19854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19854*FLEN/8, x13, x9, x10)

inst_6640:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19857*FLEN/8, x13, x9, x10)

inst_6641:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19860*FLEN/8, x13, x9, x10)

inst_6642:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19863*FLEN/8, x13, x9, x10)

inst_6643:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19866*FLEN/8, x13, x9, x10)

inst_6644:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19869*FLEN/8, x13, x9, x10)

inst_6645:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19872*FLEN/8, x13, x9, x10)

inst_6646:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19875*FLEN/8, x13, x9, x10)

inst_6647:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19878*FLEN/8, x13, x9, x10)

inst_6648:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:19881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19881*FLEN/8, x13, x9, x10)

inst_6649:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:19884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19884*FLEN/8, x13, x9, x10)

inst_6650:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:19887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19887*FLEN/8, x13, x9, x10)

inst_6651:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:19890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19890*FLEN/8, x13, x9, x10)

inst_6652:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:19893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19893*FLEN/8, x13, x9, x10)

inst_6653:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19896*FLEN/8, x13, x9, x10)

inst_6654:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19899*FLEN/8, x13, x9, x10)

inst_6655:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19902*FLEN/8, x13, x9, x10)

inst_6656:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:19905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19905*FLEN/8, x13, x9, x10)

inst_6657:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:19908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19908*FLEN/8, x13, x9, x10)

inst_6658:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:19911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19911*FLEN/8, x13, x9, x10)

inst_6659:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:19914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19914*FLEN/8, x13, x9, x10)

inst_6660:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19917*FLEN/8, x13, x9, x10)

inst_6661:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19920*FLEN/8, x13, x9, x10)

inst_6662:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19923*FLEN/8, x13, x9, x10)

inst_6663:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:19926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19926*FLEN/8, x13, x9, x10)

inst_6664:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:19929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19929*FLEN/8, x13, x9, x10)

inst_6665:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:19932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19932*FLEN/8, x13, x9, x10)

inst_6666:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:19935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19935*FLEN/8, x13, x9, x10)

inst_6667:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:19938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19938*FLEN/8, x13, x9, x10)

inst_6668:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:19941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19941*FLEN/8, x13, x9, x10)

inst_6669:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:19944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19944*FLEN/8, x13, x9, x10)

inst_6670:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:19947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19947*FLEN/8, x13, x9, x10)

inst_6671:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:19950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19950*FLEN/8, x13, x9, x10)

inst_6672:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:19953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19953*FLEN/8, x13, x9, x10)

inst_6673:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:19956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19956*FLEN/8, x13, x9, x10)

inst_6674:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:19959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19959*FLEN/8, x13, x9, x10)

inst_6675:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:19962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19962*FLEN/8, x13, x9, x10)

inst_6676:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:19965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19965*FLEN/8, x13, x9, x10)

inst_6677:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:19968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19968*FLEN/8, x13, x9, x10)

inst_6678:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:19971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19971*FLEN/8, x13, x9, x10)

inst_6679:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:19974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19974*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_52)

inst_6680:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:19977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19977*FLEN/8, x13, x9, x10)

inst_6681:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:19980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19980*FLEN/8, x13, x9, x10)

inst_6682:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:19983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19983*FLEN/8, x13, x9, x10)

inst_6683:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:19986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19986*FLEN/8, x13, x9, x10)

inst_6684:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:19989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19989*FLEN/8, x13, x9, x10)

inst_6685:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:19992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19992*FLEN/8, x13, x9, x10)

inst_6686:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:19995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19995*FLEN/8, x13, x9, x10)

inst_6687:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:19998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 19998*FLEN/8, x13, x9, x10)

inst_6688:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20001*FLEN/8, x13, x9, x10)

inst_6689:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20004*FLEN/8, x13, x9, x10)

inst_6690:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20007*FLEN/8, x13, x9, x10)

inst_6691:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20010*FLEN/8, x13, x9, x10)

inst_6692:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20013*FLEN/8, x13, x9, x10)

inst_6693:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20016*FLEN/8, x13, x9, x10)

inst_6694:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20019*FLEN/8, x13, x9, x10)

inst_6695:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20022*FLEN/8, x13, x9, x10)

inst_6696:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:20025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20025*FLEN/8, x13, x9, x10)

inst_6697:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:20028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20028*FLEN/8, x13, x9, x10)

inst_6698:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:20031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20031*FLEN/8, x13, x9, x10)

inst_6699:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:20034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20034*FLEN/8, x13, x9, x10)

inst_6700:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:20037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20037*FLEN/8, x13, x9, x10)

inst_6701:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20040*FLEN/8, x13, x9, x10)

inst_6702:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20043*FLEN/8, x13, x9, x10)

inst_6703:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20046*FLEN/8, x13, x9, x10)

inst_6704:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:20049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20049*FLEN/8, x13, x9, x10)

inst_6705:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:20052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20052*FLEN/8, x13, x9, x10)

inst_6706:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:20055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20055*FLEN/8, x13, x9, x10)

inst_6707:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:20058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20058*FLEN/8, x13, x9, x10)

inst_6708:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20061*FLEN/8, x13, x9, x10)

inst_6709:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20064*FLEN/8, x13, x9, x10)

inst_6710:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20067*FLEN/8, x13, x9, x10)

inst_6711:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:20070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20070*FLEN/8, x13, x9, x10)

inst_6712:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20073*FLEN/8, x13, x9, x10)

inst_6713:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20076*FLEN/8, x13, x9, x10)

inst_6714:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20079*FLEN/8, x13, x9, x10)

inst_6715:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20082*FLEN/8, x13, x9, x10)

inst_6716:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20085*FLEN/8, x13, x9, x10)

inst_6717:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20088*FLEN/8, x13, x9, x10)

inst_6718:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20091*FLEN/8, x13, x9, x10)

inst_6719:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20094*FLEN/8, x13, x9, x10)

inst_6720:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:20097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20097*FLEN/8, x13, x9, x10)

inst_6721:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:20100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20100*FLEN/8, x13, x9, x10)

inst_6722:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:20103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20103*FLEN/8, x13, x9, x10)

inst_6723:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:20106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20106*FLEN/8, x13, x9, x10)

inst_6724:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:20109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20109*FLEN/8, x13, x9, x10)

inst_6725:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20112*FLEN/8, x13, x9, x10)

inst_6726:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20115*FLEN/8, x13, x9, x10)

inst_6727:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20118*FLEN/8, x13, x9, x10)

inst_6728:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:20121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20121*FLEN/8, x13, x9, x10)

inst_6729:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:20124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20124*FLEN/8, x13, x9, x10)

inst_6730:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:20127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20127*FLEN/8, x13, x9, x10)

inst_6731:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:20130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20130*FLEN/8, x13, x9, x10)

inst_6732:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20133*FLEN/8, x13, x9, x10)

inst_6733:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20136*FLEN/8, x13, x9, x10)

inst_6734:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20139*FLEN/8, x13, x9, x10)

inst_6735:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:20142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20142*FLEN/8, x13, x9, x10)

inst_6736:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20145*FLEN/8, x13, x9, x10)

inst_6737:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20148*FLEN/8, x13, x9, x10)

inst_6738:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20151*FLEN/8, x13, x9, x10)

inst_6739:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20154*FLEN/8, x13, x9, x10)

inst_6740:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20157*FLEN/8, x13, x9, x10)

inst_6741:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20160*FLEN/8, x13, x9, x10)

inst_6742:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20163*FLEN/8, x13, x9, x10)

inst_6743:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20166*FLEN/8, x13, x9, x10)

inst_6744:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:20169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20169*FLEN/8, x13, x9, x10)

inst_6745:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:20172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20172*FLEN/8, x13, x9, x10)

inst_6746:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:20175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20175*FLEN/8, x13, x9, x10)

inst_6747:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:20178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20178*FLEN/8, x13, x9, x10)

inst_6748:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:20181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20181*FLEN/8, x13, x9, x10)

inst_6749:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20184*FLEN/8, x13, x9, x10)

inst_6750:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20187*FLEN/8, x13, x9, x10)

inst_6751:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20190*FLEN/8, x13, x9, x10)

inst_6752:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:20193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20193*FLEN/8, x13, x9, x10)

inst_6753:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:20196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20196*FLEN/8, x13, x9, x10)

inst_6754:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:20199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20199*FLEN/8, x13, x9, x10)

inst_6755:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:20202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20202*FLEN/8, x13, x9, x10)

inst_6756:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20205*FLEN/8, x13, x9, x10)

inst_6757:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20208*FLEN/8, x13, x9, x10)

inst_6758:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20211*FLEN/8, x13, x9, x10)

inst_6759:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:20214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20214*FLEN/8, x13, x9, x10)

inst_6760:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20217*FLEN/8, x13, x9, x10)

inst_6761:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20220*FLEN/8, x13, x9, x10)

inst_6762:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20223*FLEN/8, x13, x9, x10)

inst_6763:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20226*FLEN/8, x13, x9, x10)

inst_6764:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20229*FLEN/8, x13, x9, x10)

inst_6765:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20232*FLEN/8, x13, x9, x10)

inst_6766:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20235*FLEN/8, x13, x9, x10)

inst_6767:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20238*FLEN/8, x13, x9, x10)

inst_6768:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:20241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20241*FLEN/8, x13, x9, x10)

inst_6769:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:20244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20244*FLEN/8, x13, x9, x10)

inst_6770:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:20247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20247*FLEN/8, x13, x9, x10)

inst_6771:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:20250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20250*FLEN/8, x13, x9, x10)

inst_6772:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:20253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20253*FLEN/8, x13, x9, x10)

inst_6773:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20256*FLEN/8, x13, x9, x10)

inst_6774:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20259*FLEN/8, x13, x9, x10)

inst_6775:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20262*FLEN/8, x13, x9, x10)

inst_6776:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:20265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20265*FLEN/8, x13, x9, x10)

inst_6777:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:20268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20268*FLEN/8, x13, x9, x10)

inst_6778:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:20271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20271*FLEN/8, x13, x9, x10)

inst_6779:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:20274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20274*FLEN/8, x13, x9, x10)

inst_6780:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20277*FLEN/8, x13, x9, x10)

inst_6781:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20280*FLEN/8, x13, x9, x10)

inst_6782:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20283*FLEN/8, x13, x9, x10)

inst_6783:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:20286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20286*FLEN/8, x13, x9, x10)

inst_6784:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20289*FLEN/8, x13, x9, x10)

inst_6785:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20292*FLEN/8, x13, x9, x10)

inst_6786:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20295*FLEN/8, x13, x9, x10)

inst_6787:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20298*FLEN/8, x13, x9, x10)

inst_6788:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20301*FLEN/8, x13, x9, x10)

inst_6789:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20304*FLEN/8, x13, x9, x10)

inst_6790:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20307*FLEN/8, x13, x9, x10)

inst_6791:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20310*FLEN/8, x13, x9, x10)

inst_6792:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:20313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20313*FLEN/8, x13, x9, x10)

inst_6793:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:20316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20316*FLEN/8, x13, x9, x10)

inst_6794:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:20319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20319*FLEN/8, x13, x9, x10)

inst_6795:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:20322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20322*FLEN/8, x13, x9, x10)

inst_6796:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:20325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20325*FLEN/8, x13, x9, x10)

inst_6797:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20328*FLEN/8, x13, x9, x10)

inst_6798:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20331*FLEN/8, x13, x9, x10)

inst_6799:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20334*FLEN/8, x13, x9, x10)

inst_6800:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:20337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20337*FLEN/8, x13, x9, x10)

inst_6801:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:20340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20340*FLEN/8, x13, x9, x10)

inst_6802:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:20343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20343*FLEN/8, x13, x9, x10)

inst_6803:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:20346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20346*FLEN/8, x13, x9, x10)

inst_6804:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20349*FLEN/8, x13, x9, x10)

inst_6805:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20352*FLEN/8, x13, x9, x10)

inst_6806:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20355*FLEN/8, x13, x9, x10)

inst_6807:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:20358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20358*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_53)

inst_6808:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20361*FLEN/8, x13, x9, x10)

inst_6809:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20364*FLEN/8, x13, x9, x10)

inst_6810:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20367*FLEN/8, x13, x9, x10)

inst_6811:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20370*FLEN/8, x13, x9, x10)

inst_6812:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20373*FLEN/8, x13, x9, x10)

inst_6813:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20376*FLEN/8, x13, x9, x10)

inst_6814:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20379*FLEN/8, x13, x9, x10)

inst_6815:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20382*FLEN/8, x13, x9, x10)

inst_6816:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:20385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20385*FLEN/8, x13, x9, x10)

inst_6817:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:20388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20388*FLEN/8, x13, x9, x10)

inst_6818:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:20391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20391*FLEN/8, x13, x9, x10)

inst_6819:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:20394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20394*FLEN/8, x13, x9, x10)

inst_6820:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:20397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20397*FLEN/8, x13, x9, x10)

inst_6821:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20400*FLEN/8, x13, x9, x10)

inst_6822:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20403*FLEN/8, x13, x9, x10)

inst_6823:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20406*FLEN/8, x13, x9, x10)

inst_6824:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:20409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20409*FLEN/8, x13, x9, x10)

inst_6825:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:20412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20412*FLEN/8, x13, x9, x10)

inst_6826:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:20415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20415*FLEN/8, x13, x9, x10)

inst_6827:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:20418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20418*FLEN/8, x13, x9, x10)

inst_6828:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20421*FLEN/8, x13, x9, x10)

inst_6829:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20424*FLEN/8, x13, x9, x10)

inst_6830:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20427*FLEN/8, x13, x9, x10)

inst_6831:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:20430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20430*FLEN/8, x13, x9, x10)

inst_6832:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20433*FLEN/8, x13, x9, x10)

inst_6833:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20436*FLEN/8, x13, x9, x10)

inst_6834:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20439*FLEN/8, x13, x9, x10)

inst_6835:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20442*FLEN/8, x13, x9, x10)

inst_6836:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20445*FLEN/8, x13, x9, x10)

inst_6837:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20448*FLEN/8, x13, x9, x10)

inst_6838:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20451*FLEN/8, x13, x9, x10)

inst_6839:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20454*FLEN/8, x13, x9, x10)

inst_6840:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:20457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20457*FLEN/8, x13, x9, x10)

inst_6841:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:20460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20460*FLEN/8, x13, x9, x10)

inst_6842:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:20463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20463*FLEN/8, x13, x9, x10)

inst_6843:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:20466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20466*FLEN/8, x13, x9, x10)

inst_6844:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:20469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20469*FLEN/8, x13, x9, x10)

inst_6845:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20472*FLEN/8, x13, x9, x10)

inst_6846:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20475*FLEN/8, x13, x9, x10)

inst_6847:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20478*FLEN/8, x13, x9, x10)

inst_6848:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:20481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20481*FLEN/8, x13, x9, x10)

inst_6849:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:20484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20484*FLEN/8, x13, x9, x10)

inst_6850:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:20487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20487*FLEN/8, x13, x9, x10)

inst_6851:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:20490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20490*FLEN/8, x13, x9, x10)

inst_6852:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20493*FLEN/8, x13, x9, x10)

inst_6853:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20496*FLEN/8, x13, x9, x10)

inst_6854:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20499*FLEN/8, x13, x9, x10)

inst_6855:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:20502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20502*FLEN/8, x13, x9, x10)

inst_6856:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20505*FLEN/8, x13, x9, x10)

inst_6857:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20508*FLEN/8, x13, x9, x10)

inst_6858:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20511*FLEN/8, x13, x9, x10)

inst_6859:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20514*FLEN/8, x13, x9, x10)

inst_6860:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20517*FLEN/8, x13, x9, x10)

inst_6861:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20520*FLEN/8, x13, x9, x10)

inst_6862:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20523*FLEN/8, x13, x9, x10)

inst_6863:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20526*FLEN/8, x13, x9, x10)

inst_6864:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:20529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20529*FLEN/8, x13, x9, x10)

inst_6865:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:20532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20532*FLEN/8, x13, x9, x10)

inst_6866:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:20535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20535*FLEN/8, x13, x9, x10)

inst_6867:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:20538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20538*FLEN/8, x13, x9, x10)

inst_6868:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:20541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20541*FLEN/8, x13, x9, x10)

inst_6869:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20544*FLEN/8, x13, x9, x10)

inst_6870:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20547*FLEN/8, x13, x9, x10)

inst_6871:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20550*FLEN/8, x13, x9, x10)

inst_6872:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:20553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20553*FLEN/8, x13, x9, x10)

inst_6873:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:20556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20556*FLEN/8, x13, x9, x10)

inst_6874:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:20559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20559*FLEN/8, x13, x9, x10)

inst_6875:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:20562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20562*FLEN/8, x13, x9, x10)

inst_6876:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20565*FLEN/8, x13, x9, x10)

inst_6877:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20568*FLEN/8, x13, x9, x10)

inst_6878:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20571*FLEN/8, x13, x9, x10)

inst_6879:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:20574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20574*FLEN/8, x13, x9, x10)

inst_6880:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20577*FLEN/8, x13, x9, x10)

inst_6881:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20580*FLEN/8, x13, x9, x10)

inst_6882:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20583*FLEN/8, x13, x9, x10)

inst_6883:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20586*FLEN/8, x13, x9, x10)

inst_6884:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20589*FLEN/8, x13, x9, x10)

inst_6885:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20592*FLEN/8, x13, x9, x10)

inst_6886:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20595*FLEN/8, x13, x9, x10)

inst_6887:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20598*FLEN/8, x13, x9, x10)

inst_6888:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:20601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20601*FLEN/8, x13, x9, x10)

inst_6889:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:20604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20604*FLEN/8, x13, x9, x10)

inst_6890:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:20607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20607*FLEN/8, x13, x9, x10)

inst_6891:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:20610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20610*FLEN/8, x13, x9, x10)

inst_6892:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:20613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20613*FLEN/8, x13, x9, x10)

inst_6893:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20616*FLEN/8, x13, x9, x10)

inst_6894:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20619*FLEN/8, x13, x9, x10)

inst_6895:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20622*FLEN/8, x13, x9, x10)

inst_6896:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:20625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20625*FLEN/8, x13, x9, x10)

inst_6897:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:20628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20628*FLEN/8, x13, x9, x10)

inst_6898:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:20631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20631*FLEN/8, x13, x9, x10)

inst_6899:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:20634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20634*FLEN/8, x13, x9, x10)

inst_6900:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20637*FLEN/8, x13, x9, x10)

inst_6901:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20640*FLEN/8, x13, x9, x10)

inst_6902:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20643*FLEN/8, x13, x9, x10)

inst_6903:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:20646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20646*FLEN/8, x13, x9, x10)

inst_6904:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20649*FLEN/8, x13, x9, x10)

inst_6905:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20652*FLEN/8, x13, x9, x10)

inst_6906:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20655*FLEN/8, x13, x9, x10)

inst_6907:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20658*FLEN/8, x13, x9, x10)

inst_6908:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20661*FLEN/8, x13, x9, x10)

inst_6909:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20664*FLEN/8, x13, x9, x10)

inst_6910:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20667*FLEN/8, x13, x9, x10)

inst_6911:
// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x80855555; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20670*FLEN/8, x13, x9, x10)

inst_6912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:20673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20673*FLEN/8, x13, x9, x10)

inst_6913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:20676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20676*FLEN/8, x13, x9, x10)

inst_6914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:20679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20679*FLEN/8, x13, x9, x10)

inst_6915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:20682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20682*FLEN/8, x13, x9, x10)

inst_6916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:20685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20685*FLEN/8, x13, x9, x10)

inst_6917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20688*FLEN/8, x13, x9, x10)

inst_6918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20691*FLEN/8, x13, x9, x10)

inst_6919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20694*FLEN/8, x13, x9, x10)

inst_6920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:20697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20697*FLEN/8, x13, x9, x10)

inst_6921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:20700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20700*FLEN/8, x13, x9, x10)

inst_6922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:20703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20703*FLEN/8, x13, x9, x10)

inst_6923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:20706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20706*FLEN/8, x13, x9, x10)

inst_6924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20709*FLEN/8, x13, x9, x10)

inst_6925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20712*FLEN/8, x13, x9, x10)

inst_6926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20715*FLEN/8, x13, x9, x10)

inst_6927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:20718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20718*FLEN/8, x13, x9, x10)

inst_6928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20721*FLEN/8, x13, x9, x10)

inst_6929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20724*FLEN/8, x13, x9, x10)

inst_6930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20727*FLEN/8, x13, x9, x10)

inst_6931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20730*FLEN/8, x13, x9, x10)

inst_6932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20733*FLEN/8, x13, x9, x10)

inst_6933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20736*FLEN/8, x13, x9, x10)

inst_6934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20739*FLEN/8, x13, x9, x10)

inst_6935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20742*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_54)

inst_6936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:20745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20745*FLEN/8, x13, x9, x10)

inst_6937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:20748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20748*FLEN/8, x13, x9, x10)

inst_6938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:20751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20751*FLEN/8, x13, x9, x10)

inst_6939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:20754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20754*FLEN/8, x13, x9, x10)

inst_6940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:20757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20757*FLEN/8, x13, x9, x10)

inst_6941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20760*FLEN/8, x13, x9, x10)

inst_6942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20763*FLEN/8, x13, x9, x10)

inst_6943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20766*FLEN/8, x13, x9, x10)

inst_6944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:20769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20769*FLEN/8, x13, x9, x10)

inst_6945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:20772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20772*FLEN/8, x13, x9, x10)

inst_6946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:20775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20775*FLEN/8, x13, x9, x10)

inst_6947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:20778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20778*FLEN/8, x13, x9, x10)

inst_6948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20781*FLEN/8, x13, x9, x10)

inst_6949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20784*FLEN/8, x13, x9, x10)

inst_6950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20787*FLEN/8, x13, x9, x10)

inst_6951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:20790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20790*FLEN/8, x13, x9, x10)

inst_6952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20793*FLEN/8, x13, x9, x10)

inst_6953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20796*FLEN/8, x13, x9, x10)

inst_6954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20799*FLEN/8, x13, x9, x10)

inst_6955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20802*FLEN/8, x13, x9, x10)

inst_6956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20805*FLEN/8, x13, x9, x10)

inst_6957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20808*FLEN/8, x13, x9, x10)

inst_6958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20811*FLEN/8, x13, x9, x10)

inst_6959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20814*FLEN/8, x13, x9, x10)

inst_6960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:20817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20817*FLEN/8, x13, x9, x10)

inst_6961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:20820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20820*FLEN/8, x13, x9, x10)

inst_6962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:20823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20823*FLEN/8, x13, x9, x10)

inst_6963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:20826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20826*FLEN/8, x13, x9, x10)

inst_6964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:20829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20829*FLEN/8, x13, x9, x10)

inst_6965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20832*FLEN/8, x13, x9, x10)

inst_6966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20835*FLEN/8, x13, x9, x10)

inst_6967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20838*FLEN/8, x13, x9, x10)

inst_6968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:20841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20841*FLEN/8, x13, x9, x10)

inst_6969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:20844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20844*FLEN/8, x13, x9, x10)

inst_6970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:20847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20847*FLEN/8, x13, x9, x10)

inst_6971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:20850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20850*FLEN/8, x13, x9, x10)

inst_6972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20853*FLEN/8, x13, x9, x10)

inst_6973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20856*FLEN/8, x13, x9, x10)

inst_6974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20859*FLEN/8, x13, x9, x10)

inst_6975:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:20862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20862*FLEN/8, x13, x9, x10)

inst_6976:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20865*FLEN/8, x13, x9, x10)

inst_6977:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20868*FLEN/8, x13, x9, x10)

inst_6978:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20871*FLEN/8, x13, x9, x10)

inst_6979:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20874*FLEN/8, x13, x9, x10)

inst_6980:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20877*FLEN/8, x13, x9, x10)

inst_6981:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20880*FLEN/8, x13, x9, x10)

inst_6982:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20883*FLEN/8, x13, x9, x10)

inst_6983:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20886*FLEN/8, x13, x9, x10)

inst_6984:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:20889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20889*FLEN/8, x13, x9, x10)

inst_6985:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:20892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20892*FLEN/8, x13, x9, x10)

inst_6986:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:20895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20895*FLEN/8, x13, x9, x10)

inst_6987:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:20898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20898*FLEN/8, x13, x9, x10)

inst_6988:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:20901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20901*FLEN/8, x13, x9, x10)

inst_6989:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20904*FLEN/8, x13, x9, x10)

inst_6990:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20907*FLEN/8, x13, x9, x10)

inst_6991:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20910*FLEN/8, x13, x9, x10)

inst_6992:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:20913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20913*FLEN/8, x13, x9, x10)

inst_6993:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:20916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20916*FLEN/8, x13, x9, x10)

inst_6994:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:20919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20919*FLEN/8, x13, x9, x10)

inst_6995:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:20922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20922*FLEN/8, x13, x9, x10)

inst_6996:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20925*FLEN/8, x13, x9, x10)

inst_6997:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:20928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20928*FLEN/8, x13, x9, x10)

inst_6998:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:20931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20931*FLEN/8, x13, x9, x10)

inst_6999:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:20934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20934*FLEN/8, x13, x9, x10)

inst_7000:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:20937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20937*FLEN/8, x13, x9, x10)

inst_7001:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:20940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20940*FLEN/8, x13, x9, x10)

inst_7002:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:20943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20943*FLEN/8, x13, x9, x10)

inst_7003:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:20946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20946*FLEN/8, x13, x9, x10)

inst_7004:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:20949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20949*FLEN/8, x13, x9, x10)

inst_7005:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:20952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20952*FLEN/8, x13, x9, x10)

inst_7006:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:20955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20955*FLEN/8, x13, x9, x10)

inst_7007:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:20958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20958*FLEN/8, x13, x9, x10)

inst_7008:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:20961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20961*FLEN/8, x13, x9, x10)

inst_7009:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:20964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20964*FLEN/8, x13, x9, x10)

inst_7010:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:20967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20967*FLEN/8, x13, x9, x10)

inst_7011:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:20970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20970*FLEN/8, x13, x9, x10)

inst_7012:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:20973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20973*FLEN/8, x13, x9, x10)

inst_7013:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:20976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20976*FLEN/8, x13, x9, x10)

inst_7014:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:20979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20979*FLEN/8, x13, x9, x10)

inst_7015:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:20982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20982*FLEN/8, x13, x9, x10)

inst_7016:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:20985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20985*FLEN/8, x13, x9, x10)

inst_7017:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:20988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20988*FLEN/8, x13, x9, x10)

inst_7018:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:20991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20991*FLEN/8, x13, x9, x10)

inst_7019:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:20994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20994*FLEN/8, x13, x9, x10)

inst_7020:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:20997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 20997*FLEN/8, x13, x9, x10)

inst_7021:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21000*FLEN/8, x13, x9, x10)

inst_7022:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21003*FLEN/8, x13, x9, x10)

inst_7023:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:21006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21006*FLEN/8, x13, x9, x10)

inst_7024:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21009*FLEN/8, x13, x9, x10)

inst_7025:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21012*FLEN/8, x13, x9, x10)

inst_7026:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21015*FLEN/8, x13, x9, x10)

inst_7027:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21018*FLEN/8, x13, x9, x10)

inst_7028:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21021*FLEN/8, x13, x9, x10)

inst_7029:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21024*FLEN/8, x13, x9, x10)

inst_7030:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21027*FLEN/8, x13, x9, x10)

inst_7031:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21030*FLEN/8, x13, x9, x10)

inst_7032:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:21033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21033*FLEN/8, x13, x9, x10)

inst_7033:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:21036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21036*FLEN/8, x13, x9, x10)

inst_7034:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:21039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21039*FLEN/8, x13, x9, x10)

inst_7035:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:21042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21042*FLEN/8, x13, x9, x10)

inst_7036:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:21045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21045*FLEN/8, x13, x9, x10)

inst_7037:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21048*FLEN/8, x13, x9, x10)

inst_7038:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21051*FLEN/8, x13, x9, x10)

inst_7039:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21054*FLEN/8, x13, x9, x10)

inst_7040:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:21057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21057*FLEN/8, x13, x9, x10)

inst_7041:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:21060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21060*FLEN/8, x13, x9, x10)

inst_7042:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:21063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21063*FLEN/8, x13, x9, x10)

inst_7043:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:21066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21066*FLEN/8, x13, x9, x10)

inst_7044:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21069*FLEN/8, x13, x9, x10)

inst_7045:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21072*FLEN/8, x13, x9, x10)

inst_7046:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21075*FLEN/8, x13, x9, x10)

inst_7047:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:21078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21078*FLEN/8, x13, x9, x10)

inst_7048:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21081*FLEN/8, x13, x9, x10)

inst_7049:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21084*FLEN/8, x13, x9, x10)

inst_7050:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21087*FLEN/8, x13, x9, x10)

inst_7051:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21090*FLEN/8, x13, x9, x10)

inst_7052:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21093*FLEN/8, x13, x9, x10)

inst_7053:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21096*FLEN/8, x13, x9, x10)

inst_7054:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21099*FLEN/8, x13, x9, x10)

inst_7055:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21102*FLEN/8, x13, x9, x10)

inst_7056:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:21105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21105*FLEN/8, x13, x9, x10)

inst_7057:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:21108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21108*FLEN/8, x13, x9, x10)

inst_7058:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:21111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21111*FLEN/8, x13, x9, x10)

inst_7059:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:21114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21114*FLEN/8, x13, x9, x10)

inst_7060:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:21117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21117*FLEN/8, x13, x9, x10)

inst_7061:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21120*FLEN/8, x13, x9, x10)

inst_7062:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21123*FLEN/8, x13, x9, x10)

inst_7063:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21126*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_55)

inst_7064:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:21129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21129*FLEN/8, x13, x9, x10)

inst_7065:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:21132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21132*FLEN/8, x13, x9, x10)

inst_7066:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:21135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21135*FLEN/8, x13, x9, x10)

inst_7067:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:21138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21138*FLEN/8, x13, x9, x10)

inst_7068:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21141*FLEN/8, x13, x9, x10)

inst_7069:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21144*FLEN/8, x13, x9, x10)

inst_7070:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21147*FLEN/8, x13, x9, x10)

inst_7071:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:21150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21150*FLEN/8, x13, x9, x10)

inst_7072:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21153*FLEN/8, x13, x9, x10)

inst_7073:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21156*FLEN/8, x13, x9, x10)

inst_7074:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21159*FLEN/8, x13, x9, x10)

inst_7075:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21162*FLEN/8, x13, x9, x10)

inst_7076:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21165*FLEN/8, x13, x9, x10)

inst_7077:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21168*FLEN/8, x13, x9, x10)

inst_7078:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21171*FLEN/8, x13, x9, x10)

inst_7079:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21174*FLEN/8, x13, x9, x10)

inst_7080:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:21177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21177*FLEN/8, x13, x9, x10)

inst_7081:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:21180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21180*FLEN/8, x13, x9, x10)

inst_7082:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:21183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21183*FLEN/8, x13, x9, x10)

inst_7083:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:21186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21186*FLEN/8, x13, x9, x10)

inst_7084:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:21189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21189*FLEN/8, x13, x9, x10)

inst_7085:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21192*FLEN/8, x13, x9, x10)

inst_7086:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21195*FLEN/8, x13, x9, x10)

inst_7087:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21198*FLEN/8, x13, x9, x10)

inst_7088:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:21201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21201*FLEN/8, x13, x9, x10)

inst_7089:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:21204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21204*FLEN/8, x13, x9, x10)

inst_7090:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:21207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21207*FLEN/8, x13, x9, x10)

inst_7091:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:21210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21210*FLEN/8, x13, x9, x10)

inst_7092:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21213*FLEN/8, x13, x9, x10)

inst_7093:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21216*FLEN/8, x13, x9, x10)

inst_7094:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21219*FLEN/8, x13, x9, x10)

inst_7095:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:21222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21222*FLEN/8, x13, x9, x10)

inst_7096:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21225*FLEN/8, x13, x9, x10)

inst_7097:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21228*FLEN/8, x13, x9, x10)

inst_7098:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21231*FLEN/8, x13, x9, x10)

inst_7099:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21234*FLEN/8, x13, x9, x10)

inst_7100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21237*FLEN/8, x13, x9, x10)

inst_7101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21240*FLEN/8, x13, x9, x10)

inst_7102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21243*FLEN/8, x13, x9, x10)

inst_7103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21246*FLEN/8, x13, x9, x10)

inst_7104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:21249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21249*FLEN/8, x13, x9, x10)

inst_7105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:21252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21252*FLEN/8, x13, x9, x10)

inst_7106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:21255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21255*FLEN/8, x13, x9, x10)

inst_7107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:21258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21258*FLEN/8, x13, x9, x10)

inst_7108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:21261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21261*FLEN/8, x13, x9, x10)

inst_7109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21264*FLEN/8, x13, x9, x10)

inst_7110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21267*FLEN/8, x13, x9, x10)

inst_7111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21270*FLEN/8, x13, x9, x10)

inst_7112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:21273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21273*FLEN/8, x13, x9, x10)

inst_7113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:21276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21276*FLEN/8, x13, x9, x10)

inst_7114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:21279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21279*FLEN/8, x13, x9, x10)

inst_7115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:21282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21282*FLEN/8, x13, x9, x10)

inst_7116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21285*FLEN/8, x13, x9, x10)

inst_7117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21288*FLEN/8, x13, x9, x10)

inst_7118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21291*FLEN/8, x13, x9, x10)

inst_7119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:21294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21294*FLEN/8, x13, x9, x10)

inst_7120:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21297*FLEN/8, x13, x9, x10)

inst_7121:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21300*FLEN/8, x13, x9, x10)

inst_7122:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21303*FLEN/8, x13, x9, x10)

inst_7123:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21306*FLEN/8, x13, x9, x10)

inst_7124:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21309*FLEN/8, x13, x9, x10)

inst_7125:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21312*FLEN/8, x13, x9, x10)

inst_7126:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21315*FLEN/8, x13, x9, x10)

inst_7127:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21318*FLEN/8, x13, x9, x10)

inst_7128:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:21321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21321*FLEN/8, x13, x9, x10)

inst_7129:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:21324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21324*FLEN/8, x13, x9, x10)

inst_7130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:21327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21327*FLEN/8, x13, x9, x10)

inst_7131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:21330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21330*FLEN/8, x13, x9, x10)

inst_7132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:21333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21333*FLEN/8, x13, x9, x10)

inst_7133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21336*FLEN/8, x13, x9, x10)

inst_7134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21339*FLEN/8, x13, x9, x10)

inst_7135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21342*FLEN/8, x13, x9, x10)

inst_7136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:21345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21345*FLEN/8, x13, x9, x10)

inst_7137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:21348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21348*FLEN/8, x13, x9, x10)

inst_7138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:21351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21351*FLEN/8, x13, x9, x10)

inst_7139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:21354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21354*FLEN/8, x13, x9, x10)

inst_7140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21357*FLEN/8, x13, x9, x10)

inst_7141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21360*FLEN/8, x13, x9, x10)

inst_7142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21363*FLEN/8, x13, x9, x10)

inst_7143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:21366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21366*FLEN/8, x13, x9, x10)

inst_7144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21369*FLEN/8, x13, x9, x10)

inst_7145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21372*FLEN/8, x13, x9, x10)

inst_7146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21375*FLEN/8, x13, x9, x10)

inst_7147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21378*FLEN/8, x13, x9, x10)

inst_7148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21381*FLEN/8, x13, x9, x10)

inst_7149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21384*FLEN/8, x13, x9, x10)

inst_7150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21387*FLEN/8, x13, x9, x10)

inst_7151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21390*FLEN/8, x13, x9, x10)

inst_7152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:21393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21393*FLEN/8, x13, x9, x10)

inst_7153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:21396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21396*FLEN/8, x13, x9, x10)

inst_7154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:21399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21399*FLEN/8, x13, x9, x10)

inst_7155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:21402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21402*FLEN/8, x13, x9, x10)

inst_7156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:21405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21405*FLEN/8, x13, x9, x10)

inst_7157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21408*FLEN/8, x13, x9, x10)

inst_7158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21411*FLEN/8, x13, x9, x10)

inst_7159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21414*FLEN/8, x13, x9, x10)

inst_7160:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:21417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21417*FLEN/8, x13, x9, x10)

inst_7161:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:21420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21420*FLEN/8, x13, x9, x10)

inst_7162:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:21423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21423*FLEN/8, x13, x9, x10)

inst_7163:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:21426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21426*FLEN/8, x13, x9, x10)

inst_7164:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21429*FLEN/8, x13, x9, x10)

inst_7165:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21432*FLEN/8, x13, x9, x10)

inst_7166:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21435*FLEN/8, x13, x9, x10)

inst_7167:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:21438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21438*FLEN/8, x13, x9, x10)

inst_7168:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21441*FLEN/8, x13, x9, x10)

inst_7169:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21444*FLEN/8, x13, x9, x10)

inst_7170:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21447*FLEN/8, x13, x9, x10)

inst_7171:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21450*FLEN/8, x13, x9, x10)

inst_7172:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21453*FLEN/8, x13, x9, x10)

inst_7173:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21456*FLEN/8, x13, x9, x10)

inst_7174:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21459*FLEN/8, x13, x9, x10)

inst_7175:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21462*FLEN/8, x13, x9, x10)

inst_7176:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:21465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21465*FLEN/8, x13, x9, x10)

inst_7177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:21468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21468*FLEN/8, x13, x9, x10)

inst_7178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:21471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21471*FLEN/8, x13, x9, x10)

inst_7179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:21474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21474*FLEN/8, x13, x9, x10)

inst_7180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:21477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21477*FLEN/8, x13, x9, x10)

inst_7181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21480*FLEN/8, x13, x9, x10)

inst_7182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21483*FLEN/8, x13, x9, x10)

inst_7183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21486*FLEN/8, x13, x9, x10)

inst_7184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:21489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21489*FLEN/8, x13, x9, x10)

inst_7185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:21492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21492*FLEN/8, x13, x9, x10)

inst_7186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:21495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21495*FLEN/8, x13, x9, x10)

inst_7187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:21498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21498*FLEN/8, x13, x9, x10)

inst_7188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21501*FLEN/8, x13, x9, x10)

inst_7189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21504*FLEN/8, x13, x9, x10)

inst_7190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21507*FLEN/8, x13, x9, x10)

inst_7191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:21510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21510*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_56)

inst_7192:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21513*FLEN/8, x13, x9, x10)

inst_7193:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21516*FLEN/8, x13, x9, x10)

inst_7194:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21519*FLEN/8, x13, x9, x10)

inst_7195:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21522*FLEN/8, x13, x9, x10)

inst_7196:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21525*FLEN/8, x13, x9, x10)

inst_7197:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21528*FLEN/8, x13, x9, x10)

inst_7198:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21531*FLEN/8, x13, x9, x10)

inst_7199:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21534*FLEN/8, x13, x9, x10)

inst_7200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:21537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21537*FLEN/8, x13, x9, x10)

inst_7201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:21540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21540*FLEN/8, x13, x9, x10)

inst_7202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:21543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21543*FLEN/8, x13, x9, x10)

inst_7203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:21546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21546*FLEN/8, x13, x9, x10)

inst_7204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:21549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21549*FLEN/8, x13, x9, x10)

inst_7205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21552*FLEN/8, x13, x9, x10)

inst_7206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21555*FLEN/8, x13, x9, x10)

inst_7207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21558*FLEN/8, x13, x9, x10)

inst_7208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:21561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21561*FLEN/8, x13, x9, x10)

inst_7209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:21564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21564*FLEN/8, x13, x9, x10)

inst_7210:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:21567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21567*FLEN/8, x13, x9, x10)

inst_7211:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:21570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21570*FLEN/8, x13, x9, x10)

inst_7212:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21573*FLEN/8, x13, x9, x10)

inst_7213:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21576*FLEN/8, x13, x9, x10)

inst_7214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21579*FLEN/8, x13, x9, x10)

inst_7215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:21582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21582*FLEN/8, x13, x9, x10)

inst_7216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21585*FLEN/8, x13, x9, x10)

inst_7217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21588*FLEN/8, x13, x9, x10)

inst_7218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21591*FLEN/8, x13, x9, x10)

inst_7219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21594*FLEN/8, x13, x9, x10)

inst_7220:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21597*FLEN/8, x13, x9, x10)

inst_7221:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21600*FLEN/8, x13, x9, x10)

inst_7222:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21603*FLEN/8, x13, x9, x10)

inst_7223:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21606*FLEN/8, x13, x9, x10)

inst_7224:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:21609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21609*FLEN/8, x13, x9, x10)

inst_7225:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:21612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21612*FLEN/8, x13, x9, x10)

inst_7226:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:21615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21615*FLEN/8, x13, x9, x10)

inst_7227:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:21618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21618*FLEN/8, x13, x9, x10)

inst_7228:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:21621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21621*FLEN/8, x13, x9, x10)

inst_7229:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21624*FLEN/8, x13, x9, x10)

inst_7230:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21627*FLEN/8, x13, x9, x10)

inst_7231:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21630*FLEN/8, x13, x9, x10)

inst_7232:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:21633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21633*FLEN/8, x13, x9, x10)

inst_7233:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:21636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21636*FLEN/8, x13, x9, x10)

inst_7234:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:21639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21639*FLEN/8, x13, x9, x10)

inst_7235:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:21642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21642*FLEN/8, x13, x9, x10)

inst_7236:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21645*FLEN/8, x13, x9, x10)

inst_7237:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21648*FLEN/8, x13, x9, x10)

inst_7238:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21651*FLEN/8, x13, x9, x10)

inst_7239:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:21654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21654*FLEN/8, x13, x9, x10)

inst_7240:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21657*FLEN/8, x13, x9, x10)

inst_7241:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21660*FLEN/8, x13, x9, x10)

inst_7242:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21663*FLEN/8, x13, x9, x10)

inst_7243:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21666*FLEN/8, x13, x9, x10)

inst_7244:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21669*FLEN/8, x13, x9, x10)

inst_7245:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21672*FLEN/8, x13, x9, x10)

inst_7246:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21675*FLEN/8, x13, x9, x10)

inst_7247:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21678*FLEN/8, x13, x9, x10)

inst_7248:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:21681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21681*FLEN/8, x13, x9, x10)

inst_7249:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:21684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21684*FLEN/8, x13, x9, x10)

inst_7250:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:21687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21687*FLEN/8, x13, x9, x10)

inst_7251:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:21690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21690*FLEN/8, x13, x9, x10)

inst_7252:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:21693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21693*FLEN/8, x13, x9, x10)

inst_7253:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21696*FLEN/8, x13, x9, x10)

inst_7254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21699*FLEN/8, x13, x9, x10)

inst_7255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21702*FLEN/8, x13, x9, x10)

inst_7256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:21705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21705*FLEN/8, x13, x9, x10)

inst_7257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:21708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21708*FLEN/8, x13, x9, x10)

inst_7258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:21711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21711*FLEN/8, x13, x9, x10)

inst_7259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:21714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21714*FLEN/8, x13, x9, x10)

inst_7260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21717*FLEN/8, x13, x9, x10)

inst_7261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21720*FLEN/8, x13, x9, x10)

inst_7262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21723*FLEN/8, x13, x9, x10)

inst_7263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:21726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21726*FLEN/8, x13, x9, x10)

inst_7264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21729*FLEN/8, x13, x9, x10)

inst_7265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21732*FLEN/8, x13, x9, x10)

inst_7266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21735*FLEN/8, x13, x9, x10)

inst_7267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21738*FLEN/8, x13, x9, x10)

inst_7268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21741*FLEN/8, x13, x9, x10)

inst_7269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21744*FLEN/8, x13, x9, x10)

inst_7270:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21747*FLEN/8, x13, x9, x10)

inst_7271:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21750*FLEN/8, x13, x9, x10)

inst_7272:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:21753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21753*FLEN/8, x13, x9, x10)

inst_7273:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:21756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21756*FLEN/8, x13, x9, x10)

inst_7274:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:21759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21759*FLEN/8, x13, x9, x10)

inst_7275:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:21762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21762*FLEN/8, x13, x9, x10)

inst_7276:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:21765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21765*FLEN/8, x13, x9, x10)

inst_7277:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21768*FLEN/8, x13, x9, x10)

inst_7278:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21771*FLEN/8, x13, x9, x10)

inst_7279:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21774*FLEN/8, x13, x9, x10)

inst_7280:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:21777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21777*FLEN/8, x13, x9, x10)

inst_7281:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:21780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21780*FLEN/8, x13, x9, x10)

inst_7282:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:21783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21783*FLEN/8, x13, x9, x10)

inst_7283:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:21786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21786*FLEN/8, x13, x9, x10)

inst_7284:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21789*FLEN/8, x13, x9, x10)

inst_7285:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21792*FLEN/8, x13, x9, x10)

inst_7286:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21795*FLEN/8, x13, x9, x10)

inst_7287:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:21798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21798*FLEN/8, x13, x9, x10)

inst_7288:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21801*FLEN/8, x13, x9, x10)

inst_7289:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21804*FLEN/8, x13, x9, x10)

inst_7290:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21807*FLEN/8, x13, x9, x10)

inst_7291:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21810*FLEN/8, x13, x9, x10)

inst_7292:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21813*FLEN/8, x13, x9, x10)

inst_7293:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21816*FLEN/8, x13, x9, x10)

inst_7294:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21819*FLEN/8, x13, x9, x10)

inst_7295:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21822*FLEN/8, x13, x9, x10)

inst_7296:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:21825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21825*FLEN/8, x13, x9, x10)

inst_7297:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:21828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21828*FLEN/8, x13, x9, x10)

inst_7298:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:21831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21831*FLEN/8, x13, x9, x10)

inst_7299:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:21834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21834*FLEN/8, x13, x9, x10)

inst_7300:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:21837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21837*FLEN/8, x13, x9, x10)

inst_7301:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21840*FLEN/8, x13, x9, x10)

inst_7302:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21843*FLEN/8, x13, x9, x10)

inst_7303:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21846*FLEN/8, x13, x9, x10)

inst_7304:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:21849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21849*FLEN/8, x13, x9, x10)

inst_7305:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:21852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21852*FLEN/8, x13, x9, x10)

inst_7306:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:21855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21855*FLEN/8, x13, x9, x10)

inst_7307:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:21858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21858*FLEN/8, x13, x9, x10)

inst_7308:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21861*FLEN/8, x13, x9, x10)

inst_7309:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21864*FLEN/8, x13, x9, x10)

inst_7310:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21867*FLEN/8, x13, x9, x10)

inst_7311:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:21870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21870*FLEN/8, x13, x9, x10)

inst_7312:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21873*FLEN/8, x13, x9, x10)

inst_7313:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21876*FLEN/8, x13, x9, x10)

inst_7314:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21879*FLEN/8, x13, x9, x10)

inst_7315:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21882*FLEN/8, x13, x9, x10)

inst_7316:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21885*FLEN/8, x13, x9, x10)

inst_7317:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21888*FLEN/8, x13, x9, x10)

inst_7318:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21891*FLEN/8, x13, x9, x10)

inst_7319:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21894*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_57)

inst_7320:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:21897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21897*FLEN/8, x13, x9, x10)

inst_7321:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:21900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21900*FLEN/8, x13, x9, x10)

inst_7322:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:21903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21903*FLEN/8, x13, x9, x10)

inst_7323:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:21906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21906*FLEN/8, x13, x9, x10)

inst_7324:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:21909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21909*FLEN/8, x13, x9, x10)

inst_7325:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21912*FLEN/8, x13, x9, x10)

inst_7326:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21915*FLEN/8, x13, x9, x10)

inst_7327:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21918*FLEN/8, x13, x9, x10)

inst_7328:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:21921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21921*FLEN/8, x13, x9, x10)

inst_7329:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:21924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21924*FLEN/8, x13, x9, x10)

inst_7330:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:21927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21927*FLEN/8, x13, x9, x10)

inst_7331:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:21930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21930*FLEN/8, x13, x9, x10)

inst_7332:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:21933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21933*FLEN/8, x13, x9, x10)

inst_7333:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:21936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21936*FLEN/8, x13, x9, x10)

inst_7334:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:21939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21939*FLEN/8, x13, x9, x10)

inst_7335:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:21942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21942*FLEN/8, x13, x9, x10)

inst_7336:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:21945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21945*FLEN/8, x13, x9, x10)

inst_7337:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:21948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21948*FLEN/8, x13, x9, x10)

inst_7338:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:21951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21951*FLEN/8, x13, x9, x10)

inst_7339:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:21954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21954*FLEN/8, x13, x9, x10)

inst_7340:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:21957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21957*FLEN/8, x13, x9, x10)

inst_7341:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:21960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21960*FLEN/8, x13, x9, x10)

inst_7342:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:21963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21963*FLEN/8, x13, x9, x10)

inst_7343:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:21966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21966*FLEN/8, x13, x9, x10)

inst_7344:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:21969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21969*FLEN/8, x13, x9, x10)

inst_7345:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:21972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21972*FLEN/8, x13, x9, x10)

inst_7346:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:21975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21975*FLEN/8, x13, x9, x10)

inst_7347:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:21978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21978*FLEN/8, x13, x9, x10)

inst_7348:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:21981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21981*FLEN/8, x13, x9, x10)

inst_7349:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:21984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21984*FLEN/8, x13, x9, x10)

inst_7350:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:21987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21987*FLEN/8, x13, x9, x10)

inst_7351:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:21990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21990*FLEN/8, x13, x9, x10)

inst_7352:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:21993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21993*FLEN/8, x13, x9, x10)

inst_7353:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:21996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21996*FLEN/8, x13, x9, x10)

inst_7354:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:21999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 21999*FLEN/8, x13, x9, x10)

inst_7355:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:22002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22002*FLEN/8, x13, x9, x10)

inst_7356:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22005*FLEN/8, x13, x9, x10)

inst_7357:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22008*FLEN/8, x13, x9, x10)

inst_7358:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22011*FLEN/8, x13, x9, x10)

inst_7359:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:22014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22014*FLEN/8, x13, x9, x10)

inst_7360:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22017*FLEN/8, x13, x9, x10)

inst_7361:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22020*FLEN/8, x13, x9, x10)

inst_7362:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22023*FLEN/8, x13, x9, x10)

inst_7363:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22026*FLEN/8, x13, x9, x10)

inst_7364:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22029*FLEN/8, x13, x9, x10)

inst_7365:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22032*FLEN/8, x13, x9, x10)

inst_7366:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22035*FLEN/8, x13, x9, x10)

inst_7367:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22038*FLEN/8, x13, x9, x10)

inst_7368:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:22041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22041*FLEN/8, x13, x9, x10)

inst_7369:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:22044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22044*FLEN/8, x13, x9, x10)

inst_7370:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:22047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22047*FLEN/8, x13, x9, x10)

inst_7371:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:22050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22050*FLEN/8, x13, x9, x10)

inst_7372:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:22053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22053*FLEN/8, x13, x9, x10)

inst_7373:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22056*FLEN/8, x13, x9, x10)

inst_7374:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22059*FLEN/8, x13, x9, x10)

inst_7375:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22062*FLEN/8, x13, x9, x10)

inst_7376:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:22065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22065*FLEN/8, x13, x9, x10)

inst_7377:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:22068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22068*FLEN/8, x13, x9, x10)

inst_7378:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:22071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22071*FLEN/8, x13, x9, x10)

inst_7379:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:22074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22074*FLEN/8, x13, x9, x10)

inst_7380:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22077*FLEN/8, x13, x9, x10)

inst_7381:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22080*FLEN/8, x13, x9, x10)

inst_7382:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22083*FLEN/8, x13, x9, x10)

inst_7383:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:22086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22086*FLEN/8, x13, x9, x10)

inst_7384:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22089*FLEN/8, x13, x9, x10)

inst_7385:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22092*FLEN/8, x13, x9, x10)

inst_7386:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22095*FLEN/8, x13, x9, x10)

inst_7387:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22098*FLEN/8, x13, x9, x10)

inst_7388:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22101*FLEN/8, x13, x9, x10)

inst_7389:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22104*FLEN/8, x13, x9, x10)

inst_7390:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22107*FLEN/8, x13, x9, x10)

inst_7391:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22110*FLEN/8, x13, x9, x10)

inst_7392:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:22113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22113*FLEN/8, x13, x9, x10)

inst_7393:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:22116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22116*FLEN/8, x13, x9, x10)

inst_7394:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:22119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22119*FLEN/8, x13, x9, x10)

inst_7395:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:22122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22122*FLEN/8, x13, x9, x10)

inst_7396:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:22125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22125*FLEN/8, x13, x9, x10)

inst_7397:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22128*FLEN/8, x13, x9, x10)

inst_7398:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22131*FLEN/8, x13, x9, x10)

inst_7399:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22134*FLEN/8, x13, x9, x10)

inst_7400:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:22137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22137*FLEN/8, x13, x9, x10)

inst_7401:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:22140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22140*FLEN/8, x13, x9, x10)

inst_7402:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:22143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22143*FLEN/8, x13, x9, x10)

inst_7403:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:22146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22146*FLEN/8, x13, x9, x10)

inst_7404:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22149*FLEN/8, x13, x9, x10)

inst_7405:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22152*FLEN/8, x13, x9, x10)

inst_7406:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22155*FLEN/8, x13, x9, x10)

inst_7407:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:22158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22158*FLEN/8, x13, x9, x10)

inst_7408:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22161*FLEN/8, x13, x9, x10)

inst_7409:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22164*FLEN/8, x13, x9, x10)

inst_7410:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22167*FLEN/8, x13, x9, x10)

inst_7411:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22170*FLEN/8, x13, x9, x10)

inst_7412:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22173*FLEN/8, x13, x9, x10)

inst_7413:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22176*FLEN/8, x13, x9, x10)

inst_7414:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22179*FLEN/8, x13, x9, x10)

inst_7415:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22182*FLEN/8, x13, x9, x10)

inst_7416:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:22185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22185*FLEN/8, x13, x9, x10)

inst_7417:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:22188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22188*FLEN/8, x13, x9, x10)

inst_7418:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:22191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22191*FLEN/8, x13, x9, x10)

inst_7419:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:22194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22194*FLEN/8, x13, x9, x10)

inst_7420:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:22197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22197*FLEN/8, x13, x9, x10)

inst_7421:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22200*FLEN/8, x13, x9, x10)

inst_7422:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22203*FLEN/8, x13, x9, x10)

inst_7423:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22206*FLEN/8, x13, x9, x10)

inst_7424:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:22209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22209*FLEN/8, x13, x9, x10)

inst_7425:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:22212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22212*FLEN/8, x13, x9, x10)

inst_7426:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:22215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22215*FLEN/8, x13, x9, x10)

inst_7427:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:22218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22218*FLEN/8, x13, x9, x10)

inst_7428:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22221*FLEN/8, x13, x9, x10)

inst_7429:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22224*FLEN/8, x13, x9, x10)

inst_7430:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22227*FLEN/8, x13, x9, x10)

inst_7431:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:22230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22230*FLEN/8, x13, x9, x10)

inst_7432:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22233*FLEN/8, x13, x9, x10)

inst_7433:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22236*FLEN/8, x13, x9, x10)

inst_7434:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22239*FLEN/8, x13, x9, x10)

inst_7435:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22242*FLEN/8, x13, x9, x10)

inst_7436:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22245*FLEN/8, x13, x9, x10)

inst_7437:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22248*FLEN/8, x13, x9, x10)

inst_7438:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22251*FLEN/8, x13, x9, x10)

inst_7439:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22254*FLEN/8, x13, x9, x10)

inst_7440:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:22257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22257*FLEN/8, x13, x9, x10)

inst_7441:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:22260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22260*FLEN/8, x13, x9, x10)

inst_7442:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:22263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22263*FLEN/8, x13, x9, x10)

inst_7443:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:22266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22266*FLEN/8, x13, x9, x10)

inst_7444:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:22269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22269*FLEN/8, x13, x9, x10)

inst_7445:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22272*FLEN/8, x13, x9, x10)

inst_7446:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22275*FLEN/8, x13, x9, x10)

inst_7447:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22278*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_58)

inst_7448:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:22281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22281*FLEN/8, x13, x9, x10)

inst_7449:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:22284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22284*FLEN/8, x13, x9, x10)

inst_7450:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:22287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22287*FLEN/8, x13, x9, x10)

inst_7451:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:22290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22290*FLEN/8, x13, x9, x10)

inst_7452:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22293*FLEN/8, x13, x9, x10)

inst_7453:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22296*FLEN/8, x13, x9, x10)

inst_7454:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22299*FLEN/8, x13, x9, x10)

inst_7455:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:22302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22302*FLEN/8, x13, x9, x10)

inst_7456:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22305*FLEN/8, x13, x9, x10)

inst_7457:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22308*FLEN/8, x13, x9, x10)

inst_7458:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22311*FLEN/8, x13, x9, x10)

inst_7459:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22314*FLEN/8, x13, x9, x10)

inst_7460:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22317*FLEN/8, x13, x9, x10)

inst_7461:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22320*FLEN/8, x13, x9, x10)

inst_7462:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22323*FLEN/8, x13, x9, x10)

inst_7463:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22326*FLEN/8, x13, x9, x10)

inst_7464:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:22329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22329*FLEN/8, x13, x9, x10)

inst_7465:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:22332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22332*FLEN/8, x13, x9, x10)

inst_7466:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:22335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22335*FLEN/8, x13, x9, x10)

inst_7467:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:22338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22338*FLEN/8, x13, x9, x10)

inst_7468:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:22341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22341*FLEN/8, x13, x9, x10)

inst_7469:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22344*FLEN/8, x13, x9, x10)

inst_7470:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22347*FLEN/8, x13, x9, x10)

inst_7471:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22350*FLEN/8, x13, x9, x10)

inst_7472:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:22353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22353*FLEN/8, x13, x9, x10)

inst_7473:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:22356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22356*FLEN/8, x13, x9, x10)

inst_7474:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:22359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22359*FLEN/8, x13, x9, x10)

inst_7475:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:22362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22362*FLEN/8, x13, x9, x10)

inst_7476:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22365*FLEN/8, x13, x9, x10)

inst_7477:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22368*FLEN/8, x13, x9, x10)

inst_7478:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22371*FLEN/8, x13, x9, x10)

inst_7479:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:22374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22374*FLEN/8, x13, x9, x10)

inst_7480:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22377*FLEN/8, x13, x9, x10)

inst_7481:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22380*FLEN/8, x13, x9, x10)

inst_7482:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22383*FLEN/8, x13, x9, x10)

inst_7483:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22386*FLEN/8, x13, x9, x10)

inst_7484:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22389*FLEN/8, x13, x9, x10)

inst_7485:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22392*FLEN/8, x13, x9, x10)

inst_7486:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22395*FLEN/8, x13, x9, x10)

inst_7487:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22398*FLEN/8, x13, x9, x10)

inst_7488:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:22401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22401*FLEN/8, x13, x9, x10)

inst_7489:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:22404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22404*FLEN/8, x13, x9, x10)

inst_7490:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:22407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22407*FLEN/8, x13, x9, x10)

inst_7491:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:22410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22410*FLEN/8, x13, x9, x10)

inst_7492:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:22413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22413*FLEN/8, x13, x9, x10)

inst_7493:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22416*FLEN/8, x13, x9, x10)

inst_7494:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22419*FLEN/8, x13, x9, x10)

inst_7495:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22422*FLEN/8, x13, x9, x10)

inst_7496:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:22425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22425*FLEN/8, x13, x9, x10)

inst_7497:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:22428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22428*FLEN/8, x13, x9, x10)

inst_7498:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:22431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22431*FLEN/8, x13, x9, x10)

inst_7499:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:22434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22434*FLEN/8, x13, x9, x10)

inst_7500:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22437*FLEN/8, x13, x9, x10)

inst_7501:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22440*FLEN/8, x13, x9, x10)

inst_7502:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22443*FLEN/8, x13, x9, x10)

inst_7503:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:22446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22446*FLEN/8, x13, x9, x10)

inst_7504:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22449*FLEN/8, x13, x9, x10)

inst_7505:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22452*FLEN/8, x13, x9, x10)

inst_7506:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22455*FLEN/8, x13, x9, x10)

inst_7507:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22458*FLEN/8, x13, x9, x10)

inst_7508:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22461*FLEN/8, x13, x9, x10)

inst_7509:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22464*FLEN/8, x13, x9, x10)

inst_7510:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22467*FLEN/8, x13, x9, x10)

inst_7511:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22470*FLEN/8, x13, x9, x10)

inst_7512:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:22473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22473*FLEN/8, x13, x9, x10)

inst_7513:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:22476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22476*FLEN/8, x13, x9, x10)

inst_7514:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:22479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22479*FLEN/8, x13, x9, x10)

inst_7515:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:22482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22482*FLEN/8, x13, x9, x10)

inst_7516:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:22485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22485*FLEN/8, x13, x9, x10)

inst_7517:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22488*FLEN/8, x13, x9, x10)

inst_7518:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22491*FLEN/8, x13, x9, x10)

inst_7519:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22494*FLEN/8, x13, x9, x10)

inst_7520:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:22497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22497*FLEN/8, x13, x9, x10)

inst_7521:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:22500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22500*FLEN/8, x13, x9, x10)

inst_7522:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:22503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22503*FLEN/8, x13, x9, x10)

inst_7523:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:22506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22506*FLEN/8, x13, x9, x10)

inst_7524:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22509*FLEN/8, x13, x9, x10)

inst_7525:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22512*FLEN/8, x13, x9, x10)

inst_7526:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22515*FLEN/8, x13, x9, x10)

inst_7527:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:22518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22518*FLEN/8, x13, x9, x10)

inst_7528:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22521*FLEN/8, x13, x9, x10)

inst_7529:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22524*FLEN/8, x13, x9, x10)

inst_7530:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22527*FLEN/8, x13, x9, x10)

inst_7531:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22530*FLEN/8, x13, x9, x10)

inst_7532:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22533*FLEN/8, x13, x9, x10)

inst_7533:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22536*FLEN/8, x13, x9, x10)

inst_7534:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22539*FLEN/8, x13, x9, x10)

inst_7535:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22542*FLEN/8, x13, x9, x10)

inst_7536:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:22545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22545*FLEN/8, x13, x9, x10)

inst_7537:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:22548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22548*FLEN/8, x13, x9, x10)

inst_7538:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:22551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22551*FLEN/8, x13, x9, x10)

inst_7539:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:22554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22554*FLEN/8, x13, x9, x10)

inst_7540:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:22557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22557*FLEN/8, x13, x9, x10)

inst_7541:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22560*FLEN/8, x13, x9, x10)

inst_7542:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22563*FLEN/8, x13, x9, x10)

inst_7543:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22566*FLEN/8, x13, x9, x10)

inst_7544:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:22569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22569*FLEN/8, x13, x9, x10)

inst_7545:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:22572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22572*FLEN/8, x13, x9, x10)

inst_7546:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:22575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22575*FLEN/8, x13, x9, x10)

inst_7547:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:22578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22578*FLEN/8, x13, x9, x10)

inst_7548:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22581*FLEN/8, x13, x9, x10)

inst_7549:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22584*FLEN/8, x13, x9, x10)

inst_7550:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22587*FLEN/8, x13, x9, x10)

inst_7551:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:22590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22590*FLEN/8, x13, x9, x10)

inst_7552:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22593*FLEN/8, x13, x9, x10)

inst_7553:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22596*FLEN/8, x13, x9, x10)

inst_7554:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22599*FLEN/8, x13, x9, x10)

inst_7555:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22602*FLEN/8, x13, x9, x10)

inst_7556:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22605*FLEN/8, x13, x9, x10)

inst_7557:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22608*FLEN/8, x13, x9, x10)

inst_7558:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22611*FLEN/8, x13, x9, x10)

inst_7559:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22614*FLEN/8, x13, x9, x10)

inst_7560:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:22617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22617*FLEN/8, x13, x9, x10)

inst_7561:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:22620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22620*FLEN/8, x13, x9, x10)

inst_7562:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:22623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22623*FLEN/8, x13, x9, x10)

inst_7563:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:22626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22626*FLEN/8, x13, x9, x10)

inst_7564:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:22629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22629*FLEN/8, x13, x9, x10)

inst_7565:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22632*FLEN/8, x13, x9, x10)

inst_7566:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22635*FLEN/8, x13, x9, x10)

inst_7567:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22638*FLEN/8, x13, x9, x10)

inst_7568:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:22641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22641*FLEN/8, x13, x9, x10)

inst_7569:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:22644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22644*FLEN/8, x13, x9, x10)

inst_7570:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:22647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22647*FLEN/8, x13, x9, x10)

inst_7571:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:22650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22650*FLEN/8, x13, x9, x10)

inst_7572:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22653*FLEN/8, x13, x9, x10)

inst_7573:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22656*FLEN/8, x13, x9, x10)

inst_7574:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22659*FLEN/8, x13, x9, x10)

inst_7575:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:22662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22662*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_59)

inst_7576:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22665*FLEN/8, x13, x9, x10)

inst_7577:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22668*FLEN/8, x13, x9, x10)

inst_7578:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22671*FLEN/8, x13, x9, x10)

inst_7579:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22674*FLEN/8, x13, x9, x10)

inst_7580:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22677*FLEN/8, x13, x9, x10)

inst_7581:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22680*FLEN/8, x13, x9, x10)

inst_7582:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22683*FLEN/8, x13, x9, x10)

inst_7583:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22686*FLEN/8, x13, x9, x10)

inst_7584:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:22689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22689*FLEN/8, x13, x9, x10)

inst_7585:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:22692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22692*FLEN/8, x13, x9, x10)

inst_7586:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:22695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22695*FLEN/8, x13, x9, x10)

inst_7587:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:22698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22698*FLEN/8, x13, x9, x10)

inst_7588:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:22701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22701*FLEN/8, x13, x9, x10)

inst_7589:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22704*FLEN/8, x13, x9, x10)

inst_7590:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22707*FLEN/8, x13, x9, x10)

inst_7591:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22710*FLEN/8, x13, x9, x10)

inst_7592:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:22713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22713*FLEN/8, x13, x9, x10)

inst_7593:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:22716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22716*FLEN/8, x13, x9, x10)

inst_7594:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:22719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22719*FLEN/8, x13, x9, x10)

inst_7595:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:22722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22722*FLEN/8, x13, x9, x10)

inst_7596:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22725*FLEN/8, x13, x9, x10)

inst_7597:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22728*FLEN/8, x13, x9, x10)

inst_7598:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22731*FLEN/8, x13, x9, x10)

inst_7599:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:22734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22734*FLEN/8, x13, x9, x10)

inst_7600:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22737*FLEN/8, x13, x9, x10)

inst_7601:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22740*FLEN/8, x13, x9, x10)

inst_7602:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22743*FLEN/8, x13, x9, x10)

inst_7603:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22746*FLEN/8, x13, x9, x10)

inst_7604:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22749*FLEN/8, x13, x9, x10)

inst_7605:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22752*FLEN/8, x13, x9, x10)

inst_7606:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22755*FLEN/8, x13, x9, x10)

inst_7607:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22758*FLEN/8, x13, x9, x10)

inst_7608:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:22761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22761*FLEN/8, x13, x9, x10)

inst_7609:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:22764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22764*FLEN/8, x13, x9, x10)

inst_7610:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:22767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22767*FLEN/8, x13, x9, x10)

inst_7611:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:22770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22770*FLEN/8, x13, x9, x10)

inst_7612:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:22773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22773*FLEN/8, x13, x9, x10)

inst_7613:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22776*FLEN/8, x13, x9, x10)

inst_7614:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22779*FLEN/8, x13, x9, x10)

inst_7615:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22782*FLEN/8, x13, x9, x10)

inst_7616:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:22785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22785*FLEN/8, x13, x9, x10)

inst_7617:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:22788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22788*FLEN/8, x13, x9, x10)

inst_7618:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:22791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22791*FLEN/8, x13, x9, x10)

inst_7619:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:22794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22794*FLEN/8, x13, x9, x10)

inst_7620:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22797*FLEN/8, x13, x9, x10)

inst_7621:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22800*FLEN/8, x13, x9, x10)

inst_7622:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22803*FLEN/8, x13, x9, x10)

inst_7623:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:22806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22806*FLEN/8, x13, x9, x10)

inst_7624:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22809*FLEN/8, x13, x9, x10)

inst_7625:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22812*FLEN/8, x13, x9, x10)

inst_7626:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22815*FLEN/8, x13, x9, x10)

inst_7627:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22818*FLEN/8, x13, x9, x10)

inst_7628:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22821*FLEN/8, x13, x9, x10)

inst_7629:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22824*FLEN/8, x13, x9, x10)

inst_7630:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22827*FLEN/8, x13, x9, x10)

inst_7631:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22830*FLEN/8, x13, x9, x10)

inst_7632:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:22833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22833*FLEN/8, x13, x9, x10)

inst_7633:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:22836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22836*FLEN/8, x13, x9, x10)

inst_7634:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:22839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22839*FLEN/8, x13, x9, x10)

inst_7635:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:22842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22842*FLEN/8, x13, x9, x10)

inst_7636:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:22845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22845*FLEN/8, x13, x9, x10)

inst_7637:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22848*FLEN/8, x13, x9, x10)

inst_7638:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22851*FLEN/8, x13, x9, x10)

inst_7639:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22854*FLEN/8, x13, x9, x10)

inst_7640:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:22857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22857*FLEN/8, x13, x9, x10)

inst_7641:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:22860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22860*FLEN/8, x13, x9, x10)

inst_7642:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:22863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22863*FLEN/8, x13, x9, x10)

inst_7643:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:22866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22866*FLEN/8, x13, x9, x10)

inst_7644:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22869*FLEN/8, x13, x9, x10)

inst_7645:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22872*FLEN/8, x13, x9, x10)

inst_7646:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22875*FLEN/8, x13, x9, x10)

inst_7647:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:22878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22878*FLEN/8, x13, x9, x10)

inst_7648:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22881*FLEN/8, x13, x9, x10)

inst_7649:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22884*FLEN/8, x13, x9, x10)

inst_7650:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22887*FLEN/8, x13, x9, x10)

inst_7651:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22890*FLEN/8, x13, x9, x10)

inst_7652:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22893*FLEN/8, x13, x9, x10)

inst_7653:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22896*FLEN/8, x13, x9, x10)

inst_7654:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22899*FLEN/8, x13, x9, x10)

inst_7655:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22902*FLEN/8, x13, x9, x10)

inst_7656:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:22905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22905*FLEN/8, x13, x9, x10)

inst_7657:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:22908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22908*FLEN/8, x13, x9, x10)

inst_7658:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:22911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22911*FLEN/8, x13, x9, x10)

inst_7659:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:22914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22914*FLEN/8, x13, x9, x10)

inst_7660:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:22917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22917*FLEN/8, x13, x9, x10)

inst_7661:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22920*FLEN/8, x13, x9, x10)

inst_7662:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22923*FLEN/8, x13, x9, x10)

inst_7663:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22926*FLEN/8, x13, x9, x10)

inst_7664:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:22929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22929*FLEN/8, x13, x9, x10)

inst_7665:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:22932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22932*FLEN/8, x13, x9, x10)

inst_7666:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:22935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22935*FLEN/8, x13, x9, x10)

inst_7667:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:22938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22938*FLEN/8, x13, x9, x10)

inst_7668:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:22941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22941*FLEN/8, x13, x9, x10)

inst_7669:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:22944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22944*FLEN/8, x13, x9, x10)

inst_7670:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:22947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22947*FLEN/8, x13, x9, x10)

inst_7671:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:22950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22950*FLEN/8, x13, x9, x10)

inst_7672:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:22953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22953*FLEN/8, x13, x9, x10)

inst_7673:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:22956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22956*FLEN/8, x13, x9, x10)

inst_7674:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:22959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22959*FLEN/8, x13, x9, x10)

inst_7675:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:22962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22962*FLEN/8, x13, x9, x10)

inst_7676:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:22965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22965*FLEN/8, x13, x9, x10)

inst_7677:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:22968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22968*FLEN/8, x13, x9, x10)

inst_7678:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:22971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22971*FLEN/8, x13, x9, x10)

inst_7679:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:22974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22974*FLEN/8, x13, x9, x10)

inst_7680:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:22977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22977*FLEN/8, x13, x9, x10)

inst_7681:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:22980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22980*FLEN/8, x13, x9, x10)

inst_7682:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:22983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22983*FLEN/8, x13, x9, x10)

inst_7683:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:22986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22986*FLEN/8, x13, x9, x10)

inst_7684:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:22989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22989*FLEN/8, x13, x9, x10)

inst_7685:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:22992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22992*FLEN/8, x13, x9, x10)

inst_7686:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:22995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22995*FLEN/8, x13, x9, x10)

inst_7687:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:22998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22998*FLEN/8, x13, x9, x10)

inst_7688:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:23001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23001*FLEN/8, x13, x9, x10)

inst_7689:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:23004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23004*FLEN/8, x13, x9, x10)

inst_7690:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:23007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23007*FLEN/8, x13, x9, x10)

inst_7691:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:23010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23010*FLEN/8, x13, x9, x10)

inst_7692:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23013*FLEN/8, x13, x9, x10)

inst_7693:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23016*FLEN/8, x13, x9, x10)

inst_7694:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23019*FLEN/8, x13, x9, x10)

inst_7695:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:23022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23022*FLEN/8, x13, x9, x10)

inst_7696:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23025*FLEN/8, x13, x9, x10)

inst_7697:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23028*FLEN/8, x13, x9, x10)

inst_7698:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23031*FLEN/8, x13, x9, x10)

inst_7699:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23034*FLEN/8, x13, x9, x10)

inst_7700:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23037*FLEN/8, x13, x9, x10)

inst_7701:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23040*FLEN/8, x13, x9, x10)

inst_7702:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23043*FLEN/8, x13, x9, x10)

inst_7703:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23046*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_60)

inst_7704:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:23049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23049*FLEN/8, x13, x9, x10)

inst_7705:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:23052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23052*FLEN/8, x13, x9, x10)

inst_7706:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:23055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23055*FLEN/8, x13, x9, x10)

inst_7707:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:23058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23058*FLEN/8, x13, x9, x10)

inst_7708:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:23061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23061*FLEN/8, x13, x9, x10)

inst_7709:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23064*FLEN/8, x13, x9, x10)

inst_7710:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23067*FLEN/8, x13, x9, x10)

inst_7711:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23070*FLEN/8, x13, x9, x10)

inst_7712:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:23073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23073*FLEN/8, x13, x9, x10)

inst_7713:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:23076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23076*FLEN/8, x13, x9, x10)

inst_7714:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:23079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23079*FLEN/8, x13, x9, x10)

inst_7715:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:23082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23082*FLEN/8, x13, x9, x10)

inst_7716:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23085*FLEN/8, x13, x9, x10)

inst_7717:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23088*FLEN/8, x13, x9, x10)

inst_7718:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23091*FLEN/8, x13, x9, x10)

inst_7719:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:23094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23094*FLEN/8, x13, x9, x10)

inst_7720:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23097*FLEN/8, x13, x9, x10)

inst_7721:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23100*FLEN/8, x13, x9, x10)

inst_7722:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23103*FLEN/8, x13, x9, x10)

inst_7723:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23106*FLEN/8, x13, x9, x10)

inst_7724:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23109*FLEN/8, x13, x9, x10)

inst_7725:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23112*FLEN/8, x13, x9, x10)

inst_7726:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23115*FLEN/8, x13, x9, x10)

inst_7727:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23118*FLEN/8, x13, x9, x10)

inst_7728:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:23121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23121*FLEN/8, x13, x9, x10)

inst_7729:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:23124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23124*FLEN/8, x13, x9, x10)

inst_7730:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:23127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23127*FLEN/8, x13, x9, x10)

inst_7731:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:23130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23130*FLEN/8, x13, x9, x10)

inst_7732:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:23133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23133*FLEN/8, x13, x9, x10)

inst_7733:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23136*FLEN/8, x13, x9, x10)

inst_7734:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23139*FLEN/8, x13, x9, x10)

inst_7735:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23142*FLEN/8, x13, x9, x10)

inst_7736:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:23145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23145*FLEN/8, x13, x9, x10)

inst_7737:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:23148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23148*FLEN/8, x13, x9, x10)

inst_7738:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:23151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23151*FLEN/8, x13, x9, x10)

inst_7739:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:23154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23154*FLEN/8, x13, x9, x10)

inst_7740:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23157*FLEN/8, x13, x9, x10)

inst_7741:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23160*FLEN/8, x13, x9, x10)

inst_7742:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23163*FLEN/8, x13, x9, x10)

inst_7743:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:23166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23166*FLEN/8, x13, x9, x10)

inst_7744:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23169*FLEN/8, x13, x9, x10)

inst_7745:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23172*FLEN/8, x13, x9, x10)

inst_7746:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23175*FLEN/8, x13, x9, x10)

inst_7747:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23178*FLEN/8, x13, x9, x10)

inst_7748:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23181*FLEN/8, x13, x9, x10)

inst_7749:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23184*FLEN/8, x13, x9, x10)

inst_7750:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23187*FLEN/8, x13, x9, x10)

inst_7751:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23190*FLEN/8, x13, x9, x10)

inst_7752:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:23193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23193*FLEN/8, x13, x9, x10)

inst_7753:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:23196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23196*FLEN/8, x13, x9, x10)

inst_7754:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:23199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23199*FLEN/8, x13, x9, x10)

inst_7755:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:23202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23202*FLEN/8, x13, x9, x10)

inst_7756:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:23205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23205*FLEN/8, x13, x9, x10)

inst_7757:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23208*FLEN/8, x13, x9, x10)

inst_7758:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23211*FLEN/8, x13, x9, x10)

inst_7759:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23214*FLEN/8, x13, x9, x10)

inst_7760:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:23217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23217*FLEN/8, x13, x9, x10)

inst_7761:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:23220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23220*FLEN/8, x13, x9, x10)

inst_7762:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:23223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23223*FLEN/8, x13, x9, x10)

inst_7763:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:23226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23226*FLEN/8, x13, x9, x10)

inst_7764:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23229*FLEN/8, x13, x9, x10)

inst_7765:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23232*FLEN/8, x13, x9, x10)

inst_7766:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23235*FLEN/8, x13, x9, x10)

inst_7767:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:23238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23238*FLEN/8, x13, x9, x10)

inst_7768:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23241*FLEN/8, x13, x9, x10)

inst_7769:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23244*FLEN/8, x13, x9, x10)

inst_7770:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23247*FLEN/8, x13, x9, x10)

inst_7771:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23250*FLEN/8, x13, x9, x10)

inst_7772:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23253*FLEN/8, x13, x9, x10)

inst_7773:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23256*FLEN/8, x13, x9, x10)

inst_7774:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23259*FLEN/8, x13, x9, x10)

inst_7775:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23262*FLEN/8, x13, x9, x10)

inst_7776:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:23265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23265*FLEN/8, x13, x9, x10)

inst_7777:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:23268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23268*FLEN/8, x13, x9, x10)

inst_7778:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:23271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23271*FLEN/8, x13, x9, x10)

inst_7779:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:23274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23274*FLEN/8, x13, x9, x10)

inst_7780:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:23277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23277*FLEN/8, x13, x9, x10)

inst_7781:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23280*FLEN/8, x13, x9, x10)

inst_7782:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23283*FLEN/8, x13, x9, x10)

inst_7783:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23286*FLEN/8, x13, x9, x10)

inst_7784:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:23289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23289*FLEN/8, x13, x9, x10)

inst_7785:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:23292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23292*FLEN/8, x13, x9, x10)

inst_7786:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:23295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23295*FLEN/8, x13, x9, x10)

inst_7787:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:23298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23298*FLEN/8, x13, x9, x10)

inst_7788:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23301*FLEN/8, x13, x9, x10)

inst_7789:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23304*FLEN/8, x13, x9, x10)

inst_7790:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23307*FLEN/8, x13, x9, x10)

inst_7791:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:23310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23310*FLEN/8, x13, x9, x10)

inst_7792:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23313*FLEN/8, x13, x9, x10)

inst_7793:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23316*FLEN/8, x13, x9, x10)

inst_7794:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23319*FLEN/8, x13, x9, x10)

inst_7795:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23322*FLEN/8, x13, x9, x10)

inst_7796:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23325*FLEN/8, x13, x9, x10)

inst_7797:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23328*FLEN/8, x13, x9, x10)

inst_7798:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23331*FLEN/8, x13, x9, x10)

inst_7799:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23334*FLEN/8, x13, x9, x10)

inst_7800:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:23337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23337*FLEN/8, x13, x9, x10)

inst_7801:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:23340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23340*FLEN/8, x13, x9, x10)

inst_7802:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:23343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23343*FLEN/8, x13, x9, x10)

inst_7803:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:23346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23346*FLEN/8, x13, x9, x10)

inst_7804:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:23349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23349*FLEN/8, x13, x9, x10)

inst_7805:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23352*FLEN/8, x13, x9, x10)

inst_7806:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23355*FLEN/8, x13, x9, x10)

inst_7807:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23358*FLEN/8, x13, x9, x10)

inst_7808:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:23361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23361*FLEN/8, x13, x9, x10)

inst_7809:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:23364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23364*FLEN/8, x13, x9, x10)

inst_7810:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:23367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23367*FLEN/8, x13, x9, x10)

inst_7811:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:23370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23370*FLEN/8, x13, x9, x10)

inst_7812:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23373*FLEN/8, x13, x9, x10)

inst_7813:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23376*FLEN/8, x13, x9, x10)

inst_7814:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23379*FLEN/8, x13, x9, x10)

inst_7815:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:23382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23382*FLEN/8, x13, x9, x10)

inst_7816:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23385*FLEN/8, x13, x9, x10)

inst_7817:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23388*FLEN/8, x13, x9, x10)

inst_7818:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23391*FLEN/8, x13, x9, x10)

inst_7819:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23394*FLEN/8, x13, x9, x10)

inst_7820:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23397*FLEN/8, x13, x9, x10)

inst_7821:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23400*FLEN/8, x13, x9, x10)

inst_7822:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23403*FLEN/8, x13, x9, x10)

inst_7823:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23406*FLEN/8, x13, x9, x10)

inst_7824:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:23409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23409*FLEN/8, x13, x9, x10)

inst_7825:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:23412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23412*FLEN/8, x13, x9, x10)

inst_7826:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:23415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23415*FLEN/8, x13, x9, x10)

inst_7827:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:23418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23418*FLEN/8, x13, x9, x10)

inst_7828:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:23421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23421*FLEN/8, x13, x9, x10)

inst_7829:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23424*FLEN/8, x13, x9, x10)

inst_7830:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23427*FLEN/8, x13, x9, x10)

inst_7831:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23430*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_61)

inst_7832:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:23433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23433*FLEN/8, x13, x9, x10)

inst_7833:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:23436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23436*FLEN/8, x13, x9, x10)

inst_7834:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:23439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23439*FLEN/8, x13, x9, x10)

inst_7835:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:23442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23442*FLEN/8, x13, x9, x10)

inst_7836:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23445*FLEN/8, x13, x9, x10)

inst_7837:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23448*FLEN/8, x13, x9, x10)

inst_7838:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23451*FLEN/8, x13, x9, x10)

inst_7839:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:23454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23454*FLEN/8, x13, x9, x10)

inst_7840:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23457*FLEN/8, x13, x9, x10)

inst_7841:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23460*FLEN/8, x13, x9, x10)

inst_7842:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23463*FLEN/8, x13, x9, x10)

inst_7843:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23466*FLEN/8, x13, x9, x10)

inst_7844:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23469*FLEN/8, x13, x9, x10)

inst_7845:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23472*FLEN/8, x13, x9, x10)

inst_7846:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23475*FLEN/8, x13, x9, x10)

inst_7847:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23478*FLEN/8, x13, x9, x10)

inst_7848:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:23481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23481*FLEN/8, x13, x9, x10)

inst_7849:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:23484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23484*FLEN/8, x13, x9, x10)

inst_7850:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:23487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23487*FLEN/8, x13, x9, x10)

inst_7851:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:23490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23490*FLEN/8, x13, x9, x10)

inst_7852:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:23493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23493*FLEN/8, x13, x9, x10)

inst_7853:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23496*FLEN/8, x13, x9, x10)

inst_7854:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23499*FLEN/8, x13, x9, x10)

inst_7855:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23502*FLEN/8, x13, x9, x10)

inst_7856:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:23505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23505*FLEN/8, x13, x9, x10)

inst_7857:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:23508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23508*FLEN/8, x13, x9, x10)

inst_7858:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:23511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23511*FLEN/8, x13, x9, x10)

inst_7859:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:23514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23514*FLEN/8, x13, x9, x10)

inst_7860:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23517*FLEN/8, x13, x9, x10)

inst_7861:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23520*FLEN/8, x13, x9, x10)

inst_7862:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23523*FLEN/8, x13, x9, x10)

inst_7863:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:23526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23526*FLEN/8, x13, x9, x10)

inst_7864:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23529*FLEN/8, x13, x9, x10)

inst_7865:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23532*FLEN/8, x13, x9, x10)

inst_7866:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23535*FLEN/8, x13, x9, x10)

inst_7867:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23538*FLEN/8, x13, x9, x10)

inst_7868:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23541*FLEN/8, x13, x9, x10)

inst_7869:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23544*FLEN/8, x13, x9, x10)

inst_7870:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23547*FLEN/8, x13, x9, x10)

inst_7871:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23550*FLEN/8, x13, x9, x10)

inst_7872:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:23553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23553*FLEN/8, x13, x9, x10)

inst_7873:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:23556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23556*FLEN/8, x13, x9, x10)

inst_7874:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:23559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23559*FLEN/8, x13, x9, x10)

inst_7875:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:23562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23562*FLEN/8, x13, x9, x10)

inst_7876:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:23565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23565*FLEN/8, x13, x9, x10)

inst_7877:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23568*FLEN/8, x13, x9, x10)

inst_7878:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23571*FLEN/8, x13, x9, x10)

inst_7879:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23574*FLEN/8, x13, x9, x10)

inst_7880:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:23577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23577*FLEN/8, x13, x9, x10)

inst_7881:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:23580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23580*FLEN/8, x13, x9, x10)

inst_7882:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:23583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23583*FLEN/8, x13, x9, x10)

inst_7883:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:23586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23586*FLEN/8, x13, x9, x10)

inst_7884:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23589*FLEN/8, x13, x9, x10)

inst_7885:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23592*FLEN/8, x13, x9, x10)

inst_7886:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23595*FLEN/8, x13, x9, x10)

inst_7887:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:23598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23598*FLEN/8, x13, x9, x10)

inst_7888:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23601*FLEN/8, x13, x9, x10)

inst_7889:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23604*FLEN/8, x13, x9, x10)

inst_7890:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23607*FLEN/8, x13, x9, x10)

inst_7891:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23610*FLEN/8, x13, x9, x10)

inst_7892:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23613*FLEN/8, x13, x9, x10)

inst_7893:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23616*FLEN/8, x13, x9, x10)

inst_7894:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23619*FLEN/8, x13, x9, x10)

inst_7895:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23622*FLEN/8, x13, x9, x10)

inst_7896:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:23625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23625*FLEN/8, x13, x9, x10)

inst_7897:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:23628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23628*FLEN/8, x13, x9, x10)

inst_7898:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:23631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23631*FLEN/8, x13, x9, x10)

inst_7899:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:23634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23634*FLEN/8, x13, x9, x10)

inst_7900:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:23637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23637*FLEN/8, x13, x9, x10)

inst_7901:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23640*FLEN/8, x13, x9, x10)

inst_7902:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23643*FLEN/8, x13, x9, x10)

inst_7903:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23646*FLEN/8, x13, x9, x10)

inst_7904:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:23649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23649*FLEN/8, x13, x9, x10)

inst_7905:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:23652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23652*FLEN/8, x13, x9, x10)

inst_7906:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:23655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23655*FLEN/8, x13, x9, x10)

inst_7907:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:23658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23658*FLEN/8, x13, x9, x10)

inst_7908:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23661*FLEN/8, x13, x9, x10)

inst_7909:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23664*FLEN/8, x13, x9, x10)

inst_7910:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23667*FLEN/8, x13, x9, x10)

inst_7911:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:23670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23670*FLEN/8, x13, x9, x10)

inst_7912:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23673*FLEN/8, x13, x9, x10)

inst_7913:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23676*FLEN/8, x13, x9, x10)

inst_7914:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23679*FLEN/8, x13, x9, x10)

inst_7915:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23682*FLEN/8, x13, x9, x10)

inst_7916:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23685*FLEN/8, x13, x9, x10)

inst_7917:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23688*FLEN/8, x13, x9, x10)

inst_7918:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23691*FLEN/8, x13, x9, x10)

inst_7919:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23694*FLEN/8, x13, x9, x10)

inst_7920:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:23697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23697*FLEN/8, x13, x9, x10)

inst_7921:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:23700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23700*FLEN/8, x13, x9, x10)

inst_7922:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:23703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23703*FLEN/8, x13, x9, x10)

inst_7923:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:23706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23706*FLEN/8, x13, x9, x10)

inst_7924:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:23709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23709*FLEN/8, x13, x9, x10)

inst_7925:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23712*FLEN/8, x13, x9, x10)

inst_7926:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23715*FLEN/8, x13, x9, x10)

inst_7927:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23718*FLEN/8, x13, x9, x10)

inst_7928:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:23721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23721*FLEN/8, x13, x9, x10)

inst_7929:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:23724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23724*FLEN/8, x13, x9, x10)

inst_7930:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:23727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23727*FLEN/8, x13, x9, x10)

inst_7931:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:23730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23730*FLEN/8, x13, x9, x10)

inst_7932:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23733*FLEN/8, x13, x9, x10)

inst_7933:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23736*FLEN/8, x13, x9, x10)

inst_7934:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23739*FLEN/8, x13, x9, x10)

inst_7935:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:23742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23742*FLEN/8, x13, x9, x10)

inst_7936:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23745*FLEN/8, x13, x9, x10)

inst_7937:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23748*FLEN/8, x13, x9, x10)

inst_7938:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23751*FLEN/8, x13, x9, x10)

inst_7939:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23754*FLEN/8, x13, x9, x10)

inst_7940:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23757*FLEN/8, x13, x9, x10)

inst_7941:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23760*FLEN/8, x13, x9, x10)

inst_7942:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23763*FLEN/8, x13, x9, x10)

inst_7943:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23766*FLEN/8, x13, x9, x10)

inst_7944:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:23769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23769*FLEN/8, x13, x9, x10)

inst_7945:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:23772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23772*FLEN/8, x13, x9, x10)

inst_7946:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:23775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23775*FLEN/8, x13, x9, x10)

inst_7947:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:23778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23778*FLEN/8, x13, x9, x10)

inst_7948:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:23781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23781*FLEN/8, x13, x9, x10)

inst_7949:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23784*FLEN/8, x13, x9, x10)

inst_7950:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23787*FLEN/8, x13, x9, x10)

inst_7951:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23790*FLEN/8, x13, x9, x10)

inst_7952:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:23793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23793*FLEN/8, x13, x9, x10)

inst_7953:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:23796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23796*FLEN/8, x13, x9, x10)

inst_7954:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:23799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23799*FLEN/8, x13, x9, x10)

inst_7955:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:23802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23802*FLEN/8, x13, x9, x10)

inst_7956:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23805*FLEN/8, x13, x9, x10)

inst_7957:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23808*FLEN/8, x13, x9, x10)

inst_7958:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23811*FLEN/8, x13, x9, x10)

inst_7959:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:23814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23814*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_62)

inst_7960:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23817*FLEN/8, x13, x9, x10)

inst_7961:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23820*FLEN/8, x13, x9, x10)

inst_7962:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23823*FLEN/8, x13, x9, x10)

inst_7963:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23826*FLEN/8, x13, x9, x10)

inst_7964:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23829*FLEN/8, x13, x9, x10)

inst_7965:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23832*FLEN/8, x13, x9, x10)

inst_7966:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23835*FLEN/8, x13, x9, x10)

inst_7967:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23838*FLEN/8, x13, x9, x10)

inst_7968:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:23841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23841*FLEN/8, x13, x9, x10)

inst_7969:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:23844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23844*FLEN/8, x13, x9, x10)

inst_7970:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:23847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23847*FLEN/8, x13, x9, x10)

inst_7971:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:23850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23850*FLEN/8, x13, x9, x10)

inst_7972:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:23853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23853*FLEN/8, x13, x9, x10)

inst_7973:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23856*FLEN/8, x13, x9, x10)

inst_7974:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23859*FLEN/8, x13, x9, x10)

inst_7975:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23862*FLEN/8, x13, x9, x10)

inst_7976:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:23865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23865*FLEN/8, x13, x9, x10)

inst_7977:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:23868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23868*FLEN/8, x13, x9, x10)

inst_7978:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:23871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23871*FLEN/8, x13, x9, x10)

inst_7979:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:23874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23874*FLEN/8, x13, x9, x10)

inst_7980:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23877*FLEN/8, x13, x9, x10)

inst_7981:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23880*FLEN/8, x13, x9, x10)

inst_7982:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23883*FLEN/8, x13, x9, x10)

inst_7983:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:23886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23886*FLEN/8, x13, x9, x10)

inst_7984:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23889*FLEN/8, x13, x9, x10)

inst_7985:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23892*FLEN/8, x13, x9, x10)

inst_7986:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23895*FLEN/8, x13, x9, x10)

inst_7987:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23898*FLEN/8, x13, x9, x10)

inst_7988:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23901*FLEN/8, x13, x9, x10)

inst_7989:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23904*FLEN/8, x13, x9, x10)

inst_7990:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23907*FLEN/8, x13, x9, x10)

inst_7991:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23910*FLEN/8, x13, x9, x10)

inst_7992:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:23913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23913*FLEN/8, x13, x9, x10)

inst_7993:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:23916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23916*FLEN/8, x13, x9, x10)

inst_7994:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:23919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23919*FLEN/8, x13, x9, x10)

inst_7995:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:23922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23922*FLEN/8, x13, x9, x10)

inst_7996:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:23925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23925*FLEN/8, x13, x9, x10)

inst_7997:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:23928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23928*FLEN/8, x13, x9, x10)

inst_7998:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:23931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23931*FLEN/8, x13, x9, x10)

inst_7999:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:23934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23934*FLEN/8, x13, x9, x10)

inst_8000:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:23937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23937*FLEN/8, x13, x9, x10)

inst_8001:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:23940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23940*FLEN/8, x13, x9, x10)

inst_8002:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:23943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23943*FLEN/8, x13, x9, x10)

inst_8003:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:23946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23946*FLEN/8, x13, x9, x10)

inst_8004:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:23949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23949*FLEN/8, x13, x9, x10)

inst_8005:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:23952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23952*FLEN/8, x13, x9, x10)

inst_8006:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:23955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23955*FLEN/8, x13, x9, x10)

inst_8007:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:23958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23958*FLEN/8, x13, x9, x10)

inst_8008:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:23961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23961*FLEN/8, x13, x9, x10)

inst_8009:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:23964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23964*FLEN/8, x13, x9, x10)

inst_8010:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:23967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23967*FLEN/8, x13, x9, x10)

inst_8011:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:23970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23970*FLEN/8, x13, x9, x10)

inst_8012:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:23973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23973*FLEN/8, x13, x9, x10)

inst_8013:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:23976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23976*FLEN/8, x13, x9, x10)

inst_8014:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:23979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23979*FLEN/8, x13, x9, x10)

inst_8015:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:23982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23982*FLEN/8, x13, x9, x10)

inst_8016:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:23985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23985*FLEN/8, x13, x9, x10)

inst_8017:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:23988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23988*FLEN/8, x13, x9, x10)

inst_8018:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:23991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23991*FLEN/8, x13, x9, x10)

inst_8019:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:23994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23994*FLEN/8, x13, x9, x10)

inst_8020:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:23997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23997*FLEN/8, x13, x9, x10)

inst_8021:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24000*FLEN/8, x13, x9, x10)

inst_8022:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24003*FLEN/8, x13, x9, x10)

inst_8023:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24006*FLEN/8, x13, x9, x10)

inst_8024:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:24009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24009*FLEN/8, x13, x9, x10)

inst_8025:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:24012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24012*FLEN/8, x13, x9, x10)

inst_8026:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:24015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24015*FLEN/8, x13, x9, x10)

inst_8027:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:24018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24018*FLEN/8, x13, x9, x10)

inst_8028:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24021*FLEN/8, x13, x9, x10)

inst_8029:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24024*FLEN/8, x13, x9, x10)

inst_8030:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24027*FLEN/8, x13, x9, x10)

inst_8031:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:24030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24030*FLEN/8, x13, x9, x10)

inst_8032:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24033*FLEN/8, x13, x9, x10)

inst_8033:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24036*FLEN/8, x13, x9, x10)

inst_8034:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24039*FLEN/8, x13, x9, x10)

inst_8035:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24042*FLEN/8, x13, x9, x10)

inst_8036:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24045*FLEN/8, x13, x9, x10)

inst_8037:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24048*FLEN/8, x13, x9, x10)

inst_8038:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24051*FLEN/8, x13, x9, x10)

inst_8039:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24054*FLEN/8, x13, x9, x10)

inst_8040:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:24057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24057*FLEN/8, x13, x9, x10)

inst_8041:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:24060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24060*FLEN/8, x13, x9, x10)

inst_8042:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:24063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24063*FLEN/8, x13, x9, x10)

inst_8043:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:24066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24066*FLEN/8, x13, x9, x10)

inst_8044:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:24069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24069*FLEN/8, x13, x9, x10)

inst_8045:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24072*FLEN/8, x13, x9, x10)

inst_8046:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24075*FLEN/8, x13, x9, x10)

inst_8047:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24078*FLEN/8, x13, x9, x10)

inst_8048:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:24081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24081*FLEN/8, x13, x9, x10)

inst_8049:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:24084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24084*FLEN/8, x13, x9, x10)

inst_8050:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:24087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24087*FLEN/8, x13, x9, x10)

inst_8051:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:24090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24090*FLEN/8, x13, x9, x10)

inst_8052:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24093*FLEN/8, x13, x9, x10)

inst_8053:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24096*FLEN/8, x13, x9, x10)

inst_8054:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24099*FLEN/8, x13, x9, x10)

inst_8055:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:24102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24102*FLEN/8, x13, x9, x10)

inst_8056:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24105*FLEN/8, x13, x9, x10)

inst_8057:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24108*FLEN/8, x13, x9, x10)

inst_8058:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24111*FLEN/8, x13, x9, x10)

inst_8059:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24114*FLEN/8, x13, x9, x10)

inst_8060:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24117*FLEN/8, x13, x9, x10)

inst_8061:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24120*FLEN/8, x13, x9, x10)

inst_8062:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24123*FLEN/8, x13, x9, x10)

inst_8063:
// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24126*FLEN/8, x13, x9, x10)

inst_8064:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:24129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24129*FLEN/8, x13, x9, x10)

inst_8065:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:24132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24132*FLEN/8, x13, x9, x10)

inst_8066:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:24135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24135*FLEN/8, x13, x9, x10)

inst_8067:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:24138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24138*FLEN/8, x13, x9, x10)

inst_8068:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:24141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24141*FLEN/8, x13, x9, x10)

inst_8069:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24144*FLEN/8, x13, x9, x10)

inst_8070:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24147*FLEN/8, x13, x9, x10)

inst_8071:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24150*FLEN/8, x13, x9, x10)

inst_8072:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:24153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24153*FLEN/8, x13, x9, x10)

inst_8073:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:24156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24156*FLEN/8, x13, x9, x10)

inst_8074:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:24159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24159*FLEN/8, x13, x9, x10)

inst_8075:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:24162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24162*FLEN/8, x13, x9, x10)

inst_8076:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24165*FLEN/8, x13, x9, x10)

inst_8077:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24168*FLEN/8, x13, x9, x10)

inst_8078:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24171*FLEN/8, x13, x9, x10)

inst_8079:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:24174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24174*FLEN/8, x13, x9, x10)

inst_8080:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24177*FLEN/8, x13, x9, x10)

inst_8081:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24180*FLEN/8, x13, x9, x10)

inst_8082:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24183*FLEN/8, x13, x9, x10)

inst_8083:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24186*FLEN/8, x13, x9, x10)

inst_8084:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24189*FLEN/8, x13, x9, x10)

inst_8085:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24192*FLEN/8, x13, x9, x10)

inst_8086:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24195*FLEN/8, x13, x9, x10)

inst_8087:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24198*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_63)

inst_8088:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:24201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24201*FLEN/8, x13, x9, x10)

inst_8089:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:24204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24204*FLEN/8, x13, x9, x10)

inst_8090:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:24207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24207*FLEN/8, x13, x9, x10)

inst_8091:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:24210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24210*FLEN/8, x13, x9, x10)

inst_8092:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:24213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24213*FLEN/8, x13, x9, x10)

inst_8093:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24216*FLEN/8, x13, x9, x10)

inst_8094:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24219*FLEN/8, x13, x9, x10)

inst_8095:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24222*FLEN/8, x13, x9, x10)

inst_8096:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:24225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24225*FLEN/8, x13, x9, x10)

inst_8097:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:24228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24228*FLEN/8, x13, x9, x10)

inst_8098:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:24231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24231*FLEN/8, x13, x9, x10)

inst_8099:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:24234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24234*FLEN/8, x13, x9, x10)

inst_8100:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24237*FLEN/8, x13, x9, x10)

inst_8101:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24240*FLEN/8, x13, x9, x10)

inst_8102:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24243*FLEN/8, x13, x9, x10)

inst_8103:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:24246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24246*FLEN/8, x13, x9, x10)

inst_8104:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24249*FLEN/8, x13, x9, x10)

inst_8105:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24252*FLEN/8, x13, x9, x10)

inst_8106:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24255*FLEN/8, x13, x9, x10)

inst_8107:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24258*FLEN/8, x13, x9, x10)

inst_8108:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24261*FLEN/8, x13, x9, x10)

inst_8109:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24264*FLEN/8, x13, x9, x10)

inst_8110:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24267*FLEN/8, x13, x9, x10)

inst_8111:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24270*FLEN/8, x13, x9, x10)

inst_8112:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:24273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24273*FLEN/8, x13, x9, x10)

inst_8113:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:24276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24276*FLEN/8, x13, x9, x10)

inst_8114:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:24279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24279*FLEN/8, x13, x9, x10)

inst_8115:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:24282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24282*FLEN/8, x13, x9, x10)

inst_8116:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:24285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24285*FLEN/8, x13, x9, x10)

inst_8117:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24288*FLEN/8, x13, x9, x10)

inst_8118:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24291*FLEN/8, x13, x9, x10)

inst_8119:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24294*FLEN/8, x13, x9, x10)

inst_8120:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:24297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24297*FLEN/8, x13, x9, x10)

inst_8121:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:24300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24300*FLEN/8, x13, x9, x10)

inst_8122:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:24303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24303*FLEN/8, x13, x9, x10)

inst_8123:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:24306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24306*FLEN/8, x13, x9, x10)

inst_8124:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24309*FLEN/8, x13, x9, x10)

inst_8125:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24312*FLEN/8, x13, x9, x10)

inst_8126:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24315*FLEN/8, x13, x9, x10)

inst_8127:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:24318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24318*FLEN/8, x13, x9, x10)

inst_8128:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24321*FLEN/8, x13, x9, x10)

inst_8129:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24324*FLEN/8, x13, x9, x10)

inst_8130:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24327*FLEN/8, x13, x9, x10)

inst_8131:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24330*FLEN/8, x13, x9, x10)

inst_8132:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24333*FLEN/8, x13, x9, x10)

inst_8133:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24336*FLEN/8, x13, x9, x10)

inst_8134:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24339*FLEN/8, x13, x9, x10)

inst_8135:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24342*FLEN/8, x13, x9, x10)

inst_8136:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:24345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24345*FLEN/8, x13, x9, x10)

inst_8137:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:24348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24348*FLEN/8, x13, x9, x10)

inst_8138:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:24351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24351*FLEN/8, x13, x9, x10)

inst_8139:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:24354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24354*FLEN/8, x13, x9, x10)

inst_8140:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:24357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24357*FLEN/8, x13, x9, x10)

inst_8141:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24360*FLEN/8, x13, x9, x10)

inst_8142:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24363*FLEN/8, x13, x9, x10)

inst_8143:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24366*FLEN/8, x13, x9, x10)

inst_8144:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:24369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24369*FLEN/8, x13, x9, x10)

inst_8145:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:24372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24372*FLEN/8, x13, x9, x10)

inst_8146:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:24375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24375*FLEN/8, x13, x9, x10)

inst_8147:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:24378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24378*FLEN/8, x13, x9, x10)

inst_8148:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24381*FLEN/8, x13, x9, x10)

inst_8149:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24384*FLEN/8, x13, x9, x10)

inst_8150:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24387*FLEN/8, x13, x9, x10)

inst_8151:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:24390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24390*FLEN/8, x13, x9, x10)

inst_8152:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24393*FLEN/8, x13, x9, x10)

inst_8153:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24396*FLEN/8, x13, x9, x10)

inst_8154:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24399*FLEN/8, x13, x9, x10)

inst_8155:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24402*FLEN/8, x13, x9, x10)

inst_8156:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24405*FLEN/8, x13, x9, x10)

inst_8157:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24408*FLEN/8, x13, x9, x10)

inst_8158:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24411*FLEN/8, x13, x9, x10)

inst_8159:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24414*FLEN/8, x13, x9, x10)

inst_8160:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:24417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24417*FLEN/8, x13, x9, x10)

inst_8161:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:24420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24420*FLEN/8, x13, x9, x10)

inst_8162:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:24423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24423*FLEN/8, x13, x9, x10)

inst_8163:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:24426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24426*FLEN/8, x13, x9, x10)

inst_8164:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:24429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24429*FLEN/8, x13, x9, x10)

inst_8165:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24432*FLEN/8, x13, x9, x10)

inst_8166:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24435*FLEN/8, x13, x9, x10)

inst_8167:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24438*FLEN/8, x13, x9, x10)

inst_8168:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:24441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24441*FLEN/8, x13, x9, x10)

inst_8169:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:24444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24444*FLEN/8, x13, x9, x10)

inst_8170:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:24447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24447*FLEN/8, x13, x9, x10)

inst_8171:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:24450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24450*FLEN/8, x13, x9, x10)

inst_8172:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24453*FLEN/8, x13, x9, x10)

inst_8173:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24456*FLEN/8, x13, x9, x10)

inst_8174:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24459*FLEN/8, x13, x9, x10)

inst_8175:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:24462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24462*FLEN/8, x13, x9, x10)

inst_8176:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24465*FLEN/8, x13, x9, x10)

inst_8177:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24468*FLEN/8, x13, x9, x10)

inst_8178:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24471*FLEN/8, x13, x9, x10)

inst_8179:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24474*FLEN/8, x13, x9, x10)

inst_8180:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24477*FLEN/8, x13, x9, x10)

inst_8181:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24480*FLEN/8, x13, x9, x10)

inst_8182:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24483*FLEN/8, x13, x9, x10)

inst_8183:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24486*FLEN/8, x13, x9, x10)

inst_8184:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:24489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24489*FLEN/8, x13, x9, x10)

inst_8185:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:24492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24492*FLEN/8, x13, x9, x10)

inst_8186:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:24495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24495*FLEN/8, x13, x9, x10)

inst_8187:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:24498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24498*FLEN/8, x13, x9, x10)

inst_8188:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:24501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24501*FLEN/8, x13, x9, x10)

inst_8189:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24504*FLEN/8, x13, x9, x10)

inst_8190:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24507*FLEN/8, x13, x9, x10)

inst_8191:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24510*FLEN/8, x13, x9, x10)

inst_8192:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:24513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24513*FLEN/8, x13, x9, x10)

inst_8193:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:24516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24516*FLEN/8, x13, x9, x10)

inst_8194:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:24519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24519*FLEN/8, x13, x9, x10)

inst_8195:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:24522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24522*FLEN/8, x13, x9, x10)

inst_8196:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24525*FLEN/8, x13, x9, x10)

inst_8197:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24528*FLEN/8, x13, x9, x10)

inst_8198:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24531*FLEN/8, x13, x9, x10)

inst_8199:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:24534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24534*FLEN/8, x13, x9, x10)

inst_8200:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24537*FLEN/8, x13, x9, x10)

inst_8201:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24540*FLEN/8, x13, x9, x10)

inst_8202:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24543*FLEN/8, x13, x9, x10)

inst_8203:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24546*FLEN/8, x13, x9, x10)

inst_8204:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24549*FLEN/8, x13, x9, x10)

inst_8205:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24552*FLEN/8, x13, x9, x10)

inst_8206:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24555*FLEN/8, x13, x9, x10)

inst_8207:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24558*FLEN/8, x13, x9, x10)

inst_8208:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:24561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24561*FLEN/8, x13, x9, x10)

inst_8209:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:24564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24564*FLEN/8, x13, x9, x10)

inst_8210:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:24567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24567*FLEN/8, x13, x9, x10)

inst_8211:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:24570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24570*FLEN/8, x13, x9, x10)

inst_8212:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:24573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24573*FLEN/8, x13, x9, x10)

inst_8213:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24576*FLEN/8, x13, x9, x10)

inst_8214:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24579*FLEN/8, x13, x9, x10)

inst_8215:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24582*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_64)

inst_8216:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:24585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24585*FLEN/8, x13, x9, x10)

inst_8217:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:24588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24588*FLEN/8, x13, x9, x10)

inst_8218:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:24591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24591*FLEN/8, x13, x9, x10)

inst_8219:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:24594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24594*FLEN/8, x13, x9, x10)

inst_8220:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24597*FLEN/8, x13, x9, x10)

inst_8221:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24600*FLEN/8, x13, x9, x10)

inst_8222:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24603*FLEN/8, x13, x9, x10)

inst_8223:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:24606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24606*FLEN/8, x13, x9, x10)

inst_8224:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24609*FLEN/8, x13, x9, x10)

inst_8225:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24612*FLEN/8, x13, x9, x10)

inst_8226:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24615*FLEN/8, x13, x9, x10)

inst_8227:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24618*FLEN/8, x13, x9, x10)

inst_8228:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24621*FLEN/8, x13, x9, x10)

inst_8229:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24624*FLEN/8, x13, x9, x10)

inst_8230:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24627*FLEN/8, x13, x9, x10)

inst_8231:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24630*FLEN/8, x13, x9, x10)

inst_8232:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:24633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24633*FLEN/8, x13, x9, x10)

inst_8233:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:24636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24636*FLEN/8, x13, x9, x10)

inst_8234:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:24639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24639*FLEN/8, x13, x9, x10)

inst_8235:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:24642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24642*FLEN/8, x13, x9, x10)

inst_8236:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:24645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24645*FLEN/8, x13, x9, x10)

inst_8237:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24648*FLEN/8, x13, x9, x10)

inst_8238:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24651*FLEN/8, x13, x9, x10)

inst_8239:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24654*FLEN/8, x13, x9, x10)

inst_8240:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:24657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24657*FLEN/8, x13, x9, x10)

inst_8241:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:24660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24660*FLEN/8, x13, x9, x10)

inst_8242:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:24663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24663*FLEN/8, x13, x9, x10)

inst_8243:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:24666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24666*FLEN/8, x13, x9, x10)

inst_8244:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24669*FLEN/8, x13, x9, x10)

inst_8245:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24672*FLEN/8, x13, x9, x10)

inst_8246:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24675*FLEN/8, x13, x9, x10)

inst_8247:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:24678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24678*FLEN/8, x13, x9, x10)

inst_8248:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24681*FLEN/8, x13, x9, x10)

inst_8249:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24684*FLEN/8, x13, x9, x10)

inst_8250:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24687*FLEN/8, x13, x9, x10)

inst_8251:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24690*FLEN/8, x13, x9, x10)

inst_8252:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24693*FLEN/8, x13, x9, x10)

inst_8253:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24696*FLEN/8, x13, x9, x10)

inst_8254:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24699*FLEN/8, x13, x9, x10)

inst_8255:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24702*FLEN/8, x13, x9, x10)

inst_8256:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:24705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24705*FLEN/8, x13, x9, x10)

inst_8257:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:24708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24708*FLEN/8, x13, x9, x10)

inst_8258:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:24711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24711*FLEN/8, x13, x9, x10)

inst_8259:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:24714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24714*FLEN/8, x13, x9, x10)

inst_8260:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:24717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24717*FLEN/8, x13, x9, x10)

inst_8261:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24720*FLEN/8, x13, x9, x10)

inst_8262:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24723*FLEN/8, x13, x9, x10)

inst_8263:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24726*FLEN/8, x13, x9, x10)

inst_8264:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:24729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24729*FLEN/8, x13, x9, x10)

inst_8265:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:24732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24732*FLEN/8, x13, x9, x10)

inst_8266:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:24735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24735*FLEN/8, x13, x9, x10)

inst_8267:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:24738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24738*FLEN/8, x13, x9, x10)

inst_8268:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24741*FLEN/8, x13, x9, x10)

inst_8269:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24744*FLEN/8, x13, x9, x10)

inst_8270:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24747*FLEN/8, x13, x9, x10)

inst_8271:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:24750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24750*FLEN/8, x13, x9, x10)

inst_8272:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24753*FLEN/8, x13, x9, x10)

inst_8273:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24756*FLEN/8, x13, x9, x10)

inst_8274:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24759*FLEN/8, x13, x9, x10)

inst_8275:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24762*FLEN/8, x13, x9, x10)

inst_8276:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24765*FLEN/8, x13, x9, x10)

inst_8277:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24768*FLEN/8, x13, x9, x10)

inst_8278:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24771*FLEN/8, x13, x9, x10)

inst_8279:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24774*FLEN/8, x13, x9, x10)

inst_8280:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:24777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24777*FLEN/8, x13, x9, x10)

inst_8281:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:24780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24780*FLEN/8, x13, x9, x10)

inst_8282:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:24783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24783*FLEN/8, x13, x9, x10)

inst_8283:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:24786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24786*FLEN/8, x13, x9, x10)

inst_8284:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:24789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24789*FLEN/8, x13, x9, x10)

inst_8285:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24792*FLEN/8, x13, x9, x10)

inst_8286:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24795*FLEN/8, x13, x9, x10)

inst_8287:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24798*FLEN/8, x13, x9, x10)

inst_8288:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:24801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24801*FLEN/8, x13, x9, x10)

inst_8289:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:24804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24804*FLEN/8, x13, x9, x10)

inst_8290:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:24807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24807*FLEN/8, x13, x9, x10)

inst_8291:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:24810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24810*FLEN/8, x13, x9, x10)

inst_8292:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24813*FLEN/8, x13, x9, x10)

inst_8293:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24816*FLEN/8, x13, x9, x10)

inst_8294:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24819*FLEN/8, x13, x9, x10)

inst_8295:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:24822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24822*FLEN/8, x13, x9, x10)

inst_8296:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24825*FLEN/8, x13, x9, x10)

inst_8297:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24828*FLEN/8, x13, x9, x10)

inst_8298:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24831*FLEN/8, x13, x9, x10)

inst_8299:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24834*FLEN/8, x13, x9, x10)

inst_8300:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24837*FLEN/8, x13, x9, x10)

inst_8301:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24840*FLEN/8, x13, x9, x10)

inst_8302:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24843*FLEN/8, x13, x9, x10)

inst_8303:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24846*FLEN/8, x13, x9, x10)

inst_8304:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:24849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24849*FLEN/8, x13, x9, x10)

inst_8305:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:24852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24852*FLEN/8, x13, x9, x10)

inst_8306:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:24855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24855*FLEN/8, x13, x9, x10)

inst_8307:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:24858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24858*FLEN/8, x13, x9, x10)

inst_8308:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:24861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24861*FLEN/8, x13, x9, x10)

inst_8309:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24864*FLEN/8, x13, x9, x10)

inst_8310:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24867*FLEN/8, x13, x9, x10)

inst_8311:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24870*FLEN/8, x13, x9, x10)

inst_8312:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:24873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24873*FLEN/8, x13, x9, x10)

inst_8313:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:24876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24876*FLEN/8, x13, x9, x10)

inst_8314:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:24879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24879*FLEN/8, x13, x9, x10)

inst_8315:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:24882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24882*FLEN/8, x13, x9, x10)

inst_8316:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24885*FLEN/8, x13, x9, x10)

inst_8317:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24888*FLEN/8, x13, x9, x10)

inst_8318:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24891*FLEN/8, x13, x9, x10)

inst_8319:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:24894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24894*FLEN/8, x13, x9, x10)

inst_8320:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24897*FLEN/8, x13, x9, x10)

inst_8321:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24900*FLEN/8, x13, x9, x10)

inst_8322:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24903*FLEN/8, x13, x9, x10)

inst_8323:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24906*FLEN/8, x13, x9, x10)

inst_8324:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24909*FLEN/8, x13, x9, x10)

inst_8325:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24912*FLEN/8, x13, x9, x10)

inst_8326:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24915*FLEN/8, x13, x9, x10)

inst_8327:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24918*FLEN/8, x13, x9, x10)

inst_8328:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:24921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24921*FLEN/8, x13, x9, x10)

inst_8329:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:24924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24924*FLEN/8, x13, x9, x10)

inst_8330:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:24927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24927*FLEN/8, x13, x9, x10)

inst_8331:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:24930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24930*FLEN/8, x13, x9, x10)

inst_8332:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:24933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24933*FLEN/8, x13, x9, x10)

inst_8333:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:24936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24936*FLEN/8, x13, x9, x10)

inst_8334:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:24939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24939*FLEN/8, x13, x9, x10)

inst_8335:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:24942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24942*FLEN/8, x13, x9, x10)

inst_8336:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:24945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24945*FLEN/8, x13, x9, x10)

inst_8337:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:24948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24948*FLEN/8, x13, x9, x10)

inst_8338:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:24951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24951*FLEN/8, x13, x9, x10)

inst_8339:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:24954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24954*FLEN/8, x13, x9, x10)

inst_8340:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:24957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24957*FLEN/8, x13, x9, x10)

inst_8341:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:24960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24960*FLEN/8, x13, x9, x10)

inst_8342:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:24963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24963*FLEN/8, x13, x9, x10)

inst_8343:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:24966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24966*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_65)

inst_8344:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:24969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24969*FLEN/8, x13, x9, x10)

inst_8345:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:24972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24972*FLEN/8, x13, x9, x10)

inst_8346:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:24975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24975*FLEN/8, x13, x9, x10)

inst_8347:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:24978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24978*FLEN/8, x13, x9, x10)

inst_8348:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:24981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24981*FLEN/8, x13, x9, x10)

inst_8349:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:24984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24984*FLEN/8, x13, x9, x10)

inst_8350:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:24987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24987*FLEN/8, x13, x9, x10)

inst_8351:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:24990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24990*FLEN/8, x13, x9, x10)

inst_8352:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:24993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24993*FLEN/8, x13, x9, x10)

inst_8353:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:24996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24996*FLEN/8, x13, x9, x10)

inst_8354:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:24999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24999*FLEN/8, x13, x9, x10)

inst_8355:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:25002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25002*FLEN/8, x13, x9, x10)

inst_8356:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:25005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25005*FLEN/8, x13, x9, x10)

inst_8357:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25008*FLEN/8, x13, x9, x10)

inst_8358:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25011*FLEN/8, x13, x9, x10)

inst_8359:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25014*FLEN/8, x13, x9, x10)

inst_8360:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:25017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25017*FLEN/8, x13, x9, x10)

inst_8361:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:25020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25020*FLEN/8, x13, x9, x10)

inst_8362:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:25023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25023*FLEN/8, x13, x9, x10)

inst_8363:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:25026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25026*FLEN/8, x13, x9, x10)

inst_8364:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25029*FLEN/8, x13, x9, x10)

inst_8365:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25032*FLEN/8, x13, x9, x10)

inst_8366:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25035*FLEN/8, x13, x9, x10)

inst_8367:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:25038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25038*FLEN/8, x13, x9, x10)

inst_8368:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25041*FLEN/8, x13, x9, x10)

inst_8369:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25044*FLEN/8, x13, x9, x10)

inst_8370:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25047*FLEN/8, x13, x9, x10)

inst_8371:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25050*FLEN/8, x13, x9, x10)

inst_8372:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25053*FLEN/8, x13, x9, x10)

inst_8373:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25056*FLEN/8, x13, x9, x10)

inst_8374:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25059*FLEN/8, x13, x9, x10)

inst_8375:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25062*FLEN/8, x13, x9, x10)

inst_8376:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:25065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25065*FLEN/8, x13, x9, x10)

inst_8377:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:25068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25068*FLEN/8, x13, x9, x10)

inst_8378:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:25071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25071*FLEN/8, x13, x9, x10)

inst_8379:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:25074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25074*FLEN/8, x13, x9, x10)

inst_8380:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:25077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25077*FLEN/8, x13, x9, x10)

inst_8381:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25080*FLEN/8, x13, x9, x10)

inst_8382:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25083*FLEN/8, x13, x9, x10)

inst_8383:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25086*FLEN/8, x13, x9, x10)

inst_8384:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:25089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25089*FLEN/8, x13, x9, x10)

inst_8385:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:25092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25092*FLEN/8, x13, x9, x10)

inst_8386:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:25095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25095*FLEN/8, x13, x9, x10)

inst_8387:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:25098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25098*FLEN/8, x13, x9, x10)

inst_8388:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25101*FLEN/8, x13, x9, x10)

inst_8389:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25104*FLEN/8, x13, x9, x10)

inst_8390:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25107*FLEN/8, x13, x9, x10)

inst_8391:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:25110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25110*FLEN/8, x13, x9, x10)

inst_8392:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25113*FLEN/8, x13, x9, x10)

inst_8393:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25116*FLEN/8, x13, x9, x10)

inst_8394:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25119*FLEN/8, x13, x9, x10)

inst_8395:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25122*FLEN/8, x13, x9, x10)

inst_8396:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25125*FLEN/8, x13, x9, x10)

inst_8397:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25128*FLEN/8, x13, x9, x10)

inst_8398:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25131*FLEN/8, x13, x9, x10)

inst_8399:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25134*FLEN/8, x13, x9, x10)

inst_8400:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:25137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25137*FLEN/8, x13, x9, x10)

inst_8401:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25140*FLEN/8, x13, x9, x10)

inst_8402:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:25143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25143*FLEN/8, x13, x9, x10)

inst_8403:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25146*FLEN/8, x13, x9, x10)

inst_8404:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:25149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25149*FLEN/8, x13, x9, x10)

inst_8405:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25152*FLEN/8, x13, x9, x10)

inst_8406:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25155*FLEN/8, x13, x9, x10)

inst_8407:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25158*FLEN/8, x13, x9, x10)

inst_8408:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:25161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25161*FLEN/8, x13, x9, x10)

inst_8409:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25164*FLEN/8, x13, x9, x10)

inst_8410:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:25167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25167*FLEN/8, x13, x9, x10)

inst_8411:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25170*FLEN/8, x13, x9, x10)

inst_8412:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25173*FLEN/8, x13, x9, x10)

inst_8413:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25176*FLEN/8, x13, x9, x10)

inst_8414:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25179*FLEN/8, x13, x9, x10)

inst_8415:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25182*FLEN/8, x13, x9, x10)

inst_8416:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25185*FLEN/8, x13, x9, x10)

inst_8417:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25188*FLEN/8, x13, x9, x10)

inst_8418:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25191*FLEN/8, x13, x9, x10)

inst_8419:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25194*FLEN/8, x13, x9, x10)

inst_8420:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25197*FLEN/8, x13, x9, x10)

inst_8421:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25200*FLEN/8, x13, x9, x10)

inst_8422:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25203*FLEN/8, x13, x9, x10)

inst_8423:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25206*FLEN/8, x13, x9, x10)

inst_8424:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:25209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25209*FLEN/8, x13, x9, x10)

inst_8425:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25212*FLEN/8, x13, x9, x10)

inst_8426:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:25215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25215*FLEN/8, x13, x9, x10)

inst_8427:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25218*FLEN/8, x13, x9, x10)

inst_8428:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:25221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25221*FLEN/8, x13, x9, x10)

inst_8429:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25224*FLEN/8, x13, x9, x10)

inst_8430:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25227*FLEN/8, x13, x9, x10)

inst_8431:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25230*FLEN/8, x13, x9, x10)

inst_8432:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:25233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25233*FLEN/8, x13, x9, x10)

inst_8433:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25236*FLEN/8, x13, x9, x10)

inst_8434:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:25239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25239*FLEN/8, x13, x9, x10)

inst_8435:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25242*FLEN/8, x13, x9, x10)

inst_8436:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25245*FLEN/8, x13, x9, x10)

inst_8437:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25248*FLEN/8, x13, x9, x10)

inst_8438:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25251*FLEN/8, x13, x9, x10)

inst_8439:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25254*FLEN/8, x13, x9, x10)

inst_8440:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25257*FLEN/8, x13, x9, x10)

inst_8441:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25260*FLEN/8, x13, x9, x10)

inst_8442:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25263*FLEN/8, x13, x9, x10)

inst_8443:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25266*FLEN/8, x13, x9, x10)

inst_8444:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25269*FLEN/8, x13, x9, x10)

inst_8445:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25272*FLEN/8, x13, x9, x10)

inst_8446:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25275*FLEN/8, x13, x9, x10)

inst_8447:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25278*FLEN/8, x13, x9, x10)

inst_8448:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:25281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25281*FLEN/8, x13, x9, x10)

inst_8449:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25284*FLEN/8, x13, x9, x10)

inst_8450:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:25287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25287*FLEN/8, x13, x9, x10)

inst_8451:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25290*FLEN/8, x13, x9, x10)

inst_8452:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:25293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25293*FLEN/8, x13, x9, x10)

inst_8453:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25296*FLEN/8, x13, x9, x10)

inst_8454:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25299*FLEN/8, x13, x9, x10)

inst_8455:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25302*FLEN/8, x13, x9, x10)

inst_8456:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:25305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25305*FLEN/8, x13, x9, x10)

inst_8457:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25308*FLEN/8, x13, x9, x10)

inst_8458:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:25311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25311*FLEN/8, x13, x9, x10)

inst_8459:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25314*FLEN/8, x13, x9, x10)

inst_8460:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25317*FLEN/8, x13, x9, x10)

inst_8461:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25320*FLEN/8, x13, x9, x10)

inst_8462:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25323*FLEN/8, x13, x9, x10)

inst_8463:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25326*FLEN/8, x13, x9, x10)

inst_8464:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25329*FLEN/8, x13, x9, x10)

inst_8465:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25332*FLEN/8, x13, x9, x10)

inst_8466:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25335*FLEN/8, x13, x9, x10)

inst_8467:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25338*FLEN/8, x13, x9, x10)

inst_8468:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25341*FLEN/8, x13, x9, x10)

inst_8469:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25344*FLEN/8, x13, x9, x10)

inst_8470:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25347*FLEN/8, x13, x9, x10)

inst_8471:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25350*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_66)

inst_8472:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:25353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25353*FLEN/8, x13, x9, x10)

inst_8473:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25356*FLEN/8, x13, x9, x10)

inst_8474:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:25359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25359*FLEN/8, x13, x9, x10)

inst_8475:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25362*FLEN/8, x13, x9, x10)

inst_8476:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:25365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25365*FLEN/8, x13, x9, x10)

inst_8477:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25368*FLEN/8, x13, x9, x10)

inst_8478:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25371*FLEN/8, x13, x9, x10)

inst_8479:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25374*FLEN/8, x13, x9, x10)

inst_8480:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:25377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25377*FLEN/8, x13, x9, x10)

inst_8481:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25380*FLEN/8, x13, x9, x10)

inst_8482:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:25383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25383*FLEN/8, x13, x9, x10)

inst_8483:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25386*FLEN/8, x13, x9, x10)

inst_8484:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25389*FLEN/8, x13, x9, x10)

inst_8485:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25392*FLEN/8, x13, x9, x10)

inst_8486:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25395*FLEN/8, x13, x9, x10)

inst_8487:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25398*FLEN/8, x13, x9, x10)

inst_8488:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25401*FLEN/8, x13, x9, x10)

inst_8489:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25404*FLEN/8, x13, x9, x10)

inst_8490:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25407*FLEN/8, x13, x9, x10)

inst_8491:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25410*FLEN/8, x13, x9, x10)

inst_8492:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25413*FLEN/8, x13, x9, x10)

inst_8493:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25416*FLEN/8, x13, x9, x10)

inst_8494:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25419*FLEN/8, x13, x9, x10)

inst_8495:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25422*FLEN/8, x13, x9, x10)

inst_8496:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:25425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25425*FLEN/8, x13, x9, x10)

inst_8497:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:25428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25428*FLEN/8, x13, x9, x10)

inst_8498:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:25431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25431*FLEN/8, x13, x9, x10)

inst_8499:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:25434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25434*FLEN/8, x13, x9, x10)

inst_8500:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:25437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25437*FLEN/8, x13, x9, x10)

inst_8501:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25440*FLEN/8, x13, x9, x10)

inst_8502:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25443*FLEN/8, x13, x9, x10)

inst_8503:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25446*FLEN/8, x13, x9, x10)

inst_8504:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:25449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25449*FLEN/8, x13, x9, x10)

inst_8505:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:25452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25452*FLEN/8, x13, x9, x10)

inst_8506:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:25455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25455*FLEN/8, x13, x9, x10)

inst_8507:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:25458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25458*FLEN/8, x13, x9, x10)

inst_8508:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25461*FLEN/8, x13, x9, x10)

inst_8509:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25464*FLEN/8, x13, x9, x10)

inst_8510:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25467*FLEN/8, x13, x9, x10)

inst_8511:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:25470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25470*FLEN/8, x13, x9, x10)

inst_8512:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25473*FLEN/8, x13, x9, x10)

inst_8513:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25476*FLEN/8, x13, x9, x10)

inst_8514:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25479*FLEN/8, x13, x9, x10)

inst_8515:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25482*FLEN/8, x13, x9, x10)

inst_8516:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25485*FLEN/8, x13, x9, x10)

inst_8517:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25488*FLEN/8, x13, x9, x10)

inst_8518:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25491*FLEN/8, x13, x9, x10)

inst_8519:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25494*FLEN/8, x13, x9, x10)

inst_8520:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:25497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25497*FLEN/8, x13, x9, x10)

inst_8521:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:25500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25500*FLEN/8, x13, x9, x10)

inst_8522:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:25503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25503*FLEN/8, x13, x9, x10)

inst_8523:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:25506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25506*FLEN/8, x13, x9, x10)

inst_8524:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:25509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25509*FLEN/8, x13, x9, x10)

inst_8525:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25512*FLEN/8, x13, x9, x10)

inst_8526:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25515*FLEN/8, x13, x9, x10)

inst_8527:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25518*FLEN/8, x13, x9, x10)

inst_8528:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:25521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25521*FLEN/8, x13, x9, x10)

inst_8529:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:25524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25524*FLEN/8, x13, x9, x10)

inst_8530:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:25527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25527*FLEN/8, x13, x9, x10)

inst_8531:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:25530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25530*FLEN/8, x13, x9, x10)

inst_8532:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25533*FLEN/8, x13, x9, x10)

inst_8533:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25536*FLEN/8, x13, x9, x10)

inst_8534:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25539*FLEN/8, x13, x9, x10)

inst_8535:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:25542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25542*FLEN/8, x13, x9, x10)

inst_8536:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25545*FLEN/8, x13, x9, x10)

inst_8537:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25548*FLEN/8, x13, x9, x10)

inst_8538:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25551*FLEN/8, x13, x9, x10)

inst_8539:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25554*FLEN/8, x13, x9, x10)

inst_8540:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25557*FLEN/8, x13, x9, x10)

inst_8541:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25560*FLEN/8, x13, x9, x10)

inst_8542:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25563*FLEN/8, x13, x9, x10)

inst_8543:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25566*FLEN/8, x13, x9, x10)

inst_8544:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:25569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25569*FLEN/8, x13, x9, x10)

inst_8545:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:25572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25572*FLEN/8, x13, x9, x10)

inst_8546:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:25575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25575*FLEN/8, x13, x9, x10)

inst_8547:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:25578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25578*FLEN/8, x13, x9, x10)

inst_8548:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:25581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25581*FLEN/8, x13, x9, x10)

inst_8549:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25584*FLEN/8, x13, x9, x10)

inst_8550:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25587*FLEN/8, x13, x9, x10)

inst_8551:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25590*FLEN/8, x13, x9, x10)

inst_8552:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:25593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25593*FLEN/8, x13, x9, x10)

inst_8553:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:25596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25596*FLEN/8, x13, x9, x10)

inst_8554:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:25599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25599*FLEN/8, x13, x9, x10)

inst_8555:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:25602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25602*FLEN/8, x13, x9, x10)

inst_8556:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25605*FLEN/8, x13, x9, x10)

inst_8557:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25608*FLEN/8, x13, x9, x10)

inst_8558:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25611*FLEN/8, x13, x9, x10)

inst_8559:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:25614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25614*FLEN/8, x13, x9, x10)

inst_8560:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25617*FLEN/8, x13, x9, x10)

inst_8561:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25620*FLEN/8, x13, x9, x10)

inst_8562:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25623*FLEN/8, x13, x9, x10)

inst_8563:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25626*FLEN/8, x13, x9, x10)

inst_8564:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25629*FLEN/8, x13, x9, x10)

inst_8565:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25632*FLEN/8, x13, x9, x10)

inst_8566:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25635*FLEN/8, x13, x9, x10)

inst_8567:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25638*FLEN/8, x13, x9, x10)

inst_8568:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:25641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25641*FLEN/8, x13, x9, x10)

inst_8569:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:25644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25644*FLEN/8, x13, x9, x10)

inst_8570:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:25647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25647*FLEN/8, x13, x9, x10)

inst_8571:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:25650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25650*FLEN/8, x13, x9, x10)

inst_8572:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:25653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25653*FLEN/8, x13, x9, x10)

inst_8573:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25656*FLEN/8, x13, x9, x10)

inst_8574:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25659*FLEN/8, x13, x9, x10)

inst_8575:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25662*FLEN/8, x13, x9, x10)

inst_8576:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:25665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25665*FLEN/8, x13, x9, x10)

inst_8577:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:25668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25668*FLEN/8, x13, x9, x10)

inst_8578:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:25671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25671*FLEN/8, x13, x9, x10)

inst_8579:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:25674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25674*FLEN/8, x13, x9, x10)

inst_8580:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25677*FLEN/8, x13, x9, x10)

inst_8581:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25680*FLEN/8, x13, x9, x10)

inst_8582:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25683*FLEN/8, x13, x9, x10)

inst_8583:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:25686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25686*FLEN/8, x13, x9, x10)

inst_8584:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25689*FLEN/8, x13, x9, x10)

inst_8585:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25692*FLEN/8, x13, x9, x10)

inst_8586:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25695*FLEN/8, x13, x9, x10)

inst_8587:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25698*FLEN/8, x13, x9, x10)

inst_8588:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25701*FLEN/8, x13, x9, x10)

inst_8589:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25704*FLEN/8, x13, x9, x10)

inst_8590:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25707*FLEN/8, x13, x9, x10)

inst_8591:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25710*FLEN/8, x13, x9, x10)

inst_8592:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:25713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25713*FLEN/8, x13, x9, x10)

inst_8593:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25716*FLEN/8, x13, x9, x10)

inst_8594:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:25719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25719*FLEN/8, x13, x9, x10)

inst_8595:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25722*FLEN/8, x13, x9, x10)

inst_8596:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:25725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25725*FLEN/8, x13, x9, x10)

inst_8597:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25728*FLEN/8, x13, x9, x10)

inst_8598:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25731*FLEN/8, x13, x9, x10)

inst_8599:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25734*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_67)

inst_8600:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:25737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25737*FLEN/8, x13, x9, x10)

inst_8601:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25740*FLEN/8, x13, x9, x10)

inst_8602:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:25743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25743*FLEN/8, x13, x9, x10)

inst_8603:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25746*FLEN/8, x13, x9, x10)

inst_8604:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25749*FLEN/8, x13, x9, x10)

inst_8605:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25752*FLEN/8, x13, x9, x10)

inst_8606:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25755*FLEN/8, x13, x9, x10)

inst_8607:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25758*FLEN/8, x13, x9, x10)

inst_8608:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25761*FLEN/8, x13, x9, x10)

inst_8609:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25764*FLEN/8, x13, x9, x10)

inst_8610:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25767*FLEN/8, x13, x9, x10)

inst_8611:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25770*FLEN/8, x13, x9, x10)

inst_8612:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25773*FLEN/8, x13, x9, x10)

inst_8613:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25776*FLEN/8, x13, x9, x10)

inst_8614:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25779*FLEN/8, x13, x9, x10)

inst_8615:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25782*FLEN/8, x13, x9, x10)

inst_8616:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:25785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25785*FLEN/8, x13, x9, x10)

inst_8617:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25788*FLEN/8, x13, x9, x10)

inst_8618:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:25791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25791*FLEN/8, x13, x9, x10)

inst_8619:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25794*FLEN/8, x13, x9, x10)

inst_8620:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:25797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25797*FLEN/8, x13, x9, x10)

inst_8621:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25800*FLEN/8, x13, x9, x10)

inst_8622:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25803*FLEN/8, x13, x9, x10)

inst_8623:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25806*FLEN/8, x13, x9, x10)

inst_8624:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:25809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25809*FLEN/8, x13, x9, x10)

inst_8625:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25812*FLEN/8, x13, x9, x10)

inst_8626:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:25815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25815*FLEN/8, x13, x9, x10)

inst_8627:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25818*FLEN/8, x13, x9, x10)

inst_8628:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25821*FLEN/8, x13, x9, x10)

inst_8629:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25824*FLEN/8, x13, x9, x10)

inst_8630:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25827*FLEN/8, x13, x9, x10)

inst_8631:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25830*FLEN/8, x13, x9, x10)

inst_8632:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25833*FLEN/8, x13, x9, x10)

inst_8633:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25836*FLEN/8, x13, x9, x10)

inst_8634:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25839*FLEN/8, x13, x9, x10)

inst_8635:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25842*FLEN/8, x13, x9, x10)

inst_8636:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25845*FLEN/8, x13, x9, x10)

inst_8637:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25848*FLEN/8, x13, x9, x10)

inst_8638:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25851*FLEN/8, x13, x9, x10)

inst_8639:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25854*FLEN/8, x13, x9, x10)

inst_8640:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:25857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25857*FLEN/8, x13, x9, x10)

inst_8641:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:25860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25860*FLEN/8, x13, x9, x10)

inst_8642:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:25863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25863*FLEN/8, x13, x9, x10)

inst_8643:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:25866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25866*FLEN/8, x13, x9, x10)

inst_8644:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:25869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25869*FLEN/8, x13, x9, x10)

inst_8645:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25872*FLEN/8, x13, x9, x10)

inst_8646:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25875*FLEN/8, x13, x9, x10)

inst_8647:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25878*FLEN/8, x13, x9, x10)

inst_8648:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:25881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25881*FLEN/8, x13, x9, x10)

inst_8649:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:25884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25884*FLEN/8, x13, x9, x10)

inst_8650:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:25887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25887*FLEN/8, x13, x9, x10)

inst_8651:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:25890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25890*FLEN/8, x13, x9, x10)

inst_8652:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25893*FLEN/8, x13, x9, x10)

inst_8653:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25896*FLEN/8, x13, x9, x10)

inst_8654:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25899*FLEN/8, x13, x9, x10)

inst_8655:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:25902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25902*FLEN/8, x13, x9, x10)

inst_8656:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25905*FLEN/8, x13, x9, x10)

inst_8657:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25908*FLEN/8, x13, x9, x10)

inst_8658:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25911*FLEN/8, x13, x9, x10)

inst_8659:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25914*FLEN/8, x13, x9, x10)

inst_8660:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25917*FLEN/8, x13, x9, x10)

inst_8661:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25920*FLEN/8, x13, x9, x10)

inst_8662:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25923*FLEN/8, x13, x9, x10)

inst_8663:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25926*FLEN/8, x13, x9, x10)

inst_8664:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:25929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25929*FLEN/8, x13, x9, x10)

inst_8665:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:25932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25932*FLEN/8, x13, x9, x10)

inst_8666:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:25935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25935*FLEN/8, x13, x9, x10)

inst_8667:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:25938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25938*FLEN/8, x13, x9, x10)

inst_8668:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:25941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25941*FLEN/8, x13, x9, x10)

inst_8669:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:25944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25944*FLEN/8, x13, x9, x10)

inst_8670:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:25947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25947*FLEN/8, x13, x9, x10)

inst_8671:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:25950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25950*FLEN/8, x13, x9, x10)

inst_8672:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:25953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25953*FLEN/8, x13, x9, x10)

inst_8673:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:25956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25956*FLEN/8, x13, x9, x10)

inst_8674:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:25959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25959*FLEN/8, x13, x9, x10)

inst_8675:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:25962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25962*FLEN/8, x13, x9, x10)

inst_8676:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:25965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25965*FLEN/8, x13, x9, x10)

inst_8677:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:25968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25968*FLEN/8, x13, x9, x10)

inst_8678:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:25971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25971*FLEN/8, x13, x9, x10)

inst_8679:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:25974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25974*FLEN/8, x13, x9, x10)

inst_8680:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:25977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25977*FLEN/8, x13, x9, x10)

inst_8681:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:25980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25980*FLEN/8, x13, x9, x10)

inst_8682:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:25983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25983*FLEN/8, x13, x9, x10)

inst_8683:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:25986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25986*FLEN/8, x13, x9, x10)

inst_8684:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:25989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25989*FLEN/8, x13, x9, x10)

inst_8685:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:25992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25992*FLEN/8, x13, x9, x10)

inst_8686:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:25995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25995*FLEN/8, x13, x9, x10)

inst_8687:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:25998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25998*FLEN/8, x13, x9, x10)

inst_8688:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:26001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26001*FLEN/8, x13, x9, x10)

inst_8689:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:26004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26004*FLEN/8, x13, x9, x10)

inst_8690:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:26007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26007*FLEN/8, x13, x9, x10)

inst_8691:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:26010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26010*FLEN/8, x13, x9, x10)

inst_8692:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:26013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26013*FLEN/8, x13, x9, x10)

inst_8693:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26016*FLEN/8, x13, x9, x10)

inst_8694:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26019*FLEN/8, x13, x9, x10)

inst_8695:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26022*FLEN/8, x13, x9, x10)

inst_8696:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:26025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26025*FLEN/8, x13, x9, x10)

inst_8697:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:26028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26028*FLEN/8, x13, x9, x10)

inst_8698:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:26031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26031*FLEN/8, x13, x9, x10)

inst_8699:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:26034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26034*FLEN/8, x13, x9, x10)

inst_8700:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26037*FLEN/8, x13, x9, x10)

inst_8701:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26040*FLEN/8, x13, x9, x10)

inst_8702:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26043*FLEN/8, x13, x9, x10)

inst_8703:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:26046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26046*FLEN/8, x13, x9, x10)

inst_8704:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26049*FLEN/8, x13, x9, x10)

inst_8705:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26052*FLEN/8, x13, x9, x10)

inst_8706:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26055*FLEN/8, x13, x9, x10)

inst_8707:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26058*FLEN/8, x13, x9, x10)

inst_8708:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26061*FLEN/8, x13, x9, x10)

inst_8709:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26064*FLEN/8, x13, x9, x10)

inst_8710:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26067*FLEN/8, x13, x9, x10)

inst_8711:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26070*FLEN/8, x13, x9, x10)

inst_8712:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:26073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26073*FLEN/8, x13, x9, x10)

inst_8713:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:26076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26076*FLEN/8, x13, x9, x10)

inst_8714:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:26079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26079*FLEN/8, x13, x9, x10)

inst_8715:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:26082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26082*FLEN/8, x13, x9, x10)

inst_8716:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:26085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26085*FLEN/8, x13, x9, x10)

inst_8717:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26088*FLEN/8, x13, x9, x10)

inst_8718:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26091*FLEN/8, x13, x9, x10)

inst_8719:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26094*FLEN/8, x13, x9, x10)

inst_8720:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:26097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26097*FLEN/8, x13, x9, x10)

inst_8721:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:26100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26100*FLEN/8, x13, x9, x10)

inst_8722:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:26103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26103*FLEN/8, x13, x9, x10)

inst_8723:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:26106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26106*FLEN/8, x13, x9, x10)

inst_8724:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26109*FLEN/8, x13, x9, x10)

inst_8725:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26112*FLEN/8, x13, x9, x10)

inst_8726:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26115*FLEN/8, x13, x9, x10)

inst_8727:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:26118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26118*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_68)

inst_8728:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26121*FLEN/8, x13, x9, x10)

inst_8729:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26124*FLEN/8, x13, x9, x10)

inst_8730:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26127*FLEN/8, x13, x9, x10)

inst_8731:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26130*FLEN/8, x13, x9, x10)

inst_8732:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26133*FLEN/8, x13, x9, x10)

inst_8733:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26136*FLEN/8, x13, x9, x10)

inst_8734:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26139*FLEN/8, x13, x9, x10)

inst_8735:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26142*FLEN/8, x13, x9, x10)

inst_8736:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:26145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26145*FLEN/8, x13, x9, x10)

inst_8737:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:26148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26148*FLEN/8, x13, x9, x10)

inst_8738:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:26151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26151*FLEN/8, x13, x9, x10)

inst_8739:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:26154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26154*FLEN/8, x13, x9, x10)

inst_8740:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:26157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26157*FLEN/8, x13, x9, x10)

inst_8741:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26160*FLEN/8, x13, x9, x10)

inst_8742:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26163*FLEN/8, x13, x9, x10)

inst_8743:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26166*FLEN/8, x13, x9, x10)

inst_8744:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:26169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26169*FLEN/8, x13, x9, x10)

inst_8745:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:26172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26172*FLEN/8, x13, x9, x10)

inst_8746:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:26175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26175*FLEN/8, x13, x9, x10)

inst_8747:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:26178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26178*FLEN/8, x13, x9, x10)

inst_8748:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26181*FLEN/8, x13, x9, x10)

inst_8749:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26184*FLEN/8, x13, x9, x10)

inst_8750:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26187*FLEN/8, x13, x9, x10)

inst_8751:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:26190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26190*FLEN/8, x13, x9, x10)

inst_8752:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26193*FLEN/8, x13, x9, x10)

inst_8753:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26196*FLEN/8, x13, x9, x10)

inst_8754:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26199*FLEN/8, x13, x9, x10)

inst_8755:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26202*FLEN/8, x13, x9, x10)

inst_8756:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26205*FLEN/8, x13, x9, x10)

inst_8757:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26208*FLEN/8, x13, x9, x10)

inst_8758:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26211*FLEN/8, x13, x9, x10)

inst_8759:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26214*FLEN/8, x13, x9, x10)

inst_8760:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:26217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26217*FLEN/8, x13, x9, x10)

inst_8761:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:26220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26220*FLEN/8, x13, x9, x10)

inst_8762:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:26223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26223*FLEN/8, x13, x9, x10)

inst_8763:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:26226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26226*FLEN/8, x13, x9, x10)

inst_8764:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:26229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26229*FLEN/8, x13, x9, x10)

inst_8765:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26232*FLEN/8, x13, x9, x10)

inst_8766:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26235*FLEN/8, x13, x9, x10)

inst_8767:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26238*FLEN/8, x13, x9, x10)

inst_8768:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:26241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26241*FLEN/8, x13, x9, x10)

inst_8769:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:26244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26244*FLEN/8, x13, x9, x10)

inst_8770:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:26247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26247*FLEN/8, x13, x9, x10)

inst_8771:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:26250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26250*FLEN/8, x13, x9, x10)

inst_8772:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26253*FLEN/8, x13, x9, x10)

inst_8773:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26256*FLEN/8, x13, x9, x10)

inst_8774:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26259*FLEN/8, x13, x9, x10)

inst_8775:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:26262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26262*FLEN/8, x13, x9, x10)

inst_8776:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26265*FLEN/8, x13, x9, x10)

inst_8777:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26268*FLEN/8, x13, x9, x10)

inst_8778:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26271*FLEN/8, x13, x9, x10)

inst_8779:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26274*FLEN/8, x13, x9, x10)

inst_8780:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26277*FLEN/8, x13, x9, x10)

inst_8781:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26280*FLEN/8, x13, x9, x10)

inst_8782:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26283*FLEN/8, x13, x9, x10)

inst_8783:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26286*FLEN/8, x13, x9, x10)

inst_8784:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:26289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26289*FLEN/8, x13, x9, x10)

inst_8785:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:26292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26292*FLEN/8, x13, x9, x10)

inst_8786:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:26295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26295*FLEN/8, x13, x9, x10)

inst_8787:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:26298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26298*FLEN/8, x13, x9, x10)

inst_8788:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:26301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26301*FLEN/8, x13, x9, x10)

inst_8789:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26304*FLEN/8, x13, x9, x10)

inst_8790:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26307*FLEN/8, x13, x9, x10)

inst_8791:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26310*FLEN/8, x13, x9, x10)

inst_8792:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:26313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26313*FLEN/8, x13, x9, x10)

inst_8793:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:26316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26316*FLEN/8, x13, x9, x10)

inst_8794:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:26319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26319*FLEN/8, x13, x9, x10)

inst_8795:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:26322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26322*FLEN/8, x13, x9, x10)

inst_8796:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26325*FLEN/8, x13, x9, x10)

inst_8797:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26328*FLEN/8, x13, x9, x10)

inst_8798:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26331*FLEN/8, x13, x9, x10)

inst_8799:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:26334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26334*FLEN/8, x13, x9, x10)

inst_8800:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26337*FLEN/8, x13, x9, x10)

inst_8801:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26340*FLEN/8, x13, x9, x10)

inst_8802:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26343*FLEN/8, x13, x9, x10)

inst_8803:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26346*FLEN/8, x13, x9, x10)

inst_8804:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26349*FLEN/8, x13, x9, x10)

inst_8805:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26352*FLEN/8, x13, x9, x10)

inst_8806:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26355*FLEN/8, x13, x9, x10)

inst_8807:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26358*FLEN/8, x13, x9, x10)

inst_8808:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:26361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26361*FLEN/8, x13, x9, x10)

inst_8809:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:26364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26364*FLEN/8, x13, x9, x10)

inst_8810:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:26367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26367*FLEN/8, x13, x9, x10)

inst_8811:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:26370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26370*FLEN/8, x13, x9, x10)

inst_8812:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:26373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26373*FLEN/8, x13, x9, x10)

inst_8813:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26376*FLEN/8, x13, x9, x10)

inst_8814:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26379*FLEN/8, x13, x9, x10)

inst_8815:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26382*FLEN/8, x13, x9, x10)

inst_8816:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:26385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26385*FLEN/8, x13, x9, x10)

inst_8817:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:26388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26388*FLEN/8, x13, x9, x10)

inst_8818:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:26391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26391*FLEN/8, x13, x9, x10)

inst_8819:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:26394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26394*FLEN/8, x13, x9, x10)

inst_8820:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26397*FLEN/8, x13, x9, x10)

inst_8821:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26400*FLEN/8, x13, x9, x10)

inst_8822:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26403*FLEN/8, x13, x9, x10)

inst_8823:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:26406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26406*FLEN/8, x13, x9, x10)

inst_8824:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26409*FLEN/8, x13, x9, x10)

inst_8825:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26412*FLEN/8, x13, x9, x10)

inst_8826:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26415*FLEN/8, x13, x9, x10)

inst_8827:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26418*FLEN/8, x13, x9, x10)

inst_8828:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26421*FLEN/8, x13, x9, x10)

inst_8829:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26424*FLEN/8, x13, x9, x10)

inst_8830:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26427*FLEN/8, x13, x9, x10)

inst_8831:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26430*FLEN/8, x13, x9, x10)

inst_8832:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:26433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26433*FLEN/8, x13, x9, x10)

inst_8833:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:26436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26436*FLEN/8, x13, x9, x10)

inst_8834:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:26439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26439*FLEN/8, x13, x9, x10)

inst_8835:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:26442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26442*FLEN/8, x13, x9, x10)

inst_8836:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:26445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26445*FLEN/8, x13, x9, x10)

inst_8837:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26448*FLEN/8, x13, x9, x10)

inst_8838:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26451*FLEN/8, x13, x9, x10)

inst_8839:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26454*FLEN/8, x13, x9, x10)

inst_8840:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:26457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26457*FLEN/8, x13, x9, x10)

inst_8841:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:26460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26460*FLEN/8, x13, x9, x10)

inst_8842:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:26463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26463*FLEN/8, x13, x9, x10)

inst_8843:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:26466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26466*FLEN/8, x13, x9, x10)

inst_8844:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26469*FLEN/8, x13, x9, x10)

inst_8845:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26472*FLEN/8, x13, x9, x10)

inst_8846:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26475*FLEN/8, x13, x9, x10)

inst_8847:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:26478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26478*FLEN/8, x13, x9, x10)

inst_8848:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26481*FLEN/8, x13, x9, x10)

inst_8849:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26484*FLEN/8, x13, x9, x10)

inst_8850:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26487*FLEN/8, x13, x9, x10)

inst_8851:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26490*FLEN/8, x13, x9, x10)

inst_8852:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26493*FLEN/8, x13, x9, x10)

inst_8853:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26496*FLEN/8, x13, x9, x10)

inst_8854:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26499*FLEN/8, x13, x9, x10)

inst_8855:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26502*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_69)

inst_8856:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:26505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26505*FLEN/8, x13, x9, x10)

inst_8857:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:26508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26508*FLEN/8, x13, x9, x10)

inst_8858:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:26511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26511*FLEN/8, x13, x9, x10)

inst_8859:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:26514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26514*FLEN/8, x13, x9, x10)

inst_8860:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:26517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26517*FLEN/8, x13, x9, x10)

inst_8861:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26520*FLEN/8, x13, x9, x10)

inst_8862:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26523*FLEN/8, x13, x9, x10)

inst_8863:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26526*FLEN/8, x13, x9, x10)

inst_8864:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:26529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26529*FLEN/8, x13, x9, x10)

inst_8865:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:26532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26532*FLEN/8, x13, x9, x10)

inst_8866:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:26535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26535*FLEN/8, x13, x9, x10)

inst_8867:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:26538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26538*FLEN/8, x13, x9, x10)

inst_8868:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26541*FLEN/8, x13, x9, x10)

inst_8869:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26544*FLEN/8, x13, x9, x10)

inst_8870:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26547*FLEN/8, x13, x9, x10)

inst_8871:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:26550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26550*FLEN/8, x13, x9, x10)

inst_8872:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26553*FLEN/8, x13, x9, x10)

inst_8873:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26556*FLEN/8, x13, x9, x10)

inst_8874:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26559*FLEN/8, x13, x9, x10)

inst_8875:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26562*FLEN/8, x13, x9, x10)

inst_8876:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26565*FLEN/8, x13, x9, x10)

inst_8877:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26568*FLEN/8, x13, x9, x10)

inst_8878:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26571*FLEN/8, x13, x9, x10)

inst_8879:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26574*FLEN/8, x13, x9, x10)

inst_8880:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:26577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26577*FLEN/8, x13, x9, x10)

inst_8881:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:26580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26580*FLEN/8, x13, x9, x10)

inst_8882:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:26583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26583*FLEN/8, x13, x9, x10)

inst_8883:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:26586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26586*FLEN/8, x13, x9, x10)

inst_8884:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:26589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26589*FLEN/8, x13, x9, x10)

inst_8885:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26592*FLEN/8, x13, x9, x10)

inst_8886:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26595*FLEN/8, x13, x9, x10)

inst_8887:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26598*FLEN/8, x13, x9, x10)

inst_8888:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:26601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26601*FLEN/8, x13, x9, x10)

inst_8889:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:26604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26604*FLEN/8, x13, x9, x10)

inst_8890:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:26607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26607*FLEN/8, x13, x9, x10)

inst_8891:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:26610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26610*FLEN/8, x13, x9, x10)

inst_8892:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26613*FLEN/8, x13, x9, x10)

inst_8893:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26616*FLEN/8, x13, x9, x10)

inst_8894:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26619*FLEN/8, x13, x9, x10)

inst_8895:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:26622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26622*FLEN/8, x13, x9, x10)

inst_8896:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26625*FLEN/8, x13, x9, x10)

inst_8897:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26628*FLEN/8, x13, x9, x10)

inst_8898:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26631*FLEN/8, x13, x9, x10)

inst_8899:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26634*FLEN/8, x13, x9, x10)

inst_8900:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26637*FLEN/8, x13, x9, x10)

inst_8901:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26640*FLEN/8, x13, x9, x10)

inst_8902:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26643*FLEN/8, x13, x9, x10)

inst_8903:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26646*FLEN/8, x13, x9, x10)

inst_8904:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:26649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26649*FLEN/8, x13, x9, x10)

inst_8905:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:26652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26652*FLEN/8, x13, x9, x10)

inst_8906:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:26655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26655*FLEN/8, x13, x9, x10)

inst_8907:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:26658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26658*FLEN/8, x13, x9, x10)

inst_8908:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:26661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26661*FLEN/8, x13, x9, x10)

inst_8909:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26664*FLEN/8, x13, x9, x10)

inst_8910:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26667*FLEN/8, x13, x9, x10)

inst_8911:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26670*FLEN/8, x13, x9, x10)

inst_8912:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:26673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26673*FLEN/8, x13, x9, x10)

inst_8913:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:26676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26676*FLEN/8, x13, x9, x10)

inst_8914:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:26679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26679*FLEN/8, x13, x9, x10)

inst_8915:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:26682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26682*FLEN/8, x13, x9, x10)

inst_8916:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26685*FLEN/8, x13, x9, x10)

inst_8917:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26688*FLEN/8, x13, x9, x10)

inst_8918:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26691*FLEN/8, x13, x9, x10)

inst_8919:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:26694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26694*FLEN/8, x13, x9, x10)

inst_8920:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26697*FLEN/8, x13, x9, x10)

inst_8921:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26700*FLEN/8, x13, x9, x10)

inst_8922:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26703*FLEN/8, x13, x9, x10)

inst_8923:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26706*FLEN/8, x13, x9, x10)

inst_8924:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26709*FLEN/8, x13, x9, x10)

inst_8925:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26712*FLEN/8, x13, x9, x10)

inst_8926:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26715*FLEN/8, x13, x9, x10)

inst_8927:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26718*FLEN/8, x13, x9, x10)

inst_8928:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:26721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26721*FLEN/8, x13, x9, x10)

inst_8929:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:26724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26724*FLEN/8, x13, x9, x10)

inst_8930:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:26727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26727*FLEN/8, x13, x9, x10)

inst_8931:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:26730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26730*FLEN/8, x13, x9, x10)

inst_8932:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:26733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26733*FLEN/8, x13, x9, x10)

inst_8933:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26736*FLEN/8, x13, x9, x10)

inst_8934:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26739*FLEN/8, x13, x9, x10)

inst_8935:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26742*FLEN/8, x13, x9, x10)

inst_8936:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:26745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26745*FLEN/8, x13, x9, x10)

inst_8937:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:26748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26748*FLEN/8, x13, x9, x10)

inst_8938:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:26751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26751*FLEN/8, x13, x9, x10)

inst_8939:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:26754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26754*FLEN/8, x13, x9, x10)

inst_8940:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26757*FLEN/8, x13, x9, x10)

inst_8941:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26760*FLEN/8, x13, x9, x10)

inst_8942:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26763*FLEN/8, x13, x9, x10)

inst_8943:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:26766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26766*FLEN/8, x13, x9, x10)

inst_8944:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26769*FLEN/8, x13, x9, x10)

inst_8945:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26772*FLEN/8, x13, x9, x10)

inst_8946:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26775*FLEN/8, x13, x9, x10)

inst_8947:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26778*FLEN/8, x13, x9, x10)

inst_8948:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26781*FLEN/8, x13, x9, x10)

inst_8949:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26784*FLEN/8, x13, x9, x10)

inst_8950:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26787*FLEN/8, x13, x9, x10)

inst_8951:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26790*FLEN/8, x13, x9, x10)

inst_8952:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:26793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26793*FLEN/8, x13, x9, x10)

inst_8953:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:26796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26796*FLEN/8, x13, x9, x10)

inst_8954:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:26799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26799*FLEN/8, x13, x9, x10)

inst_8955:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:26802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26802*FLEN/8, x13, x9, x10)

inst_8956:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:26805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26805*FLEN/8, x13, x9, x10)

inst_8957:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26808*FLEN/8, x13, x9, x10)

inst_8958:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26811*FLEN/8, x13, x9, x10)

inst_8959:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26814*FLEN/8, x13, x9, x10)

inst_8960:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:26817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26817*FLEN/8, x13, x9, x10)

inst_8961:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:26820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26820*FLEN/8, x13, x9, x10)

inst_8962:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:26823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26823*FLEN/8, x13, x9, x10)

inst_8963:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:26826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26826*FLEN/8, x13, x9, x10)

inst_8964:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26829*FLEN/8, x13, x9, x10)

inst_8965:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26832*FLEN/8, x13, x9, x10)

inst_8966:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26835*FLEN/8, x13, x9, x10)

inst_8967:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:26838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26838*FLEN/8, x13, x9, x10)

inst_8968:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26841*FLEN/8, x13, x9, x10)

inst_8969:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26844*FLEN/8, x13, x9, x10)

inst_8970:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26847*FLEN/8, x13, x9, x10)

inst_8971:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26850*FLEN/8, x13, x9, x10)

inst_8972:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26853*FLEN/8, x13, x9, x10)

inst_8973:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26856*FLEN/8, x13, x9, x10)

inst_8974:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26859*FLEN/8, x13, x9, x10)

inst_8975:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26862*FLEN/8, x13, x9, x10)

inst_8976:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:26865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26865*FLEN/8, x13, x9, x10)

inst_8977:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:26868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26868*FLEN/8, x13, x9, x10)

inst_8978:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:26871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26871*FLEN/8, x13, x9, x10)

inst_8979:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:26874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26874*FLEN/8, x13, x9, x10)

inst_8980:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:26877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26877*FLEN/8, x13, x9, x10)

inst_8981:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26880*FLEN/8, x13, x9, x10)

inst_8982:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26883*FLEN/8, x13, x9, x10)

inst_8983:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26886*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_70)

inst_8984:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:26889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26889*FLEN/8, x13, x9, x10)

inst_8985:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:26892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26892*FLEN/8, x13, x9, x10)

inst_8986:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:26895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26895*FLEN/8, x13, x9, x10)

inst_8987:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:26898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26898*FLEN/8, x13, x9, x10)

inst_8988:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26901*FLEN/8, x13, x9, x10)

inst_8989:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26904*FLEN/8, x13, x9, x10)

inst_8990:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26907*FLEN/8, x13, x9, x10)

inst_8991:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:26910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26910*FLEN/8, x13, x9, x10)

inst_8992:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26913*FLEN/8, x13, x9, x10)

inst_8993:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26916*FLEN/8, x13, x9, x10)

inst_8994:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26919*FLEN/8, x13, x9, x10)

inst_8995:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26922*FLEN/8, x13, x9, x10)

inst_8996:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26925*FLEN/8, x13, x9, x10)

inst_8997:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:26928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26928*FLEN/8, x13, x9, x10)

inst_8998:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:26931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26931*FLEN/8, x13, x9, x10)

inst_8999:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:26934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26934*FLEN/8, x13, x9, x10)

inst_9000:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:26937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26937*FLEN/8, x13, x9, x10)

inst_9001:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:26940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26940*FLEN/8, x13, x9, x10)

inst_9002:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:26943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26943*FLEN/8, x13, x9, x10)

inst_9003:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:26946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26946*FLEN/8, x13, x9, x10)

inst_9004:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:26949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26949*FLEN/8, x13, x9, x10)

inst_9005:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:26952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26952*FLEN/8, x13, x9, x10)

inst_9006:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:26955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26955*FLEN/8, x13, x9, x10)

inst_9007:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:26958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26958*FLEN/8, x13, x9, x10)

inst_9008:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:26961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26961*FLEN/8, x13, x9, x10)

inst_9009:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:26964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26964*FLEN/8, x13, x9, x10)

inst_9010:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:26967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26967*FLEN/8, x13, x9, x10)

inst_9011:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:26970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26970*FLEN/8, x13, x9, x10)

inst_9012:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:26973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26973*FLEN/8, x13, x9, x10)

inst_9013:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:26976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26976*FLEN/8, x13, x9, x10)

inst_9014:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:26979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26979*FLEN/8, x13, x9, x10)

inst_9015:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:26982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26982*FLEN/8, x13, x9, x10)

inst_9016:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:26985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26985*FLEN/8, x13, x9, x10)

inst_9017:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:26988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26988*FLEN/8, x13, x9, x10)

inst_9018:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:26991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26991*FLEN/8, x13, x9, x10)

inst_9019:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:26994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26994*FLEN/8, x13, x9, x10)

inst_9020:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:26997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 26997*FLEN/8, x13, x9, x10)

inst_9021:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27000*FLEN/8, x13, x9, x10)

inst_9022:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27003*FLEN/8, x13, x9, x10)

inst_9023:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27006*FLEN/8, x13, x9, x10)

inst_9024:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:27009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27009*FLEN/8, x13, x9, x10)

inst_9025:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:27012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27012*FLEN/8, x13, x9, x10)

inst_9026:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:27015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27015*FLEN/8, x13, x9, x10)

inst_9027:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:27018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27018*FLEN/8, x13, x9, x10)

inst_9028:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:27021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27021*FLEN/8, x13, x9, x10)

inst_9029:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27024*FLEN/8, x13, x9, x10)

inst_9030:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27027*FLEN/8, x13, x9, x10)

inst_9031:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27030*FLEN/8, x13, x9, x10)

inst_9032:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:27033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27033*FLEN/8, x13, x9, x10)

inst_9033:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:27036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27036*FLEN/8, x13, x9, x10)

inst_9034:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:27039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27039*FLEN/8, x13, x9, x10)

inst_9035:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:27042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27042*FLEN/8, x13, x9, x10)

inst_9036:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27045*FLEN/8, x13, x9, x10)

inst_9037:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27048*FLEN/8, x13, x9, x10)

inst_9038:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27051*FLEN/8, x13, x9, x10)

inst_9039:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:27054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27054*FLEN/8, x13, x9, x10)

inst_9040:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27057*FLEN/8, x13, x9, x10)

inst_9041:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27060*FLEN/8, x13, x9, x10)

inst_9042:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27063*FLEN/8, x13, x9, x10)

inst_9043:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27066*FLEN/8, x13, x9, x10)

inst_9044:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27069*FLEN/8, x13, x9, x10)

inst_9045:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27072*FLEN/8, x13, x9, x10)

inst_9046:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27075*FLEN/8, x13, x9, x10)

inst_9047:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27078*FLEN/8, x13, x9, x10)

inst_9048:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:27081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27081*FLEN/8, x13, x9, x10)

inst_9049:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:27084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27084*FLEN/8, x13, x9, x10)

inst_9050:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:27087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27087*FLEN/8, x13, x9, x10)

inst_9051:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:27090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27090*FLEN/8, x13, x9, x10)

inst_9052:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:27093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27093*FLEN/8, x13, x9, x10)

inst_9053:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27096*FLEN/8, x13, x9, x10)

inst_9054:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27099*FLEN/8, x13, x9, x10)

inst_9055:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27102*FLEN/8, x13, x9, x10)

inst_9056:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:27105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27105*FLEN/8, x13, x9, x10)

inst_9057:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:27108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27108*FLEN/8, x13, x9, x10)

inst_9058:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:27111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27111*FLEN/8, x13, x9, x10)

inst_9059:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:27114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27114*FLEN/8, x13, x9, x10)

inst_9060:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27117*FLEN/8, x13, x9, x10)

inst_9061:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27120*FLEN/8, x13, x9, x10)

inst_9062:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27123*FLEN/8, x13, x9, x10)

inst_9063:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:27126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27126*FLEN/8, x13, x9, x10)

inst_9064:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27129*FLEN/8, x13, x9, x10)

inst_9065:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27132*FLEN/8, x13, x9, x10)

inst_9066:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27135*FLEN/8, x13, x9, x10)

inst_9067:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27138*FLEN/8, x13, x9, x10)

inst_9068:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27141*FLEN/8, x13, x9, x10)

inst_9069:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27144*FLEN/8, x13, x9, x10)

inst_9070:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27147*FLEN/8, x13, x9, x10)

inst_9071:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27150*FLEN/8, x13, x9, x10)

inst_9072:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:27153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27153*FLEN/8, x13, x9, x10)

inst_9073:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:27156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27156*FLEN/8, x13, x9, x10)

inst_9074:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:27159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27159*FLEN/8, x13, x9, x10)

inst_9075:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:27162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27162*FLEN/8, x13, x9, x10)

inst_9076:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:27165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27165*FLEN/8, x13, x9, x10)

inst_9077:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27168*FLEN/8, x13, x9, x10)

inst_9078:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27171*FLEN/8, x13, x9, x10)

inst_9079:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27174*FLEN/8, x13, x9, x10)

inst_9080:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:27177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27177*FLEN/8, x13, x9, x10)

inst_9081:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:27180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27180*FLEN/8, x13, x9, x10)

inst_9082:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:27183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27183*FLEN/8, x13, x9, x10)

inst_9083:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:27186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27186*FLEN/8, x13, x9, x10)

inst_9084:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27189*FLEN/8, x13, x9, x10)

inst_9085:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27192*FLEN/8, x13, x9, x10)

inst_9086:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27195*FLEN/8, x13, x9, x10)

inst_9087:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:27198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27198*FLEN/8, x13, x9, x10)

inst_9088:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27201*FLEN/8, x13, x9, x10)

inst_9089:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27204*FLEN/8, x13, x9, x10)

inst_9090:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27207*FLEN/8, x13, x9, x10)

inst_9091:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27210*FLEN/8, x13, x9, x10)

inst_9092:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27213*FLEN/8, x13, x9, x10)

inst_9093:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27216*FLEN/8, x13, x9, x10)

inst_9094:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27219*FLEN/8, x13, x9, x10)

inst_9095:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27222*FLEN/8, x13, x9, x10)

inst_9096:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:27225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27225*FLEN/8, x13, x9, x10)

inst_9097:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:27228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27228*FLEN/8, x13, x9, x10)

inst_9098:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:27231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27231*FLEN/8, x13, x9, x10)

inst_9099:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:27234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27234*FLEN/8, x13, x9, x10)

inst_9100:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:27237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27237*FLEN/8, x13, x9, x10)

inst_9101:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27240*FLEN/8, x13, x9, x10)

inst_9102:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27243*FLEN/8, x13, x9, x10)

inst_9103:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27246*FLEN/8, x13, x9, x10)

inst_9104:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:27249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27249*FLEN/8, x13, x9, x10)

inst_9105:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:27252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27252*FLEN/8, x13, x9, x10)

inst_9106:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:27255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27255*FLEN/8, x13, x9, x10)

inst_9107:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:27258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27258*FLEN/8, x13, x9, x10)

inst_9108:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27261*FLEN/8, x13, x9, x10)

inst_9109:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27264*FLEN/8, x13, x9, x10)

inst_9110:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27267*FLEN/8, x13, x9, x10)

inst_9111:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:27270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27270*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_71)

inst_9112:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27273*FLEN/8, x13, x9, x10)

inst_9113:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27276*FLEN/8, x13, x9, x10)

inst_9114:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27279*FLEN/8, x13, x9, x10)

inst_9115:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27282*FLEN/8, x13, x9, x10)

inst_9116:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27285*FLEN/8, x13, x9, x10)

inst_9117:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27288*FLEN/8, x13, x9, x10)

inst_9118:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27291*FLEN/8, x13, x9, x10)

inst_9119:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27294*FLEN/8, x13, x9, x10)

inst_9120:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:27297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27297*FLEN/8, x13, x9, x10)

inst_9121:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:27300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27300*FLEN/8, x13, x9, x10)

inst_9122:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:27303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27303*FLEN/8, x13, x9, x10)

inst_9123:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:27306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27306*FLEN/8, x13, x9, x10)

inst_9124:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:27309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27309*FLEN/8, x13, x9, x10)

inst_9125:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27312*FLEN/8, x13, x9, x10)

inst_9126:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27315*FLEN/8, x13, x9, x10)

inst_9127:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27318*FLEN/8, x13, x9, x10)

inst_9128:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:27321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27321*FLEN/8, x13, x9, x10)

inst_9129:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:27324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27324*FLEN/8, x13, x9, x10)

inst_9130:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:27327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27327*FLEN/8, x13, x9, x10)

inst_9131:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:27330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27330*FLEN/8, x13, x9, x10)

inst_9132:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27333*FLEN/8, x13, x9, x10)

inst_9133:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27336*FLEN/8, x13, x9, x10)

inst_9134:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27339*FLEN/8, x13, x9, x10)

inst_9135:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:27342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27342*FLEN/8, x13, x9, x10)

inst_9136:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27345*FLEN/8, x13, x9, x10)

inst_9137:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27348*FLEN/8, x13, x9, x10)

inst_9138:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27351*FLEN/8, x13, x9, x10)

inst_9139:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27354*FLEN/8, x13, x9, x10)

inst_9140:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27357*FLEN/8, x13, x9, x10)

inst_9141:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27360*FLEN/8, x13, x9, x10)

inst_9142:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27363*FLEN/8, x13, x9, x10)

inst_9143:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27366*FLEN/8, x13, x9, x10)

inst_9144:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:27369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27369*FLEN/8, x13, x9, x10)

inst_9145:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:27372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27372*FLEN/8, x13, x9, x10)

inst_9146:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:27375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27375*FLEN/8, x13, x9, x10)

inst_9147:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:27378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27378*FLEN/8, x13, x9, x10)

inst_9148:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:27381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27381*FLEN/8, x13, x9, x10)

inst_9149:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27384*FLEN/8, x13, x9, x10)

inst_9150:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27387*FLEN/8, x13, x9, x10)

inst_9151:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27390*FLEN/8, x13, x9, x10)

inst_9152:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:27393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27393*FLEN/8, x13, x9, x10)

inst_9153:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:27396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27396*FLEN/8, x13, x9, x10)

inst_9154:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:27399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27399*FLEN/8, x13, x9, x10)

inst_9155:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:27402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27402*FLEN/8, x13, x9, x10)

inst_9156:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27405*FLEN/8, x13, x9, x10)

inst_9157:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27408*FLEN/8, x13, x9, x10)

inst_9158:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27411*FLEN/8, x13, x9, x10)

inst_9159:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:27414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27414*FLEN/8, x13, x9, x10)

inst_9160:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27417*FLEN/8, x13, x9, x10)

inst_9161:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27420*FLEN/8, x13, x9, x10)

inst_9162:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27423*FLEN/8, x13, x9, x10)

inst_9163:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27426*FLEN/8, x13, x9, x10)

inst_9164:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27429*FLEN/8, x13, x9, x10)

inst_9165:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27432*FLEN/8, x13, x9, x10)

inst_9166:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27435*FLEN/8, x13, x9, x10)

inst_9167:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27438*FLEN/8, x13, x9, x10)

inst_9168:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:27441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27441*FLEN/8, x13, x9, x10)

inst_9169:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:27444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27444*FLEN/8, x13, x9, x10)

inst_9170:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:27447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27447*FLEN/8, x13, x9, x10)

inst_9171:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:27450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27450*FLEN/8, x13, x9, x10)

inst_9172:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:27453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27453*FLEN/8, x13, x9, x10)

inst_9173:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27456*FLEN/8, x13, x9, x10)

inst_9174:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27459*FLEN/8, x13, x9, x10)

inst_9175:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27462*FLEN/8, x13, x9, x10)

inst_9176:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:27465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27465*FLEN/8, x13, x9, x10)

inst_9177:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:27468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27468*FLEN/8, x13, x9, x10)

inst_9178:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:27471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27471*FLEN/8, x13, x9, x10)

inst_9179:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:27474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27474*FLEN/8, x13, x9, x10)

inst_9180:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27477*FLEN/8, x13, x9, x10)

inst_9181:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27480*FLEN/8, x13, x9, x10)

inst_9182:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27483*FLEN/8, x13, x9, x10)

inst_9183:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:27486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27486*FLEN/8, x13, x9, x10)

inst_9184:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27489*FLEN/8, x13, x9, x10)

inst_9185:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27492*FLEN/8, x13, x9, x10)

inst_9186:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27495*FLEN/8, x13, x9, x10)

inst_9187:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27498*FLEN/8, x13, x9, x10)

inst_9188:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27501*FLEN/8, x13, x9, x10)

inst_9189:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27504*FLEN/8, x13, x9, x10)

inst_9190:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27507*FLEN/8, x13, x9, x10)

inst_9191:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27510*FLEN/8, x13, x9, x10)

inst_9192:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:27513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27513*FLEN/8, x13, x9, x10)

inst_9193:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:27516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27516*FLEN/8, x13, x9, x10)

inst_9194:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:27519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27519*FLEN/8, x13, x9, x10)

inst_9195:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:27522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27522*FLEN/8, x13, x9, x10)

inst_9196:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:27525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27525*FLEN/8, x13, x9, x10)

inst_9197:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27528*FLEN/8, x13, x9, x10)

inst_9198:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27531*FLEN/8, x13, x9, x10)

inst_9199:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27534*FLEN/8, x13, x9, x10)

inst_9200:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:27537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27537*FLEN/8, x13, x9, x10)

inst_9201:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:27540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27540*FLEN/8, x13, x9, x10)

inst_9202:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:27543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27543*FLEN/8, x13, x9, x10)

inst_9203:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:27546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27546*FLEN/8, x13, x9, x10)

inst_9204:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27549*FLEN/8, x13, x9, x10)

inst_9205:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27552*FLEN/8, x13, x9, x10)

inst_9206:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27555*FLEN/8, x13, x9, x10)

inst_9207:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:27558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27558*FLEN/8, x13, x9, x10)

inst_9208:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27561*FLEN/8, x13, x9, x10)

inst_9209:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27564*FLEN/8, x13, x9, x10)

inst_9210:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27567*FLEN/8, x13, x9, x10)

inst_9211:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27570*FLEN/8, x13, x9, x10)

inst_9212:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27573*FLEN/8, x13, x9, x10)

inst_9213:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27576*FLEN/8, x13, x9, x10)

inst_9214:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27579*FLEN/8, x13, x9, x10)

inst_9215:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xff800000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27582*FLEN/8, x13, x9, x10)

inst_9216:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:27585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27585*FLEN/8, x13, x9, x10)

inst_9217:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:27588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27588*FLEN/8, x13, x9, x10)

inst_9218:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:27591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27591*FLEN/8, x13, x9, x10)

inst_9219:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:27594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27594*FLEN/8, x13, x9, x10)

inst_9220:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:27597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27597*FLEN/8, x13, x9, x10)

inst_9221:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27600*FLEN/8, x13, x9, x10)

inst_9222:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27603*FLEN/8, x13, x9, x10)

inst_9223:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27606*FLEN/8, x13, x9, x10)

inst_9224:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:27609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27609*FLEN/8, x13, x9, x10)

inst_9225:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:27612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27612*FLEN/8, x13, x9, x10)

inst_9226:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:27615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27615*FLEN/8, x13, x9, x10)

inst_9227:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:27618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27618*FLEN/8, x13, x9, x10)

inst_9228:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27621*FLEN/8, x13, x9, x10)

inst_9229:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27624*FLEN/8, x13, x9, x10)

inst_9230:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27627*FLEN/8, x13, x9, x10)

inst_9231:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:27630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27630*FLEN/8, x13, x9, x10)

inst_9232:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27633*FLEN/8, x13, x9, x10)

inst_9233:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27636*FLEN/8, x13, x9, x10)

inst_9234:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27639*FLEN/8, x13, x9, x10)

inst_9235:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27642*FLEN/8, x13, x9, x10)

inst_9236:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27645*FLEN/8, x13, x9, x10)

inst_9237:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27648*FLEN/8, x13, x9, x10)

inst_9238:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27651*FLEN/8, x13, x9, x10)

inst_9239:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27654*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_72)

inst_9240:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:27657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27657*FLEN/8, x13, x9, x10)

inst_9241:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:27660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27660*FLEN/8, x13, x9, x10)

inst_9242:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:27663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27663*FLEN/8, x13, x9, x10)

inst_9243:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:27666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27666*FLEN/8, x13, x9, x10)

inst_9244:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:27669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27669*FLEN/8, x13, x9, x10)

inst_9245:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27672*FLEN/8, x13, x9, x10)

inst_9246:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27675*FLEN/8, x13, x9, x10)

inst_9247:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27678*FLEN/8, x13, x9, x10)

inst_9248:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:27681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27681*FLEN/8, x13, x9, x10)

inst_9249:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:27684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27684*FLEN/8, x13, x9, x10)

inst_9250:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:27687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27687*FLEN/8, x13, x9, x10)

inst_9251:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:27690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27690*FLEN/8, x13, x9, x10)

inst_9252:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27693*FLEN/8, x13, x9, x10)

inst_9253:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27696*FLEN/8, x13, x9, x10)

inst_9254:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27699*FLEN/8, x13, x9, x10)

inst_9255:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:27702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27702*FLEN/8, x13, x9, x10)

inst_9256:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27705*FLEN/8, x13, x9, x10)

inst_9257:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27708*FLEN/8, x13, x9, x10)

inst_9258:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27711*FLEN/8, x13, x9, x10)

inst_9259:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27714*FLEN/8, x13, x9, x10)

inst_9260:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27717*FLEN/8, x13, x9, x10)

inst_9261:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27720*FLEN/8, x13, x9, x10)

inst_9262:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27723*FLEN/8, x13, x9, x10)

inst_9263:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27726*FLEN/8, x13, x9, x10)

inst_9264:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:27729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27729*FLEN/8, x13, x9, x10)

inst_9265:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:27732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27732*FLEN/8, x13, x9, x10)

inst_9266:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:27735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27735*FLEN/8, x13, x9, x10)

inst_9267:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:27738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27738*FLEN/8, x13, x9, x10)

inst_9268:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:27741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27741*FLEN/8, x13, x9, x10)

inst_9269:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27744*FLEN/8, x13, x9, x10)

inst_9270:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27747*FLEN/8, x13, x9, x10)

inst_9271:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27750*FLEN/8, x13, x9, x10)

inst_9272:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:27753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27753*FLEN/8, x13, x9, x10)

inst_9273:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:27756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27756*FLEN/8, x13, x9, x10)

inst_9274:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:27759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27759*FLEN/8, x13, x9, x10)

inst_9275:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:27762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27762*FLEN/8, x13, x9, x10)

inst_9276:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27765*FLEN/8, x13, x9, x10)

inst_9277:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27768*FLEN/8, x13, x9, x10)

inst_9278:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27771*FLEN/8, x13, x9, x10)

inst_9279:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:27774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27774*FLEN/8, x13, x9, x10)

inst_9280:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27777*FLEN/8, x13, x9, x10)

inst_9281:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27780*FLEN/8, x13, x9, x10)

inst_9282:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27783*FLEN/8, x13, x9, x10)

inst_9283:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27786*FLEN/8, x13, x9, x10)

inst_9284:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27789*FLEN/8, x13, x9, x10)

inst_9285:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27792*FLEN/8, x13, x9, x10)

inst_9286:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27795*FLEN/8, x13, x9, x10)

inst_9287:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27798*FLEN/8, x13, x9, x10)

inst_9288:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:27801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27801*FLEN/8, x13, x9, x10)

inst_9289:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:27804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27804*FLEN/8, x13, x9, x10)

inst_9290:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:27807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27807*FLEN/8, x13, x9, x10)

inst_9291:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:27810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27810*FLEN/8, x13, x9, x10)

inst_9292:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:27813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27813*FLEN/8, x13, x9, x10)

inst_9293:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27816*FLEN/8, x13, x9, x10)

inst_9294:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27819*FLEN/8, x13, x9, x10)

inst_9295:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27822*FLEN/8, x13, x9, x10)

inst_9296:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:27825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27825*FLEN/8, x13, x9, x10)

inst_9297:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:27828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27828*FLEN/8, x13, x9, x10)

inst_9298:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:27831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27831*FLEN/8, x13, x9, x10)

inst_9299:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:27834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27834*FLEN/8, x13, x9, x10)

inst_9300:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27837*FLEN/8, x13, x9, x10)

inst_9301:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27840*FLEN/8, x13, x9, x10)

inst_9302:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27843*FLEN/8, x13, x9, x10)

inst_9303:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:27846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27846*FLEN/8, x13, x9, x10)

inst_9304:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27849*FLEN/8, x13, x9, x10)

inst_9305:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27852*FLEN/8, x13, x9, x10)

inst_9306:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27855*FLEN/8, x13, x9, x10)

inst_9307:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27858*FLEN/8, x13, x9, x10)

inst_9308:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27861*FLEN/8, x13, x9, x10)

inst_9309:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27864*FLEN/8, x13, x9, x10)

inst_9310:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27867*FLEN/8, x13, x9, x10)

inst_9311:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27870*FLEN/8, x13, x9, x10)

inst_9312:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:27873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27873*FLEN/8, x13, x9, x10)

inst_9313:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:27876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27876*FLEN/8, x13, x9, x10)

inst_9314:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:27879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27879*FLEN/8, x13, x9, x10)

inst_9315:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:27882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27882*FLEN/8, x13, x9, x10)

inst_9316:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:27885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27885*FLEN/8, x13, x9, x10)

inst_9317:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27888*FLEN/8, x13, x9, x10)

inst_9318:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27891*FLEN/8, x13, x9, x10)

inst_9319:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27894*FLEN/8, x13, x9, x10)

inst_9320:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:27897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27897*FLEN/8, x13, x9, x10)

inst_9321:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:27900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27900*FLEN/8, x13, x9, x10)

inst_9322:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:27903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27903*FLEN/8, x13, x9, x10)

inst_9323:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:27906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27906*FLEN/8, x13, x9, x10)

inst_9324:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27909*FLEN/8, x13, x9, x10)

inst_9325:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27912*FLEN/8, x13, x9, x10)

inst_9326:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27915*FLEN/8, x13, x9, x10)

inst_9327:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:27918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27918*FLEN/8, x13, x9, x10)

inst_9328:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27921*FLEN/8, x13, x9, x10)

inst_9329:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27924*FLEN/8, x13, x9, x10)

inst_9330:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27927*FLEN/8, x13, x9, x10)

inst_9331:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:27930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27930*FLEN/8, x13, x9, x10)

inst_9332:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:27933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27933*FLEN/8, x13, x9, x10)

inst_9333:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:27936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27936*FLEN/8, x13, x9, x10)

inst_9334:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:27939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27939*FLEN/8, x13, x9, x10)

inst_9335:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:27942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27942*FLEN/8, x13, x9, x10)

inst_9336:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:27945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27945*FLEN/8, x13, x9, x10)

inst_9337:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:27948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27948*FLEN/8, x13, x9, x10)

inst_9338:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:27951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27951*FLEN/8, x13, x9, x10)

inst_9339:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:27954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27954*FLEN/8, x13, x9, x10)

inst_9340:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:27957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27957*FLEN/8, x13, x9, x10)

inst_9341:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:27960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27960*FLEN/8, x13, x9, x10)

inst_9342:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:27963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27963*FLEN/8, x13, x9, x10)

inst_9343:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:27966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27966*FLEN/8, x13, x9, x10)

inst_9344:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:27969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27969*FLEN/8, x13, x9, x10)

inst_9345:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:27972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27972*FLEN/8, x13, x9, x10)

inst_9346:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:27975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27975*FLEN/8, x13, x9, x10)

inst_9347:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:27978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27978*FLEN/8, x13, x9, x10)

inst_9348:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:27981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27981*FLEN/8, x13, x9, x10)

inst_9349:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:27984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27984*FLEN/8, x13, x9, x10)

inst_9350:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:27987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27987*FLEN/8, x13, x9, x10)

inst_9351:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:27990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27990*FLEN/8, x13, x9, x10)

inst_9352:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:27993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27993*FLEN/8, x13, x9, x10)

inst_9353:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:27996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27996*FLEN/8, x13, x9, x10)

inst_9354:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:27999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 27999*FLEN/8, x13, x9, x10)

inst_9355:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28002*FLEN/8, x13, x9, x10)

inst_9356:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28005*FLEN/8, x13, x9, x10)

inst_9357:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28008*FLEN/8, x13, x9, x10)

inst_9358:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28011*FLEN/8, x13, x9, x10)

inst_9359:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28014*FLEN/8, x13, x9, x10)

inst_9360:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:28017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28017*FLEN/8, x13, x9, x10)

inst_9361:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:28020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28020*FLEN/8, x13, x9, x10)

inst_9362:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:28023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28023*FLEN/8, x13, x9, x10)

inst_9363:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:28026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28026*FLEN/8, x13, x9, x10)

inst_9364:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:28029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28029*FLEN/8, x13, x9, x10)

inst_9365:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28032*FLEN/8, x13, x9, x10)

inst_9366:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28035*FLEN/8, x13, x9, x10)

inst_9367:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28038*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_73)

inst_9368:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:28041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28041*FLEN/8, x13, x9, x10)

inst_9369:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:28044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28044*FLEN/8, x13, x9, x10)

inst_9370:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:28047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28047*FLEN/8, x13, x9, x10)

inst_9371:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:28050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28050*FLEN/8, x13, x9, x10)

inst_9372:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28053*FLEN/8, x13, x9, x10)

inst_9373:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28056*FLEN/8, x13, x9, x10)

inst_9374:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28059*FLEN/8, x13, x9, x10)

inst_9375:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:28062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28062*FLEN/8, x13, x9, x10)

inst_9376:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28065*FLEN/8, x13, x9, x10)

inst_9377:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28068*FLEN/8, x13, x9, x10)

inst_9378:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28071*FLEN/8, x13, x9, x10)

inst_9379:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28074*FLEN/8, x13, x9, x10)

inst_9380:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28077*FLEN/8, x13, x9, x10)

inst_9381:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28080*FLEN/8, x13, x9, x10)

inst_9382:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28083*FLEN/8, x13, x9, x10)

inst_9383:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28086*FLEN/8, x13, x9, x10)

inst_9384:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:28089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28089*FLEN/8, x13, x9, x10)

inst_9385:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:28092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28092*FLEN/8, x13, x9, x10)

inst_9386:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:28095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28095*FLEN/8, x13, x9, x10)

inst_9387:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:28098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28098*FLEN/8, x13, x9, x10)

inst_9388:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:28101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28101*FLEN/8, x13, x9, x10)

inst_9389:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28104*FLEN/8, x13, x9, x10)

inst_9390:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28107*FLEN/8, x13, x9, x10)

inst_9391:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28110*FLEN/8, x13, x9, x10)

inst_9392:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:28113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28113*FLEN/8, x13, x9, x10)

inst_9393:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:28116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28116*FLEN/8, x13, x9, x10)

inst_9394:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:28119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28119*FLEN/8, x13, x9, x10)

inst_9395:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:28122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28122*FLEN/8, x13, x9, x10)

inst_9396:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28125*FLEN/8, x13, x9, x10)

inst_9397:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28128*FLEN/8, x13, x9, x10)

inst_9398:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28131*FLEN/8, x13, x9, x10)

inst_9399:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:28134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28134*FLEN/8, x13, x9, x10)

inst_9400:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28137*FLEN/8, x13, x9, x10)

inst_9401:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28140*FLEN/8, x13, x9, x10)

inst_9402:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28143*FLEN/8, x13, x9, x10)

inst_9403:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28146*FLEN/8, x13, x9, x10)

inst_9404:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28149*FLEN/8, x13, x9, x10)

inst_9405:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28152*FLEN/8, x13, x9, x10)

inst_9406:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28155*FLEN/8, x13, x9, x10)

inst_9407:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28158*FLEN/8, x13, x9, x10)

inst_9408:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:28161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28161*FLEN/8, x13, x9, x10)

inst_9409:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:28164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28164*FLEN/8, x13, x9, x10)

inst_9410:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:28167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28167*FLEN/8, x13, x9, x10)

inst_9411:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:28170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28170*FLEN/8, x13, x9, x10)

inst_9412:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:28173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28173*FLEN/8, x13, x9, x10)

inst_9413:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28176*FLEN/8, x13, x9, x10)

inst_9414:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28179*FLEN/8, x13, x9, x10)

inst_9415:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28182*FLEN/8, x13, x9, x10)

inst_9416:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:28185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28185*FLEN/8, x13, x9, x10)

inst_9417:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:28188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28188*FLEN/8, x13, x9, x10)

inst_9418:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:28191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28191*FLEN/8, x13, x9, x10)

inst_9419:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:28194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28194*FLEN/8, x13, x9, x10)

inst_9420:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28197*FLEN/8, x13, x9, x10)

inst_9421:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28200*FLEN/8, x13, x9, x10)

inst_9422:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28203*FLEN/8, x13, x9, x10)

inst_9423:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:28206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28206*FLEN/8, x13, x9, x10)

inst_9424:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28209*FLEN/8, x13, x9, x10)

inst_9425:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28212*FLEN/8, x13, x9, x10)

inst_9426:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28215*FLEN/8, x13, x9, x10)

inst_9427:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28218*FLEN/8, x13, x9, x10)

inst_9428:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28221*FLEN/8, x13, x9, x10)

inst_9429:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28224*FLEN/8, x13, x9, x10)

inst_9430:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28227*FLEN/8, x13, x9, x10)

inst_9431:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28230*FLEN/8, x13, x9, x10)

inst_9432:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:28233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28233*FLEN/8, x13, x9, x10)

inst_9433:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:28236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28236*FLEN/8, x13, x9, x10)

inst_9434:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:28239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28239*FLEN/8, x13, x9, x10)

inst_9435:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:28242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28242*FLEN/8, x13, x9, x10)

inst_9436:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:28245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28245*FLEN/8, x13, x9, x10)

inst_9437:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28248*FLEN/8, x13, x9, x10)

inst_9438:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28251*FLEN/8, x13, x9, x10)

inst_9439:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28254*FLEN/8, x13, x9, x10)

inst_9440:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:28257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28257*FLEN/8, x13, x9, x10)

inst_9441:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:28260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28260*FLEN/8, x13, x9, x10)

inst_9442:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:28263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28263*FLEN/8, x13, x9, x10)

inst_9443:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:28266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28266*FLEN/8, x13, x9, x10)

inst_9444:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28269*FLEN/8, x13, x9, x10)

inst_9445:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28272*FLEN/8, x13, x9, x10)

inst_9446:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28275*FLEN/8, x13, x9, x10)

inst_9447:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:28278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28278*FLEN/8, x13, x9, x10)

inst_9448:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28281*FLEN/8, x13, x9, x10)

inst_9449:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28284*FLEN/8, x13, x9, x10)

inst_9450:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28287*FLEN/8, x13, x9, x10)

inst_9451:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28290*FLEN/8, x13, x9, x10)

inst_9452:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28293*FLEN/8, x13, x9, x10)

inst_9453:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28296*FLEN/8, x13, x9, x10)

inst_9454:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28299*FLEN/8, x13, x9, x10)

inst_9455:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28302*FLEN/8, x13, x9, x10)

inst_9456:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:28305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28305*FLEN/8, x13, x9, x10)

inst_9457:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:28308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28308*FLEN/8, x13, x9, x10)

inst_9458:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:28311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28311*FLEN/8, x13, x9, x10)

inst_9459:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:28314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28314*FLEN/8, x13, x9, x10)

inst_9460:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:28317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28317*FLEN/8, x13, x9, x10)

inst_9461:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28320*FLEN/8, x13, x9, x10)

inst_9462:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28323*FLEN/8, x13, x9, x10)

inst_9463:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28326*FLEN/8, x13, x9, x10)

inst_9464:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:28329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28329*FLEN/8, x13, x9, x10)

inst_9465:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:28332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28332*FLEN/8, x13, x9, x10)

inst_9466:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:28335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28335*FLEN/8, x13, x9, x10)

inst_9467:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:28338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28338*FLEN/8, x13, x9, x10)

inst_9468:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28341*FLEN/8, x13, x9, x10)

inst_9469:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28344*FLEN/8, x13, x9, x10)

inst_9470:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28347*FLEN/8, x13, x9, x10)

inst_9471:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:28350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28350*FLEN/8, x13, x9, x10)

inst_9472:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28353*FLEN/8, x13, x9, x10)

inst_9473:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28356*FLEN/8, x13, x9, x10)

inst_9474:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28359*FLEN/8, x13, x9, x10)

inst_9475:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28362*FLEN/8, x13, x9, x10)

inst_9476:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28365*FLEN/8, x13, x9, x10)

inst_9477:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28368*FLEN/8, x13, x9, x10)

inst_9478:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28371*FLEN/8, x13, x9, x10)

inst_9479:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28374*FLEN/8, x13, x9, x10)

inst_9480:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:28377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28377*FLEN/8, x13, x9, x10)

inst_9481:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:28380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28380*FLEN/8, x13, x9, x10)

inst_9482:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:28383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28383*FLEN/8, x13, x9, x10)

inst_9483:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:28386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28386*FLEN/8, x13, x9, x10)

inst_9484:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:28389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28389*FLEN/8, x13, x9, x10)

inst_9485:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28392*FLEN/8, x13, x9, x10)

inst_9486:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28395*FLEN/8, x13, x9, x10)

inst_9487:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28398*FLEN/8, x13, x9, x10)

inst_9488:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:28401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28401*FLEN/8, x13, x9, x10)

inst_9489:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:28404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28404*FLEN/8, x13, x9, x10)

inst_9490:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:28407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28407*FLEN/8, x13, x9, x10)

inst_9491:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:28410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28410*FLEN/8, x13, x9, x10)

inst_9492:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28413*FLEN/8, x13, x9, x10)

inst_9493:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28416*FLEN/8, x13, x9, x10)

inst_9494:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28419*FLEN/8, x13, x9, x10)

inst_9495:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:28422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28422*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_74)

inst_9496:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28425*FLEN/8, x13, x9, x10)

inst_9497:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28428*FLEN/8, x13, x9, x10)

inst_9498:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28431*FLEN/8, x13, x9, x10)

inst_9499:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28434*FLEN/8, x13, x9, x10)

inst_9500:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28437*FLEN/8, x13, x9, x10)

inst_9501:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28440*FLEN/8, x13, x9, x10)

inst_9502:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28443*FLEN/8, x13, x9, x10)

inst_9503:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28446*FLEN/8, x13, x9, x10)

inst_9504:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:28449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28449*FLEN/8, x13, x9, x10)

inst_9505:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:28452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28452*FLEN/8, x13, x9, x10)

inst_9506:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:28455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28455*FLEN/8, x13, x9, x10)

inst_9507:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:28458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28458*FLEN/8, x13, x9, x10)

inst_9508:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:28461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28461*FLEN/8, x13, x9, x10)

inst_9509:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28464*FLEN/8, x13, x9, x10)

inst_9510:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28467*FLEN/8, x13, x9, x10)

inst_9511:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28470*FLEN/8, x13, x9, x10)

inst_9512:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:28473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28473*FLEN/8, x13, x9, x10)

inst_9513:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:28476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28476*FLEN/8, x13, x9, x10)

inst_9514:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:28479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28479*FLEN/8, x13, x9, x10)

inst_9515:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:28482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28482*FLEN/8, x13, x9, x10)

inst_9516:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28485*FLEN/8, x13, x9, x10)

inst_9517:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28488*FLEN/8, x13, x9, x10)

inst_9518:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28491*FLEN/8, x13, x9, x10)

inst_9519:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:28494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28494*FLEN/8, x13, x9, x10)

inst_9520:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28497*FLEN/8, x13, x9, x10)

inst_9521:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28500*FLEN/8, x13, x9, x10)

inst_9522:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28503*FLEN/8, x13, x9, x10)

inst_9523:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28506*FLEN/8, x13, x9, x10)

inst_9524:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28509*FLEN/8, x13, x9, x10)

inst_9525:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28512*FLEN/8, x13, x9, x10)

inst_9526:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28515*FLEN/8, x13, x9, x10)

inst_9527:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28518*FLEN/8, x13, x9, x10)

inst_9528:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:28521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28521*FLEN/8, x13, x9, x10)

inst_9529:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:28524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28524*FLEN/8, x13, x9, x10)

inst_9530:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:28527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28527*FLEN/8, x13, x9, x10)

inst_9531:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:28530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28530*FLEN/8, x13, x9, x10)

inst_9532:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:28533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28533*FLEN/8, x13, x9, x10)

inst_9533:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28536*FLEN/8, x13, x9, x10)

inst_9534:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28539*FLEN/8, x13, x9, x10)

inst_9535:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28542*FLEN/8, x13, x9, x10)

inst_9536:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:28545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28545*FLEN/8, x13, x9, x10)

inst_9537:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:28548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28548*FLEN/8, x13, x9, x10)

inst_9538:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:28551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28551*FLEN/8, x13, x9, x10)

inst_9539:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:28554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28554*FLEN/8, x13, x9, x10)

inst_9540:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28557*FLEN/8, x13, x9, x10)

inst_9541:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28560*FLEN/8, x13, x9, x10)

inst_9542:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28563*FLEN/8, x13, x9, x10)

inst_9543:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:28566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28566*FLEN/8, x13, x9, x10)

inst_9544:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28569*FLEN/8, x13, x9, x10)

inst_9545:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28572*FLEN/8, x13, x9, x10)

inst_9546:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28575*FLEN/8, x13, x9, x10)

inst_9547:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28578*FLEN/8, x13, x9, x10)

inst_9548:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28581*FLEN/8, x13, x9, x10)

inst_9549:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28584*FLEN/8, x13, x9, x10)

inst_9550:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28587*FLEN/8, x13, x9, x10)

inst_9551:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28590*FLEN/8, x13, x9, x10)

inst_9552:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:28593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28593*FLEN/8, x13, x9, x10)

inst_9553:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:28596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28596*FLEN/8, x13, x9, x10)

inst_9554:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:28599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28599*FLEN/8, x13, x9, x10)

inst_9555:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:28602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28602*FLEN/8, x13, x9, x10)

inst_9556:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:28605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28605*FLEN/8, x13, x9, x10)

inst_9557:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28608*FLEN/8, x13, x9, x10)

inst_9558:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28611*FLEN/8, x13, x9, x10)

inst_9559:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28614*FLEN/8, x13, x9, x10)

inst_9560:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:28617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28617*FLEN/8, x13, x9, x10)

inst_9561:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:28620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28620*FLEN/8, x13, x9, x10)

inst_9562:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:28623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28623*FLEN/8, x13, x9, x10)

inst_9563:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:28626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28626*FLEN/8, x13, x9, x10)

inst_9564:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28629*FLEN/8, x13, x9, x10)

inst_9565:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28632*FLEN/8, x13, x9, x10)

inst_9566:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28635*FLEN/8, x13, x9, x10)

inst_9567:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:28638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28638*FLEN/8, x13, x9, x10)

inst_9568:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28641*FLEN/8, x13, x9, x10)

inst_9569:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28644*FLEN/8, x13, x9, x10)

inst_9570:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28647*FLEN/8, x13, x9, x10)

inst_9571:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28650*FLEN/8, x13, x9, x10)

inst_9572:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28653*FLEN/8, x13, x9, x10)

inst_9573:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28656*FLEN/8, x13, x9, x10)

inst_9574:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28659*FLEN/8, x13, x9, x10)

inst_9575:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28662*FLEN/8, x13, x9, x10)

inst_9576:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:28665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28665*FLEN/8, x13, x9, x10)

inst_9577:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:28668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28668*FLEN/8, x13, x9, x10)

inst_9578:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:28671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28671*FLEN/8, x13, x9, x10)

inst_9579:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:28674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28674*FLEN/8, x13, x9, x10)

inst_9580:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:28677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28677*FLEN/8, x13, x9, x10)

inst_9581:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28680*FLEN/8, x13, x9, x10)

inst_9582:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28683*FLEN/8, x13, x9, x10)

inst_9583:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28686*FLEN/8, x13, x9, x10)

inst_9584:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:28689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28689*FLEN/8, x13, x9, x10)

inst_9585:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:28692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28692*FLEN/8, x13, x9, x10)

inst_9586:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:28695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28695*FLEN/8, x13, x9, x10)

inst_9587:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:28698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28698*FLEN/8, x13, x9, x10)

inst_9588:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28701*FLEN/8, x13, x9, x10)

inst_9589:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28704*FLEN/8, x13, x9, x10)

inst_9590:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28707*FLEN/8, x13, x9, x10)

inst_9591:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:28710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28710*FLEN/8, x13, x9, x10)

inst_9592:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28713*FLEN/8, x13, x9, x10)

inst_9593:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28716*FLEN/8, x13, x9, x10)

inst_9594:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28719*FLEN/8, x13, x9, x10)

inst_9595:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28722*FLEN/8, x13, x9, x10)

inst_9596:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28725*FLEN/8, x13, x9, x10)

inst_9597:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28728*FLEN/8, x13, x9, x10)

inst_9598:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28731*FLEN/8, x13, x9, x10)

inst_9599:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28734*FLEN/8, x13, x9, x10)

inst_9600:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:28737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28737*FLEN/8, x13, x9, x10)

inst_9601:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:28740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28740*FLEN/8, x13, x9, x10)

inst_9602:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:28743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28743*FLEN/8, x13, x9, x10)

inst_9603:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:28746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28746*FLEN/8, x13, x9, x10)

inst_9604:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:28749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28749*FLEN/8, x13, x9, x10)

inst_9605:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28752*FLEN/8, x13, x9, x10)

inst_9606:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28755*FLEN/8, x13, x9, x10)

inst_9607:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28758*FLEN/8, x13, x9, x10)

inst_9608:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:28761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28761*FLEN/8, x13, x9, x10)

inst_9609:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:28764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28764*FLEN/8, x13, x9, x10)

inst_9610:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:28767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28767*FLEN/8, x13, x9, x10)

inst_9611:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:28770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28770*FLEN/8, x13, x9, x10)

inst_9612:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28773*FLEN/8, x13, x9, x10)

inst_9613:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28776*FLEN/8, x13, x9, x10)

inst_9614:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28779*FLEN/8, x13, x9, x10)

inst_9615:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:28782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28782*FLEN/8, x13, x9, x10)

inst_9616:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28785*FLEN/8, x13, x9, x10)

inst_9617:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28788*FLEN/8, x13, x9, x10)

inst_9618:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28791*FLEN/8, x13, x9, x10)

inst_9619:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28794*FLEN/8, x13, x9, x10)

inst_9620:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28797*FLEN/8, x13, x9, x10)

inst_9621:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28800*FLEN/8, x13, x9, x10)

inst_9622:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28803*FLEN/8, x13, x9, x10)

inst_9623:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28806*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_75)

inst_9624:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:28809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28809*FLEN/8, x13, x9, x10)

inst_9625:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:28812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28812*FLEN/8, x13, x9, x10)

inst_9626:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:28815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28815*FLEN/8, x13, x9, x10)

inst_9627:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:28818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28818*FLEN/8, x13, x9, x10)

inst_9628:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:28821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28821*FLEN/8, x13, x9, x10)

inst_9629:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28824*FLEN/8, x13, x9, x10)

inst_9630:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28827*FLEN/8, x13, x9, x10)

inst_9631:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28830*FLEN/8, x13, x9, x10)

inst_9632:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:28833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28833*FLEN/8, x13, x9, x10)

inst_9633:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:28836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28836*FLEN/8, x13, x9, x10)

inst_9634:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:28839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28839*FLEN/8, x13, x9, x10)

inst_9635:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:28842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28842*FLEN/8, x13, x9, x10)

inst_9636:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28845*FLEN/8, x13, x9, x10)

inst_9637:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28848*FLEN/8, x13, x9, x10)

inst_9638:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28851*FLEN/8, x13, x9, x10)

inst_9639:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:28854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28854*FLEN/8, x13, x9, x10)

inst_9640:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28857*FLEN/8, x13, x9, x10)

inst_9641:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28860*FLEN/8, x13, x9, x10)

inst_9642:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28863*FLEN/8, x13, x9, x10)

inst_9643:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28866*FLEN/8, x13, x9, x10)

inst_9644:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28869*FLEN/8, x13, x9, x10)

inst_9645:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28872*FLEN/8, x13, x9, x10)

inst_9646:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28875*FLEN/8, x13, x9, x10)

inst_9647:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28878*FLEN/8, x13, x9, x10)

inst_9648:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:28881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28881*FLEN/8, x13, x9, x10)

inst_9649:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:28884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28884*FLEN/8, x13, x9, x10)

inst_9650:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:28887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28887*FLEN/8, x13, x9, x10)

inst_9651:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:28890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28890*FLEN/8, x13, x9, x10)

inst_9652:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:28893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28893*FLEN/8, x13, x9, x10)

inst_9653:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28896*FLEN/8, x13, x9, x10)

inst_9654:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28899*FLEN/8, x13, x9, x10)

inst_9655:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28902*FLEN/8, x13, x9, x10)

inst_9656:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:28905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28905*FLEN/8, x13, x9, x10)

inst_9657:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:28908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28908*FLEN/8, x13, x9, x10)

inst_9658:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:28911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28911*FLEN/8, x13, x9, x10)

inst_9659:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:28914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28914*FLEN/8, x13, x9, x10)

inst_9660:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28917*FLEN/8, x13, x9, x10)

inst_9661:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28920*FLEN/8, x13, x9, x10)

inst_9662:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28923*FLEN/8, x13, x9, x10)

inst_9663:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:28926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28926*FLEN/8, x13, x9, x10)

inst_9664:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:28929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28929*FLEN/8, x13, x9, x10)

inst_9665:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:28932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28932*FLEN/8, x13, x9, x10)

inst_9666:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:28935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28935*FLEN/8, x13, x9, x10)

inst_9667:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:28938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28938*FLEN/8, x13, x9, x10)

inst_9668:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:28941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28941*FLEN/8, x13, x9, x10)

inst_9669:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:28944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28944*FLEN/8, x13, x9, x10)

inst_9670:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:28947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28947*FLEN/8, x13, x9, x10)

inst_9671:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:28950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28950*FLEN/8, x13, x9, x10)

inst_9672:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:28953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28953*FLEN/8, x13, x9, x10)

inst_9673:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:28956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28956*FLEN/8, x13, x9, x10)

inst_9674:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:28959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28959*FLEN/8, x13, x9, x10)

inst_9675:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:28962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28962*FLEN/8, x13, x9, x10)

inst_9676:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:28965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28965*FLEN/8, x13, x9, x10)

inst_9677:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:28968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28968*FLEN/8, x13, x9, x10)

inst_9678:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:28971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28971*FLEN/8, x13, x9, x10)

inst_9679:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:28974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28974*FLEN/8, x13, x9, x10)

inst_9680:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:28977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28977*FLEN/8, x13, x9, x10)

inst_9681:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:28980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28980*FLEN/8, x13, x9, x10)

inst_9682:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:28983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28983*FLEN/8, x13, x9, x10)

inst_9683:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:28986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28986*FLEN/8, x13, x9, x10)

inst_9684:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:28989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28989*FLEN/8, x13, x9, x10)

inst_9685:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:28992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28992*FLEN/8, x13, x9, x10)

inst_9686:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:28995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28995*FLEN/8, x13, x9, x10)

inst_9687:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:28998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 28998*FLEN/8, x13, x9, x10)

inst_9688:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29001*FLEN/8, x13, x9, x10)

inst_9689:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29004*FLEN/8, x13, x9, x10)

inst_9690:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29007*FLEN/8, x13, x9, x10)

inst_9691:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29010*FLEN/8, x13, x9, x10)

inst_9692:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29013*FLEN/8, x13, x9, x10)

inst_9693:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29016*FLEN/8, x13, x9, x10)

inst_9694:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29019*FLEN/8, x13, x9, x10)

inst_9695:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29022*FLEN/8, x13, x9, x10)

inst_9696:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:29025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29025*FLEN/8, x13, x9, x10)

inst_9697:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:29028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29028*FLEN/8, x13, x9, x10)

inst_9698:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:29031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29031*FLEN/8, x13, x9, x10)

inst_9699:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:29034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29034*FLEN/8, x13, x9, x10)

inst_9700:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:29037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29037*FLEN/8, x13, x9, x10)

inst_9701:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29040*FLEN/8, x13, x9, x10)

inst_9702:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29043*FLEN/8, x13, x9, x10)

inst_9703:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29046*FLEN/8, x13, x9, x10)

inst_9704:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:29049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29049*FLEN/8, x13, x9, x10)

inst_9705:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:29052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29052*FLEN/8, x13, x9, x10)

inst_9706:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:29055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29055*FLEN/8, x13, x9, x10)

inst_9707:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:29058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29058*FLEN/8, x13, x9, x10)

inst_9708:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29061*FLEN/8, x13, x9, x10)

inst_9709:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29064*FLEN/8, x13, x9, x10)

inst_9710:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29067*FLEN/8, x13, x9, x10)

inst_9711:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:29070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29070*FLEN/8, x13, x9, x10)

inst_9712:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29073*FLEN/8, x13, x9, x10)

inst_9713:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29076*FLEN/8, x13, x9, x10)

inst_9714:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29079*FLEN/8, x13, x9, x10)

inst_9715:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29082*FLEN/8, x13, x9, x10)

inst_9716:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29085*FLEN/8, x13, x9, x10)

inst_9717:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29088*FLEN/8, x13, x9, x10)

inst_9718:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29091*FLEN/8, x13, x9, x10)

inst_9719:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29094*FLEN/8, x13, x9, x10)

inst_9720:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:29097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29097*FLEN/8, x13, x9, x10)

inst_9721:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:29100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29100*FLEN/8, x13, x9, x10)

inst_9722:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:29103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29103*FLEN/8, x13, x9, x10)

inst_9723:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:29106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29106*FLEN/8, x13, x9, x10)

inst_9724:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:29109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29109*FLEN/8, x13, x9, x10)

inst_9725:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29112*FLEN/8, x13, x9, x10)

inst_9726:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29115*FLEN/8, x13, x9, x10)

inst_9727:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29118*FLEN/8, x13, x9, x10)

inst_9728:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:29121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29121*FLEN/8, x13, x9, x10)

inst_9729:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:29124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29124*FLEN/8, x13, x9, x10)

inst_9730:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:29127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29127*FLEN/8, x13, x9, x10)

inst_9731:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:29130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29130*FLEN/8, x13, x9, x10)

inst_9732:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29133*FLEN/8, x13, x9, x10)

inst_9733:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29136*FLEN/8, x13, x9, x10)

inst_9734:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29139*FLEN/8, x13, x9, x10)

inst_9735:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:29142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29142*FLEN/8, x13, x9, x10)

inst_9736:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29145*FLEN/8, x13, x9, x10)

inst_9737:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29148*FLEN/8, x13, x9, x10)

inst_9738:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29151*FLEN/8, x13, x9, x10)

inst_9739:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29154*FLEN/8, x13, x9, x10)

inst_9740:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29157*FLEN/8, x13, x9, x10)

inst_9741:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29160*FLEN/8, x13, x9, x10)

inst_9742:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29163*FLEN/8, x13, x9, x10)

inst_9743:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29166*FLEN/8, x13, x9, x10)

inst_9744:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:29169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29169*FLEN/8, x13, x9, x10)

inst_9745:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:29172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29172*FLEN/8, x13, x9, x10)

inst_9746:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:29175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29175*FLEN/8, x13, x9, x10)

inst_9747:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:29178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29178*FLEN/8, x13, x9, x10)

inst_9748:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:29181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29181*FLEN/8, x13, x9, x10)

inst_9749:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29184*FLEN/8, x13, x9, x10)

inst_9750:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29187*FLEN/8, x13, x9, x10)

inst_9751:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29190*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_76)

inst_9752:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:29193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29193*FLEN/8, x13, x9, x10)

inst_9753:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:29196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29196*FLEN/8, x13, x9, x10)

inst_9754:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:29199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29199*FLEN/8, x13, x9, x10)

inst_9755:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:29202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29202*FLEN/8, x13, x9, x10)

inst_9756:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29205*FLEN/8, x13, x9, x10)

inst_9757:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29208*FLEN/8, x13, x9, x10)

inst_9758:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29211*FLEN/8, x13, x9, x10)

inst_9759:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:29214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29214*FLEN/8, x13, x9, x10)

inst_9760:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29217*FLEN/8, x13, x9, x10)

inst_9761:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29220*FLEN/8, x13, x9, x10)

inst_9762:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29223*FLEN/8, x13, x9, x10)

inst_9763:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29226*FLEN/8, x13, x9, x10)

inst_9764:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29229*FLEN/8, x13, x9, x10)

inst_9765:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29232*FLEN/8, x13, x9, x10)

inst_9766:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29235*FLEN/8, x13, x9, x10)

inst_9767:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29238*FLEN/8, x13, x9, x10)

inst_9768:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:29241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29241*FLEN/8, x13, x9, x10)

inst_9769:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:29244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29244*FLEN/8, x13, x9, x10)

inst_9770:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:29247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29247*FLEN/8, x13, x9, x10)

inst_9771:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:29250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29250*FLEN/8, x13, x9, x10)

inst_9772:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:29253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29253*FLEN/8, x13, x9, x10)

inst_9773:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29256*FLEN/8, x13, x9, x10)

inst_9774:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29259*FLEN/8, x13, x9, x10)

inst_9775:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29262*FLEN/8, x13, x9, x10)

inst_9776:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:29265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29265*FLEN/8, x13, x9, x10)

inst_9777:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:29268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29268*FLEN/8, x13, x9, x10)

inst_9778:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:29271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29271*FLEN/8, x13, x9, x10)

inst_9779:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:29274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29274*FLEN/8, x13, x9, x10)

inst_9780:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29277*FLEN/8, x13, x9, x10)

inst_9781:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29280*FLEN/8, x13, x9, x10)

inst_9782:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29283*FLEN/8, x13, x9, x10)

inst_9783:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:29286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29286*FLEN/8, x13, x9, x10)

inst_9784:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29289*FLEN/8, x13, x9, x10)

inst_9785:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29292*FLEN/8, x13, x9, x10)

inst_9786:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29295*FLEN/8, x13, x9, x10)

inst_9787:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29298*FLEN/8, x13, x9, x10)

inst_9788:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29301*FLEN/8, x13, x9, x10)

inst_9789:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29304*FLEN/8, x13, x9, x10)

inst_9790:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29307*FLEN/8, x13, x9, x10)

inst_9791:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29310*FLEN/8, x13, x9, x10)

inst_9792:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:29313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29313*FLEN/8, x13, x9, x10)

inst_9793:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:29316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29316*FLEN/8, x13, x9, x10)

inst_9794:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:29319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29319*FLEN/8, x13, x9, x10)

inst_9795:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:29322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29322*FLEN/8, x13, x9, x10)

inst_9796:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:29325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29325*FLEN/8, x13, x9, x10)

inst_9797:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29328*FLEN/8, x13, x9, x10)

inst_9798:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29331*FLEN/8, x13, x9, x10)

inst_9799:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29334*FLEN/8, x13, x9, x10)

inst_9800:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:29337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29337*FLEN/8, x13, x9, x10)

inst_9801:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:29340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29340*FLEN/8, x13, x9, x10)

inst_9802:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:29343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29343*FLEN/8, x13, x9, x10)

inst_9803:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:29346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29346*FLEN/8, x13, x9, x10)

inst_9804:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29349*FLEN/8, x13, x9, x10)

inst_9805:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29352*FLEN/8, x13, x9, x10)

inst_9806:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29355*FLEN/8, x13, x9, x10)

inst_9807:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:29358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29358*FLEN/8, x13, x9, x10)

inst_9808:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29361*FLEN/8, x13, x9, x10)

inst_9809:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29364*FLEN/8, x13, x9, x10)

inst_9810:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29367*FLEN/8, x13, x9, x10)

inst_9811:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29370*FLEN/8, x13, x9, x10)

inst_9812:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29373*FLEN/8, x13, x9, x10)

inst_9813:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29376*FLEN/8, x13, x9, x10)

inst_9814:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29379*FLEN/8, x13, x9, x10)

inst_9815:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29382*FLEN/8, x13, x9, x10)

inst_9816:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:29385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29385*FLEN/8, x13, x9, x10)

inst_9817:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:29388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29388*FLEN/8, x13, x9, x10)

inst_9818:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:29391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29391*FLEN/8, x13, x9, x10)

inst_9819:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:29394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29394*FLEN/8, x13, x9, x10)

inst_9820:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:29397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29397*FLEN/8, x13, x9, x10)

inst_9821:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29400*FLEN/8, x13, x9, x10)

inst_9822:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29403*FLEN/8, x13, x9, x10)

inst_9823:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29406*FLEN/8, x13, x9, x10)

inst_9824:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:29409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29409*FLEN/8, x13, x9, x10)

inst_9825:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:29412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29412*FLEN/8, x13, x9, x10)

inst_9826:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:29415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29415*FLEN/8, x13, x9, x10)

inst_9827:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:29418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29418*FLEN/8, x13, x9, x10)

inst_9828:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29421*FLEN/8, x13, x9, x10)

inst_9829:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29424*FLEN/8, x13, x9, x10)

inst_9830:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29427*FLEN/8, x13, x9, x10)

inst_9831:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:29430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29430*FLEN/8, x13, x9, x10)

inst_9832:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29433*FLEN/8, x13, x9, x10)

inst_9833:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29436*FLEN/8, x13, x9, x10)

inst_9834:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29439*FLEN/8, x13, x9, x10)

inst_9835:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29442*FLEN/8, x13, x9, x10)

inst_9836:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29445*FLEN/8, x13, x9, x10)

inst_9837:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29448*FLEN/8, x13, x9, x10)

inst_9838:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29451*FLEN/8, x13, x9, x10)

inst_9839:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29454*FLEN/8, x13, x9, x10)

inst_9840:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:29457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29457*FLEN/8, x13, x9, x10)

inst_9841:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:29460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29460*FLEN/8, x13, x9, x10)

inst_9842:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:29463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29463*FLEN/8, x13, x9, x10)

inst_9843:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:29466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29466*FLEN/8, x13, x9, x10)

inst_9844:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:29469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29469*FLEN/8, x13, x9, x10)

inst_9845:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29472*FLEN/8, x13, x9, x10)

inst_9846:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29475*FLEN/8, x13, x9, x10)

inst_9847:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29478*FLEN/8, x13, x9, x10)

inst_9848:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:29481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29481*FLEN/8, x13, x9, x10)

inst_9849:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:29484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29484*FLEN/8, x13, x9, x10)

inst_9850:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:29487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29487*FLEN/8, x13, x9, x10)

inst_9851:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:29490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29490*FLEN/8, x13, x9, x10)

inst_9852:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29493*FLEN/8, x13, x9, x10)

inst_9853:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29496*FLEN/8, x13, x9, x10)

inst_9854:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29499*FLEN/8, x13, x9, x10)

inst_9855:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:29502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29502*FLEN/8, x13, x9, x10)

inst_9856:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29505*FLEN/8, x13, x9, x10)

inst_9857:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29508*FLEN/8, x13, x9, x10)

inst_9858:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29511*FLEN/8, x13, x9, x10)

inst_9859:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29514*FLEN/8, x13, x9, x10)

inst_9860:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29517*FLEN/8, x13, x9, x10)

inst_9861:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29520*FLEN/8, x13, x9, x10)

inst_9862:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29523*FLEN/8, x13, x9, x10)

inst_9863:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29526*FLEN/8, x13, x9, x10)

inst_9864:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:29529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29529*FLEN/8, x13, x9, x10)

inst_9865:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:29532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29532*FLEN/8, x13, x9, x10)

inst_9866:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:29535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29535*FLEN/8, x13, x9, x10)

inst_9867:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:29538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29538*FLEN/8, x13, x9, x10)

inst_9868:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:29541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29541*FLEN/8, x13, x9, x10)

inst_9869:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29544*FLEN/8, x13, x9, x10)

inst_9870:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29547*FLEN/8, x13, x9, x10)

inst_9871:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29550*FLEN/8, x13, x9, x10)

inst_9872:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:29553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29553*FLEN/8, x13, x9, x10)

inst_9873:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:29556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29556*FLEN/8, x13, x9, x10)

inst_9874:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:29559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29559*FLEN/8, x13, x9, x10)

inst_9875:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:29562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29562*FLEN/8, x13, x9, x10)

inst_9876:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29565*FLEN/8, x13, x9, x10)

inst_9877:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29568*FLEN/8, x13, x9, x10)

inst_9878:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29571*FLEN/8, x13, x9, x10)

inst_9879:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:29574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29574*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_77)

inst_9880:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29577*FLEN/8, x13, x9, x10)

inst_9881:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29580*FLEN/8, x13, x9, x10)

inst_9882:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29583*FLEN/8, x13, x9, x10)

inst_9883:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29586*FLEN/8, x13, x9, x10)

inst_9884:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29589*FLEN/8, x13, x9, x10)

inst_9885:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29592*FLEN/8, x13, x9, x10)

inst_9886:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29595*FLEN/8, x13, x9, x10)

inst_9887:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29598*FLEN/8, x13, x9, x10)

inst_9888:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:29601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29601*FLEN/8, x13, x9, x10)

inst_9889:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:29604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29604*FLEN/8, x13, x9, x10)

inst_9890:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:29607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29607*FLEN/8, x13, x9, x10)

inst_9891:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:29610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29610*FLEN/8, x13, x9, x10)

inst_9892:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:29613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29613*FLEN/8, x13, x9, x10)

inst_9893:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29616*FLEN/8, x13, x9, x10)

inst_9894:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29619*FLEN/8, x13, x9, x10)

inst_9895:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29622*FLEN/8, x13, x9, x10)

inst_9896:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:29625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29625*FLEN/8, x13, x9, x10)

inst_9897:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:29628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29628*FLEN/8, x13, x9, x10)

inst_9898:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:29631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29631*FLEN/8, x13, x9, x10)

inst_9899:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:29634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29634*FLEN/8, x13, x9, x10)

inst_9900:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29637*FLEN/8, x13, x9, x10)

inst_9901:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29640*FLEN/8, x13, x9, x10)

inst_9902:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29643*FLEN/8, x13, x9, x10)

inst_9903:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:29646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29646*FLEN/8, x13, x9, x10)

inst_9904:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29649*FLEN/8, x13, x9, x10)

inst_9905:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29652*FLEN/8, x13, x9, x10)

inst_9906:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29655*FLEN/8, x13, x9, x10)

inst_9907:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29658*FLEN/8, x13, x9, x10)

inst_9908:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29661*FLEN/8, x13, x9, x10)

inst_9909:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29664*FLEN/8, x13, x9, x10)

inst_9910:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29667*FLEN/8, x13, x9, x10)

inst_9911:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29670*FLEN/8, x13, x9, x10)

inst_9912:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:29673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29673*FLEN/8, x13, x9, x10)

inst_9913:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:29676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29676*FLEN/8, x13, x9, x10)

inst_9914:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:29679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29679*FLEN/8, x13, x9, x10)

inst_9915:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:29682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29682*FLEN/8, x13, x9, x10)

inst_9916:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:29685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29685*FLEN/8, x13, x9, x10)

inst_9917:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29688*FLEN/8, x13, x9, x10)

inst_9918:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29691*FLEN/8, x13, x9, x10)

inst_9919:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29694*FLEN/8, x13, x9, x10)

inst_9920:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:29697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29697*FLEN/8, x13, x9, x10)

inst_9921:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:29700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29700*FLEN/8, x13, x9, x10)

inst_9922:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:29703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29703*FLEN/8, x13, x9, x10)

inst_9923:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:29706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29706*FLEN/8, x13, x9, x10)

inst_9924:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29709*FLEN/8, x13, x9, x10)

inst_9925:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29712*FLEN/8, x13, x9, x10)

inst_9926:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29715*FLEN/8, x13, x9, x10)

inst_9927:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:29718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29718*FLEN/8, x13, x9, x10)

inst_9928:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29721*FLEN/8, x13, x9, x10)

inst_9929:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29724*FLEN/8, x13, x9, x10)

inst_9930:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29727*FLEN/8, x13, x9, x10)

inst_9931:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29730*FLEN/8, x13, x9, x10)

inst_9932:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29733*FLEN/8, x13, x9, x10)

inst_9933:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29736*FLEN/8, x13, x9, x10)

inst_9934:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29739*FLEN/8, x13, x9, x10)

inst_9935:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29742*FLEN/8, x13, x9, x10)

inst_9936:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:29745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29745*FLEN/8, x13, x9, x10)

inst_9937:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:29748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29748*FLEN/8, x13, x9, x10)

inst_9938:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:29751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29751*FLEN/8, x13, x9, x10)

inst_9939:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:29754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29754*FLEN/8, x13, x9, x10)

inst_9940:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:29757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29757*FLEN/8, x13, x9, x10)

inst_9941:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29760*FLEN/8, x13, x9, x10)

inst_9942:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29763*FLEN/8, x13, x9, x10)

inst_9943:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29766*FLEN/8, x13, x9, x10)

inst_9944:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:29769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29769*FLEN/8, x13, x9, x10)

inst_9945:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:29772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29772*FLEN/8, x13, x9, x10)

inst_9946:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:29775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29775*FLEN/8, x13, x9, x10)

inst_9947:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:29778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29778*FLEN/8, x13, x9, x10)

inst_9948:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29781*FLEN/8, x13, x9, x10)

inst_9949:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29784*FLEN/8, x13, x9, x10)

inst_9950:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29787*FLEN/8, x13, x9, x10)

inst_9951:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:29790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29790*FLEN/8, x13, x9, x10)

inst_9952:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29793*FLEN/8, x13, x9, x10)

inst_9953:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29796*FLEN/8, x13, x9, x10)

inst_9954:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29799*FLEN/8, x13, x9, x10)

inst_9955:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29802*FLEN/8, x13, x9, x10)

inst_9956:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29805*FLEN/8, x13, x9, x10)

inst_9957:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29808*FLEN/8, x13, x9, x10)

inst_9958:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29811*FLEN/8, x13, x9, x10)

inst_9959:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29814*FLEN/8, x13, x9, x10)

inst_9960:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:29817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29817*FLEN/8, x13, x9, x10)

inst_9961:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:29820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29820*FLEN/8, x13, x9, x10)

inst_9962:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:29823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29823*FLEN/8, x13, x9, x10)

inst_9963:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:29826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29826*FLEN/8, x13, x9, x10)

inst_9964:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:29829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29829*FLEN/8, x13, x9, x10)

inst_9965:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29832*FLEN/8, x13, x9, x10)

inst_9966:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29835*FLEN/8, x13, x9, x10)

inst_9967:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29838*FLEN/8, x13, x9, x10)

inst_9968:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:29841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29841*FLEN/8, x13, x9, x10)

inst_9969:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:29844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29844*FLEN/8, x13, x9, x10)

inst_9970:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:29847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29847*FLEN/8, x13, x9, x10)

inst_9971:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:29850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29850*FLEN/8, x13, x9, x10)

inst_9972:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29853*FLEN/8, x13, x9, x10)

inst_9973:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29856*FLEN/8, x13, x9, x10)

inst_9974:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29859*FLEN/8, x13, x9, x10)

inst_9975:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:29862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29862*FLEN/8, x13, x9, x10)

inst_9976:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29865*FLEN/8, x13, x9, x10)

inst_9977:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29868*FLEN/8, x13, x9, x10)

inst_9978:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29871*FLEN/8, x13, x9, x10)

inst_9979:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29874*FLEN/8, x13, x9, x10)

inst_9980:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29877*FLEN/8, x13, x9, x10)

inst_9981:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29880*FLEN/8, x13, x9, x10)

inst_9982:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29883*FLEN/8, x13, x9, x10)

inst_9983:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29886*FLEN/8, x13, x9, x10)

inst_9984:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:29889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29889*FLEN/8, x13, x9, x10)

inst_9985:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:29892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29892*FLEN/8, x13, x9, x10)

inst_9986:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:29895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29895*FLEN/8, x13, x9, x10)

inst_9987:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:29898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29898*FLEN/8, x13, x9, x10)

inst_9988:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:29901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29901*FLEN/8, x13, x9, x10)

inst_9989:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29904*FLEN/8, x13, x9, x10)

inst_9990:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29907*FLEN/8, x13, x9, x10)

inst_9991:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29910*FLEN/8, x13, x9, x10)

inst_9992:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:29913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29913*FLEN/8, x13, x9, x10)

inst_9993:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:29916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29916*FLEN/8, x13, x9, x10)

inst_9994:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:29919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29919*FLEN/8, x13, x9, x10)

inst_9995:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:29922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29922*FLEN/8, x13, x9, x10)

inst_9996:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29925*FLEN/8, x13, x9, x10)

inst_9997:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:29928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29928*FLEN/8, x13, x9, x10)

inst_9998:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:29931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29931*FLEN/8, x13, x9, x10)

inst_9999:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:29934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29934*FLEN/8, x13, x9, x10)

inst_10000:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:29937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29937*FLEN/8, x13, x9, x10)

inst_10001:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:29940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29940*FLEN/8, x13, x9, x10)

inst_10002:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:29943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29943*FLEN/8, x13, x9, x10)

inst_10003:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:29946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29946*FLEN/8, x13, x9, x10)

inst_10004:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:29949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29949*FLEN/8, x13, x9, x10)

inst_10005:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:29952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29952*FLEN/8, x13, x9, x10)

inst_10006:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:29955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29955*FLEN/8, x13, x9, x10)

inst_10007:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:29958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29958*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_78)

inst_10008:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:29961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29961*FLEN/8, x13, x9, x10)

inst_10009:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:29964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29964*FLEN/8, x13, x9, x10)

inst_10010:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:29967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29967*FLEN/8, x13, x9, x10)

inst_10011:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:29970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29970*FLEN/8, x13, x9, x10)

inst_10012:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:29973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29973*FLEN/8, x13, x9, x10)

inst_10013:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:29976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29976*FLEN/8, x13, x9, x10)

inst_10014:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:29979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29979*FLEN/8, x13, x9, x10)

inst_10015:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:29982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29982*FLEN/8, x13, x9, x10)

inst_10016:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:29985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29985*FLEN/8, x13, x9, x10)

inst_10017:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:29988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29988*FLEN/8, x13, x9, x10)

inst_10018:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:29991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29991*FLEN/8, x13, x9, x10)

inst_10019:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:29994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29994*FLEN/8, x13, x9, x10)

inst_10020:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:29997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 29997*FLEN/8, x13, x9, x10)

inst_10021:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30000*FLEN/8, x13, x9, x10)

inst_10022:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30003*FLEN/8, x13, x9, x10)

inst_10023:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:30006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30006*FLEN/8, x13, x9, x10)

inst_10024:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30009*FLEN/8, x13, x9, x10)

inst_10025:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30012*FLEN/8, x13, x9, x10)

inst_10026:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30015*FLEN/8, x13, x9, x10)

inst_10027:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30018*FLEN/8, x13, x9, x10)

inst_10028:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30021*FLEN/8, x13, x9, x10)

inst_10029:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30024*FLEN/8, x13, x9, x10)

inst_10030:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30027*FLEN/8, x13, x9, x10)

inst_10031:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30030*FLEN/8, x13, x9, x10)

inst_10032:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:30033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30033*FLEN/8, x13, x9, x10)

inst_10033:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:30036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30036*FLEN/8, x13, x9, x10)

inst_10034:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:30039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30039*FLEN/8, x13, x9, x10)

inst_10035:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:30042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30042*FLEN/8, x13, x9, x10)

inst_10036:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:30045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30045*FLEN/8, x13, x9, x10)

inst_10037:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30048*FLEN/8, x13, x9, x10)

inst_10038:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30051*FLEN/8, x13, x9, x10)

inst_10039:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30054*FLEN/8, x13, x9, x10)

inst_10040:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:30057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30057*FLEN/8, x13, x9, x10)

inst_10041:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:30060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30060*FLEN/8, x13, x9, x10)

inst_10042:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:30063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30063*FLEN/8, x13, x9, x10)

inst_10043:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:30066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30066*FLEN/8, x13, x9, x10)

inst_10044:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30069*FLEN/8, x13, x9, x10)

inst_10045:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30072*FLEN/8, x13, x9, x10)

inst_10046:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30075*FLEN/8, x13, x9, x10)

inst_10047:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:30078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30078*FLEN/8, x13, x9, x10)

inst_10048:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30081*FLEN/8, x13, x9, x10)

inst_10049:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30084*FLEN/8, x13, x9, x10)

inst_10050:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30087*FLEN/8, x13, x9, x10)

inst_10051:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30090*FLEN/8, x13, x9, x10)

inst_10052:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30093*FLEN/8, x13, x9, x10)

inst_10053:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30096*FLEN/8, x13, x9, x10)

inst_10054:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30099*FLEN/8, x13, x9, x10)

inst_10055:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30102*FLEN/8, x13, x9, x10)

inst_10056:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:30105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30105*FLEN/8, x13, x9, x10)

inst_10057:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:30108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30108*FLEN/8, x13, x9, x10)

inst_10058:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:30111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30111*FLEN/8, x13, x9, x10)

inst_10059:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:30114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30114*FLEN/8, x13, x9, x10)

inst_10060:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:30117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30117*FLEN/8, x13, x9, x10)

inst_10061:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30120*FLEN/8, x13, x9, x10)

inst_10062:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30123*FLEN/8, x13, x9, x10)

inst_10063:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30126*FLEN/8, x13, x9, x10)

inst_10064:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:30129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30129*FLEN/8, x13, x9, x10)

inst_10065:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:30132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30132*FLEN/8, x13, x9, x10)

inst_10066:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:30135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30135*FLEN/8, x13, x9, x10)

inst_10067:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:30138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30138*FLEN/8, x13, x9, x10)

inst_10068:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30141*FLEN/8, x13, x9, x10)

inst_10069:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30144*FLEN/8, x13, x9, x10)

inst_10070:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30147*FLEN/8, x13, x9, x10)

inst_10071:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:30150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30150*FLEN/8, x13, x9, x10)

inst_10072:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30153*FLEN/8, x13, x9, x10)

inst_10073:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30156*FLEN/8, x13, x9, x10)

inst_10074:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30159*FLEN/8, x13, x9, x10)

inst_10075:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30162*FLEN/8, x13, x9, x10)

inst_10076:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30165*FLEN/8, x13, x9, x10)

inst_10077:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30168*FLEN/8, x13, x9, x10)

inst_10078:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30171*FLEN/8, x13, x9, x10)

inst_10079:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30174*FLEN/8, x13, x9, x10)

inst_10080:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:30177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30177*FLEN/8, x13, x9, x10)

inst_10081:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:30180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30180*FLEN/8, x13, x9, x10)

inst_10082:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:30183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30183*FLEN/8, x13, x9, x10)

inst_10083:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:30186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30186*FLEN/8, x13, x9, x10)

inst_10084:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:30189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30189*FLEN/8, x13, x9, x10)

inst_10085:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30192*FLEN/8, x13, x9, x10)

inst_10086:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30195*FLEN/8, x13, x9, x10)

inst_10087:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30198*FLEN/8, x13, x9, x10)

inst_10088:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:30201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30201*FLEN/8, x13, x9, x10)

inst_10089:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:30204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30204*FLEN/8, x13, x9, x10)

inst_10090:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:30207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30207*FLEN/8, x13, x9, x10)

inst_10091:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:30210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30210*FLEN/8, x13, x9, x10)

inst_10092:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30213*FLEN/8, x13, x9, x10)

inst_10093:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30216*FLEN/8, x13, x9, x10)

inst_10094:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30219*FLEN/8, x13, x9, x10)

inst_10095:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:30222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30222*FLEN/8, x13, x9, x10)

inst_10096:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30225*FLEN/8, x13, x9, x10)

inst_10097:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30228*FLEN/8, x13, x9, x10)

inst_10098:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30231*FLEN/8, x13, x9, x10)

inst_10099:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30234*FLEN/8, x13, x9, x10)

inst_10100:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30237*FLEN/8, x13, x9, x10)

inst_10101:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30240*FLEN/8, x13, x9, x10)

inst_10102:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30243*FLEN/8, x13, x9, x10)

inst_10103:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30246*FLEN/8, x13, x9, x10)

inst_10104:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:30249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30249*FLEN/8, x13, x9, x10)

inst_10105:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:30252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30252*FLEN/8, x13, x9, x10)

inst_10106:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:30255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30255*FLEN/8, x13, x9, x10)

inst_10107:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:30258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30258*FLEN/8, x13, x9, x10)

inst_10108:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:30261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30261*FLEN/8, x13, x9, x10)

inst_10109:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30264*FLEN/8, x13, x9, x10)

inst_10110:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30267*FLEN/8, x13, x9, x10)

inst_10111:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30270*FLEN/8, x13, x9, x10)

inst_10112:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:30273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30273*FLEN/8, x13, x9, x10)

inst_10113:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:30276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30276*FLEN/8, x13, x9, x10)

inst_10114:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:30279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30279*FLEN/8, x13, x9, x10)

inst_10115:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:30282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30282*FLEN/8, x13, x9, x10)

inst_10116:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30285*FLEN/8, x13, x9, x10)

inst_10117:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30288*FLEN/8, x13, x9, x10)

inst_10118:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30291*FLEN/8, x13, x9, x10)

inst_10119:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:30294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30294*FLEN/8, x13, x9, x10)

inst_10120:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30297*FLEN/8, x13, x9, x10)

inst_10121:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30300*FLEN/8, x13, x9, x10)

inst_10122:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30303*FLEN/8, x13, x9, x10)

inst_10123:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30306*FLEN/8, x13, x9, x10)

inst_10124:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30309*FLEN/8, x13, x9, x10)

inst_10125:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30312*FLEN/8, x13, x9, x10)

inst_10126:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30315*FLEN/8, x13, x9, x10)

inst_10127:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30318*FLEN/8, x13, x9, x10)

inst_10128:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:30321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30321*FLEN/8, x13, x9, x10)

inst_10129:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:30324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30324*FLEN/8, x13, x9, x10)

inst_10130:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:30327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30327*FLEN/8, x13, x9, x10)

inst_10131:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:30330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30330*FLEN/8, x13, x9, x10)

inst_10132:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:30333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30333*FLEN/8, x13, x9, x10)

inst_10133:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30336*FLEN/8, x13, x9, x10)

inst_10134:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30339*FLEN/8, x13, x9, x10)

inst_10135:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30342*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_79)

inst_10136:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:30345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30345*FLEN/8, x13, x9, x10)

inst_10137:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:30348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30348*FLEN/8, x13, x9, x10)

inst_10138:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:30351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30351*FLEN/8, x13, x9, x10)

inst_10139:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:30354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30354*FLEN/8, x13, x9, x10)

inst_10140:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30357*FLEN/8, x13, x9, x10)

inst_10141:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30360*FLEN/8, x13, x9, x10)

inst_10142:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30363*FLEN/8, x13, x9, x10)

inst_10143:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:30366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30366*FLEN/8, x13, x9, x10)

inst_10144:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30369*FLEN/8, x13, x9, x10)

inst_10145:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30372*FLEN/8, x13, x9, x10)

inst_10146:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30375*FLEN/8, x13, x9, x10)

inst_10147:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30378*FLEN/8, x13, x9, x10)

inst_10148:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30381*FLEN/8, x13, x9, x10)

inst_10149:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30384*FLEN/8, x13, x9, x10)

inst_10150:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30387*FLEN/8, x13, x9, x10)

inst_10151:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30390*FLEN/8, x13, x9, x10)

inst_10152:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:30393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30393*FLEN/8, x13, x9, x10)

inst_10153:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:30396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30396*FLEN/8, x13, x9, x10)

inst_10154:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:30399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30399*FLEN/8, x13, x9, x10)

inst_10155:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:30402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30402*FLEN/8, x13, x9, x10)

inst_10156:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:30405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30405*FLEN/8, x13, x9, x10)

inst_10157:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30408*FLEN/8, x13, x9, x10)

inst_10158:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30411*FLEN/8, x13, x9, x10)

inst_10159:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30414*FLEN/8, x13, x9, x10)

inst_10160:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:30417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30417*FLEN/8, x13, x9, x10)

inst_10161:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:30420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30420*FLEN/8, x13, x9, x10)

inst_10162:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:30423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30423*FLEN/8, x13, x9, x10)

inst_10163:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:30426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30426*FLEN/8, x13, x9, x10)

inst_10164:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30429*FLEN/8, x13, x9, x10)

inst_10165:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30432*FLEN/8, x13, x9, x10)

inst_10166:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30435*FLEN/8, x13, x9, x10)

inst_10167:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:30438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30438*FLEN/8, x13, x9, x10)

inst_10168:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30441*FLEN/8, x13, x9, x10)

inst_10169:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30444*FLEN/8, x13, x9, x10)

inst_10170:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30447*FLEN/8, x13, x9, x10)

inst_10171:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30450*FLEN/8, x13, x9, x10)

inst_10172:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30453*FLEN/8, x13, x9, x10)

inst_10173:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30456*FLEN/8, x13, x9, x10)

inst_10174:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30459*FLEN/8, x13, x9, x10)

inst_10175:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30462*FLEN/8, x13, x9, x10)

inst_10176:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:30465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30465*FLEN/8, x13, x9, x10)

inst_10177:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:30468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30468*FLEN/8, x13, x9, x10)

inst_10178:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:30471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30471*FLEN/8, x13, x9, x10)

inst_10179:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:30474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30474*FLEN/8, x13, x9, x10)

inst_10180:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:30477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30477*FLEN/8, x13, x9, x10)

inst_10181:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30480*FLEN/8, x13, x9, x10)

inst_10182:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30483*FLEN/8, x13, x9, x10)

inst_10183:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30486*FLEN/8, x13, x9, x10)

inst_10184:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:30489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30489*FLEN/8, x13, x9, x10)

inst_10185:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:30492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30492*FLEN/8, x13, x9, x10)

inst_10186:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:30495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30495*FLEN/8, x13, x9, x10)

inst_10187:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:30498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30498*FLEN/8, x13, x9, x10)

inst_10188:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30501*FLEN/8, x13, x9, x10)

inst_10189:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30504*FLEN/8, x13, x9, x10)

inst_10190:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30507*FLEN/8, x13, x9, x10)

inst_10191:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:30510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30510*FLEN/8, x13, x9, x10)

inst_10192:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30513*FLEN/8, x13, x9, x10)

inst_10193:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30516*FLEN/8, x13, x9, x10)

inst_10194:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30519*FLEN/8, x13, x9, x10)

inst_10195:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30522*FLEN/8, x13, x9, x10)

inst_10196:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30525*FLEN/8, x13, x9, x10)

inst_10197:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30528*FLEN/8, x13, x9, x10)

inst_10198:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30531*FLEN/8, x13, x9, x10)

inst_10199:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30534*FLEN/8, x13, x9, x10)

inst_10200:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:30537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30537*FLEN/8, x13, x9, x10)

inst_10201:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:30540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30540*FLEN/8, x13, x9, x10)

inst_10202:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:30543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30543*FLEN/8, x13, x9, x10)

inst_10203:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:30546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30546*FLEN/8, x13, x9, x10)

inst_10204:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:30549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30549*FLEN/8, x13, x9, x10)

inst_10205:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30552*FLEN/8, x13, x9, x10)

inst_10206:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30555*FLEN/8, x13, x9, x10)

inst_10207:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30558*FLEN/8, x13, x9, x10)

inst_10208:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:30561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30561*FLEN/8, x13, x9, x10)

inst_10209:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:30564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30564*FLEN/8, x13, x9, x10)

inst_10210:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:30567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30567*FLEN/8, x13, x9, x10)

inst_10211:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:30570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30570*FLEN/8, x13, x9, x10)

inst_10212:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30573*FLEN/8, x13, x9, x10)

inst_10213:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30576*FLEN/8, x13, x9, x10)

inst_10214:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30579*FLEN/8, x13, x9, x10)

inst_10215:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:30582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30582*FLEN/8, x13, x9, x10)

inst_10216:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30585*FLEN/8, x13, x9, x10)

inst_10217:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30588*FLEN/8, x13, x9, x10)

inst_10218:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30591*FLEN/8, x13, x9, x10)

inst_10219:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30594*FLEN/8, x13, x9, x10)

inst_10220:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30597*FLEN/8, x13, x9, x10)

inst_10221:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30600*FLEN/8, x13, x9, x10)

inst_10222:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30603*FLEN/8, x13, x9, x10)

inst_10223:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30606*FLEN/8, x13, x9, x10)

inst_10224:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:30609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30609*FLEN/8, x13, x9, x10)

inst_10225:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:30612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30612*FLEN/8, x13, x9, x10)

inst_10226:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:30615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30615*FLEN/8, x13, x9, x10)

inst_10227:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:30618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30618*FLEN/8, x13, x9, x10)

inst_10228:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:30621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30621*FLEN/8, x13, x9, x10)

inst_10229:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30624*FLEN/8, x13, x9, x10)

inst_10230:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30627*FLEN/8, x13, x9, x10)

inst_10231:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30630*FLEN/8, x13, x9, x10)

inst_10232:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:30633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30633*FLEN/8, x13, x9, x10)

inst_10233:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:30636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30636*FLEN/8, x13, x9, x10)

inst_10234:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:30639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30639*FLEN/8, x13, x9, x10)

inst_10235:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:30642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30642*FLEN/8, x13, x9, x10)

inst_10236:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30645*FLEN/8, x13, x9, x10)

inst_10237:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30648*FLEN/8, x13, x9, x10)

inst_10238:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30651*FLEN/8, x13, x9, x10)

inst_10239:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:30654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30654*FLEN/8, x13, x9, x10)

inst_10240:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30657*FLEN/8, x13, x9, x10)

inst_10241:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30660*FLEN/8, x13, x9, x10)

inst_10242:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30663*FLEN/8, x13, x9, x10)

inst_10243:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30666*FLEN/8, x13, x9, x10)

inst_10244:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30669*FLEN/8, x13, x9, x10)

inst_10245:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30672*FLEN/8, x13, x9, x10)

inst_10246:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30675*FLEN/8, x13, x9, x10)

inst_10247:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30678*FLEN/8, x13, x9, x10)

inst_10248:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:30681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30681*FLEN/8, x13, x9, x10)

inst_10249:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:30684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30684*FLEN/8, x13, x9, x10)

inst_10250:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:30687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30687*FLEN/8, x13, x9, x10)

inst_10251:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:30690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30690*FLEN/8, x13, x9, x10)

inst_10252:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:30693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30693*FLEN/8, x13, x9, x10)

inst_10253:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30696*FLEN/8, x13, x9, x10)

inst_10254:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30699*FLEN/8, x13, x9, x10)

inst_10255:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30702*FLEN/8, x13, x9, x10)

inst_10256:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:30705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30705*FLEN/8, x13, x9, x10)

inst_10257:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:30708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30708*FLEN/8, x13, x9, x10)

inst_10258:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:30711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30711*FLEN/8, x13, x9, x10)

inst_10259:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:30714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30714*FLEN/8, x13, x9, x10)

inst_10260:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30717*FLEN/8, x13, x9, x10)

inst_10261:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30720*FLEN/8, x13, x9, x10)

inst_10262:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30723*FLEN/8, x13, x9, x10)

inst_10263:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:30726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30726*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_80)

inst_10264:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30729*FLEN/8, x13, x9, x10)

inst_10265:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30732*FLEN/8, x13, x9, x10)

inst_10266:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30735*FLEN/8, x13, x9, x10)

inst_10267:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30738*FLEN/8, x13, x9, x10)

inst_10268:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30741*FLEN/8, x13, x9, x10)

inst_10269:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30744*FLEN/8, x13, x9, x10)

inst_10270:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30747*FLEN/8, x13, x9, x10)

inst_10271:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30750*FLEN/8, x13, x9, x10)

inst_10272:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:30753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30753*FLEN/8, x13, x9, x10)

inst_10273:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:30756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30756*FLEN/8, x13, x9, x10)

inst_10274:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:30759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30759*FLEN/8, x13, x9, x10)

inst_10275:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:30762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30762*FLEN/8, x13, x9, x10)

inst_10276:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:30765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30765*FLEN/8, x13, x9, x10)

inst_10277:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30768*FLEN/8, x13, x9, x10)

inst_10278:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30771*FLEN/8, x13, x9, x10)

inst_10279:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30774*FLEN/8, x13, x9, x10)

inst_10280:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:30777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30777*FLEN/8, x13, x9, x10)

inst_10281:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:30780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30780*FLEN/8, x13, x9, x10)

inst_10282:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:30783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30783*FLEN/8, x13, x9, x10)

inst_10283:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:30786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30786*FLEN/8, x13, x9, x10)

inst_10284:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30789*FLEN/8, x13, x9, x10)

inst_10285:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30792*FLEN/8, x13, x9, x10)

inst_10286:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30795*FLEN/8, x13, x9, x10)

inst_10287:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:30798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30798*FLEN/8, x13, x9, x10)

inst_10288:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30801*FLEN/8, x13, x9, x10)

inst_10289:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30804*FLEN/8, x13, x9, x10)

inst_10290:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30807*FLEN/8, x13, x9, x10)

inst_10291:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30810*FLEN/8, x13, x9, x10)

inst_10292:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30813*FLEN/8, x13, x9, x10)

inst_10293:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30816*FLEN/8, x13, x9, x10)

inst_10294:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30819*FLEN/8, x13, x9, x10)

inst_10295:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30822*FLEN/8, x13, x9, x10)

inst_10296:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:30825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30825*FLEN/8, x13, x9, x10)

inst_10297:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:30828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30828*FLEN/8, x13, x9, x10)

inst_10298:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:30831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30831*FLEN/8, x13, x9, x10)

inst_10299:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:30834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30834*FLEN/8, x13, x9, x10)

inst_10300:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:30837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30837*FLEN/8, x13, x9, x10)

inst_10301:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30840*FLEN/8, x13, x9, x10)

inst_10302:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30843*FLEN/8, x13, x9, x10)

inst_10303:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30846*FLEN/8, x13, x9, x10)

inst_10304:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:30849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30849*FLEN/8, x13, x9, x10)

inst_10305:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:30852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30852*FLEN/8, x13, x9, x10)

inst_10306:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:30855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30855*FLEN/8, x13, x9, x10)

inst_10307:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:30858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30858*FLEN/8, x13, x9, x10)

inst_10308:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30861*FLEN/8, x13, x9, x10)

inst_10309:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30864*FLEN/8, x13, x9, x10)

inst_10310:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30867*FLEN/8, x13, x9, x10)

inst_10311:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:30870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30870*FLEN/8, x13, x9, x10)

inst_10312:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30873*FLEN/8, x13, x9, x10)

inst_10313:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30876*FLEN/8, x13, x9, x10)

inst_10314:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30879*FLEN/8, x13, x9, x10)

inst_10315:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30882*FLEN/8, x13, x9, x10)

inst_10316:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30885*FLEN/8, x13, x9, x10)

inst_10317:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30888*FLEN/8, x13, x9, x10)

inst_10318:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30891*FLEN/8, x13, x9, x10)

inst_10319:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30894*FLEN/8, x13, x9, x10)

inst_10320:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:30897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30897*FLEN/8, x13, x9, x10)

inst_10321:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:30900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30900*FLEN/8, x13, x9, x10)

inst_10322:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:30903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30903*FLEN/8, x13, x9, x10)

inst_10323:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:30906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30906*FLEN/8, x13, x9, x10)

inst_10324:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:30909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30909*FLEN/8, x13, x9, x10)

inst_10325:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30912*FLEN/8, x13, x9, x10)

inst_10326:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30915*FLEN/8, x13, x9, x10)

inst_10327:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30918*FLEN/8, x13, x9, x10)

inst_10328:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:30921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30921*FLEN/8, x13, x9, x10)

inst_10329:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:30924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30924*FLEN/8, x13, x9, x10)

inst_10330:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:30927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30927*FLEN/8, x13, x9, x10)

inst_10331:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:30930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30930*FLEN/8, x13, x9, x10)

inst_10332:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:30933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30933*FLEN/8, x13, x9, x10)

inst_10333:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:30936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30936*FLEN/8, x13, x9, x10)

inst_10334:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:30939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30939*FLEN/8, x13, x9, x10)

inst_10335:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:30942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30942*FLEN/8, x13, x9, x10)

inst_10336:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:30945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30945*FLEN/8, x13, x9, x10)

inst_10337:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:30948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30948*FLEN/8, x13, x9, x10)

inst_10338:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:30951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30951*FLEN/8, x13, x9, x10)

inst_10339:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:30954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30954*FLEN/8, x13, x9, x10)

inst_10340:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:30957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30957*FLEN/8, x13, x9, x10)

inst_10341:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:30960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30960*FLEN/8, x13, x9, x10)

inst_10342:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:30963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30963*FLEN/8, x13, x9, x10)

inst_10343:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:30966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30966*FLEN/8, x13, x9, x10)

inst_10344:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:30969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30969*FLEN/8, x13, x9, x10)

inst_10345:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:30972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30972*FLEN/8, x13, x9, x10)

inst_10346:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:30975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30975*FLEN/8, x13, x9, x10)

inst_10347:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:30978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30978*FLEN/8, x13, x9, x10)

inst_10348:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:30981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30981*FLEN/8, x13, x9, x10)

inst_10349:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:30984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30984*FLEN/8, x13, x9, x10)

inst_10350:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:30987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30987*FLEN/8, x13, x9, x10)

inst_10351:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:30990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30990*FLEN/8, x13, x9, x10)

inst_10352:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:30993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30993*FLEN/8, x13, x9, x10)

inst_10353:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:30996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30996*FLEN/8, x13, x9, x10)

inst_10354:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:30999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 30999*FLEN/8, x13, x9, x10)

inst_10355:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:31002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31002*FLEN/8, x13, x9, x10)

inst_10356:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31005*FLEN/8, x13, x9, x10)

inst_10357:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31008*FLEN/8, x13, x9, x10)

inst_10358:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31011*FLEN/8, x13, x9, x10)

inst_10359:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:31014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31014*FLEN/8, x13, x9, x10)

inst_10360:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31017*FLEN/8, x13, x9, x10)

inst_10361:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31020*FLEN/8, x13, x9, x10)

inst_10362:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31023*FLEN/8, x13, x9, x10)

inst_10363:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31026*FLEN/8, x13, x9, x10)

inst_10364:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31029*FLEN/8, x13, x9, x10)

inst_10365:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31032*FLEN/8, x13, x9, x10)

inst_10366:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31035*FLEN/8, x13, x9, x10)

inst_10367:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31038*FLEN/8, x13, x9, x10)

inst_10368:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:31041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31041*FLEN/8, x13, x9, x10)

inst_10369:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:31044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31044*FLEN/8, x13, x9, x10)

inst_10370:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:31047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31047*FLEN/8, x13, x9, x10)

inst_10371:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:31050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31050*FLEN/8, x13, x9, x10)

inst_10372:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:31053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31053*FLEN/8, x13, x9, x10)

inst_10373:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31056*FLEN/8, x13, x9, x10)

inst_10374:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31059*FLEN/8, x13, x9, x10)

inst_10375:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31062*FLEN/8, x13, x9, x10)

inst_10376:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:31065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31065*FLEN/8, x13, x9, x10)

inst_10377:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:31068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31068*FLEN/8, x13, x9, x10)

inst_10378:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:31071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31071*FLEN/8, x13, x9, x10)

inst_10379:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:31074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31074*FLEN/8, x13, x9, x10)

inst_10380:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31077*FLEN/8, x13, x9, x10)

inst_10381:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31080*FLEN/8, x13, x9, x10)

inst_10382:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31083*FLEN/8, x13, x9, x10)

inst_10383:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:31086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31086*FLEN/8, x13, x9, x10)

inst_10384:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31089*FLEN/8, x13, x9, x10)

inst_10385:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31092*FLEN/8, x13, x9, x10)

inst_10386:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31095*FLEN/8, x13, x9, x10)

inst_10387:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31098*FLEN/8, x13, x9, x10)

inst_10388:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31101*FLEN/8, x13, x9, x10)

inst_10389:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31104*FLEN/8, x13, x9, x10)

inst_10390:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31107*FLEN/8, x13, x9, x10)

inst_10391:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31110*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_81)

inst_10392:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:31113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31113*FLEN/8, x13, x9, x10)

inst_10393:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:31116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31116*FLEN/8, x13, x9, x10)

inst_10394:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:31119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31119*FLEN/8, x13, x9, x10)

inst_10395:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:31122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31122*FLEN/8, x13, x9, x10)

inst_10396:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:31125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31125*FLEN/8, x13, x9, x10)

inst_10397:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31128*FLEN/8, x13, x9, x10)

inst_10398:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31131*FLEN/8, x13, x9, x10)

inst_10399:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31134*FLEN/8, x13, x9, x10)

inst_10400:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:31137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31137*FLEN/8, x13, x9, x10)

inst_10401:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:31140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31140*FLEN/8, x13, x9, x10)

inst_10402:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:31143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31143*FLEN/8, x13, x9, x10)

inst_10403:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:31146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31146*FLEN/8, x13, x9, x10)

inst_10404:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31149*FLEN/8, x13, x9, x10)

inst_10405:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31152*FLEN/8, x13, x9, x10)

inst_10406:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31155*FLEN/8, x13, x9, x10)

inst_10407:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:31158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31158*FLEN/8, x13, x9, x10)

inst_10408:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31161*FLEN/8, x13, x9, x10)

inst_10409:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31164*FLEN/8, x13, x9, x10)

inst_10410:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31167*FLEN/8, x13, x9, x10)

inst_10411:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31170*FLEN/8, x13, x9, x10)

inst_10412:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31173*FLEN/8, x13, x9, x10)

inst_10413:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31176*FLEN/8, x13, x9, x10)

inst_10414:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31179*FLEN/8, x13, x9, x10)

inst_10415:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31182*FLEN/8, x13, x9, x10)

inst_10416:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:31185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31185*FLEN/8, x13, x9, x10)

inst_10417:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:31188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31188*FLEN/8, x13, x9, x10)

inst_10418:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:31191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31191*FLEN/8, x13, x9, x10)

inst_10419:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:31194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31194*FLEN/8, x13, x9, x10)

inst_10420:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:31197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31197*FLEN/8, x13, x9, x10)

inst_10421:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31200*FLEN/8, x13, x9, x10)

inst_10422:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31203*FLEN/8, x13, x9, x10)

inst_10423:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31206*FLEN/8, x13, x9, x10)

inst_10424:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:31209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31209*FLEN/8, x13, x9, x10)

inst_10425:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:31212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31212*FLEN/8, x13, x9, x10)

inst_10426:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:31215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31215*FLEN/8, x13, x9, x10)

inst_10427:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:31218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31218*FLEN/8, x13, x9, x10)

inst_10428:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31221*FLEN/8, x13, x9, x10)

inst_10429:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31224*FLEN/8, x13, x9, x10)

inst_10430:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31227*FLEN/8, x13, x9, x10)

inst_10431:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:31230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31230*FLEN/8, x13, x9, x10)

inst_10432:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31233*FLEN/8, x13, x9, x10)

inst_10433:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31236*FLEN/8, x13, x9, x10)

inst_10434:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31239*FLEN/8, x13, x9, x10)

inst_10435:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31242*FLEN/8, x13, x9, x10)

inst_10436:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31245*FLEN/8, x13, x9, x10)

inst_10437:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31248*FLEN/8, x13, x9, x10)

inst_10438:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31251*FLEN/8, x13, x9, x10)

inst_10439:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31254*FLEN/8, x13, x9, x10)

inst_10440:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:31257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31257*FLEN/8, x13, x9, x10)

inst_10441:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:31260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31260*FLEN/8, x13, x9, x10)

inst_10442:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:31263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31263*FLEN/8, x13, x9, x10)

inst_10443:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:31266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31266*FLEN/8, x13, x9, x10)

inst_10444:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:31269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31269*FLEN/8, x13, x9, x10)

inst_10445:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31272*FLEN/8, x13, x9, x10)

inst_10446:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31275*FLEN/8, x13, x9, x10)

inst_10447:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31278*FLEN/8, x13, x9, x10)

inst_10448:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:31281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31281*FLEN/8, x13, x9, x10)

inst_10449:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:31284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31284*FLEN/8, x13, x9, x10)

inst_10450:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:31287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31287*FLEN/8, x13, x9, x10)

inst_10451:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:31290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31290*FLEN/8, x13, x9, x10)

inst_10452:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31293*FLEN/8, x13, x9, x10)

inst_10453:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31296*FLEN/8, x13, x9, x10)

inst_10454:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31299*FLEN/8, x13, x9, x10)

inst_10455:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:31302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31302*FLEN/8, x13, x9, x10)

inst_10456:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31305*FLEN/8, x13, x9, x10)

inst_10457:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31308*FLEN/8, x13, x9, x10)

inst_10458:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31311*FLEN/8, x13, x9, x10)

inst_10459:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31314*FLEN/8, x13, x9, x10)

inst_10460:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31317*FLEN/8, x13, x9, x10)

inst_10461:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31320*FLEN/8, x13, x9, x10)

inst_10462:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31323*FLEN/8, x13, x9, x10)

inst_10463:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31326*FLEN/8, x13, x9, x10)

inst_10464:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:31329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31329*FLEN/8, x13, x9, x10)

inst_10465:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:31332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31332*FLEN/8, x13, x9, x10)

inst_10466:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:31335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31335*FLEN/8, x13, x9, x10)

inst_10467:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:31338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31338*FLEN/8, x13, x9, x10)

inst_10468:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:31341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31341*FLEN/8, x13, x9, x10)

inst_10469:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31344*FLEN/8, x13, x9, x10)

inst_10470:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31347*FLEN/8, x13, x9, x10)

inst_10471:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31350*FLEN/8, x13, x9, x10)

inst_10472:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:31353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31353*FLEN/8, x13, x9, x10)

inst_10473:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:31356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31356*FLEN/8, x13, x9, x10)

inst_10474:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:31359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31359*FLEN/8, x13, x9, x10)

inst_10475:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:31362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31362*FLEN/8, x13, x9, x10)

inst_10476:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31365*FLEN/8, x13, x9, x10)

inst_10477:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31368*FLEN/8, x13, x9, x10)

inst_10478:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31371*FLEN/8, x13, x9, x10)

inst_10479:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:31374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31374*FLEN/8, x13, x9, x10)

inst_10480:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31377*FLEN/8, x13, x9, x10)

inst_10481:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31380*FLEN/8, x13, x9, x10)

inst_10482:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31383*FLEN/8, x13, x9, x10)

inst_10483:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31386*FLEN/8, x13, x9, x10)

inst_10484:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31389*FLEN/8, x13, x9, x10)

inst_10485:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31392*FLEN/8, x13, x9, x10)

inst_10486:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31395*FLEN/8, x13, x9, x10)

inst_10487:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31398*FLEN/8, x13, x9, x10)

inst_10488:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:31401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31401*FLEN/8, x13, x9, x10)

inst_10489:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:31404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31404*FLEN/8, x13, x9, x10)

inst_10490:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:31407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31407*FLEN/8, x13, x9, x10)

inst_10491:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:31410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31410*FLEN/8, x13, x9, x10)

inst_10492:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:31413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31413*FLEN/8, x13, x9, x10)

inst_10493:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31416*FLEN/8, x13, x9, x10)

inst_10494:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31419*FLEN/8, x13, x9, x10)

inst_10495:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31422*FLEN/8, x13, x9, x10)

inst_10496:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:31425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31425*FLEN/8, x13, x9, x10)

inst_10497:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:31428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31428*FLEN/8, x13, x9, x10)

inst_10498:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:31431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31431*FLEN/8, x13, x9, x10)

inst_10499:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:31434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31434*FLEN/8, x13, x9, x10)

inst_10500:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31437*FLEN/8, x13, x9, x10)

inst_10501:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31440*FLEN/8, x13, x9, x10)

inst_10502:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31443*FLEN/8, x13, x9, x10)

inst_10503:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:31446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31446*FLEN/8, x13, x9, x10)

inst_10504:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31449*FLEN/8, x13, x9, x10)

inst_10505:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31452*FLEN/8, x13, x9, x10)

inst_10506:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31455*FLEN/8, x13, x9, x10)

inst_10507:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31458*FLEN/8, x13, x9, x10)

inst_10508:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31461*FLEN/8, x13, x9, x10)

inst_10509:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31464*FLEN/8, x13, x9, x10)

inst_10510:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31467*FLEN/8, x13, x9, x10)

inst_10511:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31470*FLEN/8, x13, x9, x10)

inst_10512:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:31473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31473*FLEN/8, x13, x9, x10)

inst_10513:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:31476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31476*FLEN/8, x13, x9, x10)

inst_10514:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:31479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31479*FLEN/8, x13, x9, x10)

inst_10515:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:31482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31482*FLEN/8, x13, x9, x10)

inst_10516:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:31485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31485*FLEN/8, x13, x9, x10)

inst_10517:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31488*FLEN/8, x13, x9, x10)

inst_10518:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31491*FLEN/8, x13, x9, x10)

inst_10519:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31494*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_82)

inst_10520:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:31497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31497*FLEN/8, x13, x9, x10)

inst_10521:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:31500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31500*FLEN/8, x13, x9, x10)

inst_10522:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:31503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31503*FLEN/8, x13, x9, x10)

inst_10523:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:31506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31506*FLEN/8, x13, x9, x10)

inst_10524:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31509*FLEN/8, x13, x9, x10)

inst_10525:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31512*FLEN/8, x13, x9, x10)

inst_10526:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31515*FLEN/8, x13, x9, x10)

inst_10527:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:31518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31518*FLEN/8, x13, x9, x10)

inst_10528:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31521*FLEN/8, x13, x9, x10)

inst_10529:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31524*FLEN/8, x13, x9, x10)

inst_10530:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31527*FLEN/8, x13, x9, x10)

inst_10531:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31530*FLEN/8, x13, x9, x10)

inst_10532:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31533*FLEN/8, x13, x9, x10)

inst_10533:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31536*FLEN/8, x13, x9, x10)

inst_10534:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31539*FLEN/8, x13, x9, x10)

inst_10535:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31542*FLEN/8, x13, x9, x10)

inst_10536:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:31545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31545*FLEN/8, x13, x9, x10)

inst_10537:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:31548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31548*FLEN/8, x13, x9, x10)

inst_10538:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:31551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31551*FLEN/8, x13, x9, x10)

inst_10539:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:31554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31554*FLEN/8, x13, x9, x10)

inst_10540:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:31557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31557*FLEN/8, x13, x9, x10)

inst_10541:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31560*FLEN/8, x13, x9, x10)

inst_10542:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31563*FLEN/8, x13, x9, x10)

inst_10543:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31566*FLEN/8, x13, x9, x10)

inst_10544:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:31569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31569*FLEN/8, x13, x9, x10)

inst_10545:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:31572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31572*FLEN/8, x13, x9, x10)

inst_10546:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:31575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31575*FLEN/8, x13, x9, x10)

inst_10547:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:31578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31578*FLEN/8, x13, x9, x10)

inst_10548:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31581*FLEN/8, x13, x9, x10)

inst_10549:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31584*FLEN/8, x13, x9, x10)

inst_10550:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31587*FLEN/8, x13, x9, x10)

inst_10551:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:31590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31590*FLEN/8, x13, x9, x10)

inst_10552:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31593*FLEN/8, x13, x9, x10)

inst_10553:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31596*FLEN/8, x13, x9, x10)

inst_10554:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31599*FLEN/8, x13, x9, x10)

inst_10555:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31602*FLEN/8, x13, x9, x10)

inst_10556:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31605*FLEN/8, x13, x9, x10)

inst_10557:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31608*FLEN/8, x13, x9, x10)

inst_10558:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31611*FLEN/8, x13, x9, x10)

inst_10559:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31614*FLEN/8, x13, x9, x10)

inst_10560:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:31617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31617*FLEN/8, x13, x9, x10)

inst_10561:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:31620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31620*FLEN/8, x13, x9, x10)

inst_10562:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:31623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31623*FLEN/8, x13, x9, x10)

inst_10563:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:31626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31626*FLEN/8, x13, x9, x10)

inst_10564:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:31629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31629*FLEN/8, x13, x9, x10)

inst_10565:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31632*FLEN/8, x13, x9, x10)

inst_10566:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31635*FLEN/8, x13, x9, x10)

inst_10567:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31638*FLEN/8, x13, x9, x10)

inst_10568:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:31641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31641*FLEN/8, x13, x9, x10)

inst_10569:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:31644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31644*FLEN/8, x13, x9, x10)

inst_10570:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:31647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31647*FLEN/8, x13, x9, x10)

inst_10571:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:31650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31650*FLEN/8, x13, x9, x10)

inst_10572:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31653*FLEN/8, x13, x9, x10)

inst_10573:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31656*FLEN/8, x13, x9, x10)

inst_10574:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31659*FLEN/8, x13, x9, x10)

inst_10575:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:31662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31662*FLEN/8, x13, x9, x10)

inst_10576:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31665*FLEN/8, x13, x9, x10)

inst_10577:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31668*FLEN/8, x13, x9, x10)

inst_10578:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31671*FLEN/8, x13, x9, x10)

inst_10579:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31674*FLEN/8, x13, x9, x10)

inst_10580:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31677*FLEN/8, x13, x9, x10)

inst_10581:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31680*FLEN/8, x13, x9, x10)

inst_10582:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31683*FLEN/8, x13, x9, x10)

inst_10583:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31686*FLEN/8, x13, x9, x10)

inst_10584:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:31689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31689*FLEN/8, x13, x9, x10)

inst_10585:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:31692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31692*FLEN/8, x13, x9, x10)

inst_10586:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:31695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31695*FLEN/8, x13, x9, x10)

inst_10587:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:31698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31698*FLEN/8, x13, x9, x10)

inst_10588:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:31701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31701*FLEN/8, x13, x9, x10)

inst_10589:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31704*FLEN/8, x13, x9, x10)

inst_10590:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31707*FLEN/8, x13, x9, x10)

inst_10591:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31710*FLEN/8, x13, x9, x10)

inst_10592:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:31713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31713*FLEN/8, x13, x9, x10)

inst_10593:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:31716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31716*FLEN/8, x13, x9, x10)

inst_10594:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:31719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31719*FLEN/8, x13, x9, x10)

inst_10595:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:31722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31722*FLEN/8, x13, x9, x10)

inst_10596:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31725*FLEN/8, x13, x9, x10)

inst_10597:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31728*FLEN/8, x13, x9, x10)

inst_10598:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31731*FLEN/8, x13, x9, x10)

inst_10599:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:31734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31734*FLEN/8, x13, x9, x10)

inst_10600:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31737*FLEN/8, x13, x9, x10)

inst_10601:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31740*FLEN/8, x13, x9, x10)

inst_10602:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31743*FLEN/8, x13, x9, x10)

inst_10603:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31746*FLEN/8, x13, x9, x10)

inst_10604:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31749*FLEN/8, x13, x9, x10)

inst_10605:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31752*FLEN/8, x13, x9, x10)

inst_10606:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31755*FLEN/8, x13, x9, x10)

inst_10607:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31758*FLEN/8, x13, x9, x10)

inst_10608:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:31761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31761*FLEN/8, x13, x9, x10)

inst_10609:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:31764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31764*FLEN/8, x13, x9, x10)

inst_10610:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:31767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31767*FLEN/8, x13, x9, x10)

inst_10611:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:31770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31770*FLEN/8, x13, x9, x10)

inst_10612:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:31773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31773*FLEN/8, x13, x9, x10)

inst_10613:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31776*FLEN/8, x13, x9, x10)

inst_10614:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31779*FLEN/8, x13, x9, x10)

inst_10615:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31782*FLEN/8, x13, x9, x10)

inst_10616:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:31785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31785*FLEN/8, x13, x9, x10)

inst_10617:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:31788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31788*FLEN/8, x13, x9, x10)

inst_10618:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:31791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31791*FLEN/8, x13, x9, x10)

inst_10619:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:31794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31794*FLEN/8, x13, x9, x10)

inst_10620:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31797*FLEN/8, x13, x9, x10)

inst_10621:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31800*FLEN/8, x13, x9, x10)

inst_10622:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31803*FLEN/8, x13, x9, x10)

inst_10623:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:31806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31806*FLEN/8, x13, x9, x10)

inst_10624:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31809*FLEN/8, x13, x9, x10)

inst_10625:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31812*FLEN/8, x13, x9, x10)

inst_10626:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31815*FLEN/8, x13, x9, x10)

inst_10627:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31818*FLEN/8, x13, x9, x10)

inst_10628:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31821*FLEN/8, x13, x9, x10)

inst_10629:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31824*FLEN/8, x13, x9, x10)

inst_10630:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31827*FLEN/8, x13, x9, x10)

inst_10631:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31830*FLEN/8, x13, x9, x10)

inst_10632:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:31833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31833*FLEN/8, x13, x9, x10)

inst_10633:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:31836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31836*FLEN/8, x13, x9, x10)

inst_10634:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:31839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31839*FLEN/8, x13, x9, x10)

inst_10635:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:31842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31842*FLEN/8, x13, x9, x10)

inst_10636:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:31845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31845*FLEN/8, x13, x9, x10)

inst_10637:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31848*FLEN/8, x13, x9, x10)

inst_10638:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31851*FLEN/8, x13, x9, x10)

inst_10639:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31854*FLEN/8, x13, x9, x10)

inst_10640:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:31857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31857*FLEN/8, x13, x9, x10)

inst_10641:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:31860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31860*FLEN/8, x13, x9, x10)

inst_10642:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:31863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31863*FLEN/8, x13, x9, x10)

inst_10643:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:31866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31866*FLEN/8, x13, x9, x10)

inst_10644:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31869*FLEN/8, x13, x9, x10)

inst_10645:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31872*FLEN/8, x13, x9, x10)

inst_10646:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31875*FLEN/8, x13, x9, x10)

inst_10647:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:31878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31878*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_83)

inst_10648:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31881*FLEN/8, x13, x9, x10)

inst_10649:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31884*FLEN/8, x13, x9, x10)

inst_10650:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31887*FLEN/8, x13, x9, x10)

inst_10651:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31890*FLEN/8, x13, x9, x10)

inst_10652:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31893*FLEN/8, x13, x9, x10)

inst_10653:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31896*FLEN/8, x13, x9, x10)

inst_10654:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31899*FLEN/8, x13, x9, x10)

inst_10655:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31902*FLEN/8, x13, x9, x10)

inst_10656:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:31905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31905*FLEN/8, x13, x9, x10)

inst_10657:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:31908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31908*FLEN/8, x13, x9, x10)

inst_10658:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:31911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31911*FLEN/8, x13, x9, x10)

inst_10659:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:31914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31914*FLEN/8, x13, x9, x10)

inst_10660:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:31917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31917*FLEN/8, x13, x9, x10)

inst_10661:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31920*FLEN/8, x13, x9, x10)

inst_10662:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31923*FLEN/8, x13, x9, x10)

inst_10663:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31926*FLEN/8, x13, x9, x10)

inst_10664:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:31929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31929*FLEN/8, x13, x9, x10)

inst_10665:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:31932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31932*FLEN/8, x13, x9, x10)

inst_10666:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:31935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31935*FLEN/8, x13, x9, x10)

inst_10667:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:31938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31938*FLEN/8, x13, x9, x10)

inst_10668:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:31941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31941*FLEN/8, x13, x9, x10)

inst_10669:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:31944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31944*FLEN/8, x13, x9, x10)

inst_10670:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:31947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31947*FLEN/8, x13, x9, x10)

inst_10671:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:31950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31950*FLEN/8, x13, x9, x10)

inst_10672:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:31953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31953*FLEN/8, x13, x9, x10)

inst_10673:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:31956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31956*FLEN/8, x13, x9, x10)

inst_10674:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:31959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31959*FLEN/8, x13, x9, x10)

inst_10675:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:31962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31962*FLEN/8, x13, x9, x10)

inst_10676:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:31965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31965*FLEN/8, x13, x9, x10)

inst_10677:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:31968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31968*FLEN/8, x13, x9, x10)

inst_10678:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:31971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31971*FLEN/8, x13, x9, x10)

inst_10679:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:31974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31974*FLEN/8, x13, x9, x10)

inst_10680:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:31977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31977*FLEN/8, x13, x9, x10)

inst_10681:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:31980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31980*FLEN/8, x13, x9, x10)

inst_10682:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:31983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31983*FLEN/8, x13, x9, x10)

inst_10683:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:31986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31986*FLEN/8, x13, x9, x10)

inst_10684:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:31989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31989*FLEN/8, x13, x9, x10)

inst_10685:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:31992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31992*FLEN/8, x13, x9, x10)

inst_10686:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:31995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31995*FLEN/8, x13, x9, x10)

inst_10687:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:31998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 31998*FLEN/8, x13, x9, x10)

inst_10688:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:32001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32001*FLEN/8, x13, x9, x10)

inst_10689:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:32004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32004*FLEN/8, x13, x9, x10)

inst_10690:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:32007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32007*FLEN/8, x13, x9, x10)

inst_10691:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:32010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32010*FLEN/8, x13, x9, x10)

inst_10692:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32013*FLEN/8, x13, x9, x10)

inst_10693:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32016*FLEN/8, x13, x9, x10)

inst_10694:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32019*FLEN/8, x13, x9, x10)

inst_10695:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:32022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32022*FLEN/8, x13, x9, x10)

inst_10696:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32025*FLEN/8, x13, x9, x10)

inst_10697:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32028*FLEN/8, x13, x9, x10)

inst_10698:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32031*FLEN/8, x13, x9, x10)

inst_10699:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32034*FLEN/8, x13, x9, x10)

inst_10700:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32037*FLEN/8, x13, x9, x10)

inst_10701:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32040*FLEN/8, x13, x9, x10)

inst_10702:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32043*FLEN/8, x13, x9, x10)

inst_10703:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32046*FLEN/8, x13, x9, x10)

inst_10704:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:32049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32049*FLEN/8, x13, x9, x10)

inst_10705:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32052*FLEN/8, x13, x9, x10)

inst_10706:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:32055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32055*FLEN/8, x13, x9, x10)

inst_10707:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32058*FLEN/8, x13, x9, x10)

inst_10708:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:32061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32061*FLEN/8, x13, x9, x10)

inst_10709:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32064*FLEN/8, x13, x9, x10)

inst_10710:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32067*FLEN/8, x13, x9, x10)

inst_10711:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32070*FLEN/8, x13, x9, x10)

inst_10712:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:32073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32073*FLEN/8, x13, x9, x10)

inst_10713:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32076*FLEN/8, x13, x9, x10)

inst_10714:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:32079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32079*FLEN/8, x13, x9, x10)

inst_10715:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32082*FLEN/8, x13, x9, x10)

inst_10716:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32085*FLEN/8, x13, x9, x10)

inst_10717:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32088*FLEN/8, x13, x9, x10)

inst_10718:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32091*FLEN/8, x13, x9, x10)

inst_10719:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32094*FLEN/8, x13, x9, x10)

inst_10720:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32097*FLEN/8, x13, x9, x10)

inst_10721:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32100*FLEN/8, x13, x9, x10)

inst_10722:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32103*FLEN/8, x13, x9, x10)

inst_10723:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32106*FLEN/8, x13, x9, x10)

inst_10724:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32109*FLEN/8, x13, x9, x10)

inst_10725:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32112*FLEN/8, x13, x9, x10)

inst_10726:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32115*FLEN/8, x13, x9, x10)

inst_10727:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32118*FLEN/8, x13, x9, x10)

inst_10728:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:32121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32121*FLEN/8, x13, x9, x10)

inst_10729:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32124*FLEN/8, x13, x9, x10)

inst_10730:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:32127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32127*FLEN/8, x13, x9, x10)

inst_10731:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32130*FLEN/8, x13, x9, x10)

inst_10732:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:32133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32133*FLEN/8, x13, x9, x10)

inst_10733:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32136*FLEN/8, x13, x9, x10)

inst_10734:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32139*FLEN/8, x13, x9, x10)

inst_10735:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32142*FLEN/8, x13, x9, x10)

inst_10736:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:32145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32145*FLEN/8, x13, x9, x10)

inst_10737:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32148*FLEN/8, x13, x9, x10)

inst_10738:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:32151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32151*FLEN/8, x13, x9, x10)

inst_10739:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32154*FLEN/8, x13, x9, x10)

inst_10740:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32157*FLEN/8, x13, x9, x10)

inst_10741:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32160*FLEN/8, x13, x9, x10)

inst_10742:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32163*FLEN/8, x13, x9, x10)

inst_10743:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32166*FLEN/8, x13, x9, x10)

inst_10744:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32169*FLEN/8, x13, x9, x10)

inst_10745:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32172*FLEN/8, x13, x9, x10)

inst_10746:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32175*FLEN/8, x13, x9, x10)

inst_10747:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32178*FLEN/8, x13, x9, x10)

inst_10748:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32181*FLEN/8, x13, x9, x10)

inst_10749:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32184*FLEN/8, x13, x9, x10)

inst_10750:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32187*FLEN/8, x13, x9, x10)

inst_10751:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32190*FLEN/8, x13, x9, x10)

inst_10752:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:32193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32193*FLEN/8, x13, x9, x10)

inst_10753:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32196*FLEN/8, x13, x9, x10)

inst_10754:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:32199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32199*FLEN/8, x13, x9, x10)

inst_10755:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32202*FLEN/8, x13, x9, x10)

inst_10756:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:32205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32205*FLEN/8, x13, x9, x10)

inst_10757:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32208*FLEN/8, x13, x9, x10)

inst_10758:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32211*FLEN/8, x13, x9, x10)

inst_10759:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32214*FLEN/8, x13, x9, x10)

inst_10760:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:32217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32217*FLEN/8, x13, x9, x10)

inst_10761:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32220*FLEN/8, x13, x9, x10)

inst_10762:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:32223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32223*FLEN/8, x13, x9, x10)

inst_10763:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32226*FLEN/8, x13, x9, x10)

inst_10764:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32229*FLEN/8, x13, x9, x10)

inst_10765:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32232*FLEN/8, x13, x9, x10)

inst_10766:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32235*FLEN/8, x13, x9, x10)

inst_10767:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32238*FLEN/8, x13, x9, x10)

inst_10768:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32241*FLEN/8, x13, x9, x10)

inst_10769:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32244*FLEN/8, x13, x9, x10)

inst_10770:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32247*FLEN/8, x13, x9, x10)

inst_10771:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32250*FLEN/8, x13, x9, x10)

inst_10772:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32253*FLEN/8, x13, x9, x10)

inst_10773:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32256*FLEN/8, x13, x9, x10)

inst_10774:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32259*FLEN/8, x13, x9, x10)

inst_10775:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32262*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_84)

inst_10776:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:32265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32265*FLEN/8, x13, x9, x10)

inst_10777:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32268*FLEN/8, x13, x9, x10)

inst_10778:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:32271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32271*FLEN/8, x13, x9, x10)

inst_10779:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32274*FLEN/8, x13, x9, x10)

inst_10780:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:32277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32277*FLEN/8, x13, x9, x10)

inst_10781:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32280*FLEN/8, x13, x9, x10)

inst_10782:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32283*FLEN/8, x13, x9, x10)

inst_10783:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32286*FLEN/8, x13, x9, x10)

inst_10784:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:32289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32289*FLEN/8, x13, x9, x10)

inst_10785:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32292*FLEN/8, x13, x9, x10)

inst_10786:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:32295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32295*FLEN/8, x13, x9, x10)

inst_10787:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32298*FLEN/8, x13, x9, x10)

inst_10788:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32301*FLEN/8, x13, x9, x10)

inst_10789:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32304*FLEN/8, x13, x9, x10)

inst_10790:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32307*FLEN/8, x13, x9, x10)

inst_10791:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32310*FLEN/8, x13, x9, x10)

inst_10792:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32313*FLEN/8, x13, x9, x10)

inst_10793:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32316*FLEN/8, x13, x9, x10)

inst_10794:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32319*FLEN/8, x13, x9, x10)

inst_10795:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32322*FLEN/8, x13, x9, x10)

inst_10796:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32325*FLEN/8, x13, x9, x10)

inst_10797:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32328*FLEN/8, x13, x9, x10)

inst_10798:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32331*FLEN/8, x13, x9, x10)

inst_10799:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32334*FLEN/8, x13, x9, x10)

inst_10800:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:32337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32337*FLEN/8, x13, x9, x10)

inst_10801:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:32340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32340*FLEN/8, x13, x9, x10)

inst_10802:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:32343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32343*FLEN/8, x13, x9, x10)

inst_10803:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:32346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32346*FLEN/8, x13, x9, x10)

inst_10804:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:32349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32349*FLEN/8, x13, x9, x10)

inst_10805:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32352*FLEN/8, x13, x9, x10)

inst_10806:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32355*FLEN/8, x13, x9, x10)

inst_10807:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32358*FLEN/8, x13, x9, x10)

inst_10808:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:32361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32361*FLEN/8, x13, x9, x10)

inst_10809:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:32364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32364*FLEN/8, x13, x9, x10)

inst_10810:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:32367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32367*FLEN/8, x13, x9, x10)

inst_10811:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:32370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32370*FLEN/8, x13, x9, x10)

inst_10812:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32373*FLEN/8, x13, x9, x10)

inst_10813:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32376*FLEN/8, x13, x9, x10)

inst_10814:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32379*FLEN/8, x13, x9, x10)

inst_10815:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:32382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32382*FLEN/8, x13, x9, x10)

inst_10816:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32385*FLEN/8, x13, x9, x10)

inst_10817:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32388*FLEN/8, x13, x9, x10)

inst_10818:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32391*FLEN/8, x13, x9, x10)

inst_10819:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32394*FLEN/8, x13, x9, x10)

inst_10820:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32397*FLEN/8, x13, x9, x10)

inst_10821:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32400*FLEN/8, x13, x9, x10)

inst_10822:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32403*FLEN/8, x13, x9, x10)

inst_10823:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32406*FLEN/8, x13, x9, x10)

inst_10824:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:32409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32409*FLEN/8, x13, x9, x10)

inst_10825:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:32412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32412*FLEN/8, x13, x9, x10)

inst_10826:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:32415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32415*FLEN/8, x13, x9, x10)

inst_10827:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:32418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32418*FLEN/8, x13, x9, x10)

inst_10828:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:32421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32421*FLEN/8, x13, x9, x10)

inst_10829:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32424*FLEN/8, x13, x9, x10)

inst_10830:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32427*FLEN/8, x13, x9, x10)

inst_10831:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32430*FLEN/8, x13, x9, x10)

inst_10832:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:32433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32433*FLEN/8, x13, x9, x10)

inst_10833:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:32436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32436*FLEN/8, x13, x9, x10)

inst_10834:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:32439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32439*FLEN/8, x13, x9, x10)

inst_10835:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:32442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32442*FLEN/8, x13, x9, x10)

inst_10836:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32445*FLEN/8, x13, x9, x10)

inst_10837:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32448*FLEN/8, x13, x9, x10)

inst_10838:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32451*FLEN/8, x13, x9, x10)

inst_10839:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:32454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32454*FLEN/8, x13, x9, x10)

inst_10840:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32457*FLEN/8, x13, x9, x10)

inst_10841:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32460*FLEN/8, x13, x9, x10)

inst_10842:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32463*FLEN/8, x13, x9, x10)

inst_10843:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32466*FLEN/8, x13, x9, x10)

inst_10844:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32469*FLEN/8, x13, x9, x10)

inst_10845:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32472*FLEN/8, x13, x9, x10)

inst_10846:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32475*FLEN/8, x13, x9, x10)

inst_10847:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32478*FLEN/8, x13, x9, x10)

inst_10848:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:32481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32481*FLEN/8, x13, x9, x10)

inst_10849:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:32484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32484*FLEN/8, x13, x9, x10)

inst_10850:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:32487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32487*FLEN/8, x13, x9, x10)

inst_10851:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:32490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32490*FLEN/8, x13, x9, x10)

inst_10852:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:32493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32493*FLEN/8, x13, x9, x10)

inst_10853:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32496*FLEN/8, x13, x9, x10)

inst_10854:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32499*FLEN/8, x13, x9, x10)

inst_10855:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32502*FLEN/8, x13, x9, x10)

inst_10856:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:32505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32505*FLEN/8, x13, x9, x10)

inst_10857:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:32508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32508*FLEN/8, x13, x9, x10)

inst_10858:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:32511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32511*FLEN/8, x13, x9, x10)

inst_10859:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:32514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32514*FLEN/8, x13, x9, x10)

inst_10860:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32517*FLEN/8, x13, x9, x10)

inst_10861:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32520*FLEN/8, x13, x9, x10)

inst_10862:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32523*FLEN/8, x13, x9, x10)

inst_10863:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:32526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32526*FLEN/8, x13, x9, x10)

inst_10864:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32529*FLEN/8, x13, x9, x10)

inst_10865:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32532*FLEN/8, x13, x9, x10)

inst_10866:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32535*FLEN/8, x13, x9, x10)

inst_10867:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32538*FLEN/8, x13, x9, x10)

inst_10868:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32541*FLEN/8, x13, x9, x10)

inst_10869:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32544*FLEN/8, x13, x9, x10)

inst_10870:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32547*FLEN/8, x13, x9, x10)

inst_10871:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32550*FLEN/8, x13, x9, x10)

inst_10872:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:32553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32553*FLEN/8, x13, x9, x10)

inst_10873:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:32556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32556*FLEN/8, x13, x9, x10)

inst_10874:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:32559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32559*FLEN/8, x13, x9, x10)

inst_10875:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:32562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32562*FLEN/8, x13, x9, x10)

inst_10876:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:32565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32565*FLEN/8, x13, x9, x10)

inst_10877:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32568*FLEN/8, x13, x9, x10)

inst_10878:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32571*FLEN/8, x13, x9, x10)

inst_10879:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32574*FLEN/8, x13, x9, x10)

inst_10880:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:32577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32577*FLEN/8, x13, x9, x10)

inst_10881:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:32580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32580*FLEN/8, x13, x9, x10)

inst_10882:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:32583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32583*FLEN/8, x13, x9, x10)

inst_10883:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:32586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32586*FLEN/8, x13, x9, x10)

inst_10884:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32589*FLEN/8, x13, x9, x10)

inst_10885:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32592*FLEN/8, x13, x9, x10)

inst_10886:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32595*FLEN/8, x13, x9, x10)

inst_10887:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:32598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32598*FLEN/8, x13, x9, x10)

inst_10888:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32601*FLEN/8, x13, x9, x10)

inst_10889:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32604*FLEN/8, x13, x9, x10)

inst_10890:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32607*FLEN/8, x13, x9, x10)

inst_10891:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32610*FLEN/8, x13, x9, x10)

inst_10892:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32613*FLEN/8, x13, x9, x10)

inst_10893:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32616*FLEN/8, x13, x9, x10)

inst_10894:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32619*FLEN/8, x13, x9, x10)

inst_10895:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32622*FLEN/8, x13, x9, x10)

inst_10896:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:32625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32625*FLEN/8, x13, x9, x10)

inst_10897:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32628*FLEN/8, x13, x9, x10)

inst_10898:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:32631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32631*FLEN/8, x13, x9, x10)

inst_10899:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32634*FLEN/8, x13, x9, x10)

inst_10900:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:32637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32637*FLEN/8, x13, x9, x10)

inst_10901:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32640*FLEN/8, x13, x9, x10)

inst_10902:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32643*FLEN/8, x13, x9, x10)

inst_10903:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32646*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_85)

inst_10904:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:32649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32649*FLEN/8, x13, x9, x10)

inst_10905:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32652*FLEN/8, x13, x9, x10)

inst_10906:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:32655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32655*FLEN/8, x13, x9, x10)

inst_10907:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32658*FLEN/8, x13, x9, x10)

inst_10908:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32661*FLEN/8, x13, x9, x10)

inst_10909:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32664*FLEN/8, x13, x9, x10)

inst_10910:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32667*FLEN/8, x13, x9, x10)

inst_10911:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32670*FLEN/8, x13, x9, x10)

inst_10912:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32673*FLEN/8, x13, x9, x10)

inst_10913:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32676*FLEN/8, x13, x9, x10)

inst_10914:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32679*FLEN/8, x13, x9, x10)

inst_10915:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32682*FLEN/8, x13, x9, x10)

inst_10916:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32685*FLEN/8, x13, x9, x10)

inst_10917:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32688*FLEN/8, x13, x9, x10)

inst_10918:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32691*FLEN/8, x13, x9, x10)

inst_10919:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32694*FLEN/8, x13, x9, x10)

inst_10920:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:32697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32697*FLEN/8, x13, x9, x10)

inst_10921:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32700*FLEN/8, x13, x9, x10)

inst_10922:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:32703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32703*FLEN/8, x13, x9, x10)

inst_10923:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32706*FLEN/8, x13, x9, x10)

inst_10924:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:32709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32709*FLEN/8, x13, x9, x10)

inst_10925:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32712*FLEN/8, x13, x9, x10)

inst_10926:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32715*FLEN/8, x13, x9, x10)

inst_10927:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32718*FLEN/8, x13, x9, x10)

inst_10928:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:32721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32721*FLEN/8, x13, x9, x10)

inst_10929:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32724*FLEN/8, x13, x9, x10)

inst_10930:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:32727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32727*FLEN/8, x13, x9, x10)

inst_10931:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32730*FLEN/8, x13, x9, x10)

inst_10932:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32733*FLEN/8, x13, x9, x10)

inst_10933:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32736*FLEN/8, x13, x9, x10)

inst_10934:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32739*FLEN/8, x13, x9, x10)

inst_10935:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32742*FLEN/8, x13, x9, x10)

inst_10936:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32745*FLEN/8, x13, x9, x10)

inst_10937:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32748*FLEN/8, x13, x9, x10)

inst_10938:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32751*FLEN/8, x13, x9, x10)

inst_10939:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32754*FLEN/8, x13, x9, x10)

inst_10940:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32757*FLEN/8, x13, x9, x10)

inst_10941:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32760*FLEN/8, x13, x9, x10)

inst_10942:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32763*FLEN/8, x13, x9, x10)

inst_10943:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32766*FLEN/8, x13, x9, x10)

inst_10944:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:32769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32769*FLEN/8, x13, x9, x10)

inst_10945:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:32772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32772*FLEN/8, x13, x9, x10)

inst_10946:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:32775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32775*FLEN/8, x13, x9, x10)

inst_10947:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:32778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32778*FLEN/8, x13, x9, x10)

inst_10948:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:32781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32781*FLEN/8, x13, x9, x10)

inst_10949:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32784*FLEN/8, x13, x9, x10)

inst_10950:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32787*FLEN/8, x13, x9, x10)

inst_10951:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32790*FLEN/8, x13, x9, x10)

inst_10952:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:32793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32793*FLEN/8, x13, x9, x10)

inst_10953:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:32796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32796*FLEN/8, x13, x9, x10)

inst_10954:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:32799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32799*FLEN/8, x13, x9, x10)

inst_10955:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:32802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32802*FLEN/8, x13, x9, x10)

inst_10956:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32805*FLEN/8, x13, x9, x10)

inst_10957:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32808*FLEN/8, x13, x9, x10)

inst_10958:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32811*FLEN/8, x13, x9, x10)

inst_10959:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:32814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32814*FLEN/8, x13, x9, x10)

inst_10960:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32817*FLEN/8, x13, x9, x10)

inst_10961:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32820*FLEN/8, x13, x9, x10)

inst_10962:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32823*FLEN/8, x13, x9, x10)

inst_10963:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32826*FLEN/8, x13, x9, x10)

inst_10964:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32829*FLEN/8, x13, x9, x10)

inst_10965:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32832*FLEN/8, x13, x9, x10)

inst_10966:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32835*FLEN/8, x13, x9, x10)

inst_10967:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32838*FLEN/8, x13, x9, x10)

inst_10968:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:32841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32841*FLEN/8, x13, x9, x10)

inst_10969:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:32844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32844*FLEN/8, x13, x9, x10)

inst_10970:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:32847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32847*FLEN/8, x13, x9, x10)

inst_10971:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:32850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32850*FLEN/8, x13, x9, x10)

inst_10972:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:32853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32853*FLEN/8, x13, x9, x10)

inst_10973:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32856*FLEN/8, x13, x9, x10)

inst_10974:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32859*FLEN/8, x13, x9, x10)

inst_10975:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32862*FLEN/8, x13, x9, x10)

inst_10976:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:32865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32865*FLEN/8, x13, x9, x10)

inst_10977:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:32868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32868*FLEN/8, x13, x9, x10)

inst_10978:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:32871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32871*FLEN/8, x13, x9, x10)

inst_10979:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:32874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32874*FLEN/8, x13, x9, x10)

inst_10980:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32877*FLEN/8, x13, x9, x10)

inst_10981:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32880*FLEN/8, x13, x9, x10)

inst_10982:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32883*FLEN/8, x13, x9, x10)

inst_10983:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:32886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32886*FLEN/8, x13, x9, x10)

inst_10984:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32889*FLEN/8, x13, x9, x10)

inst_10985:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32892*FLEN/8, x13, x9, x10)

inst_10986:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32895*FLEN/8, x13, x9, x10)

inst_10987:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32898*FLEN/8, x13, x9, x10)

inst_10988:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32901*FLEN/8, x13, x9, x10)

inst_10989:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32904*FLEN/8, x13, x9, x10)

inst_10990:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32907*FLEN/8, x13, x9, x10)

inst_10991:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32910*FLEN/8, x13, x9, x10)

inst_10992:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:32913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32913*FLEN/8, x13, x9, x10)

inst_10993:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:32916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32916*FLEN/8, x13, x9, x10)

inst_10994:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:32919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32919*FLEN/8, x13, x9, x10)

inst_10995:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:32922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32922*FLEN/8, x13, x9, x10)

inst_10996:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:32925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32925*FLEN/8, x13, x9, x10)

inst_10997:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:32928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32928*FLEN/8, x13, x9, x10)

inst_10998:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:32931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32931*FLEN/8, x13, x9, x10)

inst_10999:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:32934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32934*FLEN/8, x13, x9, x10)

inst_11000:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:32937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32937*FLEN/8, x13, x9, x10)

inst_11001:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:32940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32940*FLEN/8, x13, x9, x10)

inst_11002:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:32943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32943*FLEN/8, x13, x9, x10)

inst_11003:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:32946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32946*FLEN/8, x13, x9, x10)

inst_11004:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:32949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32949*FLEN/8, x13, x9, x10)

inst_11005:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:32952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32952*FLEN/8, x13, x9, x10)

inst_11006:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:32955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32955*FLEN/8, x13, x9, x10)

inst_11007:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:32958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32958*FLEN/8, x13, x9, x10)

inst_11008:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:32961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32961*FLEN/8, x13, x9, x10)

inst_11009:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:32964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32964*FLEN/8, x13, x9, x10)

inst_11010:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:32967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32967*FLEN/8, x13, x9, x10)

inst_11011:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:32970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32970*FLEN/8, x13, x9, x10)

inst_11012:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:32973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32973*FLEN/8, x13, x9, x10)

inst_11013:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:32976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32976*FLEN/8, x13, x9, x10)

inst_11014:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:32979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32979*FLEN/8, x13, x9, x10)

inst_11015:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:32982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32982*FLEN/8, x13, x9, x10)

inst_11016:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:32985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32985*FLEN/8, x13, x9, x10)

inst_11017:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:32988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32988*FLEN/8, x13, x9, x10)

inst_11018:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:32991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32991*FLEN/8, x13, x9, x10)

inst_11019:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:32994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32994*FLEN/8, x13, x9, x10)

inst_11020:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:32997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 32997*FLEN/8, x13, x9, x10)

inst_11021:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33000*FLEN/8, x13, x9, x10)

inst_11022:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33003*FLEN/8, x13, x9, x10)

inst_11023:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33006*FLEN/8, x13, x9, x10)

inst_11024:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:33009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33009*FLEN/8, x13, x9, x10)

inst_11025:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:33012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33012*FLEN/8, x13, x9, x10)

inst_11026:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:33015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33015*FLEN/8, x13, x9, x10)

inst_11027:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:33018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33018*FLEN/8, x13, x9, x10)

inst_11028:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33021*FLEN/8, x13, x9, x10)

inst_11029:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33024*FLEN/8, x13, x9, x10)

inst_11030:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33027*FLEN/8, x13, x9, x10)

inst_11031:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:33030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33030*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_86)

inst_11032:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33033*FLEN/8, x13, x9, x10)

inst_11033:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33036*FLEN/8, x13, x9, x10)

inst_11034:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33039*FLEN/8, x13, x9, x10)

inst_11035:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33042*FLEN/8, x13, x9, x10)

inst_11036:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33045*FLEN/8, x13, x9, x10)

inst_11037:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33048*FLEN/8, x13, x9, x10)

inst_11038:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33051*FLEN/8, x13, x9, x10)

inst_11039:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33054*FLEN/8, x13, x9, x10)

inst_11040:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:33057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33057*FLEN/8, x13, x9, x10)

inst_11041:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:33060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33060*FLEN/8, x13, x9, x10)

inst_11042:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:33063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33063*FLEN/8, x13, x9, x10)

inst_11043:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:33066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33066*FLEN/8, x13, x9, x10)

inst_11044:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:33069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33069*FLEN/8, x13, x9, x10)

inst_11045:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33072*FLEN/8, x13, x9, x10)

inst_11046:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33075*FLEN/8, x13, x9, x10)

inst_11047:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33078*FLEN/8, x13, x9, x10)

inst_11048:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:33081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33081*FLEN/8, x13, x9, x10)

inst_11049:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:33084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33084*FLEN/8, x13, x9, x10)

inst_11050:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:33087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33087*FLEN/8, x13, x9, x10)

inst_11051:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:33090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33090*FLEN/8, x13, x9, x10)

inst_11052:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33093*FLEN/8, x13, x9, x10)

inst_11053:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33096*FLEN/8, x13, x9, x10)

inst_11054:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33099*FLEN/8, x13, x9, x10)

inst_11055:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:33102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33102*FLEN/8, x13, x9, x10)

inst_11056:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33105*FLEN/8, x13, x9, x10)

inst_11057:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33108*FLEN/8, x13, x9, x10)

inst_11058:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33111*FLEN/8, x13, x9, x10)

inst_11059:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33114*FLEN/8, x13, x9, x10)

inst_11060:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33117*FLEN/8, x13, x9, x10)

inst_11061:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33120*FLEN/8, x13, x9, x10)

inst_11062:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33123*FLEN/8, x13, x9, x10)

inst_11063:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33126*FLEN/8, x13, x9, x10)

inst_11064:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:33129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33129*FLEN/8, x13, x9, x10)

inst_11065:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:33132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33132*FLEN/8, x13, x9, x10)

inst_11066:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:33135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33135*FLEN/8, x13, x9, x10)

inst_11067:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:33138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33138*FLEN/8, x13, x9, x10)

inst_11068:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:33141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33141*FLEN/8, x13, x9, x10)

inst_11069:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33144*FLEN/8, x13, x9, x10)

inst_11070:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33147*FLEN/8, x13, x9, x10)

inst_11071:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33150*FLEN/8, x13, x9, x10)

inst_11072:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:33153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33153*FLEN/8, x13, x9, x10)

inst_11073:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:33156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33156*FLEN/8, x13, x9, x10)

inst_11074:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:33159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33159*FLEN/8, x13, x9, x10)

inst_11075:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:33162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33162*FLEN/8, x13, x9, x10)

inst_11076:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33165*FLEN/8, x13, x9, x10)

inst_11077:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33168*FLEN/8, x13, x9, x10)

inst_11078:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33171*FLEN/8, x13, x9, x10)

inst_11079:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:33174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33174*FLEN/8, x13, x9, x10)

inst_11080:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33177*FLEN/8, x13, x9, x10)

inst_11081:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33180*FLEN/8, x13, x9, x10)

inst_11082:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33183*FLEN/8, x13, x9, x10)

inst_11083:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33186*FLEN/8, x13, x9, x10)

inst_11084:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33189*FLEN/8, x13, x9, x10)

inst_11085:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33192*FLEN/8, x13, x9, x10)

inst_11086:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33195*FLEN/8, x13, x9, x10)

inst_11087:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33198*FLEN/8, x13, x9, x10)

inst_11088:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:33201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33201*FLEN/8, x13, x9, x10)

inst_11089:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:33204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33204*FLEN/8, x13, x9, x10)

inst_11090:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:33207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33207*FLEN/8, x13, x9, x10)

inst_11091:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:33210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33210*FLEN/8, x13, x9, x10)

inst_11092:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:33213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33213*FLEN/8, x13, x9, x10)

inst_11093:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33216*FLEN/8, x13, x9, x10)

inst_11094:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33219*FLEN/8, x13, x9, x10)

inst_11095:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33222*FLEN/8, x13, x9, x10)

inst_11096:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:33225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33225*FLEN/8, x13, x9, x10)

inst_11097:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:33228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33228*FLEN/8, x13, x9, x10)

inst_11098:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:33231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33231*FLEN/8, x13, x9, x10)

inst_11099:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:33234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33234*FLEN/8, x13, x9, x10)

inst_11100:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33237*FLEN/8, x13, x9, x10)

inst_11101:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33240*FLEN/8, x13, x9, x10)

inst_11102:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33243*FLEN/8, x13, x9, x10)

inst_11103:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:33246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33246*FLEN/8, x13, x9, x10)

inst_11104:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33249*FLEN/8, x13, x9, x10)

inst_11105:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33252*FLEN/8, x13, x9, x10)

inst_11106:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33255*FLEN/8, x13, x9, x10)

inst_11107:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33258*FLEN/8, x13, x9, x10)

inst_11108:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33261*FLEN/8, x13, x9, x10)

inst_11109:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33264*FLEN/8, x13, x9, x10)

inst_11110:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33267*FLEN/8, x13, x9, x10)

inst_11111:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33270*FLEN/8, x13, x9, x10)

inst_11112:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:33273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33273*FLEN/8, x13, x9, x10)

inst_11113:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:33276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33276*FLEN/8, x13, x9, x10)

inst_11114:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:33279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33279*FLEN/8, x13, x9, x10)

inst_11115:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:33282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33282*FLEN/8, x13, x9, x10)

inst_11116:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:33285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33285*FLEN/8, x13, x9, x10)

inst_11117:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33288*FLEN/8, x13, x9, x10)

inst_11118:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33291*FLEN/8, x13, x9, x10)

inst_11119:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33294*FLEN/8, x13, x9, x10)

inst_11120:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:33297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33297*FLEN/8, x13, x9, x10)

inst_11121:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:33300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33300*FLEN/8, x13, x9, x10)

inst_11122:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:33303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33303*FLEN/8, x13, x9, x10)

inst_11123:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:33306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33306*FLEN/8, x13, x9, x10)

inst_11124:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33309*FLEN/8, x13, x9, x10)

inst_11125:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33312*FLEN/8, x13, x9, x10)

inst_11126:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33315*FLEN/8, x13, x9, x10)

inst_11127:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:33318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33318*FLEN/8, x13, x9, x10)

inst_11128:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33321*FLEN/8, x13, x9, x10)

inst_11129:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33324*FLEN/8, x13, x9, x10)

inst_11130:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33327*FLEN/8, x13, x9, x10)

inst_11131:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33330*FLEN/8, x13, x9, x10)

inst_11132:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33333*FLEN/8, x13, x9, x10)

inst_11133:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33336*FLEN/8, x13, x9, x10)

inst_11134:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33339*FLEN/8, x13, x9, x10)

inst_11135:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33342*FLEN/8, x13, x9, x10)

inst_11136:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:33345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33345*FLEN/8, x13, x9, x10)

inst_11137:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:33348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33348*FLEN/8, x13, x9, x10)

inst_11138:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:33351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33351*FLEN/8, x13, x9, x10)

inst_11139:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:33354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33354*FLEN/8, x13, x9, x10)

inst_11140:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:33357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33357*FLEN/8, x13, x9, x10)

inst_11141:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33360*FLEN/8, x13, x9, x10)

inst_11142:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33363*FLEN/8, x13, x9, x10)

inst_11143:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33366*FLEN/8, x13, x9, x10)

inst_11144:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:33369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33369*FLEN/8, x13, x9, x10)

inst_11145:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:33372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33372*FLEN/8, x13, x9, x10)

inst_11146:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:33375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33375*FLEN/8, x13, x9, x10)

inst_11147:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:33378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33378*FLEN/8, x13, x9, x10)

inst_11148:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33381*FLEN/8, x13, x9, x10)

inst_11149:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33384*FLEN/8, x13, x9, x10)

inst_11150:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33387*FLEN/8, x13, x9, x10)

inst_11151:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:33390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33390*FLEN/8, x13, x9, x10)

inst_11152:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33393*FLEN/8, x13, x9, x10)

inst_11153:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33396*FLEN/8, x13, x9, x10)

inst_11154:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33399*FLEN/8, x13, x9, x10)

inst_11155:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33402*FLEN/8, x13, x9, x10)

inst_11156:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33405*FLEN/8, x13, x9, x10)

inst_11157:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33408*FLEN/8, x13, x9, x10)

inst_11158:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33411*FLEN/8, x13, x9, x10)

inst_11159:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33414*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_87)

inst_11160:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:33417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33417*FLEN/8, x13, x9, x10)

inst_11161:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:33420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33420*FLEN/8, x13, x9, x10)

inst_11162:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:33423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33423*FLEN/8, x13, x9, x10)

inst_11163:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:33426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33426*FLEN/8, x13, x9, x10)

inst_11164:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:33429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33429*FLEN/8, x13, x9, x10)

inst_11165:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33432*FLEN/8, x13, x9, x10)

inst_11166:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33435*FLEN/8, x13, x9, x10)

inst_11167:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33438*FLEN/8, x13, x9, x10)

inst_11168:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:33441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33441*FLEN/8, x13, x9, x10)

inst_11169:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:33444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33444*FLEN/8, x13, x9, x10)

inst_11170:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:33447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33447*FLEN/8, x13, x9, x10)

inst_11171:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:33450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33450*FLEN/8, x13, x9, x10)

inst_11172:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33453*FLEN/8, x13, x9, x10)

inst_11173:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33456*FLEN/8, x13, x9, x10)

inst_11174:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33459*FLEN/8, x13, x9, x10)

inst_11175:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:33462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33462*FLEN/8, x13, x9, x10)

inst_11176:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33465*FLEN/8, x13, x9, x10)

inst_11177:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33468*FLEN/8, x13, x9, x10)

inst_11178:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33471*FLEN/8, x13, x9, x10)

inst_11179:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33474*FLEN/8, x13, x9, x10)

inst_11180:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33477*FLEN/8, x13, x9, x10)

inst_11181:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33480*FLEN/8, x13, x9, x10)

inst_11182:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33483*FLEN/8, x13, x9, x10)

inst_11183:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33486*FLEN/8, x13, x9, x10)

inst_11184:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:33489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33489*FLEN/8, x13, x9, x10)

inst_11185:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:33492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33492*FLEN/8, x13, x9, x10)

inst_11186:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:33495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33495*FLEN/8, x13, x9, x10)

inst_11187:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:33498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33498*FLEN/8, x13, x9, x10)

inst_11188:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:33501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33501*FLEN/8, x13, x9, x10)

inst_11189:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33504*FLEN/8, x13, x9, x10)

inst_11190:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33507*FLEN/8, x13, x9, x10)

inst_11191:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33510*FLEN/8, x13, x9, x10)

inst_11192:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:33513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33513*FLEN/8, x13, x9, x10)

inst_11193:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:33516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33516*FLEN/8, x13, x9, x10)

inst_11194:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:33519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33519*FLEN/8, x13, x9, x10)

inst_11195:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:33522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33522*FLEN/8, x13, x9, x10)

inst_11196:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33525*FLEN/8, x13, x9, x10)

inst_11197:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33528*FLEN/8, x13, x9, x10)

inst_11198:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33531*FLEN/8, x13, x9, x10)

inst_11199:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:33534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33534*FLEN/8, x13, x9, x10)

inst_11200:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33537*FLEN/8, x13, x9, x10)

inst_11201:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33540*FLEN/8, x13, x9, x10)

inst_11202:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33543*FLEN/8, x13, x9, x10)

inst_11203:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33546*FLEN/8, x13, x9, x10)

inst_11204:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33549*FLEN/8, x13, x9, x10)

inst_11205:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33552*FLEN/8, x13, x9, x10)

inst_11206:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33555*FLEN/8, x13, x9, x10)

inst_11207:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33558*FLEN/8, x13, x9, x10)

inst_11208:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:33561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33561*FLEN/8, x13, x9, x10)

inst_11209:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:33564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33564*FLEN/8, x13, x9, x10)

inst_11210:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:33567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33567*FLEN/8, x13, x9, x10)

inst_11211:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:33570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33570*FLEN/8, x13, x9, x10)

inst_11212:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:33573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33573*FLEN/8, x13, x9, x10)

inst_11213:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33576*FLEN/8, x13, x9, x10)

inst_11214:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33579*FLEN/8, x13, x9, x10)

inst_11215:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33582*FLEN/8, x13, x9, x10)

inst_11216:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:33585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33585*FLEN/8, x13, x9, x10)

inst_11217:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:33588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33588*FLEN/8, x13, x9, x10)

inst_11218:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:33591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33591*FLEN/8, x13, x9, x10)

inst_11219:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:33594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33594*FLEN/8, x13, x9, x10)

inst_11220:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33597*FLEN/8, x13, x9, x10)

inst_11221:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33600*FLEN/8, x13, x9, x10)

inst_11222:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33603*FLEN/8, x13, x9, x10)

inst_11223:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:33606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33606*FLEN/8, x13, x9, x10)

inst_11224:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33609*FLEN/8, x13, x9, x10)

inst_11225:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33612*FLEN/8, x13, x9, x10)

inst_11226:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33615*FLEN/8, x13, x9, x10)

inst_11227:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33618*FLEN/8, x13, x9, x10)

inst_11228:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33621*FLEN/8, x13, x9, x10)

inst_11229:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33624*FLEN/8, x13, x9, x10)

inst_11230:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33627*FLEN/8, x13, x9, x10)

inst_11231:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33630*FLEN/8, x13, x9, x10)

inst_11232:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:33633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33633*FLEN/8, x13, x9, x10)

inst_11233:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:33636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33636*FLEN/8, x13, x9, x10)

inst_11234:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:33639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33639*FLEN/8, x13, x9, x10)

inst_11235:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:33642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33642*FLEN/8, x13, x9, x10)

inst_11236:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:33645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33645*FLEN/8, x13, x9, x10)

inst_11237:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33648*FLEN/8, x13, x9, x10)

inst_11238:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33651*FLEN/8, x13, x9, x10)

inst_11239:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33654*FLEN/8, x13, x9, x10)

inst_11240:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:33657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33657*FLEN/8, x13, x9, x10)

inst_11241:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:33660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33660*FLEN/8, x13, x9, x10)

inst_11242:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:33663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33663*FLEN/8, x13, x9, x10)

inst_11243:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:33666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33666*FLEN/8, x13, x9, x10)

inst_11244:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33669*FLEN/8, x13, x9, x10)

inst_11245:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33672*FLEN/8, x13, x9, x10)

inst_11246:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33675*FLEN/8, x13, x9, x10)

inst_11247:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:33678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33678*FLEN/8, x13, x9, x10)

inst_11248:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33681*FLEN/8, x13, x9, x10)

inst_11249:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33684*FLEN/8, x13, x9, x10)

inst_11250:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33687*FLEN/8, x13, x9, x10)

inst_11251:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33690*FLEN/8, x13, x9, x10)

inst_11252:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33693*FLEN/8, x13, x9, x10)

inst_11253:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33696*FLEN/8, x13, x9, x10)

inst_11254:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33699*FLEN/8, x13, x9, x10)

inst_11255:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33702*FLEN/8, x13, x9, x10)

inst_11256:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:33705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33705*FLEN/8, x13, x9, x10)

inst_11257:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:33708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33708*FLEN/8, x13, x9, x10)

inst_11258:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:33711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33711*FLEN/8, x13, x9, x10)

inst_11259:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:33714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33714*FLEN/8, x13, x9, x10)

inst_11260:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:33717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33717*FLEN/8, x13, x9, x10)

inst_11261:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33720*FLEN/8, x13, x9, x10)

inst_11262:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33723*FLEN/8, x13, x9, x10)

inst_11263:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33726*FLEN/8, x13, x9, x10)

inst_11264:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:33729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33729*FLEN/8, x13, x9, x10)

inst_11265:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:33732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33732*FLEN/8, x13, x9, x10)

inst_11266:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:33735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33735*FLEN/8, x13, x9, x10)

inst_11267:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:33738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33738*FLEN/8, x13, x9, x10)

inst_11268:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33741*FLEN/8, x13, x9, x10)

inst_11269:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33744*FLEN/8, x13, x9, x10)

inst_11270:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33747*FLEN/8, x13, x9, x10)

inst_11271:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:33750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33750*FLEN/8, x13, x9, x10)

inst_11272:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33753*FLEN/8, x13, x9, x10)

inst_11273:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33756*FLEN/8, x13, x9, x10)

inst_11274:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33759*FLEN/8, x13, x9, x10)

inst_11275:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33762*FLEN/8, x13, x9, x10)

inst_11276:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33765*FLEN/8, x13, x9, x10)

inst_11277:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33768*FLEN/8, x13, x9, x10)

inst_11278:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33771*FLEN/8, x13, x9, x10)

inst_11279:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33774*FLEN/8, x13, x9, x10)

inst_11280:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:33777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33777*FLEN/8, x13, x9, x10)

inst_11281:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:33780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33780*FLEN/8, x13, x9, x10)

inst_11282:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:33783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33783*FLEN/8, x13, x9, x10)

inst_11283:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:33786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33786*FLEN/8, x13, x9, x10)

inst_11284:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:33789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33789*FLEN/8, x13, x9, x10)

inst_11285:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33792*FLEN/8, x13, x9, x10)

inst_11286:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33795*FLEN/8, x13, x9, x10)

inst_11287:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33798*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_88)

inst_11288:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:33801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33801*FLEN/8, x13, x9, x10)

inst_11289:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:33804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33804*FLEN/8, x13, x9, x10)

inst_11290:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:33807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33807*FLEN/8, x13, x9, x10)

inst_11291:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:33810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33810*FLEN/8, x13, x9, x10)

inst_11292:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33813*FLEN/8, x13, x9, x10)

inst_11293:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33816*FLEN/8, x13, x9, x10)

inst_11294:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33819*FLEN/8, x13, x9, x10)

inst_11295:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:33822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33822*FLEN/8, x13, x9, x10)

inst_11296:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33825*FLEN/8, x13, x9, x10)

inst_11297:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33828*FLEN/8, x13, x9, x10)

inst_11298:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33831*FLEN/8, x13, x9, x10)

inst_11299:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33834*FLEN/8, x13, x9, x10)

inst_11300:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33837*FLEN/8, x13, x9, x10)

inst_11301:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33840*FLEN/8, x13, x9, x10)

inst_11302:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33843*FLEN/8, x13, x9, x10)

inst_11303:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33846*FLEN/8, x13, x9, x10)

inst_11304:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:33849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33849*FLEN/8, x13, x9, x10)

inst_11305:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:33852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33852*FLEN/8, x13, x9, x10)

inst_11306:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:33855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33855*FLEN/8, x13, x9, x10)

inst_11307:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:33858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33858*FLEN/8, x13, x9, x10)

inst_11308:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:33861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33861*FLEN/8, x13, x9, x10)

inst_11309:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33864*FLEN/8, x13, x9, x10)

inst_11310:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33867*FLEN/8, x13, x9, x10)

inst_11311:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33870*FLEN/8, x13, x9, x10)

inst_11312:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:33873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33873*FLEN/8, x13, x9, x10)

inst_11313:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:33876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33876*FLEN/8, x13, x9, x10)

inst_11314:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:33879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33879*FLEN/8, x13, x9, x10)

inst_11315:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:33882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33882*FLEN/8, x13, x9, x10)

inst_11316:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33885*FLEN/8, x13, x9, x10)

inst_11317:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33888*FLEN/8, x13, x9, x10)

inst_11318:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33891*FLEN/8, x13, x9, x10)

inst_11319:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:33894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33894*FLEN/8, x13, x9, x10)

inst_11320:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33897*FLEN/8, x13, x9, x10)

inst_11321:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33900*FLEN/8, x13, x9, x10)

inst_11322:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33903*FLEN/8, x13, x9, x10)

inst_11323:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33906*FLEN/8, x13, x9, x10)

inst_11324:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33909*FLEN/8, x13, x9, x10)

inst_11325:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33912*FLEN/8, x13, x9, x10)

inst_11326:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33915*FLEN/8, x13, x9, x10)

inst_11327:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33918*FLEN/8, x13, x9, x10)

inst_11328:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:33921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33921*FLEN/8, x13, x9, x10)

inst_11329:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:33924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33924*FLEN/8, x13, x9, x10)

inst_11330:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:33927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33927*FLEN/8, x13, x9, x10)

inst_11331:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:33930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33930*FLEN/8, x13, x9, x10)

inst_11332:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:33933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33933*FLEN/8, x13, x9, x10)

inst_11333:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:33936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33936*FLEN/8, x13, x9, x10)

inst_11334:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:33939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33939*FLEN/8, x13, x9, x10)

inst_11335:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:33942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33942*FLEN/8, x13, x9, x10)

inst_11336:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:33945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33945*FLEN/8, x13, x9, x10)

inst_11337:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:33948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33948*FLEN/8, x13, x9, x10)

inst_11338:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:33951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33951*FLEN/8, x13, x9, x10)

inst_11339:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:33954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33954*FLEN/8, x13, x9, x10)

inst_11340:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:33957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33957*FLEN/8, x13, x9, x10)

inst_11341:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:33960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33960*FLEN/8, x13, x9, x10)

inst_11342:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:33963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33963*FLEN/8, x13, x9, x10)

inst_11343:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:33966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33966*FLEN/8, x13, x9, x10)

inst_11344:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:33969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33969*FLEN/8, x13, x9, x10)

inst_11345:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:33972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33972*FLEN/8, x13, x9, x10)

inst_11346:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:33975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33975*FLEN/8, x13, x9, x10)

inst_11347:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:33978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33978*FLEN/8, x13, x9, x10)

inst_11348:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:33981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33981*FLEN/8, x13, x9, x10)

inst_11349:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:33984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33984*FLEN/8, x13, x9, x10)

inst_11350:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:33987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33987*FLEN/8, x13, x9, x10)

inst_11351:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:33990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33990*FLEN/8, x13, x9, x10)

inst_11352:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:33993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33993*FLEN/8, x13, x9, x10)

inst_11353:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:33996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33996*FLEN/8, x13, x9, x10)

inst_11354:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:33999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 33999*FLEN/8, x13, x9, x10)

inst_11355:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:34002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34002*FLEN/8, x13, x9, x10)

inst_11356:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:34005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34005*FLEN/8, x13, x9, x10)

inst_11357:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34008*FLEN/8, x13, x9, x10)

inst_11358:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34011*FLEN/8, x13, x9, x10)

inst_11359:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34014*FLEN/8, x13, x9, x10)

inst_11360:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:34017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34017*FLEN/8, x13, x9, x10)

inst_11361:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:34020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34020*FLEN/8, x13, x9, x10)

inst_11362:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:34023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34023*FLEN/8, x13, x9, x10)

inst_11363:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:34026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34026*FLEN/8, x13, x9, x10)

inst_11364:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34029*FLEN/8, x13, x9, x10)

inst_11365:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34032*FLEN/8, x13, x9, x10)

inst_11366:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34035*FLEN/8, x13, x9, x10)

inst_11367:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:34038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34038*FLEN/8, x13, x9, x10)

inst_11368:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34041*FLEN/8, x13, x9, x10)

inst_11369:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34044*FLEN/8, x13, x9, x10)

inst_11370:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34047*FLEN/8, x13, x9, x10)

inst_11371:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34050*FLEN/8, x13, x9, x10)

inst_11372:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34053*FLEN/8, x13, x9, x10)

inst_11373:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34056*FLEN/8, x13, x9, x10)

inst_11374:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34059*FLEN/8, x13, x9, x10)

inst_11375:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34062*FLEN/8, x13, x9, x10)

inst_11376:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:34065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34065*FLEN/8, x13, x9, x10)

inst_11377:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:34068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34068*FLEN/8, x13, x9, x10)

inst_11378:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:34071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34071*FLEN/8, x13, x9, x10)

inst_11379:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:34074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34074*FLEN/8, x13, x9, x10)

inst_11380:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:34077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34077*FLEN/8, x13, x9, x10)

inst_11381:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34080*FLEN/8, x13, x9, x10)

inst_11382:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34083*FLEN/8, x13, x9, x10)

inst_11383:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34086*FLEN/8, x13, x9, x10)

inst_11384:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:34089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34089*FLEN/8, x13, x9, x10)

inst_11385:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:34092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34092*FLEN/8, x13, x9, x10)

inst_11386:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:34095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34095*FLEN/8, x13, x9, x10)

inst_11387:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:34098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34098*FLEN/8, x13, x9, x10)

inst_11388:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34101*FLEN/8, x13, x9, x10)

inst_11389:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34104*FLEN/8, x13, x9, x10)

inst_11390:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34107*FLEN/8, x13, x9, x10)

inst_11391:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:34110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34110*FLEN/8, x13, x9, x10)

inst_11392:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34113*FLEN/8, x13, x9, x10)

inst_11393:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34116*FLEN/8, x13, x9, x10)

inst_11394:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34119*FLEN/8, x13, x9, x10)

inst_11395:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34122*FLEN/8, x13, x9, x10)

inst_11396:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34125*FLEN/8, x13, x9, x10)

inst_11397:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34128*FLEN/8, x13, x9, x10)

inst_11398:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34131*FLEN/8, x13, x9, x10)

inst_11399:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34134*FLEN/8, x13, x9, x10)

inst_11400:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:34137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34137*FLEN/8, x13, x9, x10)

inst_11401:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:34140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34140*FLEN/8, x13, x9, x10)

inst_11402:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:34143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34143*FLEN/8, x13, x9, x10)

inst_11403:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:34146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34146*FLEN/8, x13, x9, x10)

inst_11404:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:34149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34149*FLEN/8, x13, x9, x10)

inst_11405:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34152*FLEN/8, x13, x9, x10)

inst_11406:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34155*FLEN/8, x13, x9, x10)

inst_11407:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34158*FLEN/8, x13, x9, x10)

inst_11408:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:34161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34161*FLEN/8, x13, x9, x10)

inst_11409:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:34164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34164*FLEN/8, x13, x9, x10)

inst_11410:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:34167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34167*FLEN/8, x13, x9, x10)

inst_11411:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:34170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34170*FLEN/8, x13, x9, x10)

inst_11412:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34173*FLEN/8, x13, x9, x10)

inst_11413:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34176*FLEN/8, x13, x9, x10)

inst_11414:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34179*FLEN/8, x13, x9, x10)

inst_11415:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:34182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34182*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_89)

inst_11416:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34185*FLEN/8, x13, x9, x10)

inst_11417:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34188*FLEN/8, x13, x9, x10)

inst_11418:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34191*FLEN/8, x13, x9, x10)

inst_11419:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34194*FLEN/8, x13, x9, x10)

inst_11420:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34197*FLEN/8, x13, x9, x10)

inst_11421:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34200*FLEN/8, x13, x9, x10)

inst_11422:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34203*FLEN/8, x13, x9, x10)

inst_11423:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34206*FLEN/8, x13, x9, x10)

inst_11424:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:34209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34209*FLEN/8, x13, x9, x10)

inst_11425:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:34212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34212*FLEN/8, x13, x9, x10)

inst_11426:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:34215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34215*FLEN/8, x13, x9, x10)

inst_11427:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:34218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34218*FLEN/8, x13, x9, x10)

inst_11428:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:34221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34221*FLEN/8, x13, x9, x10)

inst_11429:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34224*FLEN/8, x13, x9, x10)

inst_11430:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34227*FLEN/8, x13, x9, x10)

inst_11431:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34230*FLEN/8, x13, x9, x10)

inst_11432:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:34233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34233*FLEN/8, x13, x9, x10)

inst_11433:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:34236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34236*FLEN/8, x13, x9, x10)

inst_11434:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:34239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34239*FLEN/8, x13, x9, x10)

inst_11435:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:34242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34242*FLEN/8, x13, x9, x10)

inst_11436:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34245*FLEN/8, x13, x9, x10)

inst_11437:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34248*FLEN/8, x13, x9, x10)

inst_11438:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34251*FLEN/8, x13, x9, x10)

inst_11439:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:34254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34254*FLEN/8, x13, x9, x10)

inst_11440:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34257*FLEN/8, x13, x9, x10)

inst_11441:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34260*FLEN/8, x13, x9, x10)

inst_11442:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34263*FLEN/8, x13, x9, x10)

inst_11443:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34266*FLEN/8, x13, x9, x10)

inst_11444:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34269*FLEN/8, x13, x9, x10)

inst_11445:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34272*FLEN/8, x13, x9, x10)

inst_11446:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34275*FLEN/8, x13, x9, x10)

inst_11447:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34278*FLEN/8, x13, x9, x10)

inst_11448:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:34281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34281*FLEN/8, x13, x9, x10)

inst_11449:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:34284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34284*FLEN/8, x13, x9, x10)

inst_11450:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:34287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34287*FLEN/8, x13, x9, x10)

inst_11451:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:34290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34290*FLEN/8, x13, x9, x10)

inst_11452:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:34293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34293*FLEN/8, x13, x9, x10)

inst_11453:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34296*FLEN/8, x13, x9, x10)

inst_11454:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34299*FLEN/8, x13, x9, x10)

inst_11455:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34302*FLEN/8, x13, x9, x10)

inst_11456:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:34305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34305*FLEN/8, x13, x9, x10)

inst_11457:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:34308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34308*FLEN/8, x13, x9, x10)

inst_11458:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:34311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34311*FLEN/8, x13, x9, x10)

inst_11459:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:34314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34314*FLEN/8, x13, x9, x10)

inst_11460:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34317*FLEN/8, x13, x9, x10)

inst_11461:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34320*FLEN/8, x13, x9, x10)

inst_11462:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34323*FLEN/8, x13, x9, x10)

inst_11463:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:34326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34326*FLEN/8, x13, x9, x10)

inst_11464:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34329*FLEN/8, x13, x9, x10)

inst_11465:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34332*FLEN/8, x13, x9, x10)

inst_11466:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34335*FLEN/8, x13, x9, x10)

inst_11467:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34338*FLEN/8, x13, x9, x10)

inst_11468:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34341*FLEN/8, x13, x9, x10)

inst_11469:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34344*FLEN/8, x13, x9, x10)

inst_11470:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34347*FLEN/8, x13, x9, x10)

inst_11471:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34350*FLEN/8, x13, x9, x10)

inst_11472:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:34353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34353*FLEN/8, x13, x9, x10)

inst_11473:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:34356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34356*FLEN/8, x13, x9, x10)

inst_11474:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:34359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34359*FLEN/8, x13, x9, x10)

inst_11475:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:34362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34362*FLEN/8, x13, x9, x10)

inst_11476:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:34365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34365*FLEN/8, x13, x9, x10)

inst_11477:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34368*FLEN/8, x13, x9, x10)

inst_11478:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34371*FLEN/8, x13, x9, x10)

inst_11479:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34374*FLEN/8, x13, x9, x10)

inst_11480:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:34377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34377*FLEN/8, x13, x9, x10)

inst_11481:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:34380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34380*FLEN/8, x13, x9, x10)

inst_11482:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:34383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34383*FLEN/8, x13, x9, x10)

inst_11483:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:34386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34386*FLEN/8, x13, x9, x10)

inst_11484:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34389*FLEN/8, x13, x9, x10)

inst_11485:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34392*FLEN/8, x13, x9, x10)

inst_11486:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34395*FLEN/8, x13, x9, x10)

inst_11487:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:34398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34398*FLEN/8, x13, x9, x10)

inst_11488:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34401*FLEN/8, x13, x9, x10)

inst_11489:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34404*FLEN/8, x13, x9, x10)

inst_11490:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34407*FLEN/8, x13, x9, x10)

inst_11491:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34410*FLEN/8, x13, x9, x10)

inst_11492:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34413*FLEN/8, x13, x9, x10)

inst_11493:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34416*FLEN/8, x13, x9, x10)

inst_11494:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34419*FLEN/8, x13, x9, x10)

inst_11495:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34422*FLEN/8, x13, x9, x10)

inst_11496:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:34425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34425*FLEN/8, x13, x9, x10)

inst_11497:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:34428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34428*FLEN/8, x13, x9, x10)

inst_11498:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:34431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34431*FLEN/8, x13, x9, x10)

inst_11499:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:34434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34434*FLEN/8, x13, x9, x10)

inst_11500:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:34437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34437*FLEN/8, x13, x9, x10)

inst_11501:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34440*FLEN/8, x13, x9, x10)

inst_11502:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34443*FLEN/8, x13, x9, x10)

inst_11503:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34446*FLEN/8, x13, x9, x10)

inst_11504:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:34449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34449*FLEN/8, x13, x9, x10)

inst_11505:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:34452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34452*FLEN/8, x13, x9, x10)

inst_11506:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:34455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34455*FLEN/8, x13, x9, x10)

inst_11507:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:34458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34458*FLEN/8, x13, x9, x10)

inst_11508:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34461*FLEN/8, x13, x9, x10)

inst_11509:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34464*FLEN/8, x13, x9, x10)

inst_11510:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34467*FLEN/8, x13, x9, x10)

inst_11511:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:34470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34470*FLEN/8, x13, x9, x10)

inst_11512:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34473*FLEN/8, x13, x9, x10)

inst_11513:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34476*FLEN/8, x13, x9, x10)

inst_11514:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34479*FLEN/8, x13, x9, x10)

inst_11515:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34482*FLEN/8, x13, x9, x10)

inst_11516:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34485*FLEN/8, x13, x9, x10)

inst_11517:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34488*FLEN/8, x13, x9, x10)

inst_11518:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34491*FLEN/8, x13, x9, x10)

inst_11519:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34494*FLEN/8, x13, x9, x10)

inst_11520:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:34497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34497*FLEN/8, x13, x9, x10)

inst_11521:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:34500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34500*FLEN/8, x13, x9, x10)

inst_11522:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:34503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34503*FLEN/8, x13, x9, x10)

inst_11523:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:34506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34506*FLEN/8, x13, x9, x10)

inst_11524:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:34509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34509*FLEN/8, x13, x9, x10)

inst_11525:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34512*FLEN/8, x13, x9, x10)

inst_11526:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34515*FLEN/8, x13, x9, x10)

inst_11527:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34518*FLEN/8, x13, x9, x10)

inst_11528:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:34521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34521*FLEN/8, x13, x9, x10)

inst_11529:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:34524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34524*FLEN/8, x13, x9, x10)

inst_11530:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:34527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34527*FLEN/8, x13, x9, x10)

inst_11531:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:34530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34530*FLEN/8, x13, x9, x10)

inst_11532:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34533*FLEN/8, x13, x9, x10)

inst_11533:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34536*FLEN/8, x13, x9, x10)

inst_11534:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34539*FLEN/8, x13, x9, x10)

inst_11535:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:34542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34542*FLEN/8, x13, x9, x10)

inst_11536:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34545*FLEN/8, x13, x9, x10)

inst_11537:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34548*FLEN/8, x13, x9, x10)

inst_11538:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34551*FLEN/8, x13, x9, x10)

inst_11539:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34554*FLEN/8, x13, x9, x10)

inst_11540:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34557*FLEN/8, x13, x9, x10)

inst_11541:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34560*FLEN/8, x13, x9, x10)

inst_11542:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34563*FLEN/8, x13, x9, x10)

inst_11543:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34566*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_90)

inst_11544:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:34569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34569*FLEN/8, x13, x9, x10)

inst_11545:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:34572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34572*FLEN/8, x13, x9, x10)

inst_11546:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:34575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34575*FLEN/8, x13, x9, x10)

inst_11547:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:34578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34578*FLEN/8, x13, x9, x10)

inst_11548:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:34581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34581*FLEN/8, x13, x9, x10)

inst_11549:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34584*FLEN/8, x13, x9, x10)

inst_11550:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34587*FLEN/8, x13, x9, x10)

inst_11551:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34590*FLEN/8, x13, x9, x10)

inst_11552:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:34593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34593*FLEN/8, x13, x9, x10)

inst_11553:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:34596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34596*FLEN/8, x13, x9, x10)

inst_11554:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:34599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34599*FLEN/8, x13, x9, x10)

inst_11555:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:34602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34602*FLEN/8, x13, x9, x10)

inst_11556:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34605*FLEN/8, x13, x9, x10)

inst_11557:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34608*FLEN/8, x13, x9, x10)

inst_11558:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34611*FLEN/8, x13, x9, x10)

inst_11559:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:34614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34614*FLEN/8, x13, x9, x10)

inst_11560:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34617*FLEN/8, x13, x9, x10)

inst_11561:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34620*FLEN/8, x13, x9, x10)

inst_11562:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34623*FLEN/8, x13, x9, x10)

inst_11563:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34626*FLEN/8, x13, x9, x10)

inst_11564:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34629*FLEN/8, x13, x9, x10)

inst_11565:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34632*FLEN/8, x13, x9, x10)

inst_11566:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34635*FLEN/8, x13, x9, x10)

inst_11567:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34638*FLEN/8, x13, x9, x10)

inst_11568:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:34641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34641*FLEN/8, x13, x9, x10)

inst_11569:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:34644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34644*FLEN/8, x13, x9, x10)

inst_11570:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:34647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34647*FLEN/8, x13, x9, x10)

inst_11571:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:34650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34650*FLEN/8, x13, x9, x10)

inst_11572:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:34653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34653*FLEN/8, x13, x9, x10)

inst_11573:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34656*FLEN/8, x13, x9, x10)

inst_11574:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34659*FLEN/8, x13, x9, x10)

inst_11575:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34662*FLEN/8, x13, x9, x10)

inst_11576:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:34665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34665*FLEN/8, x13, x9, x10)

inst_11577:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:34668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34668*FLEN/8, x13, x9, x10)

inst_11578:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:34671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34671*FLEN/8, x13, x9, x10)

inst_11579:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:34674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34674*FLEN/8, x13, x9, x10)

inst_11580:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34677*FLEN/8, x13, x9, x10)

inst_11581:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34680*FLEN/8, x13, x9, x10)

inst_11582:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34683*FLEN/8, x13, x9, x10)

inst_11583:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:34686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34686*FLEN/8, x13, x9, x10)

inst_11584:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34689*FLEN/8, x13, x9, x10)

inst_11585:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34692*FLEN/8, x13, x9, x10)

inst_11586:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34695*FLEN/8, x13, x9, x10)

inst_11587:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34698*FLEN/8, x13, x9, x10)

inst_11588:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34701*FLEN/8, x13, x9, x10)

inst_11589:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34704*FLEN/8, x13, x9, x10)

inst_11590:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34707*FLEN/8, x13, x9, x10)

inst_11591:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34710*FLEN/8, x13, x9, x10)

inst_11592:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:34713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34713*FLEN/8, x13, x9, x10)

inst_11593:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:34716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34716*FLEN/8, x13, x9, x10)

inst_11594:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:34719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34719*FLEN/8, x13, x9, x10)

inst_11595:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:34722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34722*FLEN/8, x13, x9, x10)

inst_11596:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:34725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34725*FLEN/8, x13, x9, x10)

inst_11597:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34728*FLEN/8, x13, x9, x10)

inst_11598:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34731*FLEN/8, x13, x9, x10)

inst_11599:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34734*FLEN/8, x13, x9, x10)

inst_11600:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:34737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34737*FLEN/8, x13, x9, x10)

inst_11601:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:34740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34740*FLEN/8, x13, x9, x10)

inst_11602:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:34743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34743*FLEN/8, x13, x9, x10)

inst_11603:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:34746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34746*FLEN/8, x13, x9, x10)

inst_11604:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34749*FLEN/8, x13, x9, x10)

inst_11605:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34752*FLEN/8, x13, x9, x10)

inst_11606:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34755*FLEN/8, x13, x9, x10)

inst_11607:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:34758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34758*FLEN/8, x13, x9, x10)

inst_11608:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34761*FLEN/8, x13, x9, x10)

inst_11609:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34764*FLEN/8, x13, x9, x10)

inst_11610:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34767*FLEN/8, x13, x9, x10)

inst_11611:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34770*FLEN/8, x13, x9, x10)

inst_11612:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34773*FLEN/8, x13, x9, x10)

inst_11613:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34776*FLEN/8, x13, x9, x10)

inst_11614:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34779*FLEN/8, x13, x9, x10)

inst_11615:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34782*FLEN/8, x13, x9, x10)

inst_11616:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:34785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34785*FLEN/8, x13, x9, x10)

inst_11617:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:34788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34788*FLEN/8, x13, x9, x10)

inst_11618:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:34791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34791*FLEN/8, x13, x9, x10)

inst_11619:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:34794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34794*FLEN/8, x13, x9, x10)

inst_11620:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:34797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34797*FLEN/8, x13, x9, x10)

inst_11621:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34800*FLEN/8, x13, x9, x10)

inst_11622:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34803*FLEN/8, x13, x9, x10)

inst_11623:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34806*FLEN/8, x13, x9, x10)

inst_11624:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:34809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34809*FLEN/8, x13, x9, x10)

inst_11625:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:34812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34812*FLEN/8, x13, x9, x10)

inst_11626:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:34815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34815*FLEN/8, x13, x9, x10)

inst_11627:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:34818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34818*FLEN/8, x13, x9, x10)

inst_11628:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34821*FLEN/8, x13, x9, x10)

inst_11629:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34824*FLEN/8, x13, x9, x10)

inst_11630:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34827*FLEN/8, x13, x9, x10)

inst_11631:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:34830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34830*FLEN/8, x13, x9, x10)

inst_11632:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34833*FLEN/8, x13, x9, x10)

inst_11633:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34836*FLEN/8, x13, x9, x10)

inst_11634:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34839*FLEN/8, x13, x9, x10)

inst_11635:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34842*FLEN/8, x13, x9, x10)

inst_11636:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34845*FLEN/8, x13, x9, x10)

inst_11637:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34848*FLEN/8, x13, x9, x10)

inst_11638:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34851*FLEN/8, x13, x9, x10)

inst_11639:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34854*FLEN/8, x13, x9, x10)

inst_11640:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:34857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34857*FLEN/8, x13, x9, x10)

inst_11641:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:34860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34860*FLEN/8, x13, x9, x10)

inst_11642:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:34863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34863*FLEN/8, x13, x9, x10)

inst_11643:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:34866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34866*FLEN/8, x13, x9, x10)

inst_11644:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:34869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34869*FLEN/8, x13, x9, x10)

inst_11645:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34872*FLEN/8, x13, x9, x10)

inst_11646:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34875*FLEN/8, x13, x9, x10)

inst_11647:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34878*FLEN/8, x13, x9, x10)

inst_11648:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:34881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34881*FLEN/8, x13, x9, x10)

inst_11649:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:34884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34884*FLEN/8, x13, x9, x10)

inst_11650:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:34887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34887*FLEN/8, x13, x9, x10)

inst_11651:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:34890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34890*FLEN/8, x13, x9, x10)

inst_11652:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34893*FLEN/8, x13, x9, x10)

inst_11653:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34896*FLEN/8, x13, x9, x10)

inst_11654:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34899*FLEN/8, x13, x9, x10)

inst_11655:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:34902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34902*FLEN/8, x13, x9, x10)

inst_11656:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34905*FLEN/8, x13, x9, x10)

inst_11657:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34908*FLEN/8, x13, x9, x10)

inst_11658:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34911*FLEN/8, x13, x9, x10)

inst_11659:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34914*FLEN/8, x13, x9, x10)

inst_11660:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34917*FLEN/8, x13, x9, x10)

inst_11661:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34920*FLEN/8, x13, x9, x10)

inst_11662:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34923*FLEN/8, x13, x9, x10)

inst_11663:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34926*FLEN/8, x13, x9, x10)

inst_11664:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:34929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34929*FLEN/8, x13, x9, x10)

inst_11665:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:34932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34932*FLEN/8, x13, x9, x10)

inst_11666:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:34935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34935*FLEN/8, x13, x9, x10)

inst_11667:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:34938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34938*FLEN/8, x13, x9, x10)

inst_11668:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:34941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34941*FLEN/8, x13, x9, x10)

inst_11669:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:34944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34944*FLEN/8, x13, x9, x10)

inst_11670:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:34947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34947*FLEN/8, x13, x9, x10)

inst_11671:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:34950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34950*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_91)

inst_11672:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:34953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34953*FLEN/8, x13, x9, x10)

inst_11673:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:34956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34956*FLEN/8, x13, x9, x10)

inst_11674:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:34959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34959*FLEN/8, x13, x9, x10)

inst_11675:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:34962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34962*FLEN/8, x13, x9, x10)

inst_11676:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:34965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34965*FLEN/8, x13, x9, x10)

inst_11677:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:34968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34968*FLEN/8, x13, x9, x10)

inst_11678:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:34971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34971*FLEN/8, x13, x9, x10)

inst_11679:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:34974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34974*FLEN/8, x13, x9, x10)

inst_11680:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:34977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34977*FLEN/8, x13, x9, x10)

inst_11681:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:34980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34980*FLEN/8, x13, x9, x10)

inst_11682:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:34983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34983*FLEN/8, x13, x9, x10)

inst_11683:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:34986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34986*FLEN/8, x13, x9, x10)

inst_11684:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:34989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34989*FLEN/8, x13, x9, x10)

inst_11685:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:34992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34992*FLEN/8, x13, x9, x10)

inst_11686:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:34995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34995*FLEN/8, x13, x9, x10)

inst_11687:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:34998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 34998*FLEN/8, x13, x9, x10)

inst_11688:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:35001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35001*FLEN/8, x13, x9, x10)

inst_11689:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:35004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35004*FLEN/8, x13, x9, x10)

inst_11690:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:35007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35007*FLEN/8, x13, x9, x10)

inst_11691:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:35010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35010*FLEN/8, x13, x9, x10)

inst_11692:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:35013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35013*FLEN/8, x13, x9, x10)

inst_11693:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35016*FLEN/8, x13, x9, x10)

inst_11694:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35019*FLEN/8, x13, x9, x10)

inst_11695:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35022*FLEN/8, x13, x9, x10)

inst_11696:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:35025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35025*FLEN/8, x13, x9, x10)

inst_11697:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:35028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35028*FLEN/8, x13, x9, x10)

inst_11698:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:35031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35031*FLEN/8, x13, x9, x10)

inst_11699:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:35034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35034*FLEN/8, x13, x9, x10)

inst_11700:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35037*FLEN/8, x13, x9, x10)

inst_11701:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35040*FLEN/8, x13, x9, x10)

inst_11702:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35043*FLEN/8, x13, x9, x10)

inst_11703:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:35046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35046*FLEN/8, x13, x9, x10)

inst_11704:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35049*FLEN/8, x13, x9, x10)

inst_11705:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35052*FLEN/8, x13, x9, x10)

inst_11706:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35055*FLEN/8, x13, x9, x10)

inst_11707:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35058*FLEN/8, x13, x9, x10)

inst_11708:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35061*FLEN/8, x13, x9, x10)

inst_11709:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35064*FLEN/8, x13, x9, x10)

inst_11710:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35067*FLEN/8, x13, x9, x10)

inst_11711:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35070*FLEN/8, x13, x9, x10)

inst_11712:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:35073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35073*FLEN/8, x13, x9, x10)

inst_11713:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:35076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35076*FLEN/8, x13, x9, x10)

inst_11714:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:35079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35079*FLEN/8, x13, x9, x10)

inst_11715:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:35082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35082*FLEN/8, x13, x9, x10)

inst_11716:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:35085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35085*FLEN/8, x13, x9, x10)

inst_11717:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35088*FLEN/8, x13, x9, x10)

inst_11718:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35091*FLEN/8, x13, x9, x10)

inst_11719:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35094*FLEN/8, x13, x9, x10)

inst_11720:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:35097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35097*FLEN/8, x13, x9, x10)

inst_11721:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:35100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35100*FLEN/8, x13, x9, x10)

inst_11722:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:35103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35103*FLEN/8, x13, x9, x10)

inst_11723:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:35106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35106*FLEN/8, x13, x9, x10)

inst_11724:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35109*FLEN/8, x13, x9, x10)

inst_11725:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35112*FLEN/8, x13, x9, x10)

inst_11726:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35115*FLEN/8, x13, x9, x10)

inst_11727:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:35118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35118*FLEN/8, x13, x9, x10)

inst_11728:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35121*FLEN/8, x13, x9, x10)

inst_11729:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35124*FLEN/8, x13, x9, x10)

inst_11730:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35127*FLEN/8, x13, x9, x10)

inst_11731:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35130*FLEN/8, x13, x9, x10)

inst_11732:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35133*FLEN/8, x13, x9, x10)

inst_11733:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35136*FLEN/8, x13, x9, x10)

inst_11734:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35139*FLEN/8, x13, x9, x10)

inst_11735:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35142*FLEN/8, x13, x9, x10)

inst_11736:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:35145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35145*FLEN/8, x13, x9, x10)

inst_11737:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:35148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35148*FLEN/8, x13, x9, x10)

inst_11738:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:35151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35151*FLEN/8, x13, x9, x10)

inst_11739:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:35154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35154*FLEN/8, x13, x9, x10)

inst_11740:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:35157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35157*FLEN/8, x13, x9, x10)

inst_11741:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35160*FLEN/8, x13, x9, x10)

inst_11742:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35163*FLEN/8, x13, x9, x10)

inst_11743:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35166*FLEN/8, x13, x9, x10)

inst_11744:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:35169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35169*FLEN/8, x13, x9, x10)

inst_11745:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:35172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35172*FLEN/8, x13, x9, x10)

inst_11746:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:35175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35175*FLEN/8, x13, x9, x10)

inst_11747:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:35178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35178*FLEN/8, x13, x9, x10)

inst_11748:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35181*FLEN/8, x13, x9, x10)

inst_11749:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35184*FLEN/8, x13, x9, x10)

inst_11750:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35187*FLEN/8, x13, x9, x10)

inst_11751:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:35190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35190*FLEN/8, x13, x9, x10)

inst_11752:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35193*FLEN/8, x13, x9, x10)

inst_11753:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35196*FLEN/8, x13, x9, x10)

inst_11754:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35199*FLEN/8, x13, x9, x10)

inst_11755:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35202*FLEN/8, x13, x9, x10)

inst_11756:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35205*FLEN/8, x13, x9, x10)

inst_11757:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35208*FLEN/8, x13, x9, x10)

inst_11758:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35211*FLEN/8, x13, x9, x10)

inst_11759:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35214*FLEN/8, x13, x9, x10)

inst_11760:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:35217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35217*FLEN/8, x13, x9, x10)

inst_11761:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:35220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35220*FLEN/8, x13, x9, x10)

inst_11762:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:35223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35223*FLEN/8, x13, x9, x10)

inst_11763:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:35226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35226*FLEN/8, x13, x9, x10)

inst_11764:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:35229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35229*FLEN/8, x13, x9, x10)

inst_11765:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35232*FLEN/8, x13, x9, x10)

inst_11766:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35235*FLEN/8, x13, x9, x10)

inst_11767:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35238*FLEN/8, x13, x9, x10)

inst_11768:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:35241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35241*FLEN/8, x13, x9, x10)

inst_11769:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:35244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35244*FLEN/8, x13, x9, x10)

inst_11770:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:35247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35247*FLEN/8, x13, x9, x10)

inst_11771:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:35250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35250*FLEN/8, x13, x9, x10)

inst_11772:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35253*FLEN/8, x13, x9, x10)

inst_11773:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35256*FLEN/8, x13, x9, x10)

inst_11774:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35259*FLEN/8, x13, x9, x10)

inst_11775:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:35262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35262*FLEN/8, x13, x9, x10)

inst_11776:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35265*FLEN/8, x13, x9, x10)

inst_11777:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35268*FLEN/8, x13, x9, x10)

inst_11778:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35271*FLEN/8, x13, x9, x10)

inst_11779:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35274*FLEN/8, x13, x9, x10)

inst_11780:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35277*FLEN/8, x13, x9, x10)

inst_11781:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35280*FLEN/8, x13, x9, x10)

inst_11782:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35283*FLEN/8, x13, x9, x10)

inst_11783:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35286*FLEN/8, x13, x9, x10)

inst_11784:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:35289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35289*FLEN/8, x13, x9, x10)

inst_11785:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:35292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35292*FLEN/8, x13, x9, x10)

inst_11786:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:35295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35295*FLEN/8, x13, x9, x10)

inst_11787:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:35298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35298*FLEN/8, x13, x9, x10)

inst_11788:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:35301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35301*FLEN/8, x13, x9, x10)

inst_11789:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35304*FLEN/8, x13, x9, x10)

inst_11790:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35307*FLEN/8, x13, x9, x10)

inst_11791:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35310*FLEN/8, x13, x9, x10)

inst_11792:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:35313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35313*FLEN/8, x13, x9, x10)

inst_11793:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:35316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35316*FLEN/8, x13, x9, x10)

inst_11794:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:35319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35319*FLEN/8, x13, x9, x10)

inst_11795:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:35322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35322*FLEN/8, x13, x9, x10)

inst_11796:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35325*FLEN/8, x13, x9, x10)

inst_11797:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35328*FLEN/8, x13, x9, x10)

inst_11798:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35331*FLEN/8, x13, x9, x10)

inst_11799:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:35334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35334*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_92)

inst_11800:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35337*FLEN/8, x13, x9, x10)

inst_11801:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35340*FLEN/8, x13, x9, x10)

inst_11802:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35343*FLEN/8, x13, x9, x10)

inst_11803:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35346*FLEN/8, x13, x9, x10)

inst_11804:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35349*FLEN/8, x13, x9, x10)

inst_11805:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35352*FLEN/8, x13, x9, x10)

inst_11806:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35355*FLEN/8, x13, x9, x10)

inst_11807:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35358*FLEN/8, x13, x9, x10)

inst_11808:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:35361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35361*FLEN/8, x13, x9, x10)

inst_11809:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:35364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35364*FLEN/8, x13, x9, x10)

inst_11810:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:35367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35367*FLEN/8, x13, x9, x10)

inst_11811:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:35370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35370*FLEN/8, x13, x9, x10)

inst_11812:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:35373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35373*FLEN/8, x13, x9, x10)

inst_11813:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35376*FLEN/8, x13, x9, x10)

inst_11814:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35379*FLEN/8, x13, x9, x10)

inst_11815:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35382*FLEN/8, x13, x9, x10)

inst_11816:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:35385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35385*FLEN/8, x13, x9, x10)

inst_11817:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:35388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35388*FLEN/8, x13, x9, x10)

inst_11818:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:35391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35391*FLEN/8, x13, x9, x10)

inst_11819:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:35394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35394*FLEN/8, x13, x9, x10)

inst_11820:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35397*FLEN/8, x13, x9, x10)

inst_11821:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35400*FLEN/8, x13, x9, x10)

inst_11822:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35403*FLEN/8, x13, x9, x10)

inst_11823:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:35406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35406*FLEN/8, x13, x9, x10)

inst_11824:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35409*FLEN/8, x13, x9, x10)

inst_11825:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35412*FLEN/8, x13, x9, x10)

inst_11826:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35415*FLEN/8, x13, x9, x10)

inst_11827:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35418*FLEN/8, x13, x9, x10)

inst_11828:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35421*FLEN/8, x13, x9, x10)

inst_11829:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35424*FLEN/8, x13, x9, x10)

inst_11830:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35427*FLEN/8, x13, x9, x10)

inst_11831:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35430*FLEN/8, x13, x9, x10)

inst_11832:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:35433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35433*FLEN/8, x13, x9, x10)

inst_11833:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:35436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35436*FLEN/8, x13, x9, x10)

inst_11834:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:35439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35439*FLEN/8, x13, x9, x10)

inst_11835:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:35442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35442*FLEN/8, x13, x9, x10)

inst_11836:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:35445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35445*FLEN/8, x13, x9, x10)

inst_11837:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35448*FLEN/8, x13, x9, x10)

inst_11838:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35451*FLEN/8, x13, x9, x10)

inst_11839:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35454*FLEN/8, x13, x9, x10)

inst_11840:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:35457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35457*FLEN/8, x13, x9, x10)

inst_11841:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:35460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35460*FLEN/8, x13, x9, x10)

inst_11842:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:35463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35463*FLEN/8, x13, x9, x10)

inst_11843:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:35466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35466*FLEN/8, x13, x9, x10)

inst_11844:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35469*FLEN/8, x13, x9, x10)

inst_11845:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35472*FLEN/8, x13, x9, x10)

inst_11846:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35475*FLEN/8, x13, x9, x10)

inst_11847:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:35478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35478*FLEN/8, x13, x9, x10)

inst_11848:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35481*FLEN/8, x13, x9, x10)

inst_11849:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35484*FLEN/8, x13, x9, x10)

inst_11850:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35487*FLEN/8, x13, x9, x10)

inst_11851:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35490*FLEN/8, x13, x9, x10)

inst_11852:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35493*FLEN/8, x13, x9, x10)

inst_11853:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35496*FLEN/8, x13, x9, x10)

inst_11854:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35499*FLEN/8, x13, x9, x10)

inst_11855:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35502*FLEN/8, x13, x9, x10)

inst_11856:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:35505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35505*FLEN/8, x13, x9, x10)

inst_11857:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:35508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35508*FLEN/8, x13, x9, x10)

inst_11858:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:35511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35511*FLEN/8, x13, x9, x10)

inst_11859:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:35514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35514*FLEN/8, x13, x9, x10)

inst_11860:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:35517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35517*FLEN/8, x13, x9, x10)

inst_11861:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35520*FLEN/8, x13, x9, x10)

inst_11862:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35523*FLEN/8, x13, x9, x10)

inst_11863:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35526*FLEN/8, x13, x9, x10)

inst_11864:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:35529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35529*FLEN/8, x13, x9, x10)

inst_11865:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:35532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35532*FLEN/8, x13, x9, x10)

inst_11866:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:35535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35535*FLEN/8, x13, x9, x10)

inst_11867:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:35538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35538*FLEN/8, x13, x9, x10)

inst_11868:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35541*FLEN/8, x13, x9, x10)

inst_11869:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35544*FLEN/8, x13, x9, x10)

inst_11870:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35547*FLEN/8, x13, x9, x10)

inst_11871:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:35550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35550*FLEN/8, x13, x9, x10)

inst_11872:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35553*FLEN/8, x13, x9, x10)

inst_11873:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35556*FLEN/8, x13, x9, x10)

inst_11874:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35559*FLEN/8, x13, x9, x10)

inst_11875:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35562*FLEN/8, x13, x9, x10)

inst_11876:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35565*FLEN/8, x13, x9, x10)

inst_11877:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35568*FLEN/8, x13, x9, x10)

inst_11878:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35571*FLEN/8, x13, x9, x10)

inst_11879:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35574*FLEN/8, x13, x9, x10)

inst_11880:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:35577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35577*FLEN/8, x13, x9, x10)

inst_11881:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:35580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35580*FLEN/8, x13, x9, x10)

inst_11882:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:35583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35583*FLEN/8, x13, x9, x10)

inst_11883:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:35586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35586*FLEN/8, x13, x9, x10)

inst_11884:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:35589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35589*FLEN/8, x13, x9, x10)

inst_11885:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35592*FLEN/8, x13, x9, x10)

inst_11886:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35595*FLEN/8, x13, x9, x10)

inst_11887:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35598*FLEN/8, x13, x9, x10)

inst_11888:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:35601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35601*FLEN/8, x13, x9, x10)

inst_11889:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:35604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35604*FLEN/8, x13, x9, x10)

inst_11890:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:35607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35607*FLEN/8, x13, x9, x10)

inst_11891:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:35610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35610*FLEN/8, x13, x9, x10)

inst_11892:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35613*FLEN/8, x13, x9, x10)

inst_11893:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35616*FLEN/8, x13, x9, x10)

inst_11894:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35619*FLEN/8, x13, x9, x10)

inst_11895:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:35622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35622*FLEN/8, x13, x9, x10)

inst_11896:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35625*FLEN/8, x13, x9, x10)

inst_11897:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35628*FLEN/8, x13, x9, x10)

inst_11898:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35631*FLEN/8, x13, x9, x10)

inst_11899:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35634*FLEN/8, x13, x9, x10)

inst_11900:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35637*FLEN/8, x13, x9, x10)

inst_11901:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35640*FLEN/8, x13, x9, x10)

inst_11902:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35643*FLEN/8, x13, x9, x10)

inst_11903:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35646*FLEN/8, x13, x9, x10)

inst_11904:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:35649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35649*FLEN/8, x13, x9, x10)

inst_11905:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:35652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35652*FLEN/8, x13, x9, x10)

inst_11906:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:35655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35655*FLEN/8, x13, x9, x10)

inst_11907:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:35658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35658*FLEN/8, x13, x9, x10)

inst_11908:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:35661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35661*FLEN/8, x13, x9, x10)

inst_11909:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35664*FLEN/8, x13, x9, x10)

inst_11910:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35667*FLEN/8, x13, x9, x10)

inst_11911:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35670*FLEN/8, x13, x9, x10)

inst_11912:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:35673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35673*FLEN/8, x13, x9, x10)

inst_11913:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:35676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35676*FLEN/8, x13, x9, x10)

inst_11914:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:35679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35679*FLEN/8, x13, x9, x10)

inst_11915:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:35682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35682*FLEN/8, x13, x9, x10)

inst_11916:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35685*FLEN/8, x13, x9, x10)

inst_11917:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35688*FLEN/8, x13, x9, x10)

inst_11918:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35691*FLEN/8, x13, x9, x10)

inst_11919:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:35694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35694*FLEN/8, x13, x9, x10)

inst_11920:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35697*FLEN/8, x13, x9, x10)

inst_11921:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35700*FLEN/8, x13, x9, x10)

inst_11922:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35703*FLEN/8, x13, x9, x10)

inst_11923:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35706*FLEN/8, x13, x9, x10)

inst_11924:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35709*FLEN/8, x13, x9, x10)

inst_11925:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35712*FLEN/8, x13, x9, x10)

inst_11926:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35715*FLEN/8, x13, x9, x10)

inst_11927:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35718*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_93)

inst_11928:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:35721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35721*FLEN/8, x13, x9, x10)

inst_11929:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:35724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35724*FLEN/8, x13, x9, x10)

inst_11930:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:35727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35727*FLEN/8, x13, x9, x10)

inst_11931:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:35730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35730*FLEN/8, x13, x9, x10)

inst_11932:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:35733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35733*FLEN/8, x13, x9, x10)

inst_11933:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35736*FLEN/8, x13, x9, x10)

inst_11934:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35739*FLEN/8, x13, x9, x10)

inst_11935:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35742*FLEN/8, x13, x9, x10)

inst_11936:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:35745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35745*FLEN/8, x13, x9, x10)

inst_11937:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:35748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35748*FLEN/8, x13, x9, x10)

inst_11938:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:35751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35751*FLEN/8, x13, x9, x10)

inst_11939:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:35754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35754*FLEN/8, x13, x9, x10)

inst_11940:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35757*FLEN/8, x13, x9, x10)

inst_11941:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35760*FLEN/8, x13, x9, x10)

inst_11942:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35763*FLEN/8, x13, x9, x10)

inst_11943:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:35766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35766*FLEN/8, x13, x9, x10)

inst_11944:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35769*FLEN/8, x13, x9, x10)

inst_11945:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35772*FLEN/8, x13, x9, x10)

inst_11946:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35775*FLEN/8, x13, x9, x10)

inst_11947:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35778*FLEN/8, x13, x9, x10)

inst_11948:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35781*FLEN/8, x13, x9, x10)

inst_11949:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35784*FLEN/8, x13, x9, x10)

inst_11950:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35787*FLEN/8, x13, x9, x10)

inst_11951:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35790*FLEN/8, x13, x9, x10)

inst_11952:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:35793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35793*FLEN/8, x13, x9, x10)

inst_11953:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:35796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35796*FLEN/8, x13, x9, x10)

inst_11954:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:35799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35799*FLEN/8, x13, x9, x10)

inst_11955:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:35802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35802*FLEN/8, x13, x9, x10)

inst_11956:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:35805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35805*FLEN/8, x13, x9, x10)

inst_11957:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35808*FLEN/8, x13, x9, x10)

inst_11958:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35811*FLEN/8, x13, x9, x10)

inst_11959:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35814*FLEN/8, x13, x9, x10)

inst_11960:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:35817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35817*FLEN/8, x13, x9, x10)

inst_11961:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:35820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35820*FLEN/8, x13, x9, x10)

inst_11962:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:35823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35823*FLEN/8, x13, x9, x10)

inst_11963:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:35826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35826*FLEN/8, x13, x9, x10)

inst_11964:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35829*FLEN/8, x13, x9, x10)

inst_11965:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35832*FLEN/8, x13, x9, x10)

inst_11966:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35835*FLEN/8, x13, x9, x10)

inst_11967:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:35838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35838*FLEN/8, x13, x9, x10)

inst_11968:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35841*FLEN/8, x13, x9, x10)

inst_11969:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35844*FLEN/8, x13, x9, x10)

inst_11970:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35847*FLEN/8, x13, x9, x10)

inst_11971:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35850*FLEN/8, x13, x9, x10)

inst_11972:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35853*FLEN/8, x13, x9, x10)

inst_11973:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35856*FLEN/8, x13, x9, x10)

inst_11974:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35859*FLEN/8, x13, x9, x10)

inst_11975:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35862*FLEN/8, x13, x9, x10)

inst_11976:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:35865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35865*FLEN/8, x13, x9, x10)

inst_11977:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:35868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35868*FLEN/8, x13, x9, x10)

inst_11978:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:35871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35871*FLEN/8, x13, x9, x10)

inst_11979:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:35874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35874*FLEN/8, x13, x9, x10)

inst_11980:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:35877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35877*FLEN/8, x13, x9, x10)

inst_11981:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35880*FLEN/8, x13, x9, x10)

inst_11982:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35883*FLEN/8, x13, x9, x10)

inst_11983:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35886*FLEN/8, x13, x9, x10)

inst_11984:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:35889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35889*FLEN/8, x13, x9, x10)

inst_11985:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:35892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35892*FLEN/8, x13, x9, x10)

inst_11986:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:35895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35895*FLEN/8, x13, x9, x10)

inst_11987:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:35898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35898*FLEN/8, x13, x9, x10)

inst_11988:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35901*FLEN/8, x13, x9, x10)

inst_11989:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35904*FLEN/8, x13, x9, x10)

inst_11990:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35907*FLEN/8, x13, x9, x10)

inst_11991:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:35910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35910*FLEN/8, x13, x9, x10)

inst_11992:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35913*FLEN/8, x13, x9, x10)

inst_11993:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35916*FLEN/8, x13, x9, x10)

inst_11994:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35919*FLEN/8, x13, x9, x10)

inst_11995:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35922*FLEN/8, x13, x9, x10)

inst_11996:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35925*FLEN/8, x13, x9, x10)

inst_11997:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:35928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35928*FLEN/8, x13, x9, x10)

inst_11998:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:35931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35931*FLEN/8, x13, x9, x10)

inst_11999:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:35934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35934*FLEN/8, x13, x9, x10)

inst_12000:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:35937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35937*FLEN/8, x13, x9, x10)

inst_12001:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:35940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35940*FLEN/8, x13, x9, x10)

inst_12002:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:35943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35943*FLEN/8, x13, x9, x10)

inst_12003:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:35946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35946*FLEN/8, x13, x9, x10)

inst_12004:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:35949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35949*FLEN/8, x13, x9, x10)

inst_12005:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:35952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35952*FLEN/8, x13, x9, x10)

inst_12006:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:35955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35955*FLEN/8, x13, x9, x10)

inst_12007:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:35958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35958*FLEN/8, x13, x9, x10)

inst_12008:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:35961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35961*FLEN/8, x13, x9, x10)

inst_12009:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:35964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35964*FLEN/8, x13, x9, x10)

inst_12010:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:35967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35967*FLEN/8, x13, x9, x10)

inst_12011:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:35970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35970*FLEN/8, x13, x9, x10)

inst_12012:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:35973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35973*FLEN/8, x13, x9, x10)

inst_12013:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:35976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35976*FLEN/8, x13, x9, x10)

inst_12014:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:35979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35979*FLEN/8, x13, x9, x10)

inst_12015:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:35982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35982*FLEN/8, x13, x9, x10)

inst_12016:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:35985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35985*FLEN/8, x13, x9, x10)

inst_12017:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:35988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35988*FLEN/8, x13, x9, x10)

inst_12018:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:35991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35991*FLEN/8, x13, x9, x10)

inst_12019:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:35994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35994*FLEN/8, x13, x9, x10)

inst_12020:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:35997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 35997*FLEN/8, x13, x9, x10)

inst_12021:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36000*FLEN/8, x13, x9, x10)

inst_12022:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36003*FLEN/8, x13, x9, x10)

inst_12023:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36006*FLEN/8, x13, x9, x10)

inst_12024:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:36009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36009*FLEN/8, x13, x9, x10)

inst_12025:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:36012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36012*FLEN/8, x13, x9, x10)

inst_12026:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:36015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36015*FLEN/8, x13, x9, x10)

inst_12027:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:36018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36018*FLEN/8, x13, x9, x10)

inst_12028:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:36021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36021*FLEN/8, x13, x9, x10)

inst_12029:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36024*FLEN/8, x13, x9, x10)

inst_12030:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36027*FLEN/8, x13, x9, x10)

inst_12031:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36030*FLEN/8, x13, x9, x10)

inst_12032:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:36033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36033*FLEN/8, x13, x9, x10)

inst_12033:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:36036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36036*FLEN/8, x13, x9, x10)

inst_12034:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:36039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36039*FLEN/8, x13, x9, x10)

inst_12035:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:36042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36042*FLEN/8, x13, x9, x10)

inst_12036:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36045*FLEN/8, x13, x9, x10)

inst_12037:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36048*FLEN/8, x13, x9, x10)

inst_12038:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36051*FLEN/8, x13, x9, x10)

inst_12039:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:36054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36054*FLEN/8, x13, x9, x10)

inst_12040:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36057*FLEN/8, x13, x9, x10)

inst_12041:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36060*FLEN/8, x13, x9, x10)

inst_12042:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36063*FLEN/8, x13, x9, x10)

inst_12043:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36066*FLEN/8, x13, x9, x10)

inst_12044:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36069*FLEN/8, x13, x9, x10)

inst_12045:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36072*FLEN/8, x13, x9, x10)

inst_12046:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36075*FLEN/8, x13, x9, x10)

inst_12047:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36078*FLEN/8, x13, x9, x10)

inst_12048:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:36081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36081*FLEN/8, x13, x9, x10)

inst_12049:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:36084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36084*FLEN/8, x13, x9, x10)

inst_12050:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:36087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36087*FLEN/8, x13, x9, x10)

inst_12051:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:36090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36090*FLEN/8, x13, x9, x10)

inst_12052:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:36093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36093*FLEN/8, x13, x9, x10)

inst_12053:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36096*FLEN/8, x13, x9, x10)

inst_12054:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36099*FLEN/8, x13, x9, x10)

inst_12055:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36102*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_94)

inst_12056:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:36105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36105*FLEN/8, x13, x9, x10)

inst_12057:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:36108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36108*FLEN/8, x13, x9, x10)

inst_12058:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:36111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36111*FLEN/8, x13, x9, x10)

inst_12059:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:36114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36114*FLEN/8, x13, x9, x10)

inst_12060:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36117*FLEN/8, x13, x9, x10)

inst_12061:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36120*FLEN/8, x13, x9, x10)

inst_12062:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36123*FLEN/8, x13, x9, x10)

inst_12063:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:36126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36126*FLEN/8, x13, x9, x10)

inst_12064:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36129*FLEN/8, x13, x9, x10)

inst_12065:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36132*FLEN/8, x13, x9, x10)

inst_12066:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36135*FLEN/8, x13, x9, x10)

inst_12067:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36138*FLEN/8, x13, x9, x10)

inst_12068:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36141*FLEN/8, x13, x9, x10)

inst_12069:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36144*FLEN/8, x13, x9, x10)

inst_12070:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36147*FLEN/8, x13, x9, x10)

inst_12071:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36150*FLEN/8, x13, x9, x10)

inst_12072:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:36153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36153*FLEN/8, x13, x9, x10)

inst_12073:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:36156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36156*FLEN/8, x13, x9, x10)

inst_12074:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:36159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36159*FLEN/8, x13, x9, x10)

inst_12075:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:36162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36162*FLEN/8, x13, x9, x10)

inst_12076:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:36165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36165*FLEN/8, x13, x9, x10)

inst_12077:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36168*FLEN/8, x13, x9, x10)

inst_12078:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36171*FLEN/8, x13, x9, x10)

inst_12079:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36174*FLEN/8, x13, x9, x10)

inst_12080:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:36177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36177*FLEN/8, x13, x9, x10)

inst_12081:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:36180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36180*FLEN/8, x13, x9, x10)

inst_12082:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:36183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36183*FLEN/8, x13, x9, x10)

inst_12083:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:36186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36186*FLEN/8, x13, x9, x10)

inst_12084:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36189*FLEN/8, x13, x9, x10)

inst_12085:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36192*FLEN/8, x13, x9, x10)

inst_12086:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36195*FLEN/8, x13, x9, x10)

inst_12087:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:36198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36198*FLEN/8, x13, x9, x10)

inst_12088:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36201*FLEN/8, x13, x9, x10)

inst_12089:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36204*FLEN/8, x13, x9, x10)

inst_12090:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36207*FLEN/8, x13, x9, x10)

inst_12091:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36210*FLEN/8, x13, x9, x10)

inst_12092:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36213*FLEN/8, x13, x9, x10)

inst_12093:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36216*FLEN/8, x13, x9, x10)

inst_12094:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36219*FLEN/8, x13, x9, x10)

inst_12095:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36222*FLEN/8, x13, x9, x10)

inst_12096:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:36225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36225*FLEN/8, x13, x9, x10)

inst_12097:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:36228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36228*FLEN/8, x13, x9, x10)

inst_12098:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:36231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36231*FLEN/8, x13, x9, x10)

inst_12099:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:36234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36234*FLEN/8, x13, x9, x10)

inst_12100:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:36237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36237*FLEN/8, x13, x9, x10)

inst_12101:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36240*FLEN/8, x13, x9, x10)

inst_12102:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36243*FLEN/8, x13, x9, x10)

inst_12103:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36246*FLEN/8, x13, x9, x10)

inst_12104:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:36249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36249*FLEN/8, x13, x9, x10)

inst_12105:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:36252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36252*FLEN/8, x13, x9, x10)

inst_12106:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:36255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36255*FLEN/8, x13, x9, x10)

inst_12107:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:36258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36258*FLEN/8, x13, x9, x10)

inst_12108:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36261*FLEN/8, x13, x9, x10)

inst_12109:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36264*FLEN/8, x13, x9, x10)

inst_12110:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36267*FLEN/8, x13, x9, x10)

inst_12111:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:36270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36270*FLEN/8, x13, x9, x10)

inst_12112:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36273*FLEN/8, x13, x9, x10)

inst_12113:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36276*FLEN/8, x13, x9, x10)

inst_12114:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36279*FLEN/8, x13, x9, x10)

inst_12115:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36282*FLEN/8, x13, x9, x10)

inst_12116:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36285*FLEN/8, x13, x9, x10)

inst_12117:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36288*FLEN/8, x13, x9, x10)

inst_12118:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36291*FLEN/8, x13, x9, x10)

inst_12119:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36294*FLEN/8, x13, x9, x10)

inst_12120:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:36297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36297*FLEN/8, x13, x9, x10)

inst_12121:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:36300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36300*FLEN/8, x13, x9, x10)

inst_12122:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:36303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36303*FLEN/8, x13, x9, x10)

inst_12123:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:36306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36306*FLEN/8, x13, x9, x10)

inst_12124:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:36309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36309*FLEN/8, x13, x9, x10)

inst_12125:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36312*FLEN/8, x13, x9, x10)

inst_12126:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36315*FLEN/8, x13, x9, x10)

inst_12127:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36318*FLEN/8, x13, x9, x10)

inst_12128:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:36321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36321*FLEN/8, x13, x9, x10)

inst_12129:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:36324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36324*FLEN/8, x13, x9, x10)

inst_12130:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:36327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36327*FLEN/8, x13, x9, x10)

inst_12131:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:36330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36330*FLEN/8, x13, x9, x10)

inst_12132:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36333*FLEN/8, x13, x9, x10)

inst_12133:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36336*FLEN/8, x13, x9, x10)

inst_12134:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36339*FLEN/8, x13, x9, x10)

inst_12135:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:36342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36342*FLEN/8, x13, x9, x10)

inst_12136:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36345*FLEN/8, x13, x9, x10)

inst_12137:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36348*FLEN/8, x13, x9, x10)

inst_12138:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36351*FLEN/8, x13, x9, x10)

inst_12139:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36354*FLEN/8, x13, x9, x10)

inst_12140:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36357*FLEN/8, x13, x9, x10)

inst_12141:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36360*FLEN/8, x13, x9, x10)

inst_12142:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36363*FLEN/8, x13, x9, x10)

inst_12143:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36366*FLEN/8, x13, x9, x10)

inst_12144:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:36369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36369*FLEN/8, x13, x9, x10)

inst_12145:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:36372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36372*FLEN/8, x13, x9, x10)

inst_12146:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:36375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36375*FLEN/8, x13, x9, x10)

inst_12147:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:36378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36378*FLEN/8, x13, x9, x10)

inst_12148:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:36381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36381*FLEN/8, x13, x9, x10)

inst_12149:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36384*FLEN/8, x13, x9, x10)

inst_12150:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36387*FLEN/8, x13, x9, x10)

inst_12151:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36390*FLEN/8, x13, x9, x10)

inst_12152:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:36393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36393*FLEN/8, x13, x9, x10)

inst_12153:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:36396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36396*FLEN/8, x13, x9, x10)

inst_12154:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:36399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36399*FLEN/8, x13, x9, x10)

inst_12155:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:36402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36402*FLEN/8, x13, x9, x10)

inst_12156:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36405*FLEN/8, x13, x9, x10)

inst_12157:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36408*FLEN/8, x13, x9, x10)

inst_12158:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36411*FLEN/8, x13, x9, x10)

inst_12159:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:36414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36414*FLEN/8, x13, x9, x10)

inst_12160:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36417*FLEN/8, x13, x9, x10)

inst_12161:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36420*FLEN/8, x13, x9, x10)

inst_12162:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36423*FLEN/8, x13, x9, x10)

inst_12163:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36426*FLEN/8, x13, x9, x10)

inst_12164:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36429*FLEN/8, x13, x9, x10)

inst_12165:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36432*FLEN/8, x13, x9, x10)

inst_12166:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36435*FLEN/8, x13, x9, x10)

inst_12167:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36438*FLEN/8, x13, x9, x10)

inst_12168:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:36441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36441*FLEN/8, x13, x9, x10)

inst_12169:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:36444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36444*FLEN/8, x13, x9, x10)

inst_12170:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:36447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36447*FLEN/8, x13, x9, x10)

inst_12171:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:36450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36450*FLEN/8, x13, x9, x10)

inst_12172:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:36453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36453*FLEN/8, x13, x9, x10)

inst_12173:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36456*FLEN/8, x13, x9, x10)

inst_12174:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36459*FLEN/8, x13, x9, x10)

inst_12175:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36462*FLEN/8, x13, x9, x10)

inst_12176:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:36465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36465*FLEN/8, x13, x9, x10)

inst_12177:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:36468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36468*FLEN/8, x13, x9, x10)

inst_12178:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:36471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36471*FLEN/8, x13, x9, x10)

inst_12179:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:36474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36474*FLEN/8, x13, x9, x10)

inst_12180:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36477*FLEN/8, x13, x9, x10)

inst_12181:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36480*FLEN/8, x13, x9, x10)

inst_12182:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36483*FLEN/8, x13, x9, x10)

inst_12183:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:36486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36486*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_95)

inst_12184:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36489*FLEN/8, x13, x9, x10)

inst_12185:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36492*FLEN/8, x13, x9, x10)

inst_12186:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36495*FLEN/8, x13, x9, x10)

inst_12187:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36498*FLEN/8, x13, x9, x10)

inst_12188:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36501*FLEN/8, x13, x9, x10)

inst_12189:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36504*FLEN/8, x13, x9, x10)

inst_12190:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36507*FLEN/8, x13, x9, x10)

inst_12191:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36510*FLEN/8, x13, x9, x10)

inst_12192:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:36513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36513*FLEN/8, x13, x9, x10)

inst_12193:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:36516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36516*FLEN/8, x13, x9, x10)

inst_12194:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:36519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36519*FLEN/8, x13, x9, x10)

inst_12195:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:36522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36522*FLEN/8, x13, x9, x10)

inst_12196:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:36525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36525*FLEN/8, x13, x9, x10)

inst_12197:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36528*FLEN/8, x13, x9, x10)

inst_12198:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36531*FLEN/8, x13, x9, x10)

inst_12199:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36534*FLEN/8, x13, x9, x10)

inst_12200:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:36537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36537*FLEN/8, x13, x9, x10)

inst_12201:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:36540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36540*FLEN/8, x13, x9, x10)

inst_12202:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:36543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36543*FLEN/8, x13, x9, x10)

inst_12203:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:36546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36546*FLEN/8, x13, x9, x10)

inst_12204:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36549*FLEN/8, x13, x9, x10)

inst_12205:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36552*FLEN/8, x13, x9, x10)

inst_12206:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36555*FLEN/8, x13, x9, x10)

inst_12207:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:36558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36558*FLEN/8, x13, x9, x10)

inst_12208:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36561*FLEN/8, x13, x9, x10)

inst_12209:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36564*FLEN/8, x13, x9, x10)

inst_12210:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36567*FLEN/8, x13, x9, x10)

inst_12211:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36570*FLEN/8, x13, x9, x10)

inst_12212:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36573*FLEN/8, x13, x9, x10)

inst_12213:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36576*FLEN/8, x13, x9, x10)

inst_12214:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36579*FLEN/8, x13, x9, x10)

inst_12215:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36582*FLEN/8, x13, x9, x10)

inst_12216:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:36585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36585*FLEN/8, x13, x9, x10)

inst_12217:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:36588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36588*FLEN/8, x13, x9, x10)

inst_12218:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:36591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36591*FLEN/8, x13, x9, x10)

inst_12219:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:36594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36594*FLEN/8, x13, x9, x10)

inst_12220:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:36597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36597*FLEN/8, x13, x9, x10)

inst_12221:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36600*FLEN/8, x13, x9, x10)

inst_12222:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36603*FLEN/8, x13, x9, x10)

inst_12223:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36606*FLEN/8, x13, x9, x10)

inst_12224:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:36609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36609*FLEN/8, x13, x9, x10)

inst_12225:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:36612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36612*FLEN/8, x13, x9, x10)

inst_12226:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:36615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36615*FLEN/8, x13, x9, x10)

inst_12227:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:36618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36618*FLEN/8, x13, x9, x10)

inst_12228:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36621*FLEN/8, x13, x9, x10)

inst_12229:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36624*FLEN/8, x13, x9, x10)

inst_12230:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36627*FLEN/8, x13, x9, x10)

inst_12231:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:36630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36630*FLEN/8, x13, x9, x10)

inst_12232:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36633*FLEN/8, x13, x9, x10)

inst_12233:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36636*FLEN/8, x13, x9, x10)

inst_12234:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36639*FLEN/8, x13, x9, x10)

inst_12235:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36642*FLEN/8, x13, x9, x10)

inst_12236:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36645*FLEN/8, x13, x9, x10)

inst_12237:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36648*FLEN/8, x13, x9, x10)

inst_12238:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36651*FLEN/8, x13, x9, x10)

inst_12239:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36654*FLEN/8, x13, x9, x10)

inst_12240:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:36657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36657*FLEN/8, x13, x9, x10)

inst_12241:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:36660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36660*FLEN/8, x13, x9, x10)

inst_12242:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:36663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36663*FLEN/8, x13, x9, x10)

inst_12243:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:36666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36666*FLEN/8, x13, x9, x10)

inst_12244:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:36669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36669*FLEN/8, x13, x9, x10)

inst_12245:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36672*FLEN/8, x13, x9, x10)

inst_12246:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36675*FLEN/8, x13, x9, x10)

inst_12247:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36678*FLEN/8, x13, x9, x10)

inst_12248:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:36681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36681*FLEN/8, x13, x9, x10)

inst_12249:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:36684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36684*FLEN/8, x13, x9, x10)

inst_12250:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:36687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36687*FLEN/8, x13, x9, x10)

inst_12251:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:36690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36690*FLEN/8, x13, x9, x10)

inst_12252:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36693*FLEN/8, x13, x9, x10)

inst_12253:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36696*FLEN/8, x13, x9, x10)

inst_12254:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36699*FLEN/8, x13, x9, x10)

inst_12255:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:36702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36702*FLEN/8, x13, x9, x10)

inst_12256:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36705*FLEN/8, x13, x9, x10)

inst_12257:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36708*FLEN/8, x13, x9, x10)

inst_12258:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36711*FLEN/8, x13, x9, x10)

inst_12259:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36714*FLEN/8, x13, x9, x10)

inst_12260:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36717*FLEN/8, x13, x9, x10)

inst_12261:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36720*FLEN/8, x13, x9, x10)

inst_12262:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36723*FLEN/8, x13, x9, x10)

inst_12263:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36726*FLEN/8, x13, x9, x10)

inst_12264:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:36729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36729*FLEN/8, x13, x9, x10)

inst_12265:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:36732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36732*FLEN/8, x13, x9, x10)

inst_12266:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:36735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36735*FLEN/8, x13, x9, x10)

inst_12267:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:36738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36738*FLEN/8, x13, x9, x10)

inst_12268:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:36741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36741*FLEN/8, x13, x9, x10)

inst_12269:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36744*FLEN/8, x13, x9, x10)

inst_12270:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36747*FLEN/8, x13, x9, x10)

inst_12271:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36750*FLEN/8, x13, x9, x10)

inst_12272:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:36753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36753*FLEN/8, x13, x9, x10)

inst_12273:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:36756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36756*FLEN/8, x13, x9, x10)

inst_12274:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:36759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36759*FLEN/8, x13, x9, x10)

inst_12275:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:36762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36762*FLEN/8, x13, x9, x10)

inst_12276:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36765*FLEN/8, x13, x9, x10)

inst_12277:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36768*FLEN/8, x13, x9, x10)

inst_12278:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36771*FLEN/8, x13, x9, x10)

inst_12279:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:36774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36774*FLEN/8, x13, x9, x10)

inst_12280:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36777*FLEN/8, x13, x9, x10)

inst_12281:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36780*FLEN/8, x13, x9, x10)

inst_12282:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36783*FLEN/8, x13, x9, x10)

inst_12283:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36786*FLEN/8, x13, x9, x10)

inst_12284:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36789*FLEN/8, x13, x9, x10)

inst_12285:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36792*FLEN/8, x13, x9, x10)

inst_12286:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36795*FLEN/8, x13, x9, x10)

inst_12287:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36798*FLEN/8, x13, x9, x10)

inst_12288:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:36801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36801*FLEN/8, x13, x9, x10)

inst_12289:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:36804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36804*FLEN/8, x13, x9, x10)

inst_12290:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:36807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36807*FLEN/8, x13, x9, x10)

inst_12291:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:36810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36810*FLEN/8, x13, x9, x10)

inst_12292:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:36813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36813*FLEN/8, x13, x9, x10)

inst_12293:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36816*FLEN/8, x13, x9, x10)

inst_12294:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36819*FLEN/8, x13, x9, x10)

inst_12295:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36822*FLEN/8, x13, x9, x10)

inst_12296:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:36825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36825*FLEN/8, x13, x9, x10)

inst_12297:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:36828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36828*FLEN/8, x13, x9, x10)

inst_12298:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:36831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36831*FLEN/8, x13, x9, x10)

inst_12299:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:36834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36834*FLEN/8, x13, x9, x10)

inst_12300:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36837*FLEN/8, x13, x9, x10)

inst_12301:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36840*FLEN/8, x13, x9, x10)

inst_12302:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36843*FLEN/8, x13, x9, x10)

inst_12303:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:36846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36846*FLEN/8, x13, x9, x10)

inst_12304:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36849*FLEN/8, x13, x9, x10)

inst_12305:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36852*FLEN/8, x13, x9, x10)

inst_12306:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36855*FLEN/8, x13, x9, x10)

inst_12307:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36858*FLEN/8, x13, x9, x10)

inst_12308:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36861*FLEN/8, x13, x9, x10)

inst_12309:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36864*FLEN/8, x13, x9, x10)

inst_12310:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36867*FLEN/8, x13, x9, x10)

inst_12311:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36870*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_96)

inst_12312:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:36873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36873*FLEN/8, x13, x9, x10)

inst_12313:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:36876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36876*FLEN/8, x13, x9, x10)

inst_12314:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:36879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36879*FLEN/8, x13, x9, x10)

inst_12315:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:36882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36882*FLEN/8, x13, x9, x10)

inst_12316:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:36885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36885*FLEN/8, x13, x9, x10)

inst_12317:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36888*FLEN/8, x13, x9, x10)

inst_12318:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36891*FLEN/8, x13, x9, x10)

inst_12319:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36894*FLEN/8, x13, x9, x10)

inst_12320:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:36897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36897*FLEN/8, x13, x9, x10)

inst_12321:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:36900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36900*FLEN/8, x13, x9, x10)

inst_12322:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:36903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36903*FLEN/8, x13, x9, x10)

inst_12323:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:36906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36906*FLEN/8, x13, x9, x10)

inst_12324:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36909*FLEN/8, x13, x9, x10)

inst_12325:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36912*FLEN/8, x13, x9, x10)

inst_12326:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36915*FLEN/8, x13, x9, x10)

inst_12327:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:36918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36918*FLEN/8, x13, x9, x10)

inst_12328:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36921*FLEN/8, x13, x9, x10)

inst_12329:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36924*FLEN/8, x13, x9, x10)

inst_12330:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36927*FLEN/8, x13, x9, x10)

inst_12331:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:36930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36930*FLEN/8, x13, x9, x10)

inst_12332:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:36933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36933*FLEN/8, x13, x9, x10)

inst_12333:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:36936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36936*FLEN/8, x13, x9, x10)

inst_12334:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:36939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36939*FLEN/8, x13, x9, x10)

inst_12335:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:36942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36942*FLEN/8, x13, x9, x10)

inst_12336:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:36945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36945*FLEN/8, x13, x9, x10)

inst_12337:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:36948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36948*FLEN/8, x13, x9, x10)

inst_12338:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:36951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36951*FLEN/8, x13, x9, x10)

inst_12339:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:36954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36954*FLEN/8, x13, x9, x10)

inst_12340:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:36957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36957*FLEN/8, x13, x9, x10)

inst_12341:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:36960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36960*FLEN/8, x13, x9, x10)

inst_12342:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:36963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36963*FLEN/8, x13, x9, x10)

inst_12343:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:36966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36966*FLEN/8, x13, x9, x10)

inst_12344:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:36969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36969*FLEN/8, x13, x9, x10)

inst_12345:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:36972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36972*FLEN/8, x13, x9, x10)

inst_12346:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:36975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36975*FLEN/8, x13, x9, x10)

inst_12347:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:36978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36978*FLEN/8, x13, x9, x10)

inst_12348:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:36981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36981*FLEN/8, x13, x9, x10)

inst_12349:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:36984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36984*FLEN/8, x13, x9, x10)

inst_12350:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:36987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36987*FLEN/8, x13, x9, x10)

inst_12351:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:36990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36990*FLEN/8, x13, x9, x10)

inst_12352:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:36993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36993*FLEN/8, x13, x9, x10)

inst_12353:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:36996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36996*FLEN/8, x13, x9, x10)

inst_12354:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:36999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 36999*FLEN/8, x13, x9, x10)

inst_12355:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37002*FLEN/8, x13, x9, x10)

inst_12356:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37005*FLEN/8, x13, x9, x10)

inst_12357:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37008*FLEN/8, x13, x9, x10)

inst_12358:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37011*FLEN/8, x13, x9, x10)

inst_12359:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37014*FLEN/8, x13, x9, x10)

inst_12360:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:37017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37017*FLEN/8, x13, x9, x10)

inst_12361:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:37020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37020*FLEN/8, x13, x9, x10)

inst_12362:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:37023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37023*FLEN/8, x13, x9, x10)

inst_12363:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:37026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37026*FLEN/8, x13, x9, x10)

inst_12364:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:37029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37029*FLEN/8, x13, x9, x10)

inst_12365:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37032*FLEN/8, x13, x9, x10)

inst_12366:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37035*FLEN/8, x13, x9, x10)

inst_12367:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37038*FLEN/8, x13, x9, x10)

inst_12368:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:37041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37041*FLEN/8, x13, x9, x10)

inst_12369:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:37044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37044*FLEN/8, x13, x9, x10)

inst_12370:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:37047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37047*FLEN/8, x13, x9, x10)

inst_12371:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:37050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37050*FLEN/8, x13, x9, x10)

inst_12372:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37053*FLEN/8, x13, x9, x10)

inst_12373:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37056*FLEN/8, x13, x9, x10)

inst_12374:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37059*FLEN/8, x13, x9, x10)

inst_12375:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:37062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37062*FLEN/8, x13, x9, x10)

inst_12376:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37065*FLEN/8, x13, x9, x10)

inst_12377:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37068*FLEN/8, x13, x9, x10)

inst_12378:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37071*FLEN/8, x13, x9, x10)

inst_12379:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37074*FLEN/8, x13, x9, x10)

inst_12380:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37077*FLEN/8, x13, x9, x10)

inst_12381:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37080*FLEN/8, x13, x9, x10)

inst_12382:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37083*FLEN/8, x13, x9, x10)

inst_12383:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37086*FLEN/8, x13, x9, x10)

inst_12384:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:37089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37089*FLEN/8, x13, x9, x10)

inst_12385:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:37092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37092*FLEN/8, x13, x9, x10)

inst_12386:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:37095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37095*FLEN/8, x13, x9, x10)

inst_12387:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:37098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37098*FLEN/8, x13, x9, x10)

inst_12388:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:37101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37101*FLEN/8, x13, x9, x10)

inst_12389:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37104*FLEN/8, x13, x9, x10)

inst_12390:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37107*FLEN/8, x13, x9, x10)

inst_12391:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37110*FLEN/8, x13, x9, x10)

inst_12392:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:37113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37113*FLEN/8, x13, x9, x10)

inst_12393:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:37116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37116*FLEN/8, x13, x9, x10)

inst_12394:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:37119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37119*FLEN/8, x13, x9, x10)

inst_12395:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:37122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37122*FLEN/8, x13, x9, x10)

inst_12396:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37125*FLEN/8, x13, x9, x10)

inst_12397:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37128*FLEN/8, x13, x9, x10)

inst_12398:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37131*FLEN/8, x13, x9, x10)

inst_12399:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:37134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37134*FLEN/8, x13, x9, x10)

inst_12400:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37137*FLEN/8, x13, x9, x10)

inst_12401:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37140*FLEN/8, x13, x9, x10)

inst_12402:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37143*FLEN/8, x13, x9, x10)

inst_12403:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37146*FLEN/8, x13, x9, x10)

inst_12404:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37149*FLEN/8, x13, x9, x10)

inst_12405:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37152*FLEN/8, x13, x9, x10)

inst_12406:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37155*FLEN/8, x13, x9, x10)

inst_12407:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37158*FLEN/8, x13, x9, x10)

inst_12408:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:37161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37161*FLEN/8, x13, x9, x10)

inst_12409:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:37164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37164*FLEN/8, x13, x9, x10)

inst_12410:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:37167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37167*FLEN/8, x13, x9, x10)

inst_12411:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:37170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37170*FLEN/8, x13, x9, x10)

inst_12412:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:37173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37173*FLEN/8, x13, x9, x10)

inst_12413:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37176*FLEN/8, x13, x9, x10)

inst_12414:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37179*FLEN/8, x13, x9, x10)

inst_12415:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37182*FLEN/8, x13, x9, x10)

inst_12416:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:37185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37185*FLEN/8, x13, x9, x10)

inst_12417:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:37188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37188*FLEN/8, x13, x9, x10)

inst_12418:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:37191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37191*FLEN/8, x13, x9, x10)

inst_12419:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:37194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37194*FLEN/8, x13, x9, x10)

inst_12420:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37197*FLEN/8, x13, x9, x10)

inst_12421:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37200*FLEN/8, x13, x9, x10)

inst_12422:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37203*FLEN/8, x13, x9, x10)

inst_12423:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:37206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37206*FLEN/8, x13, x9, x10)

inst_12424:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37209*FLEN/8, x13, x9, x10)

inst_12425:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37212*FLEN/8, x13, x9, x10)

inst_12426:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37215*FLEN/8, x13, x9, x10)

inst_12427:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37218*FLEN/8, x13, x9, x10)

inst_12428:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37221*FLEN/8, x13, x9, x10)

inst_12429:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37224*FLEN/8, x13, x9, x10)

inst_12430:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37227*FLEN/8, x13, x9, x10)

inst_12431:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37230*FLEN/8, x13, x9, x10)

inst_12432:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:37233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37233*FLEN/8, x13, x9, x10)

inst_12433:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:37236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37236*FLEN/8, x13, x9, x10)

inst_12434:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:37239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37239*FLEN/8, x13, x9, x10)

inst_12435:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:37242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37242*FLEN/8, x13, x9, x10)

inst_12436:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:37245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37245*FLEN/8, x13, x9, x10)

inst_12437:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37248*FLEN/8, x13, x9, x10)

inst_12438:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37251*FLEN/8, x13, x9, x10)

inst_12439:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37254*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_97)

inst_12440:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:37257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37257*FLEN/8, x13, x9, x10)

inst_12441:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:37260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37260*FLEN/8, x13, x9, x10)

inst_12442:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:37263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37263*FLEN/8, x13, x9, x10)

inst_12443:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:37266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37266*FLEN/8, x13, x9, x10)

inst_12444:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37269*FLEN/8, x13, x9, x10)

inst_12445:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37272*FLEN/8, x13, x9, x10)

inst_12446:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37275*FLEN/8, x13, x9, x10)

inst_12447:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:37278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37278*FLEN/8, x13, x9, x10)

inst_12448:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37281*FLEN/8, x13, x9, x10)

inst_12449:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37284*FLEN/8, x13, x9, x10)

inst_12450:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37287*FLEN/8, x13, x9, x10)

inst_12451:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37290*FLEN/8, x13, x9, x10)

inst_12452:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37293*FLEN/8, x13, x9, x10)

inst_12453:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37296*FLEN/8, x13, x9, x10)

inst_12454:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37299*FLEN/8, x13, x9, x10)

inst_12455:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37302*FLEN/8, x13, x9, x10)

inst_12456:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:37305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37305*FLEN/8, x13, x9, x10)

inst_12457:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:37308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37308*FLEN/8, x13, x9, x10)

inst_12458:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:37311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37311*FLEN/8, x13, x9, x10)

inst_12459:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:37314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37314*FLEN/8, x13, x9, x10)

inst_12460:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:37317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37317*FLEN/8, x13, x9, x10)

inst_12461:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37320*FLEN/8, x13, x9, x10)

inst_12462:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37323*FLEN/8, x13, x9, x10)

inst_12463:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37326*FLEN/8, x13, x9, x10)

inst_12464:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:37329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37329*FLEN/8, x13, x9, x10)

inst_12465:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:37332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37332*FLEN/8, x13, x9, x10)

inst_12466:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:37335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37335*FLEN/8, x13, x9, x10)

inst_12467:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:37338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37338*FLEN/8, x13, x9, x10)

inst_12468:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37341*FLEN/8, x13, x9, x10)

inst_12469:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37344*FLEN/8, x13, x9, x10)

inst_12470:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37347*FLEN/8, x13, x9, x10)

inst_12471:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:37350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37350*FLEN/8, x13, x9, x10)

inst_12472:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37353*FLEN/8, x13, x9, x10)

inst_12473:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37356*FLEN/8, x13, x9, x10)

inst_12474:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37359*FLEN/8, x13, x9, x10)

inst_12475:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37362*FLEN/8, x13, x9, x10)

inst_12476:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37365*FLEN/8, x13, x9, x10)

inst_12477:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37368*FLEN/8, x13, x9, x10)

inst_12478:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37371*FLEN/8, x13, x9, x10)

inst_12479:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37374*FLEN/8, x13, x9, x10)

inst_12480:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:37377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37377*FLEN/8, x13, x9, x10)

inst_12481:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:37380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37380*FLEN/8, x13, x9, x10)

inst_12482:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:37383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37383*FLEN/8, x13, x9, x10)

inst_12483:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:37386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37386*FLEN/8, x13, x9, x10)

inst_12484:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:37389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37389*FLEN/8, x13, x9, x10)

inst_12485:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37392*FLEN/8, x13, x9, x10)

inst_12486:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37395*FLEN/8, x13, x9, x10)

inst_12487:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37398*FLEN/8, x13, x9, x10)

inst_12488:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:37401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37401*FLEN/8, x13, x9, x10)

inst_12489:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:37404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37404*FLEN/8, x13, x9, x10)

inst_12490:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:37407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37407*FLEN/8, x13, x9, x10)

inst_12491:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:37410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37410*FLEN/8, x13, x9, x10)

inst_12492:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37413*FLEN/8, x13, x9, x10)

inst_12493:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37416*FLEN/8, x13, x9, x10)

inst_12494:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37419*FLEN/8, x13, x9, x10)

inst_12495:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:37422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37422*FLEN/8, x13, x9, x10)

inst_12496:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37425*FLEN/8, x13, x9, x10)

inst_12497:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37428*FLEN/8, x13, x9, x10)

inst_12498:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37431*FLEN/8, x13, x9, x10)

inst_12499:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37434*FLEN/8, x13, x9, x10)

inst_12500:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37437*FLEN/8, x13, x9, x10)

inst_12501:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37440*FLEN/8, x13, x9, x10)

inst_12502:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37443*FLEN/8, x13, x9, x10)

inst_12503:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37446*FLEN/8, x13, x9, x10)

inst_12504:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:37449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37449*FLEN/8, x13, x9, x10)

inst_12505:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:37452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37452*FLEN/8, x13, x9, x10)

inst_12506:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:37455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37455*FLEN/8, x13, x9, x10)

inst_12507:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:37458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37458*FLEN/8, x13, x9, x10)

inst_12508:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:37461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37461*FLEN/8, x13, x9, x10)

inst_12509:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37464*FLEN/8, x13, x9, x10)

inst_12510:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37467*FLEN/8, x13, x9, x10)

inst_12511:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37470*FLEN/8, x13, x9, x10)

inst_12512:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:37473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37473*FLEN/8, x13, x9, x10)

inst_12513:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:37476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37476*FLEN/8, x13, x9, x10)

inst_12514:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:37479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37479*FLEN/8, x13, x9, x10)

inst_12515:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:37482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37482*FLEN/8, x13, x9, x10)

inst_12516:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37485*FLEN/8, x13, x9, x10)

inst_12517:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37488*FLEN/8, x13, x9, x10)

inst_12518:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37491*FLEN/8, x13, x9, x10)

inst_12519:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:37494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37494*FLEN/8, x13, x9, x10)

inst_12520:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37497*FLEN/8, x13, x9, x10)

inst_12521:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37500*FLEN/8, x13, x9, x10)

inst_12522:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37503*FLEN/8, x13, x9, x10)

inst_12523:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37506*FLEN/8, x13, x9, x10)

inst_12524:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37509*FLEN/8, x13, x9, x10)

inst_12525:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37512*FLEN/8, x13, x9, x10)

inst_12526:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37515*FLEN/8, x13, x9, x10)

inst_12527:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37518*FLEN/8, x13, x9, x10)

inst_12528:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:37521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37521*FLEN/8, x13, x9, x10)

inst_12529:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:37524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37524*FLEN/8, x13, x9, x10)

inst_12530:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:37527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37527*FLEN/8, x13, x9, x10)

inst_12531:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:37530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37530*FLEN/8, x13, x9, x10)

inst_12532:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:37533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37533*FLEN/8, x13, x9, x10)

inst_12533:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37536*FLEN/8, x13, x9, x10)

inst_12534:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37539*FLEN/8, x13, x9, x10)

inst_12535:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37542*FLEN/8, x13, x9, x10)

inst_12536:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:37545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37545*FLEN/8, x13, x9, x10)

inst_12537:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:37548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37548*FLEN/8, x13, x9, x10)

inst_12538:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:37551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37551*FLEN/8, x13, x9, x10)

inst_12539:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:37554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37554*FLEN/8, x13, x9, x10)

inst_12540:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37557*FLEN/8, x13, x9, x10)

inst_12541:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37560*FLEN/8, x13, x9, x10)

inst_12542:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37563*FLEN/8, x13, x9, x10)

inst_12543:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:37566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37566*FLEN/8, x13, x9, x10)

inst_12544:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37569*FLEN/8, x13, x9, x10)

inst_12545:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37572*FLEN/8, x13, x9, x10)

inst_12546:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37575*FLEN/8, x13, x9, x10)

inst_12547:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37578*FLEN/8, x13, x9, x10)

inst_12548:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37581*FLEN/8, x13, x9, x10)

inst_12549:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37584*FLEN/8, x13, x9, x10)

inst_12550:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37587*FLEN/8, x13, x9, x10)

inst_12551:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37590*FLEN/8, x13, x9, x10)

inst_12552:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:37593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37593*FLEN/8, x13, x9, x10)

inst_12553:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:37596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37596*FLEN/8, x13, x9, x10)

inst_12554:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:37599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37599*FLEN/8, x13, x9, x10)

inst_12555:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:37602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37602*FLEN/8, x13, x9, x10)

inst_12556:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:37605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37605*FLEN/8, x13, x9, x10)

inst_12557:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37608*FLEN/8, x13, x9, x10)

inst_12558:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37611*FLEN/8, x13, x9, x10)

inst_12559:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37614*FLEN/8, x13, x9, x10)

inst_12560:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:37617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37617*FLEN/8, x13, x9, x10)

inst_12561:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:37620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37620*FLEN/8, x13, x9, x10)

inst_12562:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:37623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37623*FLEN/8, x13, x9, x10)

inst_12563:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:37626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37626*FLEN/8, x13, x9, x10)

inst_12564:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37629*FLEN/8, x13, x9, x10)

inst_12565:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37632*FLEN/8, x13, x9, x10)

inst_12566:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37635*FLEN/8, x13, x9, x10)

inst_12567:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:37638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37638*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_98)

inst_12568:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37641*FLEN/8, x13, x9, x10)

inst_12569:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37644*FLEN/8, x13, x9, x10)

inst_12570:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37647*FLEN/8, x13, x9, x10)

inst_12571:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37650*FLEN/8, x13, x9, x10)

inst_12572:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37653*FLEN/8, x13, x9, x10)

inst_12573:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37656*FLEN/8, x13, x9, x10)

inst_12574:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37659*FLEN/8, x13, x9, x10)

inst_12575:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37662*FLEN/8, x13, x9, x10)

inst_12576:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:37665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37665*FLEN/8, x13, x9, x10)

inst_12577:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:37668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37668*FLEN/8, x13, x9, x10)

inst_12578:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:37671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37671*FLEN/8, x13, x9, x10)

inst_12579:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:37674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37674*FLEN/8, x13, x9, x10)

inst_12580:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:37677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37677*FLEN/8, x13, x9, x10)

inst_12581:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37680*FLEN/8, x13, x9, x10)

inst_12582:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37683*FLEN/8, x13, x9, x10)

inst_12583:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37686*FLEN/8, x13, x9, x10)

inst_12584:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:37689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37689*FLEN/8, x13, x9, x10)

inst_12585:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:37692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37692*FLEN/8, x13, x9, x10)

inst_12586:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:37695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37695*FLEN/8, x13, x9, x10)

inst_12587:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:37698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37698*FLEN/8, x13, x9, x10)

inst_12588:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37701*FLEN/8, x13, x9, x10)

inst_12589:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37704*FLEN/8, x13, x9, x10)

inst_12590:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37707*FLEN/8, x13, x9, x10)

inst_12591:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:37710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37710*FLEN/8, x13, x9, x10)

inst_12592:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37713*FLEN/8, x13, x9, x10)

inst_12593:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37716*FLEN/8, x13, x9, x10)

inst_12594:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37719*FLEN/8, x13, x9, x10)

inst_12595:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37722*FLEN/8, x13, x9, x10)

inst_12596:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37725*FLEN/8, x13, x9, x10)

inst_12597:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37728*FLEN/8, x13, x9, x10)

inst_12598:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37731*FLEN/8, x13, x9, x10)

inst_12599:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37734*FLEN/8, x13, x9, x10)

inst_12600:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:37737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37737*FLEN/8, x13, x9, x10)

inst_12601:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:37740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37740*FLEN/8, x13, x9, x10)

inst_12602:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:37743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37743*FLEN/8, x13, x9, x10)

inst_12603:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:37746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37746*FLEN/8, x13, x9, x10)

inst_12604:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:37749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37749*FLEN/8, x13, x9, x10)

inst_12605:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37752*FLEN/8, x13, x9, x10)

inst_12606:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37755*FLEN/8, x13, x9, x10)

inst_12607:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37758*FLEN/8, x13, x9, x10)

inst_12608:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:37761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37761*FLEN/8, x13, x9, x10)

inst_12609:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:37764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37764*FLEN/8, x13, x9, x10)

inst_12610:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:37767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37767*FLEN/8, x13, x9, x10)

inst_12611:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:37770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37770*FLEN/8, x13, x9, x10)

inst_12612:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37773*FLEN/8, x13, x9, x10)

inst_12613:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37776*FLEN/8, x13, x9, x10)

inst_12614:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37779*FLEN/8, x13, x9, x10)

inst_12615:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:37782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37782*FLEN/8, x13, x9, x10)

inst_12616:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37785*FLEN/8, x13, x9, x10)

inst_12617:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37788*FLEN/8, x13, x9, x10)

inst_12618:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37791*FLEN/8, x13, x9, x10)

inst_12619:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37794*FLEN/8, x13, x9, x10)

inst_12620:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37797*FLEN/8, x13, x9, x10)

inst_12621:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37800*FLEN/8, x13, x9, x10)

inst_12622:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37803*FLEN/8, x13, x9, x10)

inst_12623:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37806*FLEN/8, x13, x9, x10)

inst_12624:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:37809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37809*FLEN/8, x13, x9, x10)

inst_12625:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:37812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37812*FLEN/8, x13, x9, x10)

inst_12626:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:37815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37815*FLEN/8, x13, x9, x10)

inst_12627:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:37818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37818*FLEN/8, x13, x9, x10)

inst_12628:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:37821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37821*FLEN/8, x13, x9, x10)

inst_12629:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37824*FLEN/8, x13, x9, x10)

inst_12630:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37827*FLEN/8, x13, x9, x10)

inst_12631:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37830*FLEN/8, x13, x9, x10)

inst_12632:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:37833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37833*FLEN/8, x13, x9, x10)

inst_12633:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:37836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37836*FLEN/8, x13, x9, x10)

inst_12634:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:37839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37839*FLEN/8, x13, x9, x10)

inst_12635:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:37842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37842*FLEN/8, x13, x9, x10)

inst_12636:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37845*FLEN/8, x13, x9, x10)

inst_12637:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37848*FLEN/8, x13, x9, x10)

inst_12638:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37851*FLEN/8, x13, x9, x10)

inst_12639:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:37854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37854*FLEN/8, x13, x9, x10)

inst_12640:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37857*FLEN/8, x13, x9, x10)

inst_12641:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37860*FLEN/8, x13, x9, x10)

inst_12642:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37863*FLEN/8, x13, x9, x10)

inst_12643:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37866*FLEN/8, x13, x9, x10)

inst_12644:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37869*FLEN/8, x13, x9, x10)

inst_12645:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37872*FLEN/8, x13, x9, x10)

inst_12646:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37875*FLEN/8, x13, x9, x10)

inst_12647:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37878*FLEN/8, x13, x9, x10)

inst_12648:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:37881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37881*FLEN/8, x13, x9, x10)

inst_12649:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:37884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37884*FLEN/8, x13, x9, x10)

inst_12650:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:37887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37887*FLEN/8, x13, x9, x10)

inst_12651:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:37890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37890*FLEN/8, x13, x9, x10)

inst_12652:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:37893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37893*FLEN/8, x13, x9, x10)

inst_12653:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37896*FLEN/8, x13, x9, x10)

inst_12654:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37899*FLEN/8, x13, x9, x10)

inst_12655:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37902*FLEN/8, x13, x9, x10)

inst_12656:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:37905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37905*FLEN/8, x13, x9, x10)

inst_12657:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:37908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37908*FLEN/8, x13, x9, x10)

inst_12658:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:37911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37911*FLEN/8, x13, x9, x10)

inst_12659:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:37914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37914*FLEN/8, x13, x9, x10)

inst_12660:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37917*FLEN/8, x13, x9, x10)

inst_12661:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37920*FLEN/8, x13, x9, x10)

inst_12662:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37923*FLEN/8, x13, x9, x10)

inst_12663:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:37926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37926*FLEN/8, x13, x9, x10)

inst_12664:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:37929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37929*FLEN/8, x13, x9, x10)

inst_12665:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:37932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37932*FLEN/8, x13, x9, x10)

inst_12666:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:37935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37935*FLEN/8, x13, x9, x10)

inst_12667:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:37938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37938*FLEN/8, x13, x9, x10)

inst_12668:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:37941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37941*FLEN/8, x13, x9, x10)

inst_12669:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:37944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37944*FLEN/8, x13, x9, x10)

inst_12670:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:37947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37947*FLEN/8, x13, x9, x10)

inst_12671:
// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:37950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37950*FLEN/8, x13, x9, x10)

inst_12672:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:37953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37953*FLEN/8, x13, x9, x10)

inst_12673:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:37956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37956*FLEN/8, x13, x9, x10)

inst_12674:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:37959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37959*FLEN/8, x13, x9, x10)

inst_12675:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:37962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37962*FLEN/8, x13, x9, x10)

inst_12676:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:37965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37965*FLEN/8, x13, x9, x10)

inst_12677:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:37968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37968*FLEN/8, x13, x9, x10)

inst_12678:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:37971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37971*FLEN/8, x13, x9, x10)

inst_12679:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:37974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37974*FLEN/8, x13, x9, x10)

inst_12680:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:37977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37977*FLEN/8, x13, x9, x10)

inst_12681:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:37980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37980*FLEN/8, x13, x9, x10)

inst_12682:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:37983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37983*FLEN/8, x13, x9, x10)

inst_12683:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:37986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37986*FLEN/8, x13, x9, x10)

inst_12684:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:37989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37989*FLEN/8, x13, x9, x10)

inst_12685:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:37992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37992*FLEN/8, x13, x9, x10)

inst_12686:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:37995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37995*FLEN/8, x13, x9, x10)

inst_12687:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:37998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 37998*FLEN/8, x13, x9, x10)

inst_12688:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38001*FLEN/8, x13, x9, x10)

inst_12689:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38004*FLEN/8, x13, x9, x10)

inst_12690:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38007*FLEN/8, x13, x9, x10)

inst_12691:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38010*FLEN/8, x13, x9, x10)

inst_12692:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38013*FLEN/8, x13, x9, x10)

inst_12693:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38016*FLEN/8, x13, x9, x10)

inst_12694:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38019*FLEN/8, x13, x9, x10)

inst_12695:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38022*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_99)

inst_12696:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:38025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38025*FLEN/8, x13, x9, x10)

inst_12697:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:38028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38028*FLEN/8, x13, x9, x10)

inst_12698:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:38031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38031*FLEN/8, x13, x9, x10)

inst_12699:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:38034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38034*FLEN/8, x13, x9, x10)

inst_12700:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:38037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38037*FLEN/8, x13, x9, x10)

inst_12701:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38040*FLEN/8, x13, x9, x10)

inst_12702:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38043*FLEN/8, x13, x9, x10)

inst_12703:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38046*FLEN/8, x13, x9, x10)

inst_12704:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:38049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38049*FLEN/8, x13, x9, x10)

inst_12705:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:38052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38052*FLEN/8, x13, x9, x10)

inst_12706:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:38055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38055*FLEN/8, x13, x9, x10)

inst_12707:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:38058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38058*FLEN/8, x13, x9, x10)

inst_12708:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38061*FLEN/8, x13, x9, x10)

inst_12709:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38064*FLEN/8, x13, x9, x10)

inst_12710:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38067*FLEN/8, x13, x9, x10)

inst_12711:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:38070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38070*FLEN/8, x13, x9, x10)

inst_12712:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38073*FLEN/8, x13, x9, x10)

inst_12713:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38076*FLEN/8, x13, x9, x10)

inst_12714:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38079*FLEN/8, x13, x9, x10)

inst_12715:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38082*FLEN/8, x13, x9, x10)

inst_12716:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38085*FLEN/8, x13, x9, x10)

inst_12717:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38088*FLEN/8, x13, x9, x10)

inst_12718:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38091*FLEN/8, x13, x9, x10)

inst_12719:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38094*FLEN/8, x13, x9, x10)

inst_12720:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:38097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38097*FLEN/8, x13, x9, x10)

inst_12721:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:38100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38100*FLEN/8, x13, x9, x10)

inst_12722:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:38103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38103*FLEN/8, x13, x9, x10)

inst_12723:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:38106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38106*FLEN/8, x13, x9, x10)

inst_12724:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:38109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38109*FLEN/8, x13, x9, x10)

inst_12725:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38112*FLEN/8, x13, x9, x10)

inst_12726:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38115*FLEN/8, x13, x9, x10)

inst_12727:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38118*FLEN/8, x13, x9, x10)

inst_12728:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:38121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38121*FLEN/8, x13, x9, x10)

inst_12729:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:38124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38124*FLEN/8, x13, x9, x10)

inst_12730:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:38127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38127*FLEN/8, x13, x9, x10)

inst_12731:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:38130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38130*FLEN/8, x13, x9, x10)

inst_12732:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38133*FLEN/8, x13, x9, x10)

inst_12733:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38136*FLEN/8, x13, x9, x10)

inst_12734:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38139*FLEN/8, x13, x9, x10)

inst_12735:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:38142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38142*FLEN/8, x13, x9, x10)

inst_12736:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38145*FLEN/8, x13, x9, x10)

inst_12737:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38148*FLEN/8, x13, x9, x10)

inst_12738:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38151*FLEN/8, x13, x9, x10)

inst_12739:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38154*FLEN/8, x13, x9, x10)

inst_12740:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38157*FLEN/8, x13, x9, x10)

inst_12741:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38160*FLEN/8, x13, x9, x10)

inst_12742:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38163*FLEN/8, x13, x9, x10)

inst_12743:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38166*FLEN/8, x13, x9, x10)

inst_12744:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:38169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38169*FLEN/8, x13, x9, x10)

inst_12745:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:38172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38172*FLEN/8, x13, x9, x10)

inst_12746:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:38175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38175*FLEN/8, x13, x9, x10)

inst_12747:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:38178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38178*FLEN/8, x13, x9, x10)

inst_12748:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:38181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38181*FLEN/8, x13, x9, x10)

inst_12749:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38184*FLEN/8, x13, x9, x10)

inst_12750:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38187*FLEN/8, x13, x9, x10)

inst_12751:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38190*FLEN/8, x13, x9, x10)

inst_12752:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:38193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38193*FLEN/8, x13, x9, x10)

inst_12753:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:38196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38196*FLEN/8, x13, x9, x10)

inst_12754:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:38199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38199*FLEN/8, x13, x9, x10)

inst_12755:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:38202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38202*FLEN/8, x13, x9, x10)

inst_12756:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38205*FLEN/8, x13, x9, x10)

inst_12757:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38208*FLEN/8, x13, x9, x10)

inst_12758:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38211*FLEN/8, x13, x9, x10)

inst_12759:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:38214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38214*FLEN/8, x13, x9, x10)

inst_12760:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38217*FLEN/8, x13, x9, x10)

inst_12761:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38220*FLEN/8, x13, x9, x10)

inst_12762:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38223*FLEN/8, x13, x9, x10)

inst_12763:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38226*FLEN/8, x13, x9, x10)

inst_12764:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38229*FLEN/8, x13, x9, x10)

inst_12765:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38232*FLEN/8, x13, x9, x10)

inst_12766:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38235*FLEN/8, x13, x9, x10)

inst_12767:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38238*FLEN/8, x13, x9, x10)

inst_12768:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:38241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38241*FLEN/8, x13, x9, x10)

inst_12769:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:38244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38244*FLEN/8, x13, x9, x10)

inst_12770:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:38247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38247*FLEN/8, x13, x9, x10)

inst_12771:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:38250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38250*FLEN/8, x13, x9, x10)

inst_12772:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:38253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38253*FLEN/8, x13, x9, x10)

inst_12773:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38256*FLEN/8, x13, x9, x10)

inst_12774:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38259*FLEN/8, x13, x9, x10)

inst_12775:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38262*FLEN/8, x13, x9, x10)

inst_12776:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:38265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38265*FLEN/8, x13, x9, x10)

inst_12777:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:38268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38268*FLEN/8, x13, x9, x10)

inst_12778:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:38271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38271*FLEN/8, x13, x9, x10)

inst_12779:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:38274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38274*FLEN/8, x13, x9, x10)

inst_12780:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38277*FLEN/8, x13, x9, x10)

inst_12781:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38280*FLEN/8, x13, x9, x10)

inst_12782:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38283*FLEN/8, x13, x9, x10)

inst_12783:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:38286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38286*FLEN/8, x13, x9, x10)

inst_12784:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38289*FLEN/8, x13, x9, x10)

inst_12785:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38292*FLEN/8, x13, x9, x10)

inst_12786:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38295*FLEN/8, x13, x9, x10)

inst_12787:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38298*FLEN/8, x13, x9, x10)

inst_12788:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38301*FLEN/8, x13, x9, x10)

inst_12789:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38304*FLEN/8, x13, x9, x10)

inst_12790:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38307*FLEN/8, x13, x9, x10)

inst_12791:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38310*FLEN/8, x13, x9, x10)

inst_12792:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:38313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38313*FLEN/8, x13, x9, x10)

inst_12793:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:38316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38316*FLEN/8, x13, x9, x10)

inst_12794:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:38319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38319*FLEN/8, x13, x9, x10)

inst_12795:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:38322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38322*FLEN/8, x13, x9, x10)

inst_12796:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:38325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38325*FLEN/8, x13, x9, x10)

inst_12797:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38328*FLEN/8, x13, x9, x10)

inst_12798:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38331*FLEN/8, x13, x9, x10)

inst_12799:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38334*FLEN/8, x13, x9, x10)

inst_12800:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:38337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38337*FLEN/8, x13, x9, x10)

inst_12801:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:38340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38340*FLEN/8, x13, x9, x10)

inst_12802:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:38343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38343*FLEN/8, x13, x9, x10)

inst_12803:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:38346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38346*FLEN/8, x13, x9, x10)

inst_12804:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38349*FLEN/8, x13, x9, x10)

inst_12805:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38352*FLEN/8, x13, x9, x10)

inst_12806:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38355*FLEN/8, x13, x9, x10)

inst_12807:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:38358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38358*FLEN/8, x13, x9, x10)

inst_12808:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38361*FLEN/8, x13, x9, x10)

inst_12809:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38364*FLEN/8, x13, x9, x10)

inst_12810:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38367*FLEN/8, x13, x9, x10)

inst_12811:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38370*FLEN/8, x13, x9, x10)

inst_12812:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38373*FLEN/8, x13, x9, x10)

inst_12813:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38376*FLEN/8, x13, x9, x10)

inst_12814:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38379*FLEN/8, x13, x9, x10)

inst_12815:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38382*FLEN/8, x13, x9, x10)

inst_12816:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:38385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38385*FLEN/8, x13, x9, x10)

inst_12817:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:38388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38388*FLEN/8, x13, x9, x10)

inst_12818:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:38391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38391*FLEN/8, x13, x9, x10)

inst_12819:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:38394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38394*FLEN/8, x13, x9, x10)

inst_12820:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:38397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38397*FLEN/8, x13, x9, x10)

inst_12821:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38400*FLEN/8, x13, x9, x10)

inst_12822:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38403*FLEN/8, x13, x9, x10)

inst_12823:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38406*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_100)

inst_12824:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:38409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38409*FLEN/8, x13, x9, x10)

inst_12825:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:38412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38412*FLEN/8, x13, x9, x10)

inst_12826:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:38415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38415*FLEN/8, x13, x9, x10)

inst_12827:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:38418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38418*FLEN/8, x13, x9, x10)

inst_12828:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38421*FLEN/8, x13, x9, x10)

inst_12829:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38424*FLEN/8, x13, x9, x10)

inst_12830:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38427*FLEN/8, x13, x9, x10)

inst_12831:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:38430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38430*FLEN/8, x13, x9, x10)

inst_12832:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38433*FLEN/8, x13, x9, x10)

inst_12833:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38436*FLEN/8, x13, x9, x10)

inst_12834:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38439*FLEN/8, x13, x9, x10)

inst_12835:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38442*FLEN/8, x13, x9, x10)

inst_12836:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38445*FLEN/8, x13, x9, x10)

inst_12837:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38448*FLEN/8, x13, x9, x10)

inst_12838:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38451*FLEN/8, x13, x9, x10)

inst_12839:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38454*FLEN/8, x13, x9, x10)

inst_12840:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:38457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38457*FLEN/8, x13, x9, x10)

inst_12841:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:38460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38460*FLEN/8, x13, x9, x10)

inst_12842:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:38463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38463*FLEN/8, x13, x9, x10)

inst_12843:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:38466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38466*FLEN/8, x13, x9, x10)

inst_12844:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:38469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38469*FLEN/8, x13, x9, x10)

inst_12845:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38472*FLEN/8, x13, x9, x10)

inst_12846:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38475*FLEN/8, x13, x9, x10)

inst_12847:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38478*FLEN/8, x13, x9, x10)

inst_12848:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:38481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38481*FLEN/8, x13, x9, x10)

inst_12849:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:38484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38484*FLEN/8, x13, x9, x10)

inst_12850:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:38487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38487*FLEN/8, x13, x9, x10)

inst_12851:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:38490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38490*FLEN/8, x13, x9, x10)

inst_12852:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38493*FLEN/8, x13, x9, x10)

inst_12853:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38496*FLEN/8, x13, x9, x10)

inst_12854:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38499*FLEN/8, x13, x9, x10)

inst_12855:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:38502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38502*FLEN/8, x13, x9, x10)

inst_12856:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38505*FLEN/8, x13, x9, x10)

inst_12857:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38508*FLEN/8, x13, x9, x10)

inst_12858:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38511*FLEN/8, x13, x9, x10)

inst_12859:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38514*FLEN/8, x13, x9, x10)

inst_12860:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38517*FLEN/8, x13, x9, x10)

inst_12861:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38520*FLEN/8, x13, x9, x10)

inst_12862:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38523*FLEN/8, x13, x9, x10)

inst_12863:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38526*FLEN/8, x13, x9, x10)

inst_12864:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:38529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38529*FLEN/8, x13, x9, x10)

inst_12865:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:38532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38532*FLEN/8, x13, x9, x10)

inst_12866:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:38535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38535*FLEN/8, x13, x9, x10)

inst_12867:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:38538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38538*FLEN/8, x13, x9, x10)

inst_12868:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:38541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38541*FLEN/8, x13, x9, x10)

inst_12869:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38544*FLEN/8, x13, x9, x10)

inst_12870:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38547*FLEN/8, x13, x9, x10)

inst_12871:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38550*FLEN/8, x13, x9, x10)

inst_12872:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:38553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38553*FLEN/8, x13, x9, x10)

inst_12873:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:38556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38556*FLEN/8, x13, x9, x10)

inst_12874:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:38559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38559*FLEN/8, x13, x9, x10)

inst_12875:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:38562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38562*FLEN/8, x13, x9, x10)

inst_12876:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38565*FLEN/8, x13, x9, x10)

inst_12877:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38568*FLEN/8, x13, x9, x10)

inst_12878:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38571*FLEN/8, x13, x9, x10)

inst_12879:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:38574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38574*FLEN/8, x13, x9, x10)

inst_12880:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38577*FLEN/8, x13, x9, x10)

inst_12881:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38580*FLEN/8, x13, x9, x10)

inst_12882:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38583*FLEN/8, x13, x9, x10)

inst_12883:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38586*FLEN/8, x13, x9, x10)

inst_12884:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38589*FLEN/8, x13, x9, x10)

inst_12885:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38592*FLEN/8, x13, x9, x10)

inst_12886:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38595*FLEN/8, x13, x9, x10)

inst_12887:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38598*FLEN/8, x13, x9, x10)

inst_12888:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:38601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38601*FLEN/8, x13, x9, x10)

inst_12889:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:38604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38604*FLEN/8, x13, x9, x10)

inst_12890:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:38607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38607*FLEN/8, x13, x9, x10)

inst_12891:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:38610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38610*FLEN/8, x13, x9, x10)

inst_12892:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:38613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38613*FLEN/8, x13, x9, x10)

inst_12893:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38616*FLEN/8, x13, x9, x10)

inst_12894:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38619*FLEN/8, x13, x9, x10)

inst_12895:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38622*FLEN/8, x13, x9, x10)

inst_12896:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:38625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38625*FLEN/8, x13, x9, x10)

inst_12897:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:38628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38628*FLEN/8, x13, x9, x10)

inst_12898:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:38631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38631*FLEN/8, x13, x9, x10)

inst_12899:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:38634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38634*FLEN/8, x13, x9, x10)

inst_12900:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38637*FLEN/8, x13, x9, x10)

inst_12901:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38640*FLEN/8, x13, x9, x10)

inst_12902:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38643*FLEN/8, x13, x9, x10)

inst_12903:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:38646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38646*FLEN/8, x13, x9, x10)

inst_12904:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38649*FLEN/8, x13, x9, x10)

inst_12905:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38652*FLEN/8, x13, x9, x10)

inst_12906:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38655*FLEN/8, x13, x9, x10)

inst_12907:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38658*FLEN/8, x13, x9, x10)

inst_12908:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38661*FLEN/8, x13, x9, x10)

inst_12909:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38664*FLEN/8, x13, x9, x10)

inst_12910:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38667*FLEN/8, x13, x9, x10)

inst_12911:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38670*FLEN/8, x13, x9, x10)

inst_12912:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:38673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38673*FLEN/8, x13, x9, x10)

inst_12913:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:38676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38676*FLEN/8, x13, x9, x10)

inst_12914:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:38679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38679*FLEN/8, x13, x9, x10)

inst_12915:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:38682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38682*FLEN/8, x13, x9, x10)

inst_12916:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:38685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38685*FLEN/8, x13, x9, x10)

inst_12917:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38688*FLEN/8, x13, x9, x10)

inst_12918:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38691*FLEN/8, x13, x9, x10)

inst_12919:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38694*FLEN/8, x13, x9, x10)

inst_12920:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:38697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38697*FLEN/8, x13, x9, x10)

inst_12921:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:38700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38700*FLEN/8, x13, x9, x10)

inst_12922:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:38703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38703*FLEN/8, x13, x9, x10)

inst_12923:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:38706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38706*FLEN/8, x13, x9, x10)

inst_12924:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38709*FLEN/8, x13, x9, x10)

inst_12925:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38712*FLEN/8, x13, x9, x10)

inst_12926:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38715*FLEN/8, x13, x9, x10)

inst_12927:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:38718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38718*FLEN/8, x13, x9, x10)

inst_12928:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38721*FLEN/8, x13, x9, x10)

inst_12929:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38724*FLEN/8, x13, x9, x10)

inst_12930:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38727*FLEN/8, x13, x9, x10)

inst_12931:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38730*FLEN/8, x13, x9, x10)

inst_12932:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38733*FLEN/8, x13, x9, x10)

inst_12933:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38736*FLEN/8, x13, x9, x10)

inst_12934:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38739*FLEN/8, x13, x9, x10)

inst_12935:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38742*FLEN/8, x13, x9, x10)

inst_12936:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:38745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38745*FLEN/8, x13, x9, x10)

inst_12937:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:38748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38748*FLEN/8, x13, x9, x10)

inst_12938:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:38751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38751*FLEN/8, x13, x9, x10)

inst_12939:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:38754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38754*FLEN/8, x13, x9, x10)

inst_12940:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:38757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38757*FLEN/8, x13, x9, x10)

inst_12941:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38760*FLEN/8, x13, x9, x10)

inst_12942:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38763*FLEN/8, x13, x9, x10)

inst_12943:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38766*FLEN/8, x13, x9, x10)

inst_12944:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:38769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38769*FLEN/8, x13, x9, x10)

inst_12945:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:38772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38772*FLEN/8, x13, x9, x10)

inst_12946:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:38775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38775*FLEN/8, x13, x9, x10)

inst_12947:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:38778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38778*FLEN/8, x13, x9, x10)

inst_12948:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38781*FLEN/8, x13, x9, x10)

inst_12949:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38784*FLEN/8, x13, x9, x10)

inst_12950:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38787*FLEN/8, x13, x9, x10)

inst_12951:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:38790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38790*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_101)

inst_12952:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38793*FLEN/8, x13, x9, x10)

inst_12953:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38796*FLEN/8, x13, x9, x10)

inst_12954:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38799*FLEN/8, x13, x9, x10)

inst_12955:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38802*FLEN/8, x13, x9, x10)

inst_12956:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38805*FLEN/8, x13, x9, x10)

inst_12957:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38808*FLEN/8, x13, x9, x10)

inst_12958:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38811*FLEN/8, x13, x9, x10)

inst_12959:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38814*FLEN/8, x13, x9, x10)

inst_12960:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:38817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38817*FLEN/8, x13, x9, x10)

inst_12961:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:38820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38820*FLEN/8, x13, x9, x10)

inst_12962:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:38823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38823*FLEN/8, x13, x9, x10)

inst_12963:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:38826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38826*FLEN/8, x13, x9, x10)

inst_12964:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:38829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38829*FLEN/8, x13, x9, x10)

inst_12965:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38832*FLEN/8, x13, x9, x10)

inst_12966:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38835*FLEN/8, x13, x9, x10)

inst_12967:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38838*FLEN/8, x13, x9, x10)

inst_12968:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:38841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38841*FLEN/8, x13, x9, x10)

inst_12969:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:38844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38844*FLEN/8, x13, x9, x10)

inst_12970:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:38847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38847*FLEN/8, x13, x9, x10)

inst_12971:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:38850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38850*FLEN/8, x13, x9, x10)

inst_12972:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38853*FLEN/8, x13, x9, x10)

inst_12973:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38856*FLEN/8, x13, x9, x10)

inst_12974:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38859*FLEN/8, x13, x9, x10)

inst_12975:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:38862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38862*FLEN/8, x13, x9, x10)

inst_12976:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38865*FLEN/8, x13, x9, x10)

inst_12977:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38868*FLEN/8, x13, x9, x10)

inst_12978:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38871*FLEN/8, x13, x9, x10)

inst_12979:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38874*FLEN/8, x13, x9, x10)

inst_12980:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38877*FLEN/8, x13, x9, x10)

inst_12981:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38880*FLEN/8, x13, x9, x10)

inst_12982:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38883*FLEN/8, x13, x9, x10)

inst_12983:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38886*FLEN/8, x13, x9, x10)

inst_12984:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:38889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38889*FLEN/8, x13, x9, x10)

inst_12985:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:38892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38892*FLEN/8, x13, x9, x10)

inst_12986:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:38895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38895*FLEN/8, x13, x9, x10)

inst_12987:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:38898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38898*FLEN/8, x13, x9, x10)

inst_12988:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:38901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38901*FLEN/8, x13, x9, x10)

inst_12989:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38904*FLEN/8, x13, x9, x10)

inst_12990:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38907*FLEN/8, x13, x9, x10)

inst_12991:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38910*FLEN/8, x13, x9, x10)

inst_12992:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:38913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38913*FLEN/8, x13, x9, x10)

inst_12993:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:38916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38916*FLEN/8, x13, x9, x10)

inst_12994:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:38919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38919*FLEN/8, x13, x9, x10)

inst_12995:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:38922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38922*FLEN/8, x13, x9, x10)

inst_12996:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38925*FLEN/8, x13, x9, x10)

inst_12997:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:38928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38928*FLEN/8, x13, x9, x10)

inst_12998:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:38931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38931*FLEN/8, x13, x9, x10)

inst_12999:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:38934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38934*FLEN/8, x13, x9, x10)

inst_13000:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:38937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38937*FLEN/8, x13, x9, x10)

inst_13001:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:38940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38940*FLEN/8, x13, x9, x10)

inst_13002:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:38943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38943*FLEN/8, x13, x9, x10)

inst_13003:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:38946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38946*FLEN/8, x13, x9, x10)

inst_13004:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:38949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38949*FLEN/8, x13, x9, x10)

inst_13005:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:38952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38952*FLEN/8, x13, x9, x10)

inst_13006:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:38955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38955*FLEN/8, x13, x9, x10)

inst_13007:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:38958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38958*FLEN/8, x13, x9, x10)

inst_13008:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:38961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38961*FLEN/8, x13, x9, x10)

inst_13009:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:38964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38964*FLEN/8, x13, x9, x10)

inst_13010:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:38967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38967*FLEN/8, x13, x9, x10)

inst_13011:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:38970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38970*FLEN/8, x13, x9, x10)

inst_13012:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:38973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38973*FLEN/8, x13, x9, x10)

inst_13013:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:38976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38976*FLEN/8, x13, x9, x10)

inst_13014:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:38979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38979*FLEN/8, x13, x9, x10)

inst_13015:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:38982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38982*FLEN/8, x13, x9, x10)

inst_13016:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:38985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38985*FLEN/8, x13, x9, x10)

inst_13017:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:38988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38988*FLEN/8, x13, x9, x10)

inst_13018:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:38991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38991*FLEN/8, x13, x9, x10)

inst_13019:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:38994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38994*FLEN/8, x13, x9, x10)

inst_13020:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:38997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 38997*FLEN/8, x13, x9, x10)

inst_13021:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39000*FLEN/8, x13, x9, x10)

inst_13022:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39003*FLEN/8, x13, x9, x10)

inst_13023:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39006*FLEN/8, x13, x9, x10)

inst_13024:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39009*FLEN/8, x13, x9, x10)

inst_13025:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39012*FLEN/8, x13, x9, x10)

inst_13026:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39015*FLEN/8, x13, x9, x10)

inst_13027:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39018*FLEN/8, x13, x9, x10)

inst_13028:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39021*FLEN/8, x13, x9, x10)

inst_13029:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39024*FLEN/8, x13, x9, x10)

inst_13030:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39027*FLEN/8, x13, x9, x10)

inst_13031:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39030*FLEN/8, x13, x9, x10)

inst_13032:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:39033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39033*FLEN/8, x13, x9, x10)

inst_13033:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:39036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39036*FLEN/8, x13, x9, x10)

inst_13034:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:39039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39039*FLEN/8, x13, x9, x10)

inst_13035:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:39042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39042*FLEN/8, x13, x9, x10)

inst_13036:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:39045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39045*FLEN/8, x13, x9, x10)

inst_13037:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39048*FLEN/8, x13, x9, x10)

inst_13038:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39051*FLEN/8, x13, x9, x10)

inst_13039:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39054*FLEN/8, x13, x9, x10)

inst_13040:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:39057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39057*FLEN/8, x13, x9, x10)

inst_13041:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:39060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39060*FLEN/8, x13, x9, x10)

inst_13042:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:39063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39063*FLEN/8, x13, x9, x10)

inst_13043:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:39066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39066*FLEN/8, x13, x9, x10)

inst_13044:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39069*FLEN/8, x13, x9, x10)

inst_13045:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39072*FLEN/8, x13, x9, x10)

inst_13046:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39075*FLEN/8, x13, x9, x10)

inst_13047:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39078*FLEN/8, x13, x9, x10)

inst_13048:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39081*FLEN/8, x13, x9, x10)

inst_13049:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39084*FLEN/8, x13, x9, x10)

inst_13050:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39087*FLEN/8, x13, x9, x10)

inst_13051:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39090*FLEN/8, x13, x9, x10)

inst_13052:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39093*FLEN/8, x13, x9, x10)

inst_13053:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39096*FLEN/8, x13, x9, x10)

inst_13054:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39099*FLEN/8, x13, x9, x10)

inst_13055:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39102*FLEN/8, x13, x9, x10)

inst_13056:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:39105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39105*FLEN/8, x13, x9, x10)

inst_13057:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:39108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39108*FLEN/8, x13, x9, x10)

inst_13058:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:39111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39111*FLEN/8, x13, x9, x10)

inst_13059:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:39114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39114*FLEN/8, x13, x9, x10)

inst_13060:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:39117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39117*FLEN/8, x13, x9, x10)

inst_13061:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39120*FLEN/8, x13, x9, x10)

inst_13062:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39123*FLEN/8, x13, x9, x10)

inst_13063:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39126*FLEN/8, x13, x9, x10)

inst_13064:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:39129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39129*FLEN/8, x13, x9, x10)

inst_13065:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:39132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39132*FLEN/8, x13, x9, x10)

inst_13066:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:39135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39135*FLEN/8, x13, x9, x10)

inst_13067:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:39138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39138*FLEN/8, x13, x9, x10)

inst_13068:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39141*FLEN/8, x13, x9, x10)

inst_13069:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39144*FLEN/8, x13, x9, x10)

inst_13070:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39147*FLEN/8, x13, x9, x10)

inst_13071:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39150*FLEN/8, x13, x9, x10)

inst_13072:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39153*FLEN/8, x13, x9, x10)

inst_13073:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39156*FLEN/8, x13, x9, x10)

inst_13074:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39159*FLEN/8, x13, x9, x10)

inst_13075:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39162*FLEN/8, x13, x9, x10)

inst_13076:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39165*FLEN/8, x13, x9, x10)

inst_13077:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39168*FLEN/8, x13, x9, x10)

inst_13078:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39171*FLEN/8, x13, x9, x10)

inst_13079:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39174*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_102)

inst_13080:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:39177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39177*FLEN/8, x13, x9, x10)

inst_13081:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:39180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39180*FLEN/8, x13, x9, x10)

inst_13082:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:39183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39183*FLEN/8, x13, x9, x10)

inst_13083:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:39186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39186*FLEN/8, x13, x9, x10)

inst_13084:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:39189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39189*FLEN/8, x13, x9, x10)

inst_13085:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39192*FLEN/8, x13, x9, x10)

inst_13086:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39195*FLEN/8, x13, x9, x10)

inst_13087:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39198*FLEN/8, x13, x9, x10)

inst_13088:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:39201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39201*FLEN/8, x13, x9, x10)

inst_13089:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:39204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39204*FLEN/8, x13, x9, x10)

inst_13090:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:39207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39207*FLEN/8, x13, x9, x10)

inst_13091:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:39210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39210*FLEN/8, x13, x9, x10)

inst_13092:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39213*FLEN/8, x13, x9, x10)

inst_13093:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39216*FLEN/8, x13, x9, x10)

inst_13094:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39219*FLEN/8, x13, x9, x10)

inst_13095:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39222*FLEN/8, x13, x9, x10)

inst_13096:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39225*FLEN/8, x13, x9, x10)

inst_13097:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39228*FLEN/8, x13, x9, x10)

inst_13098:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39231*FLEN/8, x13, x9, x10)

inst_13099:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39234*FLEN/8, x13, x9, x10)

inst_13100:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39237*FLEN/8, x13, x9, x10)

inst_13101:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39240*FLEN/8, x13, x9, x10)

inst_13102:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39243*FLEN/8, x13, x9, x10)

inst_13103:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39246*FLEN/8, x13, x9, x10)

inst_13104:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:39249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39249*FLEN/8, x13, x9, x10)

inst_13105:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:39252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39252*FLEN/8, x13, x9, x10)

inst_13106:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:39255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39255*FLEN/8, x13, x9, x10)

inst_13107:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:39258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39258*FLEN/8, x13, x9, x10)

inst_13108:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:39261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39261*FLEN/8, x13, x9, x10)

inst_13109:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39264*FLEN/8, x13, x9, x10)

inst_13110:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39267*FLEN/8, x13, x9, x10)

inst_13111:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39270*FLEN/8, x13, x9, x10)

inst_13112:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:39273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39273*FLEN/8, x13, x9, x10)

inst_13113:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:39276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39276*FLEN/8, x13, x9, x10)

inst_13114:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:39279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39279*FLEN/8, x13, x9, x10)

inst_13115:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:39282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39282*FLEN/8, x13, x9, x10)

inst_13116:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39285*FLEN/8, x13, x9, x10)

inst_13117:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39288*FLEN/8, x13, x9, x10)

inst_13118:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39291*FLEN/8, x13, x9, x10)

inst_13119:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:39294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39294*FLEN/8, x13, x9, x10)

inst_13120:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39297*FLEN/8, x13, x9, x10)

inst_13121:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39300*FLEN/8, x13, x9, x10)

inst_13122:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39303*FLEN/8, x13, x9, x10)

inst_13123:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39306*FLEN/8, x13, x9, x10)

inst_13124:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39309*FLEN/8, x13, x9, x10)

inst_13125:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39312*FLEN/8, x13, x9, x10)

inst_13126:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39315*FLEN/8, x13, x9, x10)

inst_13127:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39318*FLEN/8, x13, x9, x10)

inst_13128:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:39321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39321*FLEN/8, x13, x9, x10)

inst_13129:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:39324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39324*FLEN/8, x13, x9, x10)

inst_13130:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:39327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39327*FLEN/8, x13, x9, x10)

inst_13131:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:39330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39330*FLEN/8, x13, x9, x10)

inst_13132:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:39333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39333*FLEN/8, x13, x9, x10)

inst_13133:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39336*FLEN/8, x13, x9, x10)

inst_13134:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39339*FLEN/8, x13, x9, x10)

inst_13135:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39342*FLEN/8, x13, x9, x10)

inst_13136:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:39345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39345*FLEN/8, x13, x9, x10)

inst_13137:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:39348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39348*FLEN/8, x13, x9, x10)

inst_13138:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:39351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39351*FLEN/8, x13, x9, x10)

inst_13139:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:39354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39354*FLEN/8, x13, x9, x10)

inst_13140:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39357*FLEN/8, x13, x9, x10)

inst_13141:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39360*FLEN/8, x13, x9, x10)

inst_13142:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39363*FLEN/8, x13, x9, x10)

inst_13143:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:39366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39366*FLEN/8, x13, x9, x10)

inst_13144:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39369*FLEN/8, x13, x9, x10)

inst_13145:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39372*FLEN/8, x13, x9, x10)

inst_13146:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39375*FLEN/8, x13, x9, x10)

inst_13147:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39378*FLEN/8, x13, x9, x10)

inst_13148:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39381*FLEN/8, x13, x9, x10)

inst_13149:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39384*FLEN/8, x13, x9, x10)

inst_13150:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39387*FLEN/8, x13, x9, x10)

inst_13151:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39390*FLEN/8, x13, x9, x10)

inst_13152:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:39393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39393*FLEN/8, x13, x9, x10)

inst_13153:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:39396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39396*FLEN/8, x13, x9, x10)

inst_13154:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:39399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39399*FLEN/8, x13, x9, x10)

inst_13155:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:39402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39402*FLEN/8, x13, x9, x10)

inst_13156:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:39405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39405*FLEN/8, x13, x9, x10)

inst_13157:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39408*FLEN/8, x13, x9, x10)

inst_13158:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39411*FLEN/8, x13, x9, x10)

inst_13159:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39414*FLEN/8, x13, x9, x10)

inst_13160:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:39417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39417*FLEN/8, x13, x9, x10)

inst_13161:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:39420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39420*FLEN/8, x13, x9, x10)

inst_13162:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:39423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39423*FLEN/8, x13, x9, x10)

inst_13163:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:39426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39426*FLEN/8, x13, x9, x10)

inst_13164:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39429*FLEN/8, x13, x9, x10)

inst_13165:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39432*FLEN/8, x13, x9, x10)

inst_13166:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39435*FLEN/8, x13, x9, x10)

inst_13167:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:39438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39438*FLEN/8, x13, x9, x10)

inst_13168:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39441*FLEN/8, x13, x9, x10)

inst_13169:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39444*FLEN/8, x13, x9, x10)

inst_13170:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39447*FLEN/8, x13, x9, x10)

inst_13171:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39450*FLEN/8, x13, x9, x10)

inst_13172:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39453*FLEN/8, x13, x9, x10)

inst_13173:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39456*FLEN/8, x13, x9, x10)

inst_13174:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39459*FLEN/8, x13, x9, x10)

inst_13175:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39462*FLEN/8, x13, x9, x10)

inst_13176:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:39465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39465*FLEN/8, x13, x9, x10)

inst_13177:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:39468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39468*FLEN/8, x13, x9, x10)

inst_13178:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:39471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39471*FLEN/8, x13, x9, x10)

inst_13179:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:39474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39474*FLEN/8, x13, x9, x10)

inst_13180:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:39477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39477*FLEN/8, x13, x9, x10)

inst_13181:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39480*FLEN/8, x13, x9, x10)

inst_13182:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39483*FLEN/8, x13, x9, x10)

inst_13183:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39486*FLEN/8, x13, x9, x10)

inst_13184:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:39489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39489*FLEN/8, x13, x9, x10)

inst_13185:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:39492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39492*FLEN/8, x13, x9, x10)

inst_13186:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:39495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39495*FLEN/8, x13, x9, x10)

inst_13187:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:39498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39498*FLEN/8, x13, x9, x10)

inst_13188:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39501*FLEN/8, x13, x9, x10)

inst_13189:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39504*FLEN/8, x13, x9, x10)

inst_13190:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39507*FLEN/8, x13, x9, x10)

inst_13191:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:39510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39510*FLEN/8, x13, x9, x10)

inst_13192:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39513*FLEN/8, x13, x9, x10)

inst_13193:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39516*FLEN/8, x13, x9, x10)

inst_13194:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39519*FLEN/8, x13, x9, x10)

inst_13195:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39522*FLEN/8, x13, x9, x10)

inst_13196:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39525*FLEN/8, x13, x9, x10)

inst_13197:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39528*FLEN/8, x13, x9, x10)

inst_13198:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39531*FLEN/8, x13, x9, x10)

inst_13199:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39534*FLEN/8, x13, x9, x10)

inst_13200:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:39537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39537*FLEN/8, x13, x9, x10)

inst_13201:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:39540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39540*FLEN/8, x13, x9, x10)

inst_13202:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:39543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39543*FLEN/8, x13, x9, x10)

inst_13203:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:39546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39546*FLEN/8, x13, x9, x10)

inst_13204:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:39549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39549*FLEN/8, x13, x9, x10)

inst_13205:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39552*FLEN/8, x13, x9, x10)

inst_13206:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39555*FLEN/8, x13, x9, x10)

inst_13207:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39558*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_103)

inst_13208:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:39561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39561*FLEN/8, x13, x9, x10)

inst_13209:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:39564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39564*FLEN/8, x13, x9, x10)

inst_13210:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:39567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39567*FLEN/8, x13, x9, x10)

inst_13211:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:39570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39570*FLEN/8, x13, x9, x10)

inst_13212:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39573*FLEN/8, x13, x9, x10)

inst_13213:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39576*FLEN/8, x13, x9, x10)

inst_13214:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39579*FLEN/8, x13, x9, x10)

inst_13215:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39582*FLEN/8, x13, x9, x10)

inst_13216:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39585*FLEN/8, x13, x9, x10)

inst_13217:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39588*FLEN/8, x13, x9, x10)

inst_13218:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39591*FLEN/8, x13, x9, x10)

inst_13219:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39594*FLEN/8, x13, x9, x10)

inst_13220:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39597*FLEN/8, x13, x9, x10)

inst_13221:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39600*FLEN/8, x13, x9, x10)

inst_13222:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39603*FLEN/8, x13, x9, x10)

inst_13223:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39606*FLEN/8, x13, x9, x10)

inst_13224:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:39609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39609*FLEN/8, x13, x9, x10)

inst_13225:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:39612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39612*FLEN/8, x13, x9, x10)

inst_13226:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:39615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39615*FLEN/8, x13, x9, x10)

inst_13227:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:39618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39618*FLEN/8, x13, x9, x10)

inst_13228:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:39621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39621*FLEN/8, x13, x9, x10)

inst_13229:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39624*FLEN/8, x13, x9, x10)

inst_13230:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39627*FLEN/8, x13, x9, x10)

inst_13231:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39630*FLEN/8, x13, x9, x10)

inst_13232:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:39633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39633*FLEN/8, x13, x9, x10)

inst_13233:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:39636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39636*FLEN/8, x13, x9, x10)

inst_13234:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:39639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39639*FLEN/8, x13, x9, x10)

inst_13235:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:39642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39642*FLEN/8, x13, x9, x10)

inst_13236:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39645*FLEN/8, x13, x9, x10)

inst_13237:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39648*FLEN/8, x13, x9, x10)

inst_13238:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39651*FLEN/8, x13, x9, x10)

inst_13239:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39654*FLEN/8, x13, x9, x10)

inst_13240:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39657*FLEN/8, x13, x9, x10)

inst_13241:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39660*FLEN/8, x13, x9, x10)

inst_13242:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39663*FLEN/8, x13, x9, x10)

inst_13243:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39666*FLEN/8, x13, x9, x10)

inst_13244:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39669*FLEN/8, x13, x9, x10)

inst_13245:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39672*FLEN/8, x13, x9, x10)

inst_13246:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39675*FLEN/8, x13, x9, x10)

inst_13247:
// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39678*FLEN/8, x13, x9, x10)

inst_13248:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x0; valaddr_reg:x12; val_offset:39681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39681*FLEN/8, x13, x9, x10)

inst_13249:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:39684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39684*FLEN/8, x13, x9, x10)

inst_13250:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:39687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39687*FLEN/8, x13, x9, x10)

inst_13251:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:39690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39690*FLEN/8, x13, x9, x10)

inst_13252:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x2; valaddr_reg:x12; val_offset:39693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39693*FLEN/8, x13, x9, x10)

inst_13253:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39696*FLEN/8, x13, x9, x10)

inst_13254:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39699*FLEN/8, x13, x9, x10)

inst_13255:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39702*FLEN/8, x13, x9, x10)

inst_13256:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x800000; valaddr_reg:x12; val_offset:39705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39705*FLEN/8, x13, x9, x10)

inst_13257:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:39708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39708*FLEN/8, x13, x9, x10)

inst_13258:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x800001; valaddr_reg:x12; val_offset:39711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39711*FLEN/8, x13, x9, x10)

inst_13259:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:39714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39714*FLEN/8, x13, x9, x10)

inst_13260:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39717*FLEN/8, x13, x9, x10)

inst_13261:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39720*FLEN/8, x13, x9, x10)

inst_13262:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39723*FLEN/8, x13, x9, x10)

inst_13263:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0xff800000; valaddr_reg:x12; val_offset:39726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39726*FLEN/8, x13, x9, x10)

inst_13264:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39729*FLEN/8, x13, x9, x10)

inst_13265:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39732*FLEN/8, x13, x9, x10)

inst_13266:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39735*FLEN/8, x13, x9, x10)

inst_13267:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39738*FLEN/8, x13, x9, x10)

inst_13268:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39741*FLEN/8, x13, x9, x10)

inst_13269:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39744*FLEN/8, x13, x9, x10)

inst_13270:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39747*FLEN/8, x13, x9, x10)

inst_13271:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x0;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39750*FLEN/8, x13, x9, x10)

inst_13272:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x0; valaddr_reg:x12; val_offset:39753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39753*FLEN/8, x13, x9, x10)

inst_13273:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x12; val_offset:39756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39756*FLEN/8, x13, x9, x10)

inst_13274:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x1; valaddr_reg:x12; val_offset:39759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39759*FLEN/8, x13, x9, x10)

inst_13275:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x12; val_offset:39762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39762*FLEN/8, x13, x9, x10)

inst_13276:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x2; valaddr_reg:x12; val_offset:39765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39765*FLEN/8, x13, x9, x10)

inst_13277:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39768*FLEN/8, x13, x9, x10)

inst_13278:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39771*FLEN/8, x13, x9, x10)

inst_13279:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39774*FLEN/8, x13, x9, x10)

inst_13280:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x800000; valaddr_reg:x12; val_offset:39777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39777*FLEN/8, x13, x9, x10)

inst_13281:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:39780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39780*FLEN/8, x13, x9, x10)

inst_13282:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x800001; valaddr_reg:x12; val_offset:39783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39783*FLEN/8, x13, x9, x10)

inst_13283:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:39786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39786*FLEN/8, x13, x9, x10)

inst_13284:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39789*FLEN/8, x13, x9, x10)

inst_13285:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39792*FLEN/8, x13, x9, x10)

inst_13286:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39795*FLEN/8, x13, x9, x10)

inst_13287:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0xff800000; valaddr_reg:x12; val_offset:39798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39798*FLEN/8, x13, x9, x10)

inst_13288:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39801*FLEN/8, x13, x9, x10)

inst_13289:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39804*FLEN/8, x13, x9, x10)

inst_13290:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39807*FLEN/8, x13, x9, x10)

inst_13291:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39810*FLEN/8, x13, x9, x10)

inst_13292:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39813*FLEN/8, x13, x9, x10)

inst_13293:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39816*FLEN/8, x13, x9, x10)

inst_13294:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39819*FLEN/8, x13, x9, x10)

inst_13295:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39822*FLEN/8, x13, x9, x10)

inst_13296:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x0; valaddr_reg:x12; val_offset:39825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39825*FLEN/8, x13, x9, x10)

inst_13297:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x80000000; valaddr_reg:x12; val_offset:39828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39828*FLEN/8, x13, x9, x10)

inst_13298:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x1; valaddr_reg:x12; val_offset:39831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39831*FLEN/8, x13, x9, x10)

inst_13299:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x80000001; valaddr_reg:x12; val_offset:39834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39834*FLEN/8, x13, x9, x10)

inst_13300:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x2; valaddr_reg:x12; val_offset:39837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39837*FLEN/8, x13, x9, x10)

inst_13301:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39840*FLEN/8, x13, x9, x10)

inst_13302:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39843*FLEN/8, x13, x9, x10)

inst_13303:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39846*FLEN/8, x13, x9, x10)

inst_13304:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x800000; valaddr_reg:x12; val_offset:39849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39849*FLEN/8, x13, x9, x10)

inst_13305:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x80800000; valaddr_reg:x12; val_offset:39852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39852*FLEN/8, x13, x9, x10)

inst_13306:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x800001; valaddr_reg:x12; val_offset:39855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39855*FLEN/8, x13, x9, x10)

inst_13307:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x80855555; valaddr_reg:x12; val_offset:39858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39858*FLEN/8, x13, x9, x10)

inst_13308:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39861*FLEN/8, x13, x9, x10)

inst_13309:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39864*FLEN/8, x13, x9, x10)

inst_13310:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39867*FLEN/8, x13, x9, x10)

inst_13311:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0xff800000; valaddr_reg:x12; val_offset:39870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39870*FLEN/8, x13, x9, x10)

inst_13312:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39873*FLEN/8, x13, x9, x10)

inst_13313:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39876*FLEN/8, x13, x9, x10)

inst_13314:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39879*FLEN/8, x13, x9, x10)

inst_13315:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39882*FLEN/8, x13, x9, x10)

inst_13316:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39885*FLEN/8, x13, x9, x10)

inst_13317:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39888*FLEN/8, x13, x9, x10)

inst_13318:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39891*FLEN/8, x13, x9, x10)

inst_13319:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x1;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39894*FLEN/8, x13, x9, x10)

inst_13320:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x0; valaddr_reg:x12; val_offset:39897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39897*FLEN/8, x13, x9, x10)

inst_13321:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x80000000; valaddr_reg:x12; val_offset:39900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39900*FLEN/8, x13, x9, x10)

inst_13322:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x1; valaddr_reg:x12; val_offset:39903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39903*FLEN/8, x13, x9, x10)

inst_13323:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x80000001; valaddr_reg:x12; val_offset:39906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39906*FLEN/8, x13, x9, x10)

inst_13324:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x2; valaddr_reg:x12; val_offset:39909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39909*FLEN/8, x13, x9, x10)

inst_13325:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39912*FLEN/8, x13, x9, x10)

inst_13326:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39915*FLEN/8, x13, x9, x10)

inst_13327:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39918*FLEN/8, x13, x9, x10)

inst_13328:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x800000; valaddr_reg:x12; val_offset:39921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39921*FLEN/8, x13, x9, x10)

inst_13329:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x80800000; valaddr_reg:x12; val_offset:39924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39924*FLEN/8, x13, x9, x10)

inst_13330:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x800001; valaddr_reg:x12; val_offset:39927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39927*FLEN/8, x13, x9, x10)

inst_13331:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x80855555; valaddr_reg:x12; val_offset:39930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39930*FLEN/8, x13, x9, x10)

inst_13332:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:39933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39933*FLEN/8, x13, x9, x10)

inst_13333:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:39936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39936*FLEN/8, x13, x9, x10)

inst_13334:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:39939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39939*FLEN/8, x13, x9, x10)

inst_13335:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0xff800000; valaddr_reg:x12; val_offset:39942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39942*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_104)

inst_13336:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:39945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39945*FLEN/8, x13, x9, x10)

inst_13337:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:39948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39948*FLEN/8, x13, x9, x10)

inst_13338:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:39951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39951*FLEN/8, x13, x9, x10)

inst_13339:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:39954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39954*FLEN/8, x13, x9, x10)

inst_13340:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:39957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39957*FLEN/8, x13, x9, x10)

inst_13341:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:39960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39960*FLEN/8, x13, x9, x10)

inst_13342:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:39963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39963*FLEN/8, x13, x9, x10)

inst_13343:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80000001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:39966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39966*FLEN/8, x13, x9, x10)

inst_13344:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x0; valaddr_reg:x12; val_offset:39969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39969*FLEN/8, x13, x9, x10)

inst_13345:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x80000000; valaddr_reg:x12; val_offset:39972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39972*FLEN/8, x13, x9, x10)

inst_13346:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x1; valaddr_reg:x12; val_offset:39975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39975*FLEN/8, x13, x9, x10)

inst_13347:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x80000001; valaddr_reg:x12; val_offset:39978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39978*FLEN/8, x13, x9, x10)

inst_13348:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x2; valaddr_reg:x12; val_offset:39981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39981*FLEN/8, x13, x9, x10)

inst_13349:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:39984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39984*FLEN/8, x13, x9, x10)

inst_13350:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x7fffff; valaddr_reg:x12; val_offset:39987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39987*FLEN/8, x13, x9, x10)

inst_13351:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x807fffff; valaddr_reg:x12; val_offset:39990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39990*FLEN/8, x13, x9, x10)

inst_13352:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x800000; valaddr_reg:x12; val_offset:39993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39993*FLEN/8, x13, x9, x10)

inst_13353:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x80800000; valaddr_reg:x12; val_offset:39996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39996*FLEN/8, x13, x9, x10)

inst_13354:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x800001; valaddr_reg:x12; val_offset:39999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 39999*FLEN/8, x13, x9, x10)

inst_13355:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x80855555; valaddr_reg:x12; val_offset:40002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40002*FLEN/8, x13, x9, x10)

inst_13356:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40005*FLEN/8, x13, x9, x10)

inst_13357:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40008*FLEN/8, x13, x9, x10)

inst_13358:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40011*FLEN/8, x13, x9, x10)

inst_13359:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0xff800000; valaddr_reg:x12; val_offset:40014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40014*FLEN/8, x13, x9, x10)

inst_13360:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40017*FLEN/8, x13, x9, x10)

inst_13361:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40020*FLEN/8, x13, x9, x10)

inst_13362:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40023*FLEN/8, x13, x9, x10)

inst_13363:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40026*FLEN/8, x13, x9, x10)

inst_13364:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40029*FLEN/8, x13, x9, x10)

inst_13365:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40032*FLEN/8, x13, x9, x10)

inst_13366:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40035*FLEN/8, x13, x9, x10)

inst_13367:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x2;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40038*FLEN/8, x13, x9, x10)

inst_13368:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x0; valaddr_reg:x12; val_offset:40041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40041*FLEN/8, x13, x9, x10)

inst_13369:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x80000000; valaddr_reg:x12; val_offset:40044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40044*FLEN/8, x13, x9, x10)

inst_13370:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x1; valaddr_reg:x12; val_offset:40047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40047*FLEN/8, x13, x9, x10)

inst_13371:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x80000001; valaddr_reg:x12; val_offset:40050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40050*FLEN/8, x13, x9, x10)

inst_13372:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x2; valaddr_reg:x12; val_offset:40053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40053*FLEN/8, x13, x9, x10)

inst_13373:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40056*FLEN/8, x13, x9, x10)

inst_13374:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40059*FLEN/8, x13, x9, x10)

inst_13375:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40062*FLEN/8, x13, x9, x10)

inst_13376:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x800000; valaddr_reg:x12; val_offset:40065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40065*FLEN/8, x13, x9, x10)

inst_13377:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x80800000; valaddr_reg:x12; val_offset:40068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40068*FLEN/8, x13, x9, x10)

inst_13378:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x800001; valaddr_reg:x12; val_offset:40071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40071*FLEN/8, x13, x9, x10)

inst_13379:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x80855555; valaddr_reg:x12; val_offset:40074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40074*FLEN/8, x13, x9, x10)

inst_13380:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40077*FLEN/8, x13, x9, x10)

inst_13381:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40080*FLEN/8, x13, x9, x10)

inst_13382:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40083*FLEN/8, x13, x9, x10)

inst_13383:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0xff800000; valaddr_reg:x12; val_offset:40086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40086*FLEN/8, x13, x9, x10)

inst_13384:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40089*FLEN/8, x13, x9, x10)

inst_13385:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40092*FLEN/8, x13, x9, x10)

inst_13386:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40095*FLEN/8, x13, x9, x10)

inst_13387:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40098*FLEN/8, x13, x9, x10)

inst_13388:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40101*FLEN/8, x13, x9, x10)

inst_13389:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40104*FLEN/8, x13, x9, x10)

inst_13390:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40107*FLEN/8, x13, x9, x10)

inst_13391:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40110*FLEN/8, x13, x9, x10)

inst_13392:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:40113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40113*FLEN/8, x13, x9, x10)

inst_13393:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:40116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40116*FLEN/8, x13, x9, x10)

inst_13394:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:40119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40119*FLEN/8, x13, x9, x10)

inst_13395:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:40122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40122*FLEN/8, x13, x9, x10)

inst_13396:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:40125*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40125*FLEN/8, x13, x9, x10)

inst_13397:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40128*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40128*FLEN/8, x13, x9, x10)

inst_13398:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40131*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40131*FLEN/8, x13, x9, x10)

inst_13399:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40134*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40134*FLEN/8, x13, x9, x10)

inst_13400:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:40137*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40137*FLEN/8, x13, x9, x10)

inst_13401:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:40140*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40140*FLEN/8, x13, x9, x10)

inst_13402:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:40143*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40143*FLEN/8, x13, x9, x10)

inst_13403:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:40146*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40146*FLEN/8, x13, x9, x10)

inst_13404:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40149*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40149*FLEN/8, x13, x9, x10)

inst_13405:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40152*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40152*FLEN/8, x13, x9, x10)

inst_13406:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40155*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40155*FLEN/8, x13, x9, x10)

inst_13407:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:40158*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40158*FLEN/8, x13, x9, x10)

inst_13408:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40161*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40161*FLEN/8, x13, x9, x10)

inst_13409:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40164*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40164*FLEN/8, x13, x9, x10)

inst_13410:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40167*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40167*FLEN/8, x13, x9, x10)

inst_13411:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40170*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40170*FLEN/8, x13, x9, x10)

inst_13412:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40173*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40173*FLEN/8, x13, x9, x10)

inst_13413:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40176*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40176*FLEN/8, x13, x9, x10)

inst_13414:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40179*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40179*FLEN/8, x13, x9, x10)

inst_13415:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40182*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40182*FLEN/8, x13, x9, x10)

inst_13416:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x0; valaddr_reg:x12; val_offset:40185*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40185*FLEN/8, x13, x9, x10)

inst_13417:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:40188*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40188*FLEN/8, x13, x9, x10)

inst_13418:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x1; valaddr_reg:x12; val_offset:40191*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40191*FLEN/8, x13, x9, x10)

inst_13419:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:40194*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40194*FLEN/8, x13, x9, x10)

inst_13420:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x2; valaddr_reg:x12; val_offset:40197*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40197*FLEN/8, x13, x9, x10)

inst_13421:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40200*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40200*FLEN/8, x13, x9, x10)

inst_13422:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40203*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40203*FLEN/8, x13, x9, x10)

inst_13423:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40206*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40206*FLEN/8, x13, x9, x10)

inst_13424:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:40209*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40209*FLEN/8, x13, x9, x10)

inst_13425:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:40212*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40212*FLEN/8, x13, x9, x10)

inst_13426:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:40215*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40215*FLEN/8, x13, x9, x10)

inst_13427:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:40218*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40218*FLEN/8, x13, x9, x10)

inst_13428:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40221*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40221*FLEN/8, x13, x9, x10)

inst_13429:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40224*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40224*FLEN/8, x13, x9, x10)

inst_13430:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40227*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40227*FLEN/8, x13, x9, x10)

inst_13431:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:40230*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40230*FLEN/8, x13, x9, x10)

inst_13432:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40233*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40233*FLEN/8, x13, x9, x10)

inst_13433:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40236*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40236*FLEN/8, x13, x9, x10)

inst_13434:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40239*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40239*FLEN/8, x13, x9, x10)

inst_13435:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40242*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40242*FLEN/8, x13, x9, x10)

inst_13436:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40245*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40245*FLEN/8, x13, x9, x10)

inst_13437:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40248*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40248*FLEN/8, x13, x9, x10)

inst_13438:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40251*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40251*FLEN/8, x13, x9, x10)

inst_13439:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40254*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40254*FLEN/8, x13, x9, x10)

inst_13440:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x0; valaddr_reg:x12; val_offset:40257*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40257*FLEN/8, x13, x9, x10)

inst_13441:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:40260*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40260*FLEN/8, x13, x9, x10)

inst_13442:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x1; valaddr_reg:x12; val_offset:40263*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40263*FLEN/8, x13, x9, x10)

inst_13443:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:40266*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40266*FLEN/8, x13, x9, x10)

inst_13444:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x2; valaddr_reg:x12; val_offset:40269*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40269*FLEN/8, x13, x9, x10)

inst_13445:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40272*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40272*FLEN/8, x13, x9, x10)

inst_13446:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40275*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40275*FLEN/8, x13, x9, x10)

inst_13447:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40278*FLEN/8, x13, x9, x10)

inst_13448:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x800000; valaddr_reg:x12; val_offset:40281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40281*FLEN/8, x13, x9, x10)

inst_13449:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:40284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40284*FLEN/8, x13, x9, x10)

inst_13450:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x800001; valaddr_reg:x12; val_offset:40287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40287*FLEN/8, x13, x9, x10)

inst_13451:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:40290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40290*FLEN/8, x13, x9, x10)

inst_13452:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40293*FLEN/8, x13, x9, x10)

inst_13453:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40296*FLEN/8, x13, x9, x10)

inst_13454:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40299*FLEN/8, x13, x9, x10)

inst_13455:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:40302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40302*FLEN/8, x13, x9, x10)

inst_13456:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40305*FLEN/8, x13, x9, x10)

inst_13457:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40308*FLEN/8, x13, x9, x10)

inst_13458:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40311*FLEN/8, x13, x9, x10)

inst_13459:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40314*FLEN/8, x13, x9, x10)

inst_13460:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40317*FLEN/8, x13, x9, x10)

inst_13461:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40320*FLEN/8, x13, x9, x10)

inst_13462:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40323*FLEN/8, x13, x9, x10)

inst_13463:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40326*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_105)

inst_13464:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x0; valaddr_reg:x12; val_offset:40329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40329*FLEN/8, x13, x9, x10)

inst_13465:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:40332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40332*FLEN/8, x13, x9, x10)

inst_13466:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x1; valaddr_reg:x12; val_offset:40335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40335*FLEN/8, x13, x9, x10)

inst_13467:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:40338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40338*FLEN/8, x13, x9, x10)

inst_13468:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x2; valaddr_reg:x12; val_offset:40341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40341*FLEN/8, x13, x9, x10)

inst_13469:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40344*FLEN/8, x13, x9, x10)

inst_13470:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40347*FLEN/8, x13, x9, x10)

inst_13471:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40350*FLEN/8, x13, x9, x10)

inst_13472:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x800000; valaddr_reg:x12; val_offset:40353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40353*FLEN/8, x13, x9, x10)

inst_13473:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:40356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40356*FLEN/8, x13, x9, x10)

inst_13474:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x800001; valaddr_reg:x12; val_offset:40359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40359*FLEN/8, x13, x9, x10)

inst_13475:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:40362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40362*FLEN/8, x13, x9, x10)

inst_13476:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40365*FLEN/8, x13, x9, x10)

inst_13477:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40368*FLEN/8, x13, x9, x10)

inst_13478:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40371*FLEN/8, x13, x9, x10)

inst_13479:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:40374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40374*FLEN/8, x13, x9, x10)

inst_13480:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40377*FLEN/8, x13, x9, x10)

inst_13481:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40380*FLEN/8, x13, x9, x10)

inst_13482:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40383*FLEN/8, x13, x9, x10)

inst_13483:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40386*FLEN/8, x13, x9, x10)

inst_13484:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40389*FLEN/8, x13, x9, x10)

inst_13485:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40392*FLEN/8, x13, x9, x10)

inst_13486:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40395*FLEN/8, x13, x9, x10)

inst_13487:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40398*FLEN/8, x13, x9, x10)

inst_13488:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x0; valaddr_reg:x12; val_offset:40401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40401*FLEN/8, x13, x9, x10)

inst_13489:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:40404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40404*FLEN/8, x13, x9, x10)

inst_13490:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x1; valaddr_reg:x12; val_offset:40407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40407*FLEN/8, x13, x9, x10)

inst_13491:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:40410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40410*FLEN/8, x13, x9, x10)

inst_13492:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x2; valaddr_reg:x12; val_offset:40413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40413*FLEN/8, x13, x9, x10)

inst_13493:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40416*FLEN/8, x13, x9, x10)

inst_13494:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40419*FLEN/8, x13, x9, x10)

inst_13495:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40422*FLEN/8, x13, x9, x10)

inst_13496:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x800000; valaddr_reg:x12; val_offset:40425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40425*FLEN/8, x13, x9, x10)

inst_13497:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:40428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40428*FLEN/8, x13, x9, x10)

inst_13498:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x800001; valaddr_reg:x12; val_offset:40431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40431*FLEN/8, x13, x9, x10)

inst_13499:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:40434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40434*FLEN/8, x13, x9, x10)

inst_13500:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40437*FLEN/8, x13, x9, x10)

inst_13501:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40440*FLEN/8, x13, x9, x10)

inst_13502:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40443*FLEN/8, x13, x9, x10)

inst_13503:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:40446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40446*FLEN/8, x13, x9, x10)

inst_13504:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40449*FLEN/8, x13, x9, x10)

inst_13505:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40452*FLEN/8, x13, x9, x10)

inst_13506:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40455*FLEN/8, x13, x9, x10)

inst_13507:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40458*FLEN/8, x13, x9, x10)

inst_13508:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40461*FLEN/8, x13, x9, x10)

inst_13509:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40464*FLEN/8, x13, x9, x10)

inst_13510:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40467*FLEN/8, x13, x9, x10)

inst_13511:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40470*FLEN/8, x13, x9, x10)

inst_13512:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x0; valaddr_reg:x12; val_offset:40473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40473*FLEN/8, x13, x9, x10)

inst_13513:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x80000000; valaddr_reg:x12; val_offset:40476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40476*FLEN/8, x13, x9, x10)

inst_13514:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x1; valaddr_reg:x12; val_offset:40479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40479*FLEN/8, x13, x9, x10)

inst_13515:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x80000001; valaddr_reg:x12; val_offset:40482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40482*FLEN/8, x13, x9, x10)

inst_13516:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x2; valaddr_reg:x12; val_offset:40485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40485*FLEN/8, x13, x9, x10)

inst_13517:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40488*FLEN/8, x13, x9, x10)

inst_13518:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40491*FLEN/8, x13, x9, x10)

inst_13519:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40494*FLEN/8, x13, x9, x10)

inst_13520:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x800000; valaddr_reg:x12; val_offset:40497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40497*FLEN/8, x13, x9, x10)

inst_13521:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x80800000; valaddr_reg:x12; val_offset:40500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40500*FLEN/8, x13, x9, x10)

inst_13522:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x800001; valaddr_reg:x12; val_offset:40503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40503*FLEN/8, x13, x9, x10)

inst_13523:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x80855555; valaddr_reg:x12; val_offset:40506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40506*FLEN/8, x13, x9, x10)

inst_13524:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40509*FLEN/8, x13, x9, x10)

inst_13525:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40512*FLEN/8, x13, x9, x10)

inst_13526:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40515*FLEN/8, x13, x9, x10)

inst_13527:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0xff800000; valaddr_reg:x12; val_offset:40518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40518*FLEN/8, x13, x9, x10)

inst_13528:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40521*FLEN/8, x13, x9, x10)

inst_13529:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40524*FLEN/8, x13, x9, x10)

inst_13530:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40527*FLEN/8, x13, x9, x10)

inst_13531:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40530*FLEN/8, x13, x9, x10)

inst_13532:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40533*FLEN/8, x13, x9, x10)

inst_13533:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40536*FLEN/8, x13, x9, x10)

inst_13534:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40539*FLEN/8, x13, x9, x10)

inst_13535:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x80855555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40542*FLEN/8, x13, x9, x10)

inst_13536:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:40545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40545*FLEN/8, x13, x9, x10)

inst_13537:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:40548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40548*FLEN/8, x13, x9, x10)

inst_13538:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:40551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40551*FLEN/8, x13, x9, x10)

inst_13539:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:40554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40554*FLEN/8, x13, x9, x10)

inst_13540:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:40557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40557*FLEN/8, x13, x9, x10)

inst_13541:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40560*FLEN/8, x13, x9, x10)

inst_13542:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40563*FLEN/8, x13, x9, x10)

inst_13543:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40566*FLEN/8, x13, x9, x10)

inst_13544:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:40569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40569*FLEN/8, x13, x9, x10)

inst_13545:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:40572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40572*FLEN/8, x13, x9, x10)

inst_13546:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:40575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40575*FLEN/8, x13, x9, x10)

inst_13547:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:40578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40578*FLEN/8, x13, x9, x10)

inst_13548:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40581*FLEN/8, x13, x9, x10)

inst_13549:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40584*FLEN/8, x13, x9, x10)

inst_13550:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40587*FLEN/8, x13, x9, x10)

inst_13551:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:40590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40590*FLEN/8, x13, x9, x10)

inst_13552:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40593*FLEN/8, x13, x9, x10)

inst_13553:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40596*FLEN/8, x13, x9, x10)

inst_13554:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40599*FLEN/8, x13, x9, x10)

inst_13555:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40602*FLEN/8, x13, x9, x10)

inst_13556:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40605*FLEN/8, x13, x9, x10)

inst_13557:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40608*FLEN/8, x13, x9, x10)

inst_13558:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40611*FLEN/8, x13, x9, x10)

inst_13559:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40614*FLEN/8, x13, x9, x10)

inst_13560:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x0; valaddr_reg:x12; val_offset:40617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40617*FLEN/8, x13, x9, x10)

inst_13561:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x80000000; valaddr_reg:x12; val_offset:40620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40620*FLEN/8, x13, x9, x10)

inst_13562:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x1; valaddr_reg:x12; val_offset:40623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40623*FLEN/8, x13, x9, x10)

inst_13563:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x80000001; valaddr_reg:x12; val_offset:40626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40626*FLEN/8, x13, x9, x10)

inst_13564:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x2; valaddr_reg:x12; val_offset:40629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40629*FLEN/8, x13, x9, x10)

inst_13565:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40632*FLEN/8, x13, x9, x10)

inst_13566:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40635*FLEN/8, x13, x9, x10)

inst_13567:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40638*FLEN/8, x13, x9, x10)

inst_13568:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x800000; valaddr_reg:x12; val_offset:40641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40641*FLEN/8, x13, x9, x10)

inst_13569:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x80800000; valaddr_reg:x12; val_offset:40644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40644*FLEN/8, x13, x9, x10)

inst_13570:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x800001; valaddr_reg:x12; val_offset:40647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40647*FLEN/8, x13, x9, x10)

inst_13571:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x80855555; valaddr_reg:x12; val_offset:40650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40650*FLEN/8, x13, x9, x10)

inst_13572:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40653*FLEN/8, x13, x9, x10)

inst_13573:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40656*FLEN/8, x13, x9, x10)

inst_13574:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40659*FLEN/8, x13, x9, x10)

inst_13575:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0xff800000; valaddr_reg:x12; val_offset:40662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40662*FLEN/8, x13, x9, x10)

inst_13576:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40665*FLEN/8, x13, x9, x10)

inst_13577:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40668*FLEN/8, x13, x9, x10)

inst_13578:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40671*FLEN/8, x13, x9, x10)

inst_13579:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40674*FLEN/8, x13, x9, x10)

inst_13580:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40677*FLEN/8, x13, x9, x10)

inst_13581:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40680*FLEN/8, x13, x9, x10)

inst_13582:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40683*FLEN/8, x13, x9, x10)

inst_13583:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40686*FLEN/8, x13, x9, x10)

inst_13584:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x0; valaddr_reg:x12; val_offset:40689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40689*FLEN/8, x13, x9, x10)

inst_13585:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:40692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40692*FLEN/8, x13, x9, x10)

inst_13586:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x1; valaddr_reg:x12; val_offset:40695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40695*FLEN/8, x13, x9, x10)

inst_13587:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:40698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40698*FLEN/8, x13, x9, x10)

inst_13588:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x2; valaddr_reg:x12; val_offset:40701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40701*FLEN/8, x13, x9, x10)

inst_13589:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40704*FLEN/8, x13, x9, x10)

inst_13590:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40707*FLEN/8, x13, x9, x10)

inst_13591:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40710*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_106)

inst_13592:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:40713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40713*FLEN/8, x13, x9, x10)

inst_13593:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:40716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40716*FLEN/8, x13, x9, x10)

inst_13594:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:40719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40719*FLEN/8, x13, x9, x10)

inst_13595:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:40722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40722*FLEN/8, x13, x9, x10)

inst_13596:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40725*FLEN/8, x13, x9, x10)

inst_13597:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40728*FLEN/8, x13, x9, x10)

inst_13598:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40731*FLEN/8, x13, x9, x10)

inst_13599:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:40734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40734*FLEN/8, x13, x9, x10)

inst_13600:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40737*FLEN/8, x13, x9, x10)

inst_13601:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40740*FLEN/8, x13, x9, x10)

inst_13602:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40743*FLEN/8, x13, x9, x10)

inst_13603:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40746*FLEN/8, x13, x9, x10)

inst_13604:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40749*FLEN/8, x13, x9, x10)

inst_13605:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40752*FLEN/8, x13, x9, x10)

inst_13606:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40755*FLEN/8, x13, x9, x10)

inst_13607:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40758*FLEN/8, x13, x9, x10)

inst_13608:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x0; valaddr_reg:x12; val_offset:40761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40761*FLEN/8, x13, x9, x10)

inst_13609:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:40764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40764*FLEN/8, x13, x9, x10)

inst_13610:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x1; valaddr_reg:x12; val_offset:40767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40767*FLEN/8, x13, x9, x10)

inst_13611:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:40770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40770*FLEN/8, x13, x9, x10)

inst_13612:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x2; valaddr_reg:x12; val_offset:40773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40773*FLEN/8, x13, x9, x10)

inst_13613:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40776*FLEN/8, x13, x9, x10)

inst_13614:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40779*FLEN/8, x13, x9, x10)

inst_13615:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40782*FLEN/8, x13, x9, x10)

inst_13616:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x800000; valaddr_reg:x12; val_offset:40785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40785*FLEN/8, x13, x9, x10)

inst_13617:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:40788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40788*FLEN/8, x13, x9, x10)

inst_13618:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x800001; valaddr_reg:x12; val_offset:40791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40791*FLEN/8, x13, x9, x10)

inst_13619:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:40794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40794*FLEN/8, x13, x9, x10)

inst_13620:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40797*FLEN/8, x13, x9, x10)

inst_13621:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40800*FLEN/8, x13, x9, x10)

inst_13622:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40803*FLEN/8, x13, x9, x10)

inst_13623:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:40806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40806*FLEN/8, x13, x9, x10)

inst_13624:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40809*FLEN/8, x13, x9, x10)

inst_13625:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40812*FLEN/8, x13, x9, x10)

inst_13626:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40815*FLEN/8, x13, x9, x10)

inst_13627:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40818*FLEN/8, x13, x9, x10)

inst_13628:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40821*FLEN/8, x13, x9, x10)

inst_13629:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40824*FLEN/8, x13, x9, x10)

inst_13630:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40827*FLEN/8, x13, x9, x10)

inst_13631:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xff800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40830*FLEN/8, x13, x9, x10)

inst_13632:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x0; valaddr_reg:x12; val_offset:40833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40833*FLEN/8, x13, x9, x10)

inst_13633:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:40836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40836*FLEN/8, x13, x9, x10)

inst_13634:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x1; valaddr_reg:x12; val_offset:40839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40839*FLEN/8, x13, x9, x10)

inst_13635:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:40842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40842*FLEN/8, x13, x9, x10)

inst_13636:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x2; valaddr_reg:x12; val_offset:40845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40845*FLEN/8, x13, x9, x10)

inst_13637:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40848*FLEN/8, x13, x9, x10)

inst_13638:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40851*FLEN/8, x13, x9, x10)

inst_13639:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40854*FLEN/8, x13, x9, x10)

inst_13640:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:40857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40857*FLEN/8, x13, x9, x10)

inst_13641:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:40860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40860*FLEN/8, x13, x9, x10)

inst_13642:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:40863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40863*FLEN/8, x13, x9, x10)

inst_13643:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:40866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40866*FLEN/8, x13, x9, x10)

inst_13644:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40869*FLEN/8, x13, x9, x10)

inst_13645:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40872*FLEN/8, x13, x9, x10)

inst_13646:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40875*FLEN/8, x13, x9, x10)

inst_13647:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:40878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40878*FLEN/8, x13, x9, x10)

inst_13648:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40881*FLEN/8, x13, x9, x10)

inst_13649:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40884*FLEN/8, x13, x9, x10)

inst_13650:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40887*FLEN/8, x13, x9, x10)

inst_13651:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40890*FLEN/8, x13, x9, x10)

inst_13652:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40893*FLEN/8, x13, x9, x10)

inst_13653:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40896*FLEN/8, x13, x9, x10)

inst_13654:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40899*FLEN/8, x13, x9, x10)

inst_13655:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40902*FLEN/8, x13, x9, x10)

inst_13656:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x0; valaddr_reg:x12; val_offset:40905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40905*FLEN/8, x13, x9, x10)

inst_13657:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x80000000; valaddr_reg:x12; val_offset:40908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40908*FLEN/8, x13, x9, x10)

inst_13658:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x1; valaddr_reg:x12; val_offset:40911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40911*FLEN/8, x13, x9, x10)

inst_13659:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x80000001; valaddr_reg:x12; val_offset:40914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40914*FLEN/8, x13, x9, x10)

inst_13660:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x2; valaddr_reg:x12; val_offset:40917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40917*FLEN/8, x13, x9, x10)

inst_13661:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40920*FLEN/8, x13, x9, x10)

inst_13662:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40923*FLEN/8, x13, x9, x10)

inst_13663:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40926*FLEN/8, x13, x9, x10)

inst_13664:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x800000; valaddr_reg:x12; val_offset:40929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40929*FLEN/8, x13, x9, x10)

inst_13665:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x80800000; valaddr_reg:x12; val_offset:40932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40932*FLEN/8, x13, x9, x10)

inst_13666:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x800001; valaddr_reg:x12; val_offset:40935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40935*FLEN/8, x13, x9, x10)

inst_13667:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x80855555; valaddr_reg:x12; val_offset:40938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40938*FLEN/8, x13, x9, x10)

inst_13668:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:40941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40941*FLEN/8, x13, x9, x10)

inst_13669:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:40944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40944*FLEN/8, x13, x9, x10)

inst_13670:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:40947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40947*FLEN/8, x13, x9, x10)

inst_13671:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0xff800000; valaddr_reg:x12; val_offset:40950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40950*FLEN/8, x13, x9, x10)

inst_13672:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:40953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40953*FLEN/8, x13, x9, x10)

inst_13673:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:40956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40956*FLEN/8, x13, x9, x10)

inst_13674:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:40959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40959*FLEN/8, x13, x9, x10)

inst_13675:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:40962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40962*FLEN/8, x13, x9, x10)

inst_13676:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:40965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40965*FLEN/8, x13, x9, x10)

inst_13677:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:40968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40968*FLEN/8, x13, x9, x10)

inst_13678:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:40971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40971*FLEN/8, x13, x9, x10)

inst_13679:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:40974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40974*FLEN/8, x13, x9, x10)

inst_13680:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x0; valaddr_reg:x12; val_offset:40977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40977*FLEN/8, x13, x9, x10)

inst_13681:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x80000000; valaddr_reg:x12; val_offset:40980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40980*FLEN/8, x13, x9, x10)

inst_13682:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x1; valaddr_reg:x12; val_offset:40983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40983*FLEN/8, x13, x9, x10)

inst_13683:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x80000001; valaddr_reg:x12; val_offset:40986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40986*FLEN/8, x13, x9, x10)

inst_13684:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x2; valaddr_reg:x12; val_offset:40989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40989*FLEN/8, x13, x9, x10)

inst_13685:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:40992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40992*FLEN/8, x13, x9, x10)

inst_13686:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:40995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40995*FLEN/8, x13, x9, x10)

inst_13687:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:40998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 40998*FLEN/8, x13, x9, x10)

inst_13688:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x800000; valaddr_reg:x12; val_offset:41001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41001*FLEN/8, x13, x9, x10)

inst_13689:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x80800000; valaddr_reg:x12; val_offset:41004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41004*FLEN/8, x13, x9, x10)

inst_13690:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x800001; valaddr_reg:x12; val_offset:41007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41007*FLEN/8, x13, x9, x10)

inst_13691:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x80855555; valaddr_reg:x12; val_offset:41010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41010*FLEN/8, x13, x9, x10)

inst_13692:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:41013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41013*FLEN/8, x13, x9, x10)

inst_13693:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41016*FLEN/8, x13, x9, x10)

inst_13694:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:41019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41019*FLEN/8, x13, x9, x10)

inst_13695:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0xff800000; valaddr_reg:x12; val_offset:41022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41022*FLEN/8, x13, x9, x10)

inst_13696:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:41025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41025*FLEN/8, x13, x9, x10)

inst_13697:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:41028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41028*FLEN/8, x13, x9, x10)

inst_13698:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:41031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41031*FLEN/8, x13, x9, x10)

inst_13699:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:41034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41034*FLEN/8, x13, x9, x10)

inst_13700:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:41037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41037*FLEN/8, x13, x9, x10)

inst_13701:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:41040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41040*FLEN/8, x13, x9, x10)

inst_13702:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:41043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41043*FLEN/8, x13, x9, x10)

inst_13703:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:41046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41046*FLEN/8, x13, x9, x10)

inst_13704:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x0; valaddr_reg:x12; val_offset:41049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41049*FLEN/8, x13, x9, x10)

inst_13705:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x80000000; valaddr_reg:x12; val_offset:41052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41052*FLEN/8, x13, x9, x10)

inst_13706:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x1; valaddr_reg:x12; val_offset:41055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41055*FLEN/8, x13, x9, x10)

inst_13707:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x80000001; valaddr_reg:x12; val_offset:41058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41058*FLEN/8, x13, x9, x10)

inst_13708:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x2; valaddr_reg:x12; val_offset:41061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41061*FLEN/8, x13, x9, x10)

inst_13709:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:41064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41064*FLEN/8, x13, x9, x10)

inst_13710:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x7fffff; valaddr_reg:x12; val_offset:41067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41067*FLEN/8, x13, x9, x10)

inst_13711:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41070*FLEN/8, x13, x9, x10)

inst_13712:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x800000; valaddr_reg:x12; val_offset:41073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41073*FLEN/8, x13, x9, x10)

inst_13713:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x80800000; valaddr_reg:x12; val_offset:41076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41076*FLEN/8, x13, x9, x10)

inst_13714:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x800001; valaddr_reg:x12; val_offset:41079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41079*FLEN/8, x13, x9, x10)

inst_13715:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x80855555; valaddr_reg:x12; val_offset:41082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41082*FLEN/8, x13, x9, x10)

inst_13716:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:41085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41085*FLEN/8, x13, x9, x10)

inst_13717:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41088*FLEN/8, x13, x9, x10)

inst_13718:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x7f800000; valaddr_reg:x12; val_offset:41091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41091*FLEN/8, x13, x9, x10)

inst_13719:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0xff800000; valaddr_reg:x12; val_offset:41094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41094*FLEN/8, x13, x9, x10)
RVTEST_SIGBASE(x9,signature_x9_107)

inst_13720:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:41097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41097*FLEN/8, x13, x9, x10)

inst_13721:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0xffc00000; valaddr_reg:x12; val_offset:41100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41100*FLEN/8, x13, x9, x10)

inst_13722:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:41103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41103*FLEN/8, x13, x9, x10)

inst_13723:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0xffc55555; valaddr_reg:x12; val_offset:41106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41106*FLEN/8, x13, x9, x10)

inst_13724:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x7f800001; valaddr_reg:x12; val_offset:41109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41109*FLEN/8, x13, x9, x10)

inst_13725:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:41112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41112*FLEN/8, x13, x9, x10)

inst_13726:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0x3f800000; valaddr_reg:x12; val_offset:41115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41115*FLEN/8, x13, x9, x10)

inst_13727:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
op3val:0xbf800000; valaddr_reg:x12; val_offset:41118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41118*FLEN/8, x13, x9, x10)

inst_13728:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x0; valaddr_reg:x12; val_offset:41121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41121*FLEN/8, x13, x9, x10)

inst_13729:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x80000000; valaddr_reg:x12; val_offset:41124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41124*FLEN/8, x13, x9, x10)

inst_13730:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x1; valaddr_reg:x12; val_offset:41127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41127*FLEN/8, x13, x9, x10)

inst_13731:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x80000001; valaddr_reg:x12; val_offset:41130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41130*FLEN/8, x13, x9, x10)

inst_13732:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x2; valaddr_reg:x12; val_offset:41133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41133*FLEN/8, x13, x9, x10)

inst_13733:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:41136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41136*FLEN/8, x13, x9, x10)

inst_13734:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x7fffff; valaddr_reg:x12; val_offset:41139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41139*FLEN/8, x13, x9, x10)

inst_13735:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41142*FLEN/8, x13, x9, x10)

inst_13736:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x800000; valaddr_reg:x12; val_offset:41145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41145*FLEN/8, x13, x9, x10)

inst_13737:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x80800000; valaddr_reg:x12; val_offset:41148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41148*FLEN/8, x13, x9, x10)

inst_13738:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x800001; valaddr_reg:x12; val_offset:41151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41151*FLEN/8, x13, x9, x10)

inst_13739:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x80855555; valaddr_reg:x12; val_offset:41154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41154*FLEN/8, x13, x9, x10)

inst_13740:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:41157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41157*FLEN/8, x13, x9, x10)

inst_13741:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41160*FLEN/8, x13, x9, x10)

inst_13742:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x7f800000; valaddr_reg:x12; val_offset:41163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41163*FLEN/8, x13, x9, x10)

inst_13743:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0xff800000; valaddr_reg:x12; val_offset:41166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41166*FLEN/8, x13, x9, x10)

inst_13744:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:41169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41169*FLEN/8, x13, x9, x10)

inst_13745:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0xffc00000; valaddr_reg:x12; val_offset:41172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41172*FLEN/8, x13, x9, x10)

inst_13746:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:41175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41175*FLEN/8, x13, x9, x10)

inst_13747:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0xffc55555; valaddr_reg:x12; val_offset:41178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41178*FLEN/8, x13, x9, x10)

inst_13748:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x7f800001; valaddr_reg:x12; val_offset:41181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41181*FLEN/8, x13, x9, x10)

inst_13749:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:41184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41184*FLEN/8, x13, x9, x10)

inst_13750:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0x3f800000; valaddr_reg:x12; val_offset:41187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41187*FLEN/8, x13, x9, x10)

inst_13751:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
op3val:0xbf800000; valaddr_reg:x12; val_offset:41190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41190*FLEN/8, x13, x9, x10)

inst_13752:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x0; valaddr_reg:x12; val_offset:41193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41193*FLEN/8, x13, x9, x10)

inst_13753:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x80000000; valaddr_reg:x12; val_offset:41196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41196*FLEN/8, x13, x9, x10)

inst_13754:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x1; valaddr_reg:x12; val_offset:41199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41199*FLEN/8, x13, x9, x10)

inst_13755:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x80000001; valaddr_reg:x12; val_offset:41202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41202*FLEN/8, x13, x9, x10)

inst_13756:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x2; valaddr_reg:x12; val_offset:41205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41205*FLEN/8, x13, x9, x10)

inst_13757:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:41208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41208*FLEN/8, x13, x9, x10)

inst_13758:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x7fffff; valaddr_reg:x12; val_offset:41211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41211*FLEN/8, x13, x9, x10)

inst_13759:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41214*FLEN/8, x13, x9, x10)

inst_13760:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x800000; valaddr_reg:x12; val_offset:41217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41217*FLEN/8, x13, x9, x10)

inst_13761:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x80800000; valaddr_reg:x12; val_offset:41220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41220*FLEN/8, x13, x9, x10)

inst_13762:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x800001; valaddr_reg:x12; val_offset:41223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41223*FLEN/8, x13, x9, x10)

inst_13763:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x80855555; valaddr_reg:x12; val_offset:41226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41226*FLEN/8, x13, x9, x10)

inst_13764:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:41229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41229*FLEN/8, x13, x9, x10)

inst_13765:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41232*FLEN/8, x13, x9, x10)

inst_13766:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x7f800000; valaddr_reg:x12; val_offset:41235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41235*FLEN/8, x13, x9, x10)

inst_13767:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0xff800000; valaddr_reg:x12; val_offset:41238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41238*FLEN/8, x13, x9, x10)

inst_13768:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:41241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41241*FLEN/8, x13, x9, x10)

inst_13769:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0xffc00000; valaddr_reg:x12; val_offset:41244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41244*FLEN/8, x13, x9, x10)

inst_13770:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:41247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41247*FLEN/8, x13, x9, x10)

inst_13771:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0xffc55555; valaddr_reg:x12; val_offset:41250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41250*FLEN/8, x13, x9, x10)

inst_13772:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x7f800001; valaddr_reg:x12; val_offset:41253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41253*FLEN/8, x13, x9, x10)

inst_13773:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:41256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41256*FLEN/8, x13, x9, x10)

inst_13774:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0x3f800000; valaddr_reg:x12; val_offset:41259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41259*FLEN/8, x13, x9, x10)

inst_13775:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
op3val:0xbf800000; valaddr_reg:x12; val_offset:41262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41262*FLEN/8, x13, x9, x10)

inst_13776:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x0; valaddr_reg:x12; val_offset:41265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41265*FLEN/8, x13, x9, x10)

inst_13777:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:41268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41268*FLEN/8, x13, x9, x10)

inst_13778:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x1; valaddr_reg:x12; val_offset:41271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41271*FLEN/8, x13, x9, x10)

inst_13779:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:41274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41274*FLEN/8, x13, x9, x10)

inst_13780:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x2; valaddr_reg:x12; val_offset:41277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41277*FLEN/8, x13, x9, x10)

inst_13781:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:41280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41280*FLEN/8, x13, x9, x10)

inst_13782:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:41283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41283*FLEN/8, x13, x9, x10)

inst_13783:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41286*FLEN/8, x13, x9, x10)

inst_13784:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x800000; valaddr_reg:x12; val_offset:41289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41289*FLEN/8, x13, x9, x10)

inst_13785:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:41292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41292*FLEN/8, x13, x9, x10)

inst_13786:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x800001; valaddr_reg:x12; val_offset:41295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41295*FLEN/8, x13, x9, x10)

inst_13787:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:41298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41298*FLEN/8, x13, x9, x10)

inst_13788:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:41301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41301*FLEN/8, x13, x9, x10)

inst_13789:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41304*FLEN/8, x13, x9, x10)

inst_13790:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:41307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41307*FLEN/8, x13, x9, x10)

inst_13791:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:41310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41310*FLEN/8, x13, x9, x10)

inst_13792:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:41313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41313*FLEN/8, x13, x9, x10)

inst_13793:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:41316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41316*FLEN/8, x13, x9, x10)

inst_13794:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:41319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41319*FLEN/8, x13, x9, x10)

inst_13795:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:41322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41322*FLEN/8, x13, x9, x10)

inst_13796:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:41325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41325*FLEN/8, x13, x9, x10)

inst_13797:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:41328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41328*FLEN/8, x13, x9, x10)

inst_13798:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:41331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41331*FLEN/8, x13, x9, x10)

inst_13799:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:41334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41334*FLEN/8, x13, x9, x10)

inst_13800:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x0; valaddr_reg:x12; val_offset:41337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41337*FLEN/8, x13, x9, x10)

inst_13801:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x80000000; valaddr_reg:x12; val_offset:41340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41340*FLEN/8, x13, x9, x10)

inst_13802:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x1; valaddr_reg:x12; val_offset:41343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41343*FLEN/8, x13, x9, x10)

inst_13803:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x80000001; valaddr_reg:x12; val_offset:41346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41346*FLEN/8, x13, x9, x10)

inst_13804:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000002 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x2; valaddr_reg:x12; val_offset:41349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41349*FLEN/8, x13, x9, x10)

inst_13805:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:41352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41352*FLEN/8, x13, x9, x10)

inst_13806:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x7fffff; valaddr_reg:x12; val_offset:41355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41355*FLEN/8, x13, x9, x10)

inst_13807:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41358*FLEN/8, x13, x9, x10)

inst_13808:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x800000; valaddr_reg:x12; val_offset:41361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41361*FLEN/8, x13, x9, x10)

inst_13809:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x80800000; valaddr_reg:x12; val_offset:41364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41364*FLEN/8, x13, x9, x10)

inst_13810:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x800001; valaddr_reg:x12; val_offset:41367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41367*FLEN/8, x13, x9, x10)

inst_13811:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x80855555; valaddr_reg:x12; val_offset:41370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41370*FLEN/8, x13, x9, x10)

inst_13812:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x7f7fffff; valaddr_reg:x12; val_offset:41373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41373*FLEN/8, x13, x9, x10)

inst_13813:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41376*FLEN/8, x13, x9, x10)

inst_13814:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x7f800000; valaddr_reg:x12; val_offset:41379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41379*FLEN/8, x13, x9, x10)

inst_13815:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0xff800000; valaddr_reg:x12; val_offset:41382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41382*FLEN/8, x13, x9, x10)

inst_13816:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x7fc00000; valaddr_reg:x12; val_offset:41385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41385*FLEN/8, x13, x9, x10)

inst_13817:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0xffc00000; valaddr_reg:x12; val_offset:41388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41388*FLEN/8, x13, x9, x10)

inst_13818:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x400001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x7fc00001; valaddr_reg:x12; val_offset:41391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41391*FLEN/8, x13, x9, x10)

inst_13819:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x455555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0xffc55555; valaddr_reg:x12; val_offset:41394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41394*FLEN/8, x13, x9, x10)

inst_13820:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xff and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x7f800001; valaddr_reg:x12; val_offset:41397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41397*FLEN/8, x13, x9, x10)

inst_13821:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xff and fm3 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0xffaaaaaa; valaddr_reg:x12; val_offset:41400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41400*FLEN/8, x13, x9, x10)

inst_13822:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0x3f800000; valaddr_reg:x12; val_offset:41403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41403*FLEN/8, x13, x9, x10)

inst_13823:
// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0xffffffff and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
op3val:0xbf800000; valaddr_reg:x12; val_offset:41406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41406*FLEN/8, x13, x9, x10)

inst_13824:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x80000000; valaddr_reg:x12; val_offset:41409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41409*FLEN/8, x13, x9, x10)

inst_13825:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x1; valaddr_reg:x12; val_offset:41412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41412*FLEN/8, x13, x9, x10)

inst_13826:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x80000001; valaddr_reg:x12; val_offset:41415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41415*FLEN/8, x13, x9, x10)

inst_13827:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x807ffffe; valaddr_reg:x12; val_offset:41418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41418*FLEN/8, x13, x9, x10)

inst_13828:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x12; val_offset:41421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41421*FLEN/8, x13, x9, x10)

inst_13829:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41424*FLEN/8, x13, x9, x10)

inst_13830:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x80800000; valaddr_reg:x12; val_offset:41427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41427*FLEN/8, x13, x9, x10)

inst_13831:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x80855555; valaddr_reg:x12; val_offset:41430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41430*FLEN/8, x13, x9, x10)

inst_13832:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x807fffff; valaddr_reg:x12; val_offset:41433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41433*FLEN/8, x13, x9, x10)

inst_13833:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x80800000; valaddr_reg:x12; val_offset:41436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41436*FLEN/8, x13, x9, x10)

inst_13834:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055555 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0x80855555; valaddr_reg:x12; val_offset:41439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41439*FLEN/8, x13, x9, x10)

inst_13835:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0xffffffff  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x80000000;
op3val:0xff7fffff; valaddr_reg:x12; val_offset:41442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 41442*FLEN/8, x13, x9, x10)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(8388608,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(8388609,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2139095039,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2139095040,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2143289344,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2143289345,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2139095041,64,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(0,32,FLEN)
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NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_107:
    .fill 232*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
