
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.1
// timestamp : Tue Jun 20 09:43:04 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/abd/abd-data/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/abd/abd-data/riscv-ctg/sample_cgfs/rv32i_zcb.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lh instruction of the RISC-V RV32_Zca_Zcb extension for the clh covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zca_Zcb")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 != rd, rd==x14, rs1==x11, imm_val == 0, 
// opcode: c.lh; op1:x11; dest:x14; immval:0x0
TEST_LOAD(x1,x2,0,x11,x14,0x0,0*XLEN/8,c.lh,0)

inst_1:
// rs1 == rd, rd==x13, rs1==x13, imm_val == 2, 
// opcode: c.lh; op1:x13; dest:x13; immval:0x2
TEST_LOAD(x1,x2,0,x13,x13,0x2,1*XLEN/8,c.lh,0)

inst_2:
// rd==x12, rs1==x9, 
// opcode: c.lh; op1:x9; dest:x12; immval:0x0
TEST_LOAD(x1,x2,0,x9,x12,0x0,2*XLEN/8,c.lh,0)

inst_3:
// rd==x15, rs1==x8, 
// opcode: c.lh; op1:x8; dest:x15; immval:0x0
TEST_LOAD(x1,x2,0,x8,x15,0x0,3*XLEN/8,c.lh,0)

inst_4:
// rd==x11, rs1==x10, 
// opcode: c.lh; op1:x10; dest:x11; immval:0x0
TEST_LOAD(x1,x2,0,x10,x11,0x0,4*XLEN/8,c.lh,0)

inst_5:
// rd==x8, rs1==x14, 
// opcode: c.lh; op1:x14; dest:x8; immval:0x0
TEST_LOAD(x1,x2,0,x14,x8,0x0,5*XLEN/8,c.lh,0)

inst_6:
// rd==x9, rs1==x12, 
// opcode: c.lh; op1:x12; dest:x9; immval:0x0
TEST_LOAD(x1,x2,0,x12,x9,0x0,6*XLEN/8,c.lh,0)

inst_7:
// rd==x10, rs1==x15, 
// opcode: c.lh; op1:x15; dest:x10; immval:0x0
TEST_LOAD(x1,x2,0,x15,x10,0x0,7*XLEN/8,c.lh,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((XLEN/8)/4),4,0xdeadbeef


signature_x1_1:
    .fill 8*((XLEN/8)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
