diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 70151f545d0c023f16c8a5dddc0115088d8a6c69..ec1575e6b5ff484622abae7a27186b2789374bb9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1486,6 +1486,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xcvbi",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvmem",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvhwlp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvsimd",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2712,6 +2713,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmem");
     case INSN_CLASS_XCVHWLP:
       return riscv_subset_supports (rps, "xcvhwlp");
+    case INSN_CLASS_XCVSIMD:
+      return riscv_subset_supports (rps, "xcvsimd");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2976,6 +2979,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvmem";
     case INSN_CLASS_XCVHWLP:
       return "xcvhwlp";
+    case INSN_CLASS_XCVSIMD:
+      return "xcvsimd";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 57df5d8a305ce4ffab0e554a87bd53c9e4484bd7..12e025fa088d1365aadc8fe47d7e0b86670a981e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1539,6 +1539,21 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	      used_bits |= ENCODE_CV_HWLP_UIMM5(-1U);
 	      ++oparg; break;
 	    }
+	  else if (oparg[1] == '4')
+	    {
+	      used_bits |= ENCODE_CV_UIMM5(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '5')
+	    {
+	      used_bits |= ENCODE_CV_SIMD_IMM6(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '8')
+	    {
+	      used_bits |= ENCODE_CV_SIMD_UIMM6(-1U);
+	      ++oparg; break;
+	    }
 	  break;
 	case 'c': break; /* Macro operand, must be symbol or constant.  */
 	case 'I': break; /* Macro operand, must be constant.  */
@@ -3559,9 +3574,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      asarg = expr_parse_end;
 	      continue;
 	      /* CORE-V Specific.
-	         b1: pc rel 12 bits offset for cv.starti and cv.endi
-	             sign-extended immediate as pc rel displacement for hwloop
-	         b2: pc rel 5 bits unsigned offset for cv.setupi  */
+		 b1: pc rel 12 bits offset for cv.starti and cv.endi
+		     sign-extended immediate as pc rel displacement for hwloop
+		 b2: pc rel 5 bits unsigned offset for cv.setupi
+		 b4: 5 bits signed immediate bits[24..20]
+		 b5: 6 bits signed immediate bits	 */
 	    case 'b':
 	      if (oparg[1] == '1')
 		{
@@ -3626,6 +3643,41 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		    *imm_reloc = BFD_RELOC_RISCV_CVPCREL_URS1;
 		  }
 		}
+	      else if (oparg[1] == '4')
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-16 || imm_expr->X_add_number>15)
+		  as_bad(_("immediate value must be 5-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_UIMM5 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '5')
+		// b5: imm6 bits signed immediate bits
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-32 || imm_expr->X_add_number>31)
+		  as_bad(_("immediate value must be 6-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_SIMD_IMM6 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '8')
+		// b8: uimm6 bits unsigned immediate bits
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<0 || imm_expr->X_add_number>63)
+		  as_bad(_("immediate value must be 6-bit unsigned, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_SIMD_UIMM6 (imm_expr->X_add_number);
+		  ++oparg;
+		}
 	      else
 		{
 		  my_getExpression (imm_expr, asarg);
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index fd88585f551838f4e74357f976c29bfb0171870b..2178a99b2b0cd25a8a54ce8c8d3b6aebe37f5e61 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -770,6 +770,11 @@ It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-man
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvsimd
+The Xcvsimd extension provides instructions for SIMD operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..d42b44dd49f36bf3e26a35483cf73d887c70b8f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-b-fail.s
+#error_output: cv-simd-abs-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..93156ef3807ffcdcb873b769978b46141755d804
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs.b x32,x32'
+.*: Error: illegal operands `cv.abs.b x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e2dfb8e054ff138d3fe458d0d514727f366b8201
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.abs.b x32, x32
+    cv.abs.b x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b50e9508bb465b33277e3dad9ad88129ce3fe19a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7000107b          	cv.abs.b	zero,zero
+   4:	700090fb          	cv.abs.b	ra,ra
+   8:	7001117b          	cv.abs.b	sp,sp
+   c:	7004147b          	cv.abs.b	s0,s0
+  10:	700a1a7b          	cv.abs.b	s4,s4
+  14:	700f9ffb          	cv.abs.b	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6ea328015fedd1b42a574de7d792f1df51084f32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.abs.b x0, x0
+    cv.abs.b x1, x1
+    cv.abs.b x2, x2
+    cv.abs.b x8, x8
+    cv.abs.b x20, x20
+    cv.abs.b x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b3938c89647cbf9c811a0b3f401e34552d3a8f9f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-h-fail.s
+#error_output: cv-simd-abs-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..74867e1b6115664a3d5e67c3601cd15844530528
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs.h x32,x32'
+.*: Error: illegal operands `cv.abs.h x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..930e79ae5bca2040034469b9f5fa2a92bfe4939a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.abs.h x32, x32
+    cv.abs.h x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b8d09bb427f7a55fbeffafe03c2c8dc91d98cad7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7000007b          	cv.abs.h	zero,zero
+   4:	700080fb          	cv.abs.h	ra,ra
+   8:	7001017b          	cv.abs.h	sp,sp
+   c:	7004047b          	cv.abs.h	s0,s0
+  10:	700a0a7b          	cv.abs.h	s4,s4
+  14:	700f8ffb          	cv.abs.h	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..050f403799c29f267c66d101dd3f7b1d9e238b78
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.abs.h x0, x0
+    cv.abs.h x1, x1
+    cv.abs.h x2, x2
+    cv.abs.h x8, x8
+    cv.abs.h x20, x20
+    cv.abs.h x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1105a46a384baca129096b51bf2514de1988a0ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-b-fail.s
+#error_output: cv-simd-add-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..e43a2c5536b9477c04b375bab3c885c47e3c6194
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.b x32,x32,x32'
+.*: Error: illegal operands `cv.add.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..193a295e8586534a9155d86d10e7991f3d424141
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.b x32, x32, x32
+    cv.add.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..371e0fb6af664726dd5400245ca08a686a9c796f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000107b          	cv.add.b	zero,zero,zero
+   4:	001090fb          	cv.add.b	ra,ra,ra
+   8:	0021117b          	cv.add.b	sp,sp,sp
+   c:	0084147b          	cv.add.b	s0,s0,s0
+  10:	014a1a7b          	cv.add.b	s4,s4,s4
+  14:	01ff9ffb          	cv.add.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2cdf11e26d860df41b2995ced04ea5badbfefae5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.b x0, x0, x0
+    cv.add.b x1, x1, x1
+    cv.add.b x2, x2, x2
+    cv.add.b x8, x8, x8
+    cv.add.b x20, x20, x20
+    cv.add.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0430f5445d09e95aa251b9702ff1fec61040ae3d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div2-fail.s
+#error_output: cv-simd-add-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..aaf581ef21d37b048b07a8160817ab17e17be4c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..dbf1be61ca31f876d7ec1da217836d1a44352615
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.div2 x32, x32, x32
+    cv.add.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ec7c9478a2e258661ba68495d4bf067f1a419d09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00207b          	cv.add.div2	zero,zero,zero
+   4:	6c10a0fb          	cv.add.div2	ra,ra,ra
+   8:	6c21217b          	cv.add.div2	sp,sp,sp
+   c:	6c84247b          	cv.add.div2	s0,s0,s0
+  10:	6d4a2a7b          	cv.add.div2	s4,s4,s4
+  14:	6dffaffb          	cv.add.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..396bda9ee77bf6e6bfa11d1d347e4ea2bd35dd54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.div2 x0, x0, x0
+    cv.add.div2 x1, x1, x1
+    cv.add.div2 x2, x2, x2
+    cv.add.div2 x8, x8, x8
+    cv.add.div2 x20, x20, x20
+    cv.add.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..950e50f68f007523c895a90de6229b8926949d7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div4-fail.s
+#error_output: cv-simd-add-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4f91c5031c8743289acee561eaf77b5d28dc089c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7dd658bdcda76f35b130a0cd6f6df8143ecbfbd5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.div4 x32, x32, x32
+    cv.add.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b2ab67c3e464808337fb3de2ee4c58963a4854bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00407b          	cv.add.div4	zero,zero,zero
+   4:	6c10c0fb          	cv.add.div4	ra,ra,ra
+   8:	6c21417b          	cv.add.div4	sp,sp,sp
+   c:	6c84447b          	cv.add.div4	s0,s0,s0
+  10:	6d4a4a7b          	cv.add.div4	s4,s4,s4
+  14:	6dffcffb          	cv.add.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e4587ce815c9ad0903e6705571918bddbf597aef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.div4 x0, x0, x0
+    cv.add.div4 x1, x1, x1
+    cv.add.div4 x2, x2, x2
+    cv.add.div4 x8, x8, x8
+    cv.add.div4 x20, x20, x20
+    cv.add.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..dc238baf678fcd1152dfb4c86bbb23d58c3bb2fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div8-fail.s
+#error_output: cv-simd-add-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b5628ada078cecc2990e83b1dc7d5e336adf51da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..bedbed050a87372a3443e6efaa0a1bb872f530e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.div8 x32, x32, x32
+    cv.add.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..df2687734a66f0ac4db6e413b3bf18040a678f98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00607b          	cv.add.div8	zero,zero,zero
+   4:	6c10e0fb          	cv.add.div8	ra,ra,ra
+   8:	6c21617b          	cv.add.div8	sp,sp,sp
+   c:	6c84647b          	cv.add.div8	s0,s0,s0
+  10:	6d4a6a7b          	cv.add.div8	s4,s4,s4
+  14:	6dffeffb          	cv.add.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2472f00f34bca0ff2c86caddaba166be10d8aa06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.div8 x0, x0, x0
+    cv.add.div8 x1, x1, x1
+    cv.add.div8 x2, x2, x2
+    cv.add.div8 x8, x8, x8
+    cv.add.div8 x20, x20, x20
+    cv.add.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2955fadd13505032b2de3caf21f93e5810b401b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-h-fail.s
+#error_output: cv-simd-add-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a82b28674ac4b9595a9578fa4ab37856efd8d71f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.h x32,x32,x32'
+.*: Error: illegal operands `cv.add.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..148bf21959fb6979b0dce518225fb7f0bd2a14c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.h x32, x32, x32
+    cv.add.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..1a8515046a60030e88479a943b646b79b96e197f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d
@@ -0,0 +1,15 @@
+#as: -march=rv32i_xcvsimd
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000007b          	cv.add.h	zero,zero,zero
+   4:	001080fb          	cv.add.h	ra,ra,ra
+   8:	0021017b          	cv.add.h	sp,sp,sp
+   c:	0084047b          	cv.add.h	s0,s0,s0
+  10:	014a0a7b          	cv.add.h	s4,s4,s4
+  14:	01ff8ffb          	cv.add.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2a4bd6942a71a382d2e9e57c5b15eee850d4f177
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.h x0, x0, x0
+    cv.add.h x1, x1, x1
+    cv.add.h x2, x2, x2
+    cv.add.h x8, x8, x8
+    cv.add.h x20, x20, x20
+    cv.add.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..5203f945385ff4db45f62e597b7f1f4dbc86e468
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-b-fail.s
+#error_output: cv-simd-add-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..20b1f4fa1dde701c64cee42a9feff02f3cadb264
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.add.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2a89aca5751f08463c7458170ce6556ea9e415d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.sc.b x32, x32, x32
+    cv.add.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..70c4d4d7a5f9fe88736da9fef5e99770a0874d83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000507b          	cv.add.sc.b	zero,zero,zero
+   4:	0010d0fb          	cv.add.sc.b	ra,ra,ra
+   8:	0021517b          	cv.add.sc.b	sp,sp,sp
+   c:	0084547b          	cv.add.sc.b	s0,s0,s0
+  10:	014a5a7b          	cv.add.sc.b	s4,s4,s4
+  14:	01ffdffb          	cv.add.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4a3401d7a5fa2d80588167b5d909d6a38f8bb86c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.sc.b x0, x0, x0
+    cv.add.sc.b x1, x1, x1
+    cv.add.sc.b x2, x2, x2
+    cv.add.sc.b x8, x8, x8
+    cv.add.sc.b x20, x20, x20
+    cv.add.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..da90549036e25f468d27388a50274e685568e08b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-h-fail.s
+#error_output: cv-simd-add-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..eaba711f44a5417471959b8a5c688ed76ec67ebe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.add.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9fc87c807d626a085ad538b494e4aac3f83881dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.add.sc.h x32, x32, x32
+    cv.add.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6292cead61a4f41d6164b48c92cff1d22aa00a5d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000407b          	cv.add.sc.h	zero,zero,zero
+   4:	0010c0fb          	cv.add.sc.h	ra,ra,ra
+   8:	0021417b          	cv.add.sc.h	sp,sp,sp
+   c:	0084447b          	cv.add.sc.h	s0,s0,s0
+  10:	014a4a7b          	cv.add.sc.h	s4,s4,s4
+  14:	01ffcffb          	cv.add.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7aeee046c477179c04c0b0b87ed32f907c7ace3c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.add.sc.h x0, x0, x0
+    cv.add.sc.h x1, x1, x1
+    cv.add.sc.h x2, x2, x2
+    cv.add.sc.h x8, x8, x8
+    cv.add.sc.h x20, x20, x20
+    cv.add.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..4a887bf0b0311d7ce603bf99c774b6724872b01e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-b-fail.s
+#error_output: cv-simd-add-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c3f90cce75989939cee9724e7bc2647eb72b0743
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.add.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..4aa7c516c00d043d69ef287e1b2b3a19579f8423
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.add.sci.b x32, x32, 20
+    cv.add.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.add.sci.b x6, x7, -33
+    cv.add.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a619e5c2a7ef74f4a2f2a4bfccc7f435668b7b3d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	00a0707b          	cv.add.sci.b	zero,zero,20
+   4:	00a0f0fb          	cv.add.sci.b	ra,ra,20
+   8:	00a1717b          	cv.add.sci.b	sp,sp,20
+   c:	00a4747b          	cv.add.sci.b	s0,s0,20
+  10:	00aa7a7b          	cv.add.sci.b	s4,s4,20
+  14:	00affffb          	cv.add.sci.b	t6,t6,20
+  18:	0103f37b          	cv.add.sci.b	t1,t2,-32
+  1c:	0003f37b          	cv.add.sci.b	t1,t2,0
+  20:	02f3f37b          	cv.add.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1261bd2801e999d78c8cf149d9cc0188d4fb1467
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.add.sci.b x0, x0, 20
+    cv.add.sci.b x1, x1, 20
+    cv.add.sci.b x2, x2, 20
+    cv.add.sci.b x8, x8, 20
+    cv.add.sci.b x20, x20, 20
+    cv.add.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.add.sci.b x6, x7, -32
+    cv.add.sci.b x6, x7, 0
+    cv.add.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0903b08b12a58a4a846e08ef7bbdda6a015a1973
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-h-fail.s
+#error_output: cv-simd-add-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..2f0656f83a364e52d32aed8b181de6184d5d6168
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.add.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7a1cf469a2333e73462a293e46a8bce55dc24250
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.add.sci.h x32, x32, 20
+    cv.add.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.add.sci.h x6, x7, -33
+    cv.add.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8feb432283e5d1a1bf9fbca2c81430b99ab21336
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	00a0607b          	cv.add.sci.h	zero,zero,20
+   4:	00a0e0fb          	cv.add.sci.h	ra,ra,20
+   8:	00a1617b          	cv.add.sci.h	sp,sp,20
+   c:	00a4647b          	cv.add.sci.h	s0,s0,20
+  10:	00aa6a7b          	cv.add.sci.h	s4,s4,20
+  14:	00afeffb          	cv.add.sci.h	t6,t6,20
+  18:	0103e37b          	cv.add.sci.h	t1,t2,-32
+  1c:	0003e37b          	cv.add.sci.h	t1,t2,0
+  20:	02f3e37b          	cv.add.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..027ca49550eceafc21c531e95953117fa0ddb6aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.add.sci.h x0, x0, 20
+    cv.add.sci.h x1, x1, 20
+    cv.add.sci.h x2, x2, 20
+    cv.add.sci.h x8, x8, 20
+    cv.add.sci.h x20, x20, 20
+    cv.add.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.add.sci.h x6, x7, -32
+    cv.add.sci.h x6, x7, 0
+    cv.add.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..90dcc73303d9f48736b41280f7820e3c91ec7893
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-b-fail.s
+#error_output: cv-simd-and-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..18102aad53f5f3a1a062316312b5bb6cbb136945
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.b x32,x32,x32'
+.*: Error: illegal operands `cv.and.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..192fd54d16f6d430aa8539d244d3ea57e295d62d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.and.b x32, x32, x32
+    cv.and.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..3c04c58671c7de3bd9af0127897056e267fa2f0b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800107b          	cv.and.b	zero,zero,zero
+   4:	681090fb          	cv.and.b	ra,ra,ra
+   8:	6821117b          	cv.and.b	sp,sp,sp
+   c:	6884147b          	cv.and.b	s0,s0,s0
+  10:	694a1a7b          	cv.and.b	s4,s4,s4
+  14:	69ff9ffb          	cv.and.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7a84aa939750cf5abf2f8da6e2f16656e7124926
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.and.b x0, x0, x0
+    cv.and.b x1, x1, x1
+    cv.and.b x2, x2, x2
+    cv.and.b x8, x8, x8
+    cv.and.b x20, x20, x20
+    cv.and.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8afc79a69b7ae741767edf4884d3764d24dc8f2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-h-fail.s
+#error_output: cv-simd-and-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a12d6a349db67622a6c675030f34cb248837334b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.h x32,x32,x32'
+.*: Error: illegal operands `cv.and.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..98a278b3e3bebbbe652365d4aff1f426ab4a7041
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.and.h x32, x32, x32
+    cv.and.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..543d22a8acc7cf8ed81b4d3de0519a1e6392cd4e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800007b          	cv.and.h	zero,zero,zero
+   4:	681080fb          	cv.and.h	ra,ra,ra
+   8:	6821017b          	cv.and.h	sp,sp,sp
+   c:	6884047b          	cv.and.h	s0,s0,s0
+  10:	694a0a7b          	cv.and.h	s4,s4,s4
+  14:	69ff8ffb          	cv.and.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2d3149b667aedd50a2925e7f281df3058662aa9d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.and.h x0, x0, x0
+    cv.and.h x1, x1, x1
+    cv.and.h x2, x2, x2
+    cv.and.h x8, x8, x8
+    cv.and.h x20, x20, x20
+    cv.and.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..6144978cf6c25651cab43e373f9468d0bb5ebcf4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-b-fail.s
+#error_output: cv-simd-and-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..cf9dd0e29351614d62e93437418dab1ea4c90426
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.and.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..780f7532e9b1f71d50a1ec032025c1e07ff75467
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.and.sc.b x32, x32, x32
+    cv.and.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..303b08034efe7543e70d95782e2a37b812ba1a16
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800507b          	cv.and.sc.b	zero,zero,zero
+   4:	6810d0fb          	cv.and.sc.b	ra,ra,ra
+   8:	6821517b          	cv.and.sc.b	sp,sp,sp
+   c:	6884547b          	cv.and.sc.b	s0,s0,s0
+  10:	694a5a7b          	cv.and.sc.b	s4,s4,s4
+  14:	69ffdffb          	cv.and.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..a4e742fe76e2cc239659b8be5f047f3557da926f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.and.sc.b x0, x0, x0
+    cv.and.sc.b x1, x1, x1
+    cv.and.sc.b x2, x2, x2
+    cv.and.sc.b x8, x8, x8
+    cv.and.sc.b x20, x20, x20
+    cv.and.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..c8bb0149d9a2185e09a549cea6d9ed47c7b32356
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-h-fail.s
+#error_output: cv-simd-and-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..cc0e3329db6f8672267e741479f02c3898112235
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.and.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c09eb0d1abc2cc6a121239ed01930cbad5fa7b04
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.and.sc.h x32, x32, x32
+    cv.and.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..66eee81b941a787b34d192a722d67da3257fd0ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800407b          	cv.and.sc.h	zero,zero,zero
+   4:	6810c0fb          	cv.and.sc.h	ra,ra,ra
+   8:	6821417b          	cv.and.sc.h	sp,sp,sp
+   c:	6884447b          	cv.and.sc.h	s0,s0,s0
+  10:	694a4a7b          	cv.and.sc.h	s4,s4,s4
+  14:	69ffcffb          	cv.and.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..28830c19bee3ba70e75e6a235ac016bdd4980874
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.and.sc.h x0, x0, x0
+    cv.and.sc.h x1, x1, x1
+    cv.and.sc.h x2, x2, x2
+    cv.and.sc.h x8, x8, x8
+    cv.and.sc.h x20, x20, x20
+    cv.and.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f208bb9600e93d30f7e235b9838a59aae15d48fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-b-fail.s
+#error_output: cv-simd-and-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a259452d78d929dfcc1d5e25dcb61c77178651ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.and.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..caa19414c30a3734c82f03d6cc0a013e69493bdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.and.sci.b x32, x32, 20
+    cv.and.sci.b x33, x33, 20
+    #Boundary Ibmediate Values Test
+    cv.and.sci.b x6, x7, -33
+    cv.and.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..df234b3bfe18fc4e45b76cd85019f49b0ba373c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	68a0707b          	cv.and.sci.b	zero,zero,20
+   4:	68a0f0fb          	cv.and.sci.b	ra,ra,20
+   8:	68a1717b          	cv.and.sci.b	sp,sp,20
+   c:	68a4747b          	cv.and.sci.b	s0,s0,20
+  10:	68aa7a7b          	cv.and.sci.b	s4,s4,20
+  14:	68affffb          	cv.and.sci.b	t6,t6,20
+  18:	6903f37b          	cv.and.sci.b	t1,t2,-32
+  1c:	6803f37b          	cv.and.sci.b	t1,t2,0
+  20:	6af3f37b          	cv.and.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4db2d1d79a7c441254a224dc47189b7ec047d8b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.and.sci.b x0, x0, 20
+    cv.and.sci.b x1, x1, 20
+    cv.and.sci.b x2, x2, 20
+    cv.and.sci.b x8, x8, 20
+    cv.and.sci.b x20, x20, 20
+    cv.and.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.and.sci.b x6, x7, -32
+    cv.and.sci.b x6, x7, 0
+    cv.and.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3f17a36db1409a7b6b5f2cebd447b5b7394541ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-h-fail.s
+#error_output: cv-simd-and-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3564a7fce868538ab2fea244881b059af3f1f68e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.and.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..25b85f2a3e93e90189388b150548e4184e2034e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.and.sci.h x32, x32, 20
+    cv.and.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.and.sci.h x6, x7, -33
+    cv.and.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e9f68737c8e13f758f89efcbb9011c72316187ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	68a0607b          	cv.and.sci.h	zero,zero,20
+   4:	68a0e0fb          	cv.and.sci.h	ra,ra,20
+   8:	68a1617b          	cv.and.sci.h	sp,sp,20
+   c:	68a4647b          	cv.and.sci.h	s0,s0,20
+  10:	68aa6a7b          	cv.and.sci.h	s4,s4,20
+  14:	68afeffb          	cv.and.sci.h	t6,t6,20
+  18:	6903e37b          	cv.and.sci.h	t1,t2,-32
+  1c:	6803e37b          	cv.and.sci.h	t1,t2,0
+  20:	6af3e37b          	cv.and.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4abb2f3daa8b22292de26e19007348a15db918f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.and.sci.h x0, x0, 20
+    cv.and.sci.h x1, x1, 20
+    cv.and.sci.h x2, x2, 20
+    cv.and.sci.h x8, x8, 20
+    cv.and.sci.h x20, x20, 20
+    cv.and.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.and.sci.h x6, x7, -32
+    cv.and.sci.h x6, x7, 0
+    cv.and.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8e1fedc4f4ba118d0b754411f8d655050f81b9c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-b-fail.s
+#error_output: cv-simd-avg-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7b693315d5ee0aac6d76bfc801f0804519a7f872
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.b x32,x32,x32'
+.*: Error: illegal operands `cv.avg.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..93711991590610b09e484a7f88567132396b6fa5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avg.b x32, x32, x32
+    cv.avg.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..2f6b39e151a05de8cdac1abf9e412e8544819294
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000107b          	cv.avg.b	zero,zero,zero
+   4:	101090fb          	cv.avg.b	ra,ra,ra
+   8:	1021117b          	cv.avg.b	sp,sp,sp
+   c:	1084147b          	cv.avg.b	s0,s0,s0
+  10:	114a1a7b          	cv.avg.b	s4,s4,s4
+  14:	11ff9ffb          	cv.avg.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1829a24774baaf2b8ff9541e2cdaf53e31ad6fa0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avg.b x0, x0, x0
+    cv.avg.b x1, x1, x1
+    cv.avg.b x2, x2, x2
+    cv.avg.b x8, x8, x8
+    cv.avg.b x20, x20, x20
+    cv.avg.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..027118446fb26a7e53efbf06bf77db0191d0b52b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-h-fail.s
+#error_output: cv-simd-avg-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..387e31e1f043871d93672cba2f1be1078091f10a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.h x32,x32,x32'
+.*: Error: illegal operands `cv.avg.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9a9171b76aa6793f7278daa93307f2e1b7b94338
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avg.h x32, x32, x32
+    cv.avg.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..044b292c4502b6268b01f13871f713b33b6b1b78
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000007b          	cv.avg.h	zero,zero,zero
+   4:	101080fb          	cv.avg.h	ra,ra,ra
+   8:	1021017b          	cv.avg.h	sp,sp,sp
+   c:	1084047b          	cv.avg.h	s0,s0,s0
+  10:	114a0a7b          	cv.avg.h	s4,s4,s4
+  14:	11ff8ffb          	cv.avg.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6572f47bc24c110e1eeb7bb4c35ff4c50d407dab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avg.h x0, x0, x0
+    cv.avg.h x1, x1, x1
+    cv.avg.h x2, x2, x2
+    cv.avg.h x8, x8, x8
+    cv.avg.h x20, x20, x20
+    cv.avg.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a452363f4d7162ccfb726e149e834b949c8967cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-b-fail.s
+#error_output: cv-simd-avg-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..dd22457c92d859379a3f2343c0983642f9e67839
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.avg.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b4fcc7157f045a4209f8b94b89d4e3203826c2e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avg.sc.b x32, x32, x32
+    cv.avg.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..24c9362fec00c7db94fba8717bab01d8e203ef54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000507b          	cv.avg.sc.b	zero,zero,zero
+   4:	1010d0fb          	cv.avg.sc.b	ra,ra,ra
+   8:	1021517b          	cv.avg.sc.b	sp,sp,sp
+   c:	1084547b          	cv.avg.sc.b	s0,s0,s0
+  10:	114a5a7b          	cv.avg.sc.b	s4,s4,s4
+  14:	11ffdffb          	cv.avg.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..65417deec84d33f6214aa8dff483683f35e09e76
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avg.sc.b x0, x0, x0
+    cv.avg.sc.b x1, x1, x1
+    cv.avg.sc.b x2, x2, x2
+    cv.avg.sc.b x8, x8, x8
+    cv.avg.sc.b x20, x20, x20
+    cv.avg.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..5e48b00300672bdece608c0ef2b6a7b8707856a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-h-fail.s
+#error_output: cv-simd-avg-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3df6422a9d431e32b32608db05f45b996ebd7c72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.avg.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f0e769cee1b2b53fed8808ca0ceafe4cbb179b4d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avg.sc.h x32, x32, x32
+    cv.avg.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f4cd1bcfe739603ef185dcd4e0fb4ae5ffd9fd13
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000407b          	cv.avg.sc.h	zero,zero,zero
+   4:	1010c0fb          	cv.avg.sc.h	ra,ra,ra
+   8:	1021417b          	cv.avg.sc.h	sp,sp,sp
+   c:	1084447b          	cv.avg.sc.h	s0,s0,s0
+  10:	114a4a7b          	cv.avg.sc.h	s4,s4,s4
+  14:	11ffcffb          	cv.avg.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6642c8e983665b0b5eb9b631f1b4cc6eb6311f51
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avg.sc.h x0, x0, x0
+    cv.avg.sc.h x1, x1, x1
+    cv.avg.sc.h x2, x2, x2
+    cv.avg.sc.h x8, x8, x8
+    cv.avg.sc.h x20, x20, x20
+    cv.avg.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..166015a1156c7872cf6ef9c7bdb250bdf221cd71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-b-fail.s
+#error_output: cv-simd-avg-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1d66f52499bcc6f4b686a037c246364664dc0557
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.avg.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5eed74ad3c63a7613fd2f170bddcd4ca239a7409
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.avg.sci.b x32, x32, 20
+    cv.avg.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avg.sci.b x6, x7, -33
+    cv.avg.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..023b3201d14e1ec6edd58c517928f648b7c3d1c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	10a0707b          	cv.avg.sci.b	zero,zero,20
+   4:	10a0f0fb          	cv.avg.sci.b	ra,ra,20
+   8:	10a1717b          	cv.avg.sci.b	sp,sp,20
+   c:	10a4747b          	cv.avg.sci.b	s0,s0,20
+  10:	10aa7a7b          	cv.avg.sci.b	s4,s4,20
+  14:	10affffb          	cv.avg.sci.b	t6,t6,20
+  18:	1103f37b          	cv.avg.sci.b	t1,t2,-32
+  1c:	1003f37b          	cv.avg.sci.b	t1,t2,0
+  20:	12f3f37b          	cv.avg.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..726677aaa973619e97fcef697542aef65d3bc26a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.avg.sci.b x0, x0, 20
+    cv.avg.sci.b x1, x1, 20
+    cv.avg.sci.b x2, x2, 20
+    cv.avg.sci.b x8, x8, 20
+    cv.avg.sci.b x20, x20, 20
+    cv.avg.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.avg.sci.b x6, x7, -32
+    cv.avg.sci.b x6, x7, 0
+    cv.avg.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..d995769504d2ec7de513ab582a1186479a441923
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-h-fail.s
+#error_output: cv-simd-avg-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a5bc7a5cdb947dc87c5e31ee8b2ea4c04f28b193
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.avg.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ae476ed9475dc08db772b4cc6945a8422362b70e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.avg.sci.h x32, x32, 20
+    cv.avg.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avg.sci.h x6, x7, -33
+    cv.avg.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..43e6089b2b9d469819b2c48f78e60a8d1a80f354
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	10a0607b          	cv.avg.sci.h	zero,zero,20
+   4:	10a0e0fb          	cv.avg.sci.h	ra,ra,20
+   8:	10a1617b          	cv.avg.sci.h	sp,sp,20
+   c:	10a4647b          	cv.avg.sci.h	s0,s0,20
+  10:	10aa6a7b          	cv.avg.sci.h	s4,s4,20
+  14:	10afeffb          	cv.avg.sci.h	t6,t6,20
+  18:	1103e37b          	cv.avg.sci.h	t1,t2,-32
+  1c:	1003e37b          	cv.avg.sci.h	t1,t2,0
+  20:	12f3e37b          	cv.avg.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..831c7812e69002846c0d762bd9317e736647503f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.avg.sci.h x0, x0, 20
+    cv.avg.sci.h x1, x1, 20
+    cv.avg.sci.h x2, x2, 20
+    cv.avg.sci.h x8, x8, 20
+    cv.avg.sci.h x20, x20, 20
+    cv.avg.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.avg.sci.h x6, x7, -32
+    cv.avg.sci.h x6, x7, 0
+    cv.avg.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..af1ddbe83cac98acfeb538d13da147a57fc2023e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-b-fail.s
+#error_output: cv-simd-avgu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..945d5b11ad7e846992944091c6e2427065ff000f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.b x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b82b8f11107615a17a61b57f076d45656be97ecd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avgu.b x32, x32, x32
+    cv.avgu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f7e548a3ca2723bef81f867dc625bd0110732ad1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800107b          	cv.avgu.b	zero,zero,zero
+   4:	181090fb          	cv.avgu.b	ra,ra,ra
+   8:	1821117b          	cv.avgu.b	sp,sp,sp
+   c:	1884147b          	cv.avgu.b	s0,s0,s0
+  10:	194a1a7b          	cv.avgu.b	s4,s4,s4
+  14:	19ff9ffb          	cv.avgu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b36cadcaf2d976b9d8f50f72e961970f52cb3ae4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avgu.b x0, x0, x0
+    cv.avgu.b x1, x1, x1
+    cv.avgu.b x2, x2, x2
+    cv.avgu.b x8, x8, x8
+    cv.avgu.b x20, x20, x20
+    cv.avgu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..caabe1b56afbe0b42706e377d3151b8a5011d276
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-h-fail.s
+#error_output: cv-simd-avgu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7c8f1554713f268b10a371de4df3b60fc3a7a096
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.h x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a384e97dad04de3559eb9aeb78dc8d3b1c67e4b7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avgu.h x32, x32, x32
+    cv.avgu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..21d3e815119b5b7e9c5533e8f645aebbbda973ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800007b          	cv.avgu.h	zero,zero,zero
+   4:	181080fb          	cv.avgu.h	ra,ra,ra
+   8:	1821017b          	cv.avgu.h	sp,sp,sp
+   c:	1884047b          	cv.avgu.h	s0,s0,s0
+  10:	194a0a7b          	cv.avgu.h	s4,s4,s4
+  14:	19ff8ffb          	cv.avgu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7f5cc08c4598bec3c098b75dfaa1686ef8bbbc80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avgu.h x0, x0, x0
+    cv.avgu.h x1, x1, x1
+    cv.avgu.h x2, x2, x2
+    cv.avgu.h x8, x8, x8
+    cv.avgu.h x20, x20, x20
+    cv.avgu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..9528a0ef082ccd0735efd9a5dc1224c3aca86c14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-b-fail.s
+#error_output: cv-simd-avgu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..477e1703fd2c8bc03474e538628bed40a4d9877c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a778c92bcdcd6f862cf5a16ba6704f332bf56ce3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avgu.sc.b x32, x32, x32
+    cv.avgu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4b7819c570569e1fd52a2144b8e02a8f6c7d5fd4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800507b          	cv.avgu.sc.b	zero,zero,zero
+   4:	1810d0fb          	cv.avgu.sc.b	ra,ra,ra
+   8:	1821517b          	cv.avgu.sc.b	sp,sp,sp
+   c:	1884547b          	cv.avgu.sc.b	s0,s0,s0
+  10:	194a5a7b          	cv.avgu.sc.b	s4,s4,s4
+  14:	19ffdffb          	cv.avgu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..731cb07109e7ede7582adef6a75171b6a7c0e012
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avgu.sc.b x0, x0, x0
+    cv.avgu.sc.b x1, x1, x1
+    cv.avgu.sc.b x2, x2, x2
+    cv.avgu.sc.b x8, x8, x8
+    cv.avgu.sc.b x20, x20, x20
+    cv.avgu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..63ae30b9c62fbe2bb62aedc790adf54159f2b37a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-h-fail.s
+#error_output: cv-simd-avgu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b4192d02b66ea5a82ecaad91770d37fb0d81e8fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..bd031f155f3835ec6600040343fc6940ee988237
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.avgu.sc.h x32, x32, x32
+    cv.avgu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c084dbd8aede2e7fd6997bd0f1e43facc0cbfe10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800407b          	cv.avgu.sc.h	zero,zero,zero
+   4:	1810c0fb          	cv.avgu.sc.h	ra,ra,ra
+   8:	1821417b          	cv.avgu.sc.h	sp,sp,sp
+   c:	1884447b          	cv.avgu.sc.h	s0,s0,s0
+  10:	194a4a7b          	cv.avgu.sc.h	s4,s4,s4
+  14:	19ffcffb          	cv.avgu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b22a133e9d908777296d57b826c8e0024cfa53e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.avgu.sc.h x0, x0, x0
+    cv.avgu.sc.h x1, x1, x1
+    cv.avgu.sc.h x2, x2, x2
+    cv.avgu.sc.h x8, x8, x8
+    cv.avgu.sc.h x20, x20, x20
+    cv.avgu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..071985022d02de58066e7ccf18a262734a7c1950
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-b-fail.s
+#error_output: cv-simd-avgu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..241f8ae13414808a5ae74b8b0b1a91126ccce898
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.avgu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ae5db455cb505c7712a3045be90ff05eaf96dbe0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.avgu.sci.b x32, x32, 20
+    cv.avgu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avgu.sci.b x6, x7, -1
+    cv.avgu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0668fe1848da7b365441bfc52fbfc50564d09f5a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	18a0707b          	cv.avgu.sci.b	zero,zero,20
+   4:	18a0f0fb          	cv.avgu.sci.b	ra,ra,20
+   8:	18a1717b          	cv.avgu.sci.b	sp,sp,20
+   c:	18a4747b          	cv.avgu.sci.b	s0,s0,20
+  10:	18aa7a7b          	cv.avgu.sci.b	s4,s4,20
+  14:	18affffb          	cv.avgu.sci.b	t6,t6,20
+  18:	1803f37b          	cv.avgu.sci.b	t1,t2,0
+  1c:	1bf3f37b          	cv.avgu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7aa5738dc0a80916cd84426ff71352a3a59db9c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.avgu.sci.b x0, x0, 20
+    cv.avgu.sci.b x1, x1, 20
+    cv.avgu.sci.b x2, x2, 20
+    cv.avgu.sci.b x8, x8, 20
+    cv.avgu.sci.b x20, x20, 20
+    cv.avgu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.avgu.sci.b x6, x7, 0
+    cv.avgu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..398239769ffc46dba7c18cca6428d194d3c5b709
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-h-fail.s
+#error_output: cv-simd-avgu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ec018bdd1efb042731618eba68ace1cb2ea64c63
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.avgu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..fce52e92e85f027011603b1baac4d0cea17c18ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.avgu.sci.h x32, x32, 20
+    cv.avgu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avgu.sci.h x6, x7, -1
+    cv.avgu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..1f9902d0dc415704d0b7972ed1b4c642ce335e70
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	18a0607b          	cv.avgu.sci.h	zero,zero,20
+   4:	18a0e0fb          	cv.avgu.sci.h	ra,ra,20
+   8:	18a1617b          	cv.avgu.sci.h	sp,sp,20
+   c:	18a4647b          	cv.avgu.sci.h	s0,s0,20
+  10:	18aa6a7b          	cv.avgu.sci.h	s4,s4,20
+  14:	18afeffb          	cv.avgu.sci.h	t6,t6,20
+  18:	1803e37b          	cv.avgu.sci.h	t1,t2,0
+  1c:	1bf3e37b          	cv.avgu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b4465c415a5513836dd20e8a114c53c0eb3ad13a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.avgu.sci.h x0, x0, 20
+    cv.avgu.sci.h x1, x1, 20
+    cv.avgu.sci.h x2, x2, 20
+    cv.avgu.sci.h x8, x8, 20
+    cv.avgu.sci.h x20, x20, 20
+    cv.avgu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.avgu.sci.h x6, x7, 0
+    cv.avgu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2a3318d5dfe7d83ab913fd9b6cab8bc8fccc649b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-b-fail.s
+#error_output: cv-simd-cmpeq-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4aac9f46da2e1d80c73e0b7409e70f08fcf5b47b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9b6e33703a32575e7562755f82a9ba1f176c7c99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpeq.b x32, x32, x32
+    cv.cmpeq.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..bd2b2f9b0a6e225f87cfb66c3b4782bff38a1bfd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400107b          	cv.cmpeq.b	zero,zero,zero
+   4:	041090fb          	cv.cmpeq.b	ra,ra,ra
+   8:	0421117b          	cv.cmpeq.b	sp,sp,sp
+   c:	0484147b          	cv.cmpeq.b	s0,s0,s0
+  10:	054a1a7b          	cv.cmpeq.b	s4,s4,s4
+  14:	05ff9ffb          	cv.cmpeq.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..11496e533c99ab221c068d4eb6bf2938ccfec65e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpeq.b x0, x0, x0
+    cv.cmpeq.b x1, x1, x1
+    cv.cmpeq.b x2, x2, x2
+    cv.cmpeq.b x8, x8, x8
+    cv.cmpeq.b x20, x20, x20
+    cv.cmpeq.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b258f49d2ece1f223f0d64d43554ec1d7908d085
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-h-fail.s
+#error_output: cv-simd-cmpeq-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a4a2d73299caa4e80d4c879fe66524c88cc828d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7e5f0d0b0d12da231d365004a8f1e9248bb47f9d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpeq.h x32, x32, x32
+    cv.cmpeq.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f5e540083111d6b8be6c658a389472aa8b04efeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400007b          	cv.cmpeq.h	zero,zero,zero
+   4:	041080fb          	cv.cmpeq.h	ra,ra,ra
+   8:	0421017b          	cv.cmpeq.h	sp,sp,sp
+   c:	0484047b          	cv.cmpeq.h	s0,s0,s0
+  10:	054a0a7b          	cv.cmpeq.h	s4,s4,s4
+  14:	05ff8ffb          	cv.cmpeq.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..209aff817702ff10b473c00f3e69c7df11744d0d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpeq.h x0, x0, x0
+    cv.cmpeq.h x1, x1, x1
+    cv.cmpeq.h x2, x2, x2
+    cv.cmpeq.h x8, x8, x8
+    cv.cmpeq.h x20, x20, x20
+    cv.cmpeq.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e2fe218cdd429bdecd787337064ec37641a7031c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-b-fail.s
+#error_output: cv-simd-cmpeq-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..43c0f88c42b8acc1ce61ebac2c68fb4a5005f3b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e4923d9594382e69ec6bb387e8341c1f19baa39e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpeq.sc.b x32, x32, x32
+    cv.cmpeq.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..81d4ee3964cbb545b13d370aa431bdb03eede4fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400507b          	cv.cmpeq.sc.b	zero,zero,zero
+   4:	0410d0fb          	cv.cmpeq.sc.b	ra,ra,ra
+   8:	0421517b          	cv.cmpeq.sc.b	sp,sp,sp
+   c:	0484547b          	cv.cmpeq.sc.b	s0,s0,s0
+  10:	054a5a7b          	cv.cmpeq.sc.b	s4,s4,s4
+  14:	05ffdffb          	cv.cmpeq.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..a67ccd388e91817e8cb6d5fe6abadc741897cfa0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpeq.sc.b x0, x0, x0
+    cv.cmpeq.sc.b x1, x1, x1
+    cv.cmpeq.sc.b x2, x2, x2
+    cv.cmpeq.sc.b x8, x8, x8
+    cv.cmpeq.sc.b x20, x20, x20
+    cv.cmpeq.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..cc28bad796d65c1c47abe65fd844feb0d79c3ed1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-h-fail.s
+#error_output: cv-simd-cmpeq-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..13275a99112e892820bff9ef53c8767729216f6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c09e8c9fc214ecb68b5dd38d4f62a03b8d92ac82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpeq.sc.h x32, x32, x32
+    cv.cmpeq.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..11a5774ebc9eb366466efd5087f9a18c6afde5ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400407b          	cv.cmpeq.sc.h	zero,zero,zero
+   4:	0410c0fb          	cv.cmpeq.sc.h	ra,ra,ra
+   8:	0421417b          	cv.cmpeq.sc.h	sp,sp,sp
+   c:	0484447b          	cv.cmpeq.sc.h	s0,s0,s0
+  10:	054a4a7b          	cv.cmpeq.sc.h	s4,s4,s4
+  14:	05ffcffb          	cv.cmpeq.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f8f2c279618464c676a65228d777c01c6585723b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpeq.sc.h x0, x0, x0
+    cv.cmpeq.sc.h x1, x1, x1
+    cv.cmpeq.sc.h x2, x2, x2
+    cv.cmpeq.sc.h x8, x8, x8
+    cv.cmpeq.sc.h x20, x20, x20
+    cv.cmpeq.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..ee63eaa3a7c930cbadf05e2784122e1a6818524c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-b-fail.s
+#error_output: cv-simd-cmpeq-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0d488f66ce123394cb524f9234534397af81ca37
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpeq.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..eb02b37328425a6eb1ad5269adae8154f41cf853
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpeq.sci.b x32, x32, 20
+    cv.cmpeq.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpeq.sci.b x6, x7, -33
+    cv.cmpeq.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c0dead860d99f68ca16a155901b100002bd9b0ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	04a0707b          	cv.cmpeq.sci.b	zero,zero,20
+   4:	04a0f0fb          	cv.cmpeq.sci.b	ra,ra,20
+   8:	04a1717b          	cv.cmpeq.sci.b	sp,sp,20
+   c:	04a4747b          	cv.cmpeq.sci.b	s0,s0,20
+  10:	04aa7a7b          	cv.cmpeq.sci.b	s4,s4,20
+  14:	04affffb          	cv.cmpeq.sci.b	t6,t6,20
+  18:	0503f37b          	cv.cmpeq.sci.b	t1,t2,-32
+  1c:	0403f37b          	cv.cmpeq.sci.b	t1,t2,0
+  20:	06f3f37b          	cv.cmpeq.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..891c61def45497e1a4ff4583c3dad16deee80d23
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpeq.sci.b x0, x0, 20
+    cv.cmpeq.sci.b x1, x1, 20
+    cv.cmpeq.sci.b x2, x2, 20
+    cv.cmpeq.sci.b x8, x8, 20
+    cv.cmpeq.sci.b x20, x20, 20
+    cv.cmpeq.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpeq.sci.b x6, x7, -32
+    cv.cmpeq.sci.b x6, x7, 0
+    cv.cmpeq.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..878e99672f705ac31aa240da2d64e4dde1a82241
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-h-fail.s
+#error_output: cv-simd-cmpeq-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..77a6cd56bf16a578407cc923e56e7d5680d82f6b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpeq.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ece9bd5b297835ab375e850e62156015dda55dcc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpeq.sci.h x32, x32, 20
+    cv.cmpeq.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpeq.sci.h x6, x7, -33
+    cv.cmpeq.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..302d2f80cc3984fcbeb0870c2b995af13cf3ce64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	04a0607b          	cv.cmpeq.sci.h	zero,zero,20
+   4:	04a0e0fb          	cv.cmpeq.sci.h	ra,ra,20
+   8:	04a1617b          	cv.cmpeq.sci.h	sp,sp,20
+   c:	04a4647b          	cv.cmpeq.sci.h	s0,s0,20
+  10:	04aa6a7b          	cv.cmpeq.sci.h	s4,s4,20
+  14:	04afeffb          	cv.cmpeq.sci.h	t6,t6,20
+  18:	0503e37b          	cv.cmpeq.sci.h	t1,t2,-32
+  1c:	0403e37b          	cv.cmpeq.sci.h	t1,t2,0
+  20:	06f3e37b          	cv.cmpeq.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4eee62b625f2536bcd3028bce8eb1f9a5e4d38b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpeq.sci.h x0, x0, 20
+    cv.cmpeq.sci.h x1, x1, 20
+    cv.cmpeq.sci.h x2, x2, 20
+    cv.cmpeq.sci.h x8, x8, 20
+    cv.cmpeq.sci.h x20, x20, 20
+    cv.cmpeq.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpeq.sci.h x6, x7, -32
+    cv.cmpeq.sci.h x6, x7, 0
+    cv.cmpeq.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..644f83b569280b9d262b6a0b1bbf6998cb41fa73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-b-fail.s
+#error_output: cv-simd-cmpge-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a08e74fe104ffbb1f2252051730360c22df7995b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0d5a7453124ce670e1ec5a2462fc51d0366eddea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpge.b x32, x32, x32
+    cv.cmpge.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..029840c70d52679b2e1fc20d07b5c4cd7313326b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00107b          	cv.cmpge.b	zero,zero,zero
+   4:	1c1090fb          	cv.cmpge.b	ra,ra,ra
+   8:	1c21117b          	cv.cmpge.b	sp,sp,sp
+   c:	1c84147b          	cv.cmpge.b	s0,s0,s0
+  10:	1d4a1a7b          	cv.cmpge.b	s4,s4,s4
+  14:	1dff9ffb          	cv.cmpge.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..126d8b52de2c2db4dee2c39dfed70202eb16230d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpge.b x0, x0, x0
+    cv.cmpge.b x1, x1, x1
+    cv.cmpge.b x2, x2, x2
+    cv.cmpge.b x8, x8, x8
+    cv.cmpge.b x20, x20, x20
+    cv.cmpge.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..7b7d123aa74de3100fe91ddcee8182e7b1156fed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-h-fail.s
+#error_output: cv-simd-cmpge-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a9f0019ae9528c9ded6004b3ed21520c464ccb72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..650213a4591b7adcb556a023cae6c603cb78a7bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpge.h x32, x32, x32
+    cv.cmpge.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4ba0160c2548e2565f7d4fc612e78118400ef528
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00007b          	cv.cmpge.h	zero,zero,zero
+   4:	1c1080fb          	cv.cmpge.h	ra,ra,ra
+   8:	1c21017b          	cv.cmpge.h	sp,sp,sp
+   c:	1c84047b          	cv.cmpge.h	s0,s0,s0
+  10:	1d4a0a7b          	cv.cmpge.h	s4,s4,s4
+  14:	1dff8ffb          	cv.cmpge.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6a6dd7f6aecd6f6c329fc2363c9aa988fc5446b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpge.h x0, x0, x0
+    cv.cmpge.h x1, x1, x1
+    cv.cmpge.h x2, x2, x2
+    cv.cmpge.h x8, x8, x8
+    cv.cmpge.h x20, x20, x20
+    cv.cmpge.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..996cd49af1594184cffe22208e116cd6d2cc54e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-b-fail.s
+#error_output: cv-simd-cmpge-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..2d73720e32cfa940b916267e5fc409f17eefb2f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9c13024b08b1d954f383cef083a6d29e7635eec5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpge.sc.b x32, x32, x32
+    cv.cmpge.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f00943ab68e8e0f0e5bd7da3adfb791f587f301e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00507b          	cv.cmpge.sc.b	zero,zero,zero
+   4:	1c10d0fb          	cv.cmpge.sc.b	ra,ra,ra
+   8:	1c21517b          	cv.cmpge.sc.b	sp,sp,sp
+   c:	1c84547b          	cv.cmpge.sc.b	s0,s0,s0
+  10:	1d4a5a7b          	cv.cmpge.sc.b	s4,s4,s4
+  14:	1dffdffb          	cv.cmpge.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..d6a61c21eae441573fe2fc7eb15f374f6f0348d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpge.sc.b x0, x0, x0
+    cv.cmpge.sc.b x1, x1, x1
+    cv.cmpge.sc.b x2, x2, x2
+    cv.cmpge.sc.b x8, x8, x8
+    cv.cmpge.sc.b x20, x20, x20
+    cv.cmpge.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e74c232991a44842c2825e147fc20f7cadefe8c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-h-fail.s
+#error_output: cv-simd-cmpge-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..97c55e41c9083ce23de846b0ba58b8474ed4ea37
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..93bbb03db2ad8df6560f17c373e903bc41515e9d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpge.sc.h x32, x32, x32
+    cv.cmpge.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d44d2258a42ea24d8e98b14802e0b522106274b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00407b          	cv.cmpge.sc.h	zero,zero,zero
+   4:	1c10c0fb          	cv.cmpge.sc.h	ra,ra,ra
+   8:	1c21417b          	cv.cmpge.sc.h	sp,sp,sp
+   c:	1c84447b          	cv.cmpge.sc.h	s0,s0,s0
+  10:	1d4a4a7b          	cv.cmpge.sc.h	s4,s4,s4
+  14:	1dffcffb          	cv.cmpge.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1458f22df0648b3b992ec7abc776cb2ed1514312
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpge.sc.h x0, x0, x0
+    cv.cmpge.sc.h x1, x1, x1
+    cv.cmpge.sc.h x2, x2, x2
+    cv.cmpge.sc.h x8, x8, x8
+    cv.cmpge.sc.h x20, x20, x20
+    cv.cmpge.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..80122bf062d2b5fe0a0ead86fdc8b5d41693c06a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-b-fail.s
+#error_output: cv-simd-cmpge-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..cfebdde1262a4be066047b57840ee6bb6a5e211d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpge.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e87d0d2bbd78758ab85a6fe46fda9ac45bb7c123
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpge.sci.b x32, x32, 20
+    cv.cmpge.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpge.sci.b x6, x7, -33
+    cv.cmpge.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c7c0838d69e3bc9fee1b5e105766c3c64e84053f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1ca0707b          	cv.cmpge.sci.b	zero,zero,20
+   4:	1ca0f0fb          	cv.cmpge.sci.b	ra,ra,20
+   8:	1ca1717b          	cv.cmpge.sci.b	sp,sp,20
+   c:	1ca4747b          	cv.cmpge.sci.b	s0,s0,20
+  10:	1caa7a7b          	cv.cmpge.sci.b	s4,s4,20
+  14:	1caffffb          	cv.cmpge.sci.b	t6,t6,20
+  18:	1d03f37b          	cv.cmpge.sci.b	t1,t2,-32
+  1c:	1c03f37b          	cv.cmpge.sci.b	t1,t2,0
+  20:	1ef3f37b          	cv.cmpge.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f78c97537c81fb2cd9692720c63b13f8b2df1fec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpge.sci.b x0, x0, 20
+    cv.cmpge.sci.b x1, x1, 20
+    cv.cmpge.sci.b x2, x2, 20
+    cv.cmpge.sci.b x8, x8, 20
+    cv.cmpge.sci.b x20, x20, 20
+    cv.cmpge.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpge.sci.b x6, x7, -32
+    cv.cmpge.sci.b x6, x7, 0
+    cv.cmpge.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b5a66ffd965968de42b98173ca88798c5c9eb6f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-h-fail.s
+#error_output: cv-simd-cmpge-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b29956b0d6c6330a7c4e905334339c9e95a0eb29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpge.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..07ec29ce17f5c2b21f1b574ed58e5bda0d4b0818
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpge.sci.h x32, x32, 20
+    cv.cmpge.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpge.sci.h x6, x7, -33
+    cv.cmpge.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4651c97bf4c57138ac4755dc0a51f13077c44c73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1ca0607b          	cv.cmpge.sci.h	zero,zero,20
+   4:	1ca0e0fb          	cv.cmpge.sci.h	ra,ra,20
+   8:	1ca1617b          	cv.cmpge.sci.h	sp,sp,20
+   c:	1ca4647b          	cv.cmpge.sci.h	s0,s0,20
+  10:	1caa6a7b          	cv.cmpge.sci.h	s4,s4,20
+  14:	1cafeffb          	cv.cmpge.sci.h	t6,t6,20
+  18:	1d03e37b          	cv.cmpge.sci.h	t1,t2,-32
+  1c:	1c03e37b          	cv.cmpge.sci.h	t1,t2,0
+  20:	1ef3e37b          	cv.cmpge.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..0410c9bcfd93abbc7651fb90f3961ff58314779b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpge.sci.h x0, x0, 20
+    cv.cmpge.sci.h x1, x1, 20
+    cv.cmpge.sci.h x2, x2, 20
+    cv.cmpge.sci.h x8, x8, 20
+    cv.cmpge.sci.h x20, x20, 20
+    cv.cmpge.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpge.sci.h x6, x7, -32
+    cv.cmpge.sci.h x6, x7, 0
+    cv.cmpge.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..52fbe0058e438b0723098523fe4e001cb8f07581
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-b-fail.s
+#error_output: cv-simd-cmpgeu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a5765fd2abbeedfdb022b79614ab7a07ee65e4e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..92c5cdcd72b1327747eff3dde873763b90cd54d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgeu.b x32, x32, x32
+    cv.cmpgeu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..755a62d7636915d8cfbfa6344c3bf8799ce41a93
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00107b          	cv.cmpgeu.b	zero,zero,zero
+   4:	3c1090fb          	cv.cmpgeu.b	ra,ra,ra
+   8:	3c21117b          	cv.cmpgeu.b	sp,sp,sp
+   c:	3c84147b          	cv.cmpgeu.b	s0,s0,s0
+  10:	3d4a1a7b          	cv.cmpgeu.b	s4,s4,s4
+  14:	3dff9ffb          	cv.cmpgeu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..a5102117823cfe8248657fedb5a561c6d3aee95b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgeu.b x0, x0, x0
+    cv.cmpgeu.b x1, x1, x1
+    cv.cmpgeu.b x2, x2, x2
+    cv.cmpgeu.b x8, x8, x8
+    cv.cmpgeu.b x20, x20, x20
+    cv.cmpgeu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b026ee73432ea09fad76bc36dcbf4d58b339373a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-h-fail.s
+#error_output: cv-simd-cmpgeu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..237d1505e056e82d846137dc94f471fbd977b706
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e1f496e794b63c39dca883869b774ab14cfc4e40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgeu.h x32, x32, x32
+    cv.cmpgeu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ba0f05878ed369da2ea37903466637829899443a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00007b          	cv.cmpgeu.h	zero,zero,zero
+   4:	3c1080fb          	cv.cmpgeu.h	ra,ra,ra
+   8:	3c21017b          	cv.cmpgeu.h	sp,sp,sp
+   c:	3c84047b          	cv.cmpgeu.h	s0,s0,s0
+  10:	3d4a0a7b          	cv.cmpgeu.h	s4,s4,s4
+  14:	3dff8ffb          	cv.cmpgeu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..845f740d6630b46b8dc4d23355e592ded5347d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgeu.h x0, x0, x0
+    cv.cmpgeu.h x1, x1, x1
+    cv.cmpgeu.h x2, x2, x2
+    cv.cmpgeu.h x8, x8, x8
+    cv.cmpgeu.h x20, x20, x20
+    cv.cmpgeu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..92885ecc5a793e862f7a6e768e2a53e6217cc314
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-b-fail.s
+#error_output: cv-simd-cmpgeu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..d80803402ba6a6b4815ff3ad83a7126580d37beb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b2072fb84a9e0ff28a5376a0ed4020286f5c16b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgeu.sc.b x32, x32, x32
+    cv.cmpgeu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..11cf81d6cceb9fd81c2d2e737415c9500b55a009
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00507b          	cv.cmpgeu.sc.b	zero,zero,zero
+   4:	3c10d0fb          	cv.cmpgeu.sc.b	ra,ra,ra
+   8:	3c21517b          	cv.cmpgeu.sc.b	sp,sp,sp
+   c:	3c84547b          	cv.cmpgeu.sc.b	s0,s0,s0
+  10:	3d4a5a7b          	cv.cmpgeu.sc.b	s4,s4,s4
+  14:	3dffdffb          	cv.cmpgeu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..d9da9a8b4a645e91c9f25095e6614cad217a3ef7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgeu.sc.b x0, x0, x0
+    cv.cmpgeu.sc.b x1, x1, x1
+    cv.cmpgeu.sc.b x2, x2, x2
+    cv.cmpgeu.sc.b x8, x8, x8
+    cv.cmpgeu.sc.b x20, x20, x20
+    cv.cmpgeu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e8e302d2f8687e6a94231803c63200d2a4e1acdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-h-fail.s
+#error_output: cv-simd-cmpgeu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..711b5fd0a4f60308e89bf5838c4f7eaf33deebda
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..1c55aedb1c5fa6551018748c4f437355a9aab228
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgeu.sc.h x32, x32, x32
+    cv.cmpgeu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..145bff760d6870276077837d73982e7528263fb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00407b          	cv.cmpgeu.sc.h	zero,zero,zero
+   4:	3c10c0fb          	cv.cmpgeu.sc.h	ra,ra,ra
+   8:	3c21417b          	cv.cmpgeu.sc.h	sp,sp,sp
+   c:	3c84447b          	cv.cmpgeu.sc.h	s0,s0,s0
+  10:	3d4a4a7b          	cv.cmpgeu.sc.h	s4,s4,s4
+  14:	3dffcffb          	cv.cmpgeu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..98e27220e32316d9ec6b80fa8029fb186cd2187e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgeu.sc.h x0, x0, x0
+    cv.cmpgeu.sc.h x1, x1, x1
+    cv.cmpgeu.sc.h x2, x2, x2
+    cv.cmpgeu.sc.h x8, x8, x8
+    cv.cmpgeu.sc.h x20, x20, x20
+    cv.cmpgeu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..6f30fc63775732266195cd2492da416ff5660cef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-b-fail.s
+#error_output: cv-simd-cmpgeu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..199cf8e267728f21f9aba11e3e1de15d094f1d4b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgeu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6955651cd243910adf77c8fbd3fcd904951bcb09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgeu.sci.b x32, x32, 20
+    cv.cmpgeu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgeu.sci.b x6, x7, -1
+    cv.cmpgeu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..23bad539c546e7200f2a9b508f7f088f57fe786c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3ca0707b          	cv.cmpgeu.sci.b	zero,zero,20
+   4:	3ca0f0fb          	cv.cmpgeu.sci.b	ra,ra,20
+   8:	3ca1717b          	cv.cmpgeu.sci.b	sp,sp,20
+   c:	3ca4747b          	cv.cmpgeu.sci.b	s0,s0,20
+  10:	3caa7a7b          	cv.cmpgeu.sci.b	s4,s4,20
+  14:	3caffffb          	cv.cmpgeu.sci.b	t6,t6,20
+  18:	3c03f37b          	cv.cmpgeu.sci.b	t1,t2,0
+  1c:	3ff3f37b          	cv.cmpgeu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3daba991f75f12a20126b34876d740799fd8e10d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpgeu.sci.b x0, x0, 20
+    cv.cmpgeu.sci.b x1, x1, 20
+    cv.cmpgeu.sci.b x2, x2, 20
+    cv.cmpgeu.sci.b x8, x8, 20
+    cv.cmpgeu.sci.b x20, x20, 20
+    cv.cmpgeu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgeu.sci.b x6, x7, 0
+    cv.cmpgeu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..850860ea8555f5ada88e8b316d6799f9cb802ba0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-h-fail.s
+#error_output: cv-simd-cmpgeu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..81243bb67d0a2efd0daf0e9ccc776dcf0cd8e692
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgeu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6a18505bb39a5f733c322f3b096eb7803b733745
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgeu.sci.h x32, x32, 20
+    cv.cmpgeu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgeu.sci.h x6, x7, -1
+    cv.cmpgeu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8cfd2a472988bb7715f42e1acb2e4474f1d616ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3ca0607b          	cv.cmpgeu.sci.h	zero,zero,20
+   4:	3ca0e0fb          	cv.cmpgeu.sci.h	ra,ra,20
+   8:	3ca1617b          	cv.cmpgeu.sci.h	sp,sp,20
+   c:	3ca4647b          	cv.cmpgeu.sci.h	s0,s0,20
+  10:	3caa6a7b          	cv.cmpgeu.sci.h	s4,s4,20
+  14:	3cafeffb          	cv.cmpgeu.sci.h	t6,t6,20
+  18:	3c03e37b          	cv.cmpgeu.sci.h	t1,t2,0
+  1c:	3ff3e37b          	cv.cmpgeu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..dface2db869742a6131ede8b7b738bf65e506696
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpgeu.sci.h x0, x0, 20
+    cv.cmpgeu.sci.h x1, x1, 20
+    cv.cmpgeu.sci.h x2, x2, 20
+    cv.cmpgeu.sci.h x8, x8, 20
+    cv.cmpgeu.sci.h x20, x20, 20
+    cv.cmpgeu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgeu.sci.h x6, x7, 0
+    cv.cmpgeu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..06713e63512354bdc6b82ee8b4d4922fe613e112
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-b-fail.s
+#error_output: cv-simd-cmpgt-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4e68125dad43295d70e6f400ebc2df2be1dc1358
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6cf859be6d80370e9bff12b86a7d405ee9cc52b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgt.b x32, x32, x32
+    cv.cmpgt.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..daf50430a15c87f183f6042cc13dbac83db005c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400107b          	cv.cmpgt.b	zero,zero,zero
+   4:	141090fb          	cv.cmpgt.b	ra,ra,ra
+   8:	1421117b          	cv.cmpgt.b	sp,sp,sp
+   c:	1484147b          	cv.cmpgt.b	s0,s0,s0
+  10:	154a1a7b          	cv.cmpgt.b	s4,s4,s4
+  14:	15ff9ffb          	cv.cmpgt.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9f2f9a82321ebe25782552520a1659531dc3798c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgt.b x0, x0, x0
+    cv.cmpgt.b x1, x1, x1
+    cv.cmpgt.b x2, x2, x2
+    cv.cmpgt.b x8, x8, x8
+    cv.cmpgt.b x20, x20, x20
+    cv.cmpgt.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b1f8f066bb72bacaabd5879c13fbef94f2f635e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-h-fail.s
+#error_output: cv-simd-cmpgt-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9237078e20a0736078b432d20c82affb2ce29626
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5a371c9183b16ca262ea99b7325f30abdefbfbd9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgt.h x32, x32, x32
+    cv.cmpgt.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..74de9d8d350f3e5b91b3556e4b81a6ea6239ab0c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400007b          	cv.cmpgt.h	zero,zero,zero
+   4:	141080fb          	cv.cmpgt.h	ra,ra,ra
+   8:	1421017b          	cv.cmpgt.h	sp,sp,sp
+   c:	1484047b          	cv.cmpgt.h	s0,s0,s0
+  10:	154a0a7b          	cv.cmpgt.h	s4,s4,s4
+  14:	15ff8ffb          	cv.cmpgt.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..57ebba6ea322b7d291484db40f61eeaa47cfcb90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgt.h x0, x0, x0
+    cv.cmpgt.h x1, x1, x1
+    cv.cmpgt.h x2, x2, x2
+    cv.cmpgt.h x8, x8, x8
+    cv.cmpgt.h x20, x20, x20
+    cv.cmpgt.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8bf0da8cbe06ba7ed6a3e648ee481b4c3a9756e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-b-fail.s
+#error_output: cv-simd-cmpgt-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..526c0b90ba96bdc2ad6e2fc55a757a37081129f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..943b1fffa8f4b6d2205704a6e47dc0ac2526b579
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgt.sc.b x32, x32, x32
+    cv.cmpgt.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a724df267d7884e71e0a845c7d8ed84af1fd1d87
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400507b          	cv.cmpgt.sc.b	zero,zero,zero
+   4:	1410d0fb          	cv.cmpgt.sc.b	ra,ra,ra
+   8:	1421517b          	cv.cmpgt.sc.b	sp,sp,sp
+   c:	1484547b          	cv.cmpgt.sc.b	s0,s0,s0
+  10:	154a5a7b          	cv.cmpgt.sc.b	s4,s4,s4
+  14:	15ffdffb          	cv.cmpgt.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..64d3f2aac57c51fffaec5b662815fcfc90a274e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgt.sc.b x0, x0, x0
+    cv.cmpgt.sc.b x1, x1, x1
+    cv.cmpgt.sc.b x2, x2, x2
+    cv.cmpgt.sc.b x8, x8, x8
+    cv.cmpgt.sc.b x20, x20, x20
+    cv.cmpgt.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..03744bfd7064b0a40992038104b8cae37f225042
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-h-fail.s
+#error_output: cv-simd-cmpgt-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..e13663d6149fb7e240bdac2b2906331816e0e01d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a218dae2ff9bd6b32b1e4bc505193211273a8538
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgt.sc.h x32, x32, x32
+    cv.cmpgt.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ea7792b141123703d41267ae10007cc6dda6f463
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400407b          	cv.cmpgt.sc.h	zero,zero,zero
+   4:	1410c0fb          	cv.cmpgt.sc.h	ra,ra,ra
+   8:	1421417b          	cv.cmpgt.sc.h	sp,sp,sp
+   c:	1484447b          	cv.cmpgt.sc.h	s0,s0,s0
+  10:	154a4a7b          	cv.cmpgt.sc.h	s4,s4,s4
+  14:	15ffcffb          	cv.cmpgt.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1571837994b4bc8335227531cd5f1a3c906f5bff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgt.sc.h x0, x0, x0
+    cv.cmpgt.sc.h x1, x1, x1
+    cv.cmpgt.sc.h x2, x2, x2
+    cv.cmpgt.sc.h x8, x8, x8
+    cv.cmpgt.sc.h x20, x20, x20
+    cv.cmpgt.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2919d4bb629abe75a72a683d3bd49153b800c869
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-b-fail.s
+#error_output: cv-simd-cmpgt-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0afcded817f341d82c999d47bee84a6cb141d616
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgt.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..24eede735b51bda2eea59e5cb00ffe3622ac0709
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgt.sci.b x32, x32, 20
+    cv.cmpgt.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgt.sci.b x6, x7, -33
+    cv.cmpgt.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..da3734fc1dcf0d7cb623b4664aab7c778b4f64ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	14a0707b          	cv.cmpgt.sci.b	zero,zero,20
+   4:	14a0f0fb          	cv.cmpgt.sci.b	ra,ra,20
+   8:	14a1717b          	cv.cmpgt.sci.b	sp,sp,20
+   c:	14a4747b          	cv.cmpgt.sci.b	s0,s0,20
+  10:	14aa7a7b          	cv.cmpgt.sci.b	s4,s4,20
+  14:	14affffb          	cv.cmpgt.sci.b	t6,t6,20
+  18:	1503f37b          	cv.cmpgt.sci.b	t1,t2,-32
+  1c:	1403f37b          	cv.cmpgt.sci.b	t1,t2,0
+  20:	16f3f37b          	cv.cmpgt.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..62b1dae3c958b1a125ebdb70bc815be5b5f704a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpgt.sci.b x0, x0, 20
+    cv.cmpgt.sci.b x1, x1, 20
+    cv.cmpgt.sci.b x2, x2, 20
+    cv.cmpgt.sci.b x8, x8, 20
+    cv.cmpgt.sci.b x20, x20, 20
+    cv.cmpgt.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgt.sci.b x6, x7, -32
+    cv.cmpgt.sci.b x6, x7, 0
+    cv.cmpgt.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..c90370a2788d065edf088d6e7460ae3392d260cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-h-fail.s
+#error_output: cv-simd-cmpgt-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..cb3234ffa5dc714ba5cbeb5838d5b72702b1fc22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgt.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..080c6f85615613fe66f6ec7081b77304176a37df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgt.sci.h x32, x32, 20
+    cv.cmpgt.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgt.sci.h x6, x7, -33
+    cv.cmpgt.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..844dc76a0205867e251323a8c10cc209d258048b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	14a0607b          	cv.cmpgt.sci.h	zero,zero,20
+   4:	14a0e0fb          	cv.cmpgt.sci.h	ra,ra,20
+   8:	14a1617b          	cv.cmpgt.sci.h	sp,sp,20
+   c:	14a4647b          	cv.cmpgt.sci.h	s0,s0,20
+  10:	14aa6a7b          	cv.cmpgt.sci.h	s4,s4,20
+  14:	14afeffb          	cv.cmpgt.sci.h	t6,t6,20
+  18:	1503e37b          	cv.cmpgt.sci.h	t1,t2,-32
+  1c:	1403e37b          	cv.cmpgt.sci.h	t1,t2,0
+  20:	16f3e37b          	cv.cmpgt.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7b0722efa313bf35aa22cd8d35cd6094b2212dd9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpgt.sci.h x0, x0, 20
+    cv.cmpgt.sci.h x1, x1, 20
+    cv.cmpgt.sci.h x2, x2, 20
+    cv.cmpgt.sci.h x8, x8, 20
+    cv.cmpgt.sci.h x20, x20, 20
+    cv.cmpgt.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgt.sci.h x6, x7, -32
+    cv.cmpgt.sci.h x6, x7, 0
+    cv.cmpgt.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..63ee1bdc4bd33ccc5db0b2f1a083564df768cf7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-b-fail.s
+#error_output: cv-simd-cmpgtu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..dec5965c1488324ba4bf8a5f303cd51c4688dfe0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..bb12cf5f7b88ace1ad04d2d8c5c45f0953fedd14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgtu.b x32, x32, x32
+    cv.cmpgtu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5d3aa8d7ff5a806bfa9c547c5caeea94ec4e1c9f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400107b          	cv.cmpgtu.b	zero,zero,zero
+   4:	341090fb          	cv.cmpgtu.b	ra,ra,ra
+   8:	3421117b          	cv.cmpgtu.b	sp,sp,sp
+   c:	3484147b          	cv.cmpgtu.b	s0,s0,s0
+  10:	354a1a7b          	cv.cmpgtu.b	s4,s4,s4
+  14:	35ff9ffb          	cv.cmpgtu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e5d782a39fb8abfae680004b11ed6d6deff85c30
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgtu.b x0, x0, x0
+    cv.cmpgtu.b x1, x1, x1
+    cv.cmpgtu.b x2, x2, x2
+    cv.cmpgtu.b x8, x8, x8
+    cv.cmpgtu.b x20, x20, x20
+    cv.cmpgtu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fb528c575088a8f064bcc5bc6a33fcb4e2ac9457
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-h-fail.s
+#error_output: cv-simd-cmpgtu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..09b6b0c67fb4b5d0a3ae2594eeceb13da153f6ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..091f250ea419ee9f1b17d5bdacbf7efdcea26d06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgtu.h x32, x32, x32
+    cv.cmpgtu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a08da4ff5b29885f7e1a1e4d4ab50e3579ff7d22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400007b          	cv.cmpgtu.h	zero,zero,zero
+   4:	341080fb          	cv.cmpgtu.h	ra,ra,ra
+   8:	3421017b          	cv.cmpgtu.h	sp,sp,sp
+   c:	3484047b          	cv.cmpgtu.h	s0,s0,s0
+  10:	354a0a7b          	cv.cmpgtu.h	s4,s4,s4
+  14:	35ff8ffb          	cv.cmpgtu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..0abafa19fb2622275cf21e467a11bc2b85a8072c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgtu.h x0, x0, x0
+    cv.cmpgtu.h x1, x1, x1
+    cv.cmpgtu.h x2, x2, x2
+    cv.cmpgtu.h x8, x8, x8
+    cv.cmpgtu.h x20, x20, x20
+    cv.cmpgtu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..cebe6125b5c86cfd16c74654f6288eb69caee0c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-b-fail.s
+#error_output: cv-simd-cmpgtu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..8e61b4687f9ffc419f540382bbba72c635393ac5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0a443a7a17a423973e4251bf9ee8cab40b60e0db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgtu.sc.b x32, x32, x32
+    cv.cmpgtu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..cfbe16753df61cd8cc87393466c0b6075c788983
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400507b          	cv.cmpgtu.sc.b	zero,zero,zero
+   4:	3410d0fb          	cv.cmpgtu.sc.b	ra,ra,ra
+   8:	3421517b          	cv.cmpgtu.sc.b	sp,sp,sp
+   c:	3484547b          	cv.cmpgtu.sc.b	s0,s0,s0
+  10:	354a5a7b          	cv.cmpgtu.sc.b	s4,s4,s4
+  14:	35ffdffb          	cv.cmpgtu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..d8e0fbd37ec188020bc4a0b3e236bf6980d306f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgtu.sc.b x0, x0, x0
+    cv.cmpgtu.sc.b x1, x1, x1
+    cv.cmpgtu.sc.b x2, x2, x2
+    cv.cmpgtu.sc.b x8, x8, x8
+    cv.cmpgtu.sc.b x20, x20, x20
+    cv.cmpgtu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3dfb1d87383cc056381c419aa43bf74ad0a23320
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-h-fail.s
+#error_output: cv-simd-cmpgtu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..db82748d2ab4f5f3b5131d7c46eb658e13cb2e95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..cfe448a8400b6a668c1219cd5c4a63488bc0c50d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgtu.sc.h x32, x32, x32
+    cv.cmpgtu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..46f600935f640e340ceb10ce5193e3387d0b1765
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400407b          	cv.cmpgtu.sc.h	zero,zero,zero
+   4:	3410c0fb          	cv.cmpgtu.sc.h	ra,ra,ra
+   8:	3421417b          	cv.cmpgtu.sc.h	sp,sp,sp
+   c:	3484447b          	cv.cmpgtu.sc.h	s0,s0,s0
+  10:	354a4a7b          	cv.cmpgtu.sc.h	s4,s4,s4
+  14:	35ffcffb          	cv.cmpgtu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..615a7aad62e2e9dc431dfe57405102ff3eb855df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpgtu.sc.h x0, x0, x0
+    cv.cmpgtu.sc.h x1, x1, x1
+    cv.cmpgtu.sc.h x2, x2, x2
+    cv.cmpgtu.sc.h x8, x8, x8
+    cv.cmpgtu.sc.h x20, x20, x20
+    cv.cmpgtu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..511d8b716534053fb8bd76df5fdc8094913f4e13
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-b-fail.s
+#error_output: cv-simd-cmpgtu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..765eb803d777901eb54fc1978f37382b70cc30fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgtu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ad185f999cc317aff7ed6bb663e6409ee28e6bee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgtu.sci.b x32, x32, 20
+    cv.cmpgtu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgtu.sci.b x6, x7, -1
+    cv.cmpgtu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8e23044594437be3838d05c1b565e7a3f519e2a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	34a0707b          	cv.cmpgtu.sci.b	zero,zero,20
+   4:	34a0f0fb          	cv.cmpgtu.sci.b	ra,ra,20
+   8:	34a1717b          	cv.cmpgtu.sci.b	sp,sp,20
+   c:	34a4747b          	cv.cmpgtu.sci.b	s0,s0,20
+  10:	34aa7a7b          	cv.cmpgtu.sci.b	s4,s4,20
+  14:	34affffb          	cv.cmpgtu.sci.b	t6,t6,20
+  18:	3403f37b          	cv.cmpgtu.sci.b	t1,t2,0
+  1c:	37f3f37b          	cv.cmpgtu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3ce3f202013a1e1b2c783cf4f68d9d87972a430f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpgtu.sci.b x0, x0, 20
+    cv.cmpgtu.sci.b x1, x1, 20
+    cv.cmpgtu.sci.b x2, x2, 20
+    cv.cmpgtu.sci.b x8, x8, 20
+    cv.cmpgtu.sci.b x20, x20, 20
+    cv.cmpgtu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgtu.sci.b x6, x7, 0
+    cv.cmpgtu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..7813fc68442a351b641cbebbc20a756cc24b69da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-h-fail.s
+#error_output: cv-simd-cmpgtu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..424630562ee615c4cdac5dc434fd0f3996e3c9aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgtu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..dcddabad478bac07610fa01f6c0fd10c1e8ca0b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpgtu.sci.h x32, x32, 20
+    cv.cmpgtu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgtu.sci.h x6, x7, -1
+    cv.cmpgtu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..9f7ea98e3fa908a3ed0ce60ccc4b49802b79807c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	34a0607b          	cv.cmpgtu.sci.h	zero,zero,20
+   4:	34a0e0fb          	cv.cmpgtu.sci.h	ra,ra,20
+   8:	34a1617b          	cv.cmpgtu.sci.h	sp,sp,20
+   c:	34a4647b          	cv.cmpgtu.sci.h	s0,s0,20
+  10:	34aa6a7b          	cv.cmpgtu.sci.h	s4,s4,20
+  14:	34afeffb          	cv.cmpgtu.sci.h	t6,t6,20
+  18:	3403e37b          	cv.cmpgtu.sci.h	t1,t2,0
+  1c:	37f3e37b          	cv.cmpgtu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..45772b22ecebf4493755fa061a392b3d425cb8f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpgtu.sci.h x0, x0, 20
+    cv.cmpgtu.sci.h x1, x1, 20
+    cv.cmpgtu.sci.h x2, x2, 20
+    cv.cmpgtu.sci.h x8, x8, 20
+    cv.cmpgtu.sci.h x20, x20, 20
+    cv.cmpgtu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgtu.sci.h x6, x7, 0
+    cv.cmpgtu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a6907dd5a958c9dba4495a68309e57a7005cc4a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-b-fail.s
+#error_output: cv-simd-cmple-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c1ce1e95e57f0ceb14d6ab2c8eac6f5f1709c8e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..50277474e665f13a652c848860e776c7eb86c120
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmple.b x32, x32, x32
+    cv.cmple.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..927374db6cf0f2a1ab1d63dad07e1e66b82b279e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00107b          	cv.cmple.b	zero,zero,zero
+   4:	2c1090fb          	cv.cmple.b	ra,ra,ra
+   8:	2c21117b          	cv.cmple.b	sp,sp,sp
+   c:	2c84147b          	cv.cmple.b	s0,s0,s0
+  10:	2d4a1a7b          	cv.cmple.b	s4,s4,s4
+  14:	2dff9ffb          	cv.cmple.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..fdf4eb245f92c85706732f280ba2b42d9088f5bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmple.b x0, x0, x0
+    cv.cmple.b x1, x1, x1
+    cv.cmple.b x2, x2, x2
+    cv.cmple.b x8, x8, x8
+    cv.cmple.b x20, x20, x20
+    cv.cmple.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..bbc68c94565bdc0271b7849bf5a842a62f2fac5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-h-fail.s
+#error_output: cv-simd-cmple-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..90dc4e90829143fac1a57e96784959458baf143a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..3cee9fff6ef76d82fc023ac142a15ca85a91f4ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmple.h x32, x32, x32
+    cv.cmple.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b98c0094d42b97b6e1142adf09d66e6338a5b62a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00007b          	cv.cmple.h	zero,zero,zero
+   4:	2c1080fb          	cv.cmple.h	ra,ra,ra
+   8:	2c21017b          	cv.cmple.h	sp,sp,sp
+   c:	2c84047b          	cv.cmple.h	s0,s0,s0
+  10:	2d4a0a7b          	cv.cmple.h	s4,s4,s4
+  14:	2dff8ffb          	cv.cmple.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..35c2c462cc73973c42c8a6483413393da0df18e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmple.h x0, x0, x0
+    cv.cmple.h x1, x1, x1
+    cv.cmple.h x2, x2, x2
+    cv.cmple.h x8, x8, x8
+    cv.cmple.h x20, x20, x20
+    cv.cmple.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..74c37e5f187720ed7584c5eeb1664cd320dbb760
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-b-fail.s
+#error_output: cv-simd-cmple-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..74b287452ea6663623a6cffb4db8874fc91e3004
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..32deb90d22db2c995affc53870f4b7ee1831fcc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmple.sc.b x32, x32, x32
+    cv.cmple.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..00120c978624ffac1aa37d2d55294e32c6ad7733
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00507b          	cv.cmple.sc.b	zero,zero,zero
+   4:	2c10d0fb          	cv.cmple.sc.b	ra,ra,ra
+   8:	2c21517b          	cv.cmple.sc.b	sp,sp,sp
+   c:	2c84547b          	cv.cmple.sc.b	s0,s0,s0
+  10:	2d4a5a7b          	cv.cmple.sc.b	s4,s4,s4
+  14:	2dffdffb          	cv.cmple.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..45b55184e03b49da7d725e2f9a35c446c37fdb02
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmple.sc.b x0, x0, x0
+    cv.cmple.sc.b x1, x1, x1
+    cv.cmple.sc.b x2, x2, x2
+    cv.cmple.sc.b x8, x8, x8
+    cv.cmple.sc.b x20, x20, x20
+    cv.cmple.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..86ba75fde128a8f7db6470705ab94f24fdf3414c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-h-fail.s
+#error_output: cv-simd-cmple-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..781dcb28e9a29bbcd845ff86bcaeb031a2ed4cb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..8a480a2c4e4738579700e115b7543d26fd89238b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmple.sc.h x32, x32, x32
+    cv.cmple.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..750cf51f0fdead80484e9dafddc3926b311e3bba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00407b          	cv.cmple.sc.h	zero,zero,zero
+   4:	2c10c0fb          	cv.cmple.sc.h	ra,ra,ra
+   8:	2c21417b          	cv.cmple.sc.h	sp,sp,sp
+   c:	2c84447b          	cv.cmple.sc.h	s0,s0,s0
+  10:	2d4a4a7b          	cv.cmple.sc.h	s4,s4,s4
+  14:	2dffcffb          	cv.cmple.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..719bd8652bff24b538922c0b35d5c64499bf19b7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmple.sc.h x0, x0, x0
+    cv.cmple.sc.h x1, x1, x1
+    cv.cmple.sc.h x2, x2, x2
+    cv.cmple.sc.h x8, x8, x8
+    cv.cmple.sc.h x20, x20, x20
+    cv.cmple.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..92aaddd59ff9984aa53e957271e103880912e3fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-b-fail.s
+#error_output: cv-simd-cmple-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..6fbc895b3ea3f2e2f626244631e9428801242084
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmple.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7b461b9ce787c0b77b90da7f961b9851e7ee85ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmple.sci.b x32, x32, 20
+    cv.cmple.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmple.sci.b x6, x7, -33
+    cv.cmple.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c9851df4ad5923a43854576a89fe24caad0da4f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2ca0707b          	cv.cmple.sci.b	zero,zero,20
+   4:	2ca0f0fb          	cv.cmple.sci.b	ra,ra,20
+   8:	2ca1717b          	cv.cmple.sci.b	sp,sp,20
+   c:	2ca4747b          	cv.cmple.sci.b	s0,s0,20
+  10:	2caa7a7b          	cv.cmple.sci.b	s4,s4,20
+  14:	2caffffb          	cv.cmple.sci.b	t6,t6,20
+  18:	2d03f37b          	cv.cmple.sci.b	t1,t2,-32
+  1c:	2c03f37b          	cv.cmple.sci.b	t1,t2,0
+  20:	2ef3f37b          	cv.cmple.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..8db8a1e3568fd5dbfbc0570bc48d40774d2753b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmple.sci.b x0, x0, 20
+    cv.cmple.sci.b x1, x1, 20
+    cv.cmple.sci.b x2, x2, 20
+    cv.cmple.sci.b x8, x8, 20
+    cv.cmple.sci.b x20, x20, 20
+    cv.cmple.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmple.sci.b x6, x7, -32
+    cv.cmple.sci.b x6, x7, 0
+    cv.cmple.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..30002602360ea5b93a4f8cfb0a55d4a196af1416
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-h-fail.s
+#error_output: cv-simd-cmple-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ccbf473dbd3dc5c45f4d75bf0fa4f71c9a277b1d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmple.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7e8beb8dfae68133c35ead1a78116a8bedcebd90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmple.sci.h x32, x32, 20
+    cv.cmple.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmple.sci.h x6, x7, -33
+    cv.cmple.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0a10894d659f67f4606253cf0dce16dffe0507a1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2ca0607b          	cv.cmple.sci.h	zero,zero,20
+   4:	2ca0e0fb          	cv.cmple.sci.h	ra,ra,20
+   8:	2ca1617b          	cv.cmple.sci.h	sp,sp,20
+   c:	2ca4647b          	cv.cmple.sci.h	s0,s0,20
+  10:	2caa6a7b          	cv.cmple.sci.h	s4,s4,20
+  14:	2cafeffb          	cv.cmple.sci.h	t6,t6,20
+  18:	2d03e37b          	cv.cmple.sci.h	t1,t2,-32
+  1c:	2c03e37b          	cv.cmple.sci.h	t1,t2,0
+  20:	2ef3e37b          	cv.cmple.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..83031daecf2dc9d2524b4d4c5faef4b6b0ffc63d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmple.sci.h x0, x0, 20
+    cv.cmple.sci.h x1, x1, 20
+    cv.cmple.sci.h x2, x2, 20
+    cv.cmple.sci.h x8, x8, 20
+    cv.cmple.sci.h x20, x20, 20
+    cv.cmple.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmple.sci.h x6, x7, -32
+    cv.cmple.sci.h x6, x7, 0
+    cv.cmple.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..635991b60972e32ac2c16016eb3e70b6e4783baa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-b-fail.s
+#error_output: cv-simd-cmpleu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..906bb044ca7790a245e5c2c6bcb59a846e091369
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..4635be74d748a90d271ba56cdd5cf632c4b5d9bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpleu.b x32, x32, x32
+    cv.cmpleu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8cb04f5a11ae5d277970a7ed51105ca322f8d703
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00107b          	cv.cmpleu.b	zero,zero,zero
+   4:	4c1090fb          	cv.cmpleu.b	ra,ra,ra
+   8:	4c21117b          	cv.cmpleu.b	sp,sp,sp
+   c:	4c84147b          	cv.cmpleu.b	s0,s0,s0
+  10:	4d4a1a7b          	cv.cmpleu.b	s4,s4,s4
+  14:	4dff9ffb          	cv.cmpleu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7762ca7ab7d58beb168173a11ef963e2c11151a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpleu.b x0, x0, x0
+    cv.cmpleu.b x1, x1, x1
+    cv.cmpleu.b x2, x2, x2
+    cv.cmpleu.b x8, x8, x8
+    cv.cmpleu.b x20, x20, x20
+    cv.cmpleu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f2a3d69363c2e1e6f57e97c9382568b3a0bf040b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-h-fail.s
+#error_output: cv-simd-cmpleu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1bcab7179eb037f43003bcf8fe8d01074380f558
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2de8808711a584ef34bf4e0c1414e92a2bccf2b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpleu.h x32, x32, x32
+    cv.cmpleu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..88510d9e8229f3dece027561c3313789268b4d72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00007b          	cv.cmpleu.h	zero,zero,zero
+   4:	4c1080fb          	cv.cmpleu.h	ra,ra,ra
+   8:	4c21017b          	cv.cmpleu.h	sp,sp,sp
+   c:	4c84047b          	cv.cmpleu.h	s0,s0,s0
+  10:	4d4a0a7b          	cv.cmpleu.h	s4,s4,s4
+  14:	4dff8ffb          	cv.cmpleu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3b2ac7beaed699100d20fd47d91ec89b1e653d75
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpleu.h x0, x0, x0
+    cv.cmpleu.h x1, x1, x1
+    cv.cmpleu.h x2, x2, x2
+    cv.cmpleu.h x8, x8, x8
+    cv.cmpleu.h x20, x20, x20
+    cv.cmpleu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3dbb33176789d3e179b731bb31f050592c3f70d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-b-fail.s
+#error_output: cv-simd-cmpleu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..5fde1fae238c6a8f15b945dfd0ad7b84e2b0ad9c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5cd69fd76a4bd9b3ac3a856a67de97e21812a6b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpleu.sc.b x32, x32, x32
+    cv.cmpleu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..25200479d3547da15765f66f69a7bdf2c26993f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00507b          	cv.cmpleu.sc.b	zero,zero,zero
+   4:	4c10d0fb          	cv.cmpleu.sc.b	ra,ra,ra
+   8:	4c21517b          	cv.cmpleu.sc.b	sp,sp,sp
+   c:	4c84547b          	cv.cmpleu.sc.b	s0,s0,s0
+  10:	4d4a5a7b          	cv.cmpleu.sc.b	s4,s4,s4
+  14:	4dffdffb          	cv.cmpleu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5a99d7b127c15512fd0fbff8a7a1e91857829523
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpleu.sc.b x0, x0, x0
+    cv.cmpleu.sc.b x1, x1, x1
+    cv.cmpleu.sc.b x2, x2, x2
+    cv.cmpleu.sc.b x8, x8, x8
+    cv.cmpleu.sc.b x20, x20, x20
+    cv.cmpleu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..9ddd9d42c7b2333602ff4272ceb181d138f0c9ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-h-fail.s
+#error_output: cv-simd-cmpleu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..11438240a92599e7f95b50ac836202fd7ac5d7e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..632933d7e6313ecab603762b7b512b20b5b70a31
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpleu.sc.h x32, x32, x32
+    cv.cmpleu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..acbfa417945149af4581ef1859c96de5755e4ee3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00407b          	cv.cmpleu.sc.h	zero,zero,zero
+   4:	4c10c0fb          	cv.cmpleu.sc.h	ra,ra,ra
+   8:	4c21417b          	cv.cmpleu.sc.h	sp,sp,sp
+   c:	4c84447b          	cv.cmpleu.sc.h	s0,s0,s0
+  10:	4d4a4a7b          	cv.cmpleu.sc.h	s4,s4,s4
+  14:	4dffcffb          	cv.cmpleu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..762af31e6e2ae1144043e46f19e78bb976560aa4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpleu.sc.h x0, x0, x0
+    cv.cmpleu.sc.h x1, x1, x1
+    cv.cmpleu.sc.h x2, x2, x2
+    cv.cmpleu.sc.h x8, x8, x8
+    cv.cmpleu.sc.h x20, x20, x20
+    cv.cmpleu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..81a56d4c797f3614e6840eff044104bc339630ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-b-fail.s
+#error_output: cv-simd-cmpleu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..589af59d74e167ce8db4389528295ce5a94d2ce6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpleu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..10cff6aa7e9ca16a68d4218cd70614d523a42db0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpleu.sci.b x32, x32, 20
+    cv.cmpleu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpleu.sci.b x6, x7, -1
+    cv.cmpleu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8a0ac6cbdfc946c143e8da3100ab1672b195079d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4ca0707b          	cv.cmpleu.sci.b	zero,zero,20
+   4:	4ca0f0fb          	cv.cmpleu.sci.b	ra,ra,20
+   8:	4ca1717b          	cv.cmpleu.sci.b	sp,sp,20
+   c:	4ca4747b          	cv.cmpleu.sci.b	s0,s0,20
+  10:	4caa7a7b          	cv.cmpleu.sci.b	s4,s4,20
+  14:	4caffffb          	cv.cmpleu.sci.b	t6,t6,20
+  18:	4c03f37b          	cv.cmpleu.sci.b	t1,t2,0
+  1c:	4ff3f37b          	cv.cmpleu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..18b39b9a503decc7aad3cc3ad6fa0dccabb32173
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpleu.sci.b x0, x0, 20
+    cv.cmpleu.sci.b x1, x1, 20
+    cv.cmpleu.sci.b x2, x2, 20
+    cv.cmpleu.sci.b x8, x8, 20
+    cv.cmpleu.sci.b x20, x20, 20
+    cv.cmpleu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpleu.sci.b x6, x7, 0
+    cv.cmpleu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..34a81b5cd8a40610618eaed59b7152c1259f24c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-h-fail.s
+#error_output: cv-simd-cmpleu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a7969bb4db211009a69b93ea00160493430c6e18
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpleu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..28c094b0ba89d877078a9aebe536b9439fcb9f4b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpleu.sci.h x32, x32, 20
+    cv.cmpleu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpleu.sci.h x6, x7, -1
+    cv.cmpleu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..83ca67a305e5ce500c307e9845cde4fd72f66a9c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4ca0607b          	cv.cmpleu.sci.h	zero,zero,20
+   4:	4ca0e0fb          	cv.cmpleu.sci.h	ra,ra,20
+   8:	4ca1617b          	cv.cmpleu.sci.h	sp,sp,20
+   c:	4ca4647b          	cv.cmpleu.sci.h	s0,s0,20
+  10:	4caa6a7b          	cv.cmpleu.sci.h	s4,s4,20
+  14:	4cafeffb          	cv.cmpleu.sci.h	t6,t6,20
+  18:	4c03e37b          	cv.cmpleu.sci.h	t1,t2,0
+  1c:	4ff3e37b          	cv.cmpleu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e554c9c7df34d9b7ee870313cb8a46fff3f40f75
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpleu.sci.h x0, x0, 20
+    cv.cmpleu.sci.h x1, x1, 20
+    cv.cmpleu.sci.h x2, x2, 20
+    cv.cmpleu.sci.h x8, x8, 20
+    cv.cmpleu.sci.h x20, x20, 20
+    cv.cmpleu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpleu.sci.h x6, x7, 0
+    cv.cmpleu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..242b75786d65acea89579f5344bea8d928d9da56
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-b-fail.s
+#error_output: cv-simd-cmplt-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0f98b08b92e8fe0e90efe99bdf0df6feed7549ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a9d537f3a0e63b3f24cc66f2b2540ce611627b92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmplt.b x32, x32, x32
+    cv.cmplt.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..90d4f22903e3b4f8430a2263debf13c7daf916eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400107b          	cv.cmplt.b	zero,zero,zero
+   4:	241090fb          	cv.cmplt.b	ra,ra,ra
+   8:	2421117b          	cv.cmplt.b	sp,sp,sp
+   c:	2484147b          	cv.cmplt.b	s0,s0,s0
+  10:	254a1a7b          	cv.cmplt.b	s4,s4,s4
+  14:	25ff9ffb          	cv.cmplt.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9f45e2e18c0ae7dca2dc00ac8d0f756d180dd0ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmplt.b x0, x0, x0
+    cv.cmplt.b x1, x1, x1
+    cv.cmplt.b x2, x2, x2
+    cv.cmplt.b x8, x8, x8
+    cv.cmplt.b x20, x20, x20
+    cv.cmplt.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fddea37a26f78beb7e9d22a433f0155077975751
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-h-fail.s
+#error_output: cv-simd-cmplt-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b2c5298e1e3890d177354080afaea5da2013236e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0726a8edb5d8ac8476dc9cf8e3c98bce531de74f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmplt.h x32, x32, x32
+    cv.cmplt.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..42b980e670e2b453614b89a0f9e68bb98cf2d50d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400007b          	cv.cmplt.h	zero,zero,zero
+   4:	241080fb          	cv.cmplt.h	ra,ra,ra
+   8:	2421017b          	cv.cmplt.h	sp,sp,sp
+   c:	2484047b          	cv.cmplt.h	s0,s0,s0
+  10:	254a0a7b          	cv.cmplt.h	s4,s4,s4
+  14:	25ff8ffb          	cv.cmplt.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1c7cdac3adacf5278a1481461cccac095b8480f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmplt.h x0, x0, x0
+    cv.cmplt.h x1, x1, x1
+    cv.cmplt.h x2, x2, x2
+    cv.cmplt.h x8, x8, x8
+    cv.cmplt.h x20, x20, x20
+    cv.cmplt.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..20491b47b117e9698072d1bad6d74d2735c96ee0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-b-fail.s
+#error_output: cv-simd-cmplt-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..bc8340f218b506c3c9c9037a4337d470b04bc99e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..625d424590c9ef7560be3b8e90c0a7f702cbaffb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmplt.sc.b x32, x32, x32
+    cv.cmplt.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..58dc2cc24589ad1d11fb8e9e5ad3162684f28d1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400507b          	cv.cmplt.sc.b	zero,zero,zero
+   4:	2410d0fb          	cv.cmplt.sc.b	ra,ra,ra
+   8:	2421517b          	cv.cmplt.sc.b	sp,sp,sp
+   c:	2484547b          	cv.cmplt.sc.b	s0,s0,s0
+  10:	254a5a7b          	cv.cmplt.sc.b	s4,s4,s4
+  14:	25ffdffb          	cv.cmplt.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f1220c4781c8d31da48b655b17136a3043f0ef78
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmplt.sc.b x0, x0, x0
+    cv.cmplt.sc.b x1, x1, x1
+    cv.cmplt.sc.b x2, x2, x2
+    cv.cmplt.sc.b x8, x8, x8
+    cv.cmplt.sc.b x20, x20, x20
+    cv.cmplt.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..9aa9ab6b6eead5ef5af17e27c11ce46d60d76ea0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-h-fail.s
+#error_output: cv-simd-cmplt-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9d7c9e054799f70bba420c5ede35bfb37b536af4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ae4a89cbb5e238e9082084a3924d8de837c4a8b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmplt.sc.h x32, x32, x32
+    cv.cmplt.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c3a5de547e3c64f6db4207603f61ae355ff18dd9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400407b          	cv.cmplt.sc.h	zero,zero,zero
+   4:	2410c0fb          	cv.cmplt.sc.h	ra,ra,ra
+   8:	2421417b          	cv.cmplt.sc.h	sp,sp,sp
+   c:	2484447b          	cv.cmplt.sc.h	s0,s0,s0
+  10:	254a4a7b          	cv.cmplt.sc.h	s4,s4,s4
+  14:	25ffcffb          	cv.cmplt.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2955c8393afc8fc3fd5378d6fb0bcde872207e11
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmplt.sc.h x0, x0, x0
+    cv.cmplt.sc.h x1, x1, x1
+    cv.cmplt.sc.h x2, x2, x2
+    cv.cmplt.sc.h x8, x8, x8
+    cv.cmplt.sc.h x20, x20, x20
+    cv.cmplt.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f678f979ab37ab8de5bde4f2e0ff699424315d79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-b-fail.s
+#error_output: cv-simd-cmplt-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..2d5cdad6b800c285eca11206778fb03e4294bec3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmplt.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..95ffaa84598ce72f54aa5fcf123bad8b71be69d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmplt.sci.b x32, x32, 20
+    cv.cmplt.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmplt.sci.b x6, x7, -33
+    cv.cmplt.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..7ff96089553087b51f8670d9e8b484c2d9c70b83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	24a0707b          	cv.cmplt.sci.b	zero,zero,20
+   4:	24a0f0fb          	cv.cmplt.sci.b	ra,ra,20
+   8:	24a1717b          	cv.cmplt.sci.b	sp,sp,20
+   c:	24a4747b          	cv.cmplt.sci.b	s0,s0,20
+  10:	24aa7a7b          	cv.cmplt.sci.b	s4,s4,20
+  14:	24affffb          	cv.cmplt.sci.b	t6,t6,20
+  18:	2503f37b          	cv.cmplt.sci.b	t1,t2,-32
+  1c:	2403f37b          	cv.cmplt.sci.b	t1,t2,0
+  20:	26f3f37b          	cv.cmplt.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f6037aca241b0e3184f599402038d86da7ffc6be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmplt.sci.b x0, x0, 20
+    cv.cmplt.sci.b x1, x1, 20
+    cv.cmplt.sci.b x2, x2, 20
+    cv.cmplt.sci.b x8, x8, 20
+    cv.cmplt.sci.b x20, x20, 20
+    cv.cmplt.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmplt.sci.b x6, x7, -32
+    cv.cmplt.sci.b x6, x7, 0
+    cv.cmplt.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..094b86805e48af9c73cac8919e67286aaff0e6d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-h-fail.s
+#error_output: cv-simd-cmplt-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..6be7bcaf461c55de84de8cef7156c021b792fdab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmplt.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..8094f165b019ffb95c45599eae65e321f33e388b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmplt.sci.h x32, x32, 20
+    cv.cmplt.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmplt.sci.h x6, x7, -33
+    cv.cmplt.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..74831942dc155f73c12fea6512a8ad1c41d6dcbc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	24a0607b          	cv.cmplt.sci.h	zero,zero,20
+   4:	24a0e0fb          	cv.cmplt.sci.h	ra,ra,20
+   8:	24a1617b          	cv.cmplt.sci.h	sp,sp,20
+   c:	24a4647b          	cv.cmplt.sci.h	s0,s0,20
+  10:	24aa6a7b          	cv.cmplt.sci.h	s4,s4,20
+  14:	24afeffb          	cv.cmplt.sci.h	t6,t6,20
+  18:	2503e37b          	cv.cmplt.sci.h	t1,t2,-32
+  1c:	2403e37b          	cv.cmplt.sci.h	t1,t2,0
+  20:	26f3e37b          	cv.cmplt.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..0b83b1ba472e985f31971e848455d78bb28262fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmplt.sci.h x0, x0, 20
+    cv.cmplt.sci.h x1, x1, 20
+    cv.cmplt.sci.h x2, x2, 20
+    cv.cmplt.sci.h x8, x8, 20
+    cv.cmplt.sci.h x20, x20, 20
+    cv.cmplt.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmplt.sci.h x6, x7, -32
+    cv.cmplt.sci.h x6, x7, 0
+    cv.cmplt.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0050c0dfcbcc4371834e062ce3c7443614c940cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-b-fail.s
+#error_output: cv-simd-cmpltu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..199b24d2c5ee19a111c9558b5a2df88ad22fadc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5e1a3a8ea127b77f7417874a358d5ea0edb10680
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpltu.b x32, x32, x32
+    cv.cmpltu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ae5e5d804c48da2c13035c6eeddeb666b7271d49
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400107b          	cv.cmpltu.b	zero,zero,zero
+   4:	441090fb          	cv.cmpltu.b	ra,ra,ra
+   8:	4421117b          	cv.cmpltu.b	sp,sp,sp
+   c:	4484147b          	cv.cmpltu.b	s0,s0,s0
+  10:	454a1a7b          	cv.cmpltu.b	s4,s4,s4
+  14:	45ff9ffb          	cv.cmpltu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..0b0ee26947c297dc75cd748a96000b76476ffa91
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpltu.b x0, x0, x0
+    cv.cmpltu.b x1, x1, x1
+    cv.cmpltu.b x2, x2, x2
+    cv.cmpltu.b x8, x8, x8
+    cv.cmpltu.b x20, x20, x20
+    cv.cmpltu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b37c94721eed34dce20597883493c9bbac86fa53
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-h-fail.s
+#error_output: cv-simd-cmpltu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7ec17d16181fe7bda6337f9ccf2652a24948cb8b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9aa13b92603365dec0f5980f0693d18b02ef076a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpltu.h x32, x32, x32
+    cv.cmpltu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4c15ec5cc45c4dad0dfd539581bfdef24d5177e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400007b          	cv.cmpltu.h	zero,zero,zero
+   4:	441080fb          	cv.cmpltu.h	ra,ra,ra
+   8:	4421017b          	cv.cmpltu.h	sp,sp,sp
+   c:	4484047b          	cv.cmpltu.h	s0,s0,s0
+  10:	454a0a7b          	cv.cmpltu.h	s4,s4,s4
+  14:	45ff8ffb          	cv.cmpltu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c39a583ba732fa3c64ff9ac096bfc652166d158f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpltu.h x0, x0, x0
+    cv.cmpltu.h x1, x1, x1
+    cv.cmpltu.h x2, x2, x2
+    cv.cmpltu.h x8, x8, x8
+    cv.cmpltu.h x20, x20, x20
+    cv.cmpltu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..50bab346eecd4c500dd6d8671d8d0ff7f500403b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-b-fail.s
+#error_output: cv-simd-cmpltu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0b4c9992e7f41a056fdb54a33ec2c073f7117a44
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..15ec07644d91b39b44859c069152285a9673e9eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpltu.sc.b x32, x32, x32
+    cv.cmpltu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..3aa01db8faad7173e124de275554520f4fdabd94
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400507b          	cv.cmpltu.sc.b	zero,zero,zero
+   4:	4410d0fb          	cv.cmpltu.sc.b	ra,ra,ra
+   8:	4421517b          	cv.cmpltu.sc.b	sp,sp,sp
+   c:	4484547b          	cv.cmpltu.sc.b	s0,s0,s0
+  10:	454a5a7b          	cv.cmpltu.sc.b	s4,s4,s4
+  14:	45ffdffb          	cv.cmpltu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..65383b469ba85e6f530ab9d58d8c01e623dd34dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpltu.sc.b x0, x0, x0
+    cv.cmpltu.sc.b x1, x1, x1
+    cv.cmpltu.sc.b x2, x2, x2
+    cv.cmpltu.sc.b x8, x8, x8
+    cv.cmpltu.sc.b x20, x20, x20
+    cv.cmpltu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8422ac02345118f65e09c4749a18aa1264db6cd2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-h-fail.s
+#error_output: cv-simd-cmpltu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..aa73e2dd5e16dab21fb7da76058ca146966d517d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0cd45cc2ca55f31fc341aa10a764421866b45ee5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpltu.sc.h x32, x32, x32
+    cv.cmpltu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6437841a4fa8f21e522569749646e93750b5fb96
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400407b          	cv.cmpltu.sc.h	zero,zero,zero
+   4:	4410c0fb          	cv.cmpltu.sc.h	ra,ra,ra
+   8:	4421417b          	cv.cmpltu.sc.h	sp,sp,sp
+   c:	4484447b          	cv.cmpltu.sc.h	s0,s0,s0
+  10:	454a4a7b          	cv.cmpltu.sc.h	s4,s4,s4
+  14:	45ffcffb          	cv.cmpltu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6dc3ad7e8473e584918d7ccb3a93cfb989ed1b26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpltu.sc.h x0, x0, x0
+    cv.cmpltu.sc.h x1, x1, x1
+    cv.cmpltu.sc.h x2, x2, x2
+    cv.cmpltu.sc.h x8, x8, x8
+    cv.cmpltu.sc.h x20, x20, x20
+    cv.cmpltu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..ed3751de4798800bc3e3b5db8a11864028dc2a7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-b-fail.s
+#error_output: cv-simd-cmpltu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..810a82147fabd9a8fb0a186b32b3d2028353fffb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpltu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..38366b77c2396a6b7ba0e62b9c8fcacefa8b6c31
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpltu.sci.b x32, x32, 20
+    cv.cmpltu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpltu.sci.b x6, x7, -1
+    cv.cmpltu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..2ff3f7dc5fac18a814aa176d3cffc416a49f8885
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	44a0707b          	cv.cmpltu.sci.b	zero,zero,20
+   4:	44a0f0fb          	cv.cmpltu.sci.b	ra,ra,20
+   8:	44a1717b          	cv.cmpltu.sci.b	sp,sp,20
+   c:	44a4747b          	cv.cmpltu.sci.b	s0,s0,20
+  10:	44aa7a7b          	cv.cmpltu.sci.b	s4,s4,20
+  14:	44affffb          	cv.cmpltu.sci.b	t6,t6,20
+  18:	4403f37b          	cv.cmpltu.sci.b	t1,t2,0
+  1c:	47f3f37b          	cv.cmpltu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f1cfc54b99f1ac4d35d4e8565321f05893cd3ee1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpltu.sci.b x0, x0, 20
+    cv.cmpltu.sci.b x1, x1, 20
+    cv.cmpltu.sci.b x2, x2, 20
+    cv.cmpltu.sci.b x8, x8, 20
+    cv.cmpltu.sci.b x20, x20, 20
+    cv.cmpltu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpltu.sci.b x6, x7, 0
+    cv.cmpltu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..4b4a7bee8805320009549d42ce8f8ae4707d6a42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-h-fail.s
+#error_output: cv-simd-cmpltu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..73a451bfcccac3e7ca76b58beff26d4ea0dab48a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpltu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..d34d0e0d59315bbd05c276b9db93bc280b28a31c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpltu.sci.h x32, x32, 20
+    cv.cmpltu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpltu.sci.h x6, x7, -1
+    cv.cmpltu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5c59dce3e5438f58b151be3addaa840010a0dbf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	44a0607b          	cv.cmpltu.sci.h	zero,zero,20
+   4:	44a0e0fb          	cv.cmpltu.sci.h	ra,ra,20
+   8:	44a1617b          	cv.cmpltu.sci.h	sp,sp,20
+   c:	44a4647b          	cv.cmpltu.sci.h	s0,s0,20
+  10:	44aa6a7b          	cv.cmpltu.sci.h	s4,s4,20
+  14:	44afeffb          	cv.cmpltu.sci.h	t6,t6,20
+  18:	4403e37b          	cv.cmpltu.sci.h	t1,t2,0
+  1c:	47f3e37b          	cv.cmpltu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..d7f2cf1bd3450c286f8e6accb4b388525c6bbd0f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.cmpltu.sci.h x0, x0, 20
+    cv.cmpltu.sci.h x1, x1, 20
+    cv.cmpltu.sci.h x2, x2, 20
+    cv.cmpltu.sci.h x8, x8, 20
+    cv.cmpltu.sci.h x20, x20, 20
+    cv.cmpltu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpltu.sci.h x6, x7, 0
+    cv.cmpltu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..51af5dec96365559c5b1e96631edb6e77b94d5ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-b-fail.s
+#error_output: cv-simd-cmpne-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..17dd8aad0d5566327bde86d76fed32e051d015d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..233113481ac91437eebe9f677f970a733a18f214
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpne.b x32, x32, x32
+    cv.cmpne.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8d034c7e505e26cda14690d9d387c346672be10f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00107b          	cv.cmpne.b	zero,zero,zero
+   4:	0c1090fb          	cv.cmpne.b	ra,ra,ra
+   8:	0c21117b          	cv.cmpne.b	sp,sp,sp
+   c:	0c84147b          	cv.cmpne.b	s0,s0,s0
+  10:	0d4a1a7b          	cv.cmpne.b	s4,s4,s4
+  14:	0dff9ffb          	cv.cmpne.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1aa74bbcaa34cf1651b8d75162a859bafd85f4f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpne.b x0, x0, x0
+    cv.cmpne.b x1, x1, x1
+    cv.cmpne.b x2, x2, x2
+    cv.cmpne.b x8, x8, x8
+    cv.cmpne.b x20, x20, x20
+    cv.cmpne.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..624ccd8aaaa51862de004d3f95fbae30753fca2a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-h-fail.s
+#error_output: cv-simd-cmpne-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0b53e8f593c9a70d96b611baac1138e2f69e87d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e071346366899ee4f45c741d640b9942ee4e9001
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpne.h x32, x32, x32
+    cv.cmpne.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..029e561a41e248f20103e5ff14a726b59b7d7f17
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00007b          	cv.cmpne.h	zero,zero,zero
+   4:	0c1080fb          	cv.cmpne.h	ra,ra,ra
+   8:	0c21017b          	cv.cmpne.h	sp,sp,sp
+   c:	0c84047b          	cv.cmpne.h	s0,s0,s0
+  10:	0d4a0a7b          	cv.cmpne.h	s4,s4,s4
+  14:	0dff8ffb          	cv.cmpne.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..19fbad0f6c1cf5af5f6526319ace6423adbc88ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpne.h x0, x0, x0
+    cv.cmpne.h x1, x1, x1
+    cv.cmpne.h x2, x2, x2
+    cv.cmpne.h x8, x8, x8
+    cv.cmpne.h x20, x20, x20
+    cv.cmpne.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..aff55fbae53410c51171372bd393209bb8d3e19e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-b-fail.s
+#error_output: cv-simd-cmpne-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..24afd89655890db7138c50061f53f7cb2261c618
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..90d11e545a74bbd4c80c2a10fee11720ea7855b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpne.sc.b x32, x32, x32
+    cv.cmpne.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..503ca16c0e591a4895a9f97f245c8f3fe2632e8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00507b          	cv.cmpne.sc.b	zero,zero,zero
+   4:	0c10d0fb          	cv.cmpne.sc.b	ra,ra,ra
+   8:	0c21517b          	cv.cmpne.sc.b	sp,sp,sp
+   c:	0c84547b          	cv.cmpne.sc.b	s0,s0,s0
+  10:	0d4a5a7b          	cv.cmpne.sc.b	s4,s4,s4
+  14:	0dffdffb          	cv.cmpne.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..576e327fbc1835cf53f4b11916ce671a1b9964a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpne.sc.b x0, x0, x0
+    cv.cmpne.sc.b x1, x1, x1
+    cv.cmpne.sc.b x2, x2, x2
+    cv.cmpne.sc.b x8, x8, x8
+    cv.cmpne.sc.b x20, x20, x20
+    cv.cmpne.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fc715061d72ea6383bd62ed18e01433a86335d27
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-h-fail.s
+#error_output: cv-simd-cmpne-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..34854ac8eeecc6e24275b6ef4ca6bf8685a1a2e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..3a14c6acb87b2eac904a0e5129d2a1495984ed09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpne.sc.h x32, x32, x32
+    cv.cmpne.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5d36594c891cb394f309a4b5d20cd83ab424fcfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00407b          	cv.cmpne.sc.h	zero,zero,zero
+   4:	0c10c0fb          	cv.cmpne.sc.h	ra,ra,ra
+   8:	0c21417b          	cv.cmpne.sc.h	sp,sp,sp
+   c:	0c84447b          	cv.cmpne.sc.h	s0,s0,s0
+  10:	0d4a4a7b          	cv.cmpne.sc.h	s4,s4,s4
+  14:	0dffcffb          	cv.cmpne.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..25f87fe96266ed5e6203c1b0c2f22abd0585d663
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cmpne.sc.h x0, x0, x0
+    cv.cmpne.sc.h x1, x1, x1
+    cv.cmpne.sc.h x2, x2, x2
+    cv.cmpne.sc.h x8, x8, x8
+    cv.cmpne.sc.h x20, x20, x20
+    cv.cmpne.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..83e37b667931f4c604c4ef897f96b634b064d9f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-b-fail.s
+#error_output: cv-simd-cmpne-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9ad1b198f54f6eda7755c4e966eb7ebf9d6df710
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpne.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a1b8fe168e8fb26728962e1dcfe670ce92a46381
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpne.sci.b x32, x32, 20
+    cv.cmpne.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpne.sci.b x6, x7, -33
+    cv.cmpne.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0c20249d25e5760f1a6575df2a0c527f11455d31
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0ca0707b          	cv.cmpne.sci.b	zero,zero,20
+   4:	0ca0f0fb          	cv.cmpne.sci.b	ra,ra,20
+   8:	0ca1717b          	cv.cmpne.sci.b	sp,sp,20
+   c:	0ca4747b          	cv.cmpne.sci.b	s0,s0,20
+  10:	0caa7a7b          	cv.cmpne.sci.b	s4,s4,20
+  14:	0caffffb          	cv.cmpne.sci.b	t6,t6,20
+  18:	0d03f37b          	cv.cmpne.sci.b	t1,t2,-32
+  1c:	0c03f37b          	cv.cmpne.sci.b	t1,t2,0
+  20:	0ef3f37b          	cv.cmpne.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..301a3a024dc4e9a9b36b77d341a7e716a40c5172
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpne.sci.b x0, x0, 20
+    cv.cmpne.sci.b x1, x1, 20
+    cv.cmpne.sci.b x2, x2, 20
+    cv.cmpne.sci.b x8, x8, 20
+    cv.cmpne.sci.b x20, x20, 20
+    cv.cmpne.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpne.sci.b x6, x7, -32
+    cv.cmpne.sci.b x6, x7, 0
+    cv.cmpne.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0a2f50e59c416c7062a9bfc2021a6fe6454fd971
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-h-fail.s
+#error_output: cv-simd-cmpne-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..eba861843c8a16b607b65b29660e78ce197e8c69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpne.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6a1f2f7dd6fa84a620ded72222cd480ac8fe04e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.cmpne.sci.h x32, x32, 20
+    cv.cmpne.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpne.sci.h x6, x7, -33
+    cv.cmpne.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..19a3e4cfe7315281d9b94c40f03e5afb4327678e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0ca0607b          	cv.cmpne.sci.h	zero,zero,20
+   4:	0ca0e0fb          	cv.cmpne.sci.h	ra,ra,20
+   8:	0ca1617b          	cv.cmpne.sci.h	sp,sp,20
+   c:	0ca4647b          	cv.cmpne.sci.h	s0,s0,20
+  10:	0caa6a7b          	cv.cmpne.sci.h	s4,s4,20
+  14:	0cafeffb          	cv.cmpne.sci.h	t6,t6,20
+  18:	0d03e37b          	cv.cmpne.sci.h	t1,t2,-32
+  1c:	0c03e37b          	cv.cmpne.sci.h	t1,t2,0
+  20:	0ef3e37b          	cv.cmpne.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..984ded1e0903170268fd21d585f0b6c8c33d0cef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.cmpne.sci.h x0, x0, 20
+    cv.cmpne.sci.h x1, x1, 20
+    cv.cmpne.sci.h x2, x2, 20
+    cv.cmpne.sci.h x8, x8, 20
+    cv.cmpne.sci.h x20, x20, 20
+    cv.cmpne.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpne.sci.h x6, x7, -32
+    cv.cmpne.sci.h x6, x7, 0
+    cv.cmpne.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a0605a093091be3fc32160e351b785f12cb2c724
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxconj-fail.s
+#error_output: cv-simd-cplxconj-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ed0844fae23382ec5b3e8282c9785332218420ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxconj x32,x32'
+.*: Error: illegal operands `cv.cplxconj x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..04e3716485bba81177714dffcb9a14c7ef5f96b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxconj x32, x32
+    cv.cplxconj x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c380f769cf8af940292042a9a821854717b12bad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxconj-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5c00007b          	cv.cplxconj	zero,zero
+   4:	5c0080fb          	cv.cplxconj	ra,ra
+   8:	5c01017b          	cv.cplxconj	sp,sp
+   c:	5c04047b          	cv.cplxconj	s0,s0
+  10:	5c0a0a7b          	cv.cplxconj	s4,s4
+  14:	5c0f8ffb          	cv.cplxconj	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..36b163b8d08f46e4b89ea298f9d16f48e748a640
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxconj x0, x0
+    cv.cplxconj x1, x1
+    cv.cplxconj x2, x2
+    cv.cplxconj x8, x8
+    cv.cplxconj x20, x20
+    cv.cplxconj x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..7fb7a62b8a04208e6d5d80463727fd1f9786d0e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div2-fail.s
+#error_output: cv-simd-cplxmul-i-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9af5157824dee564ed90bd3d4c1c7a6d13920e44
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..d6fa16ff4f1a65122718a2b5f028a9a9e935fd9e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.i.div2 x32, x32, x32
+    cv.cplxmul.i.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..582b2c63c1e90b066eb431135e3bdb9e3709e227
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600207b          	cv.cplxmul.i.div2	zero,zero,zero
+   4:	5610a0fb          	cv.cplxmul.i.div2	ra,ra,ra
+   8:	5621217b          	cv.cplxmul.i.div2	sp,sp,sp
+   c:	5684247b          	cv.cplxmul.i.div2	s0,s0,s0
+  10:	574a2a7b          	cv.cplxmul.i.div2	s4,s4,s4
+  14:	57ffaffb          	cv.cplxmul.i.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4eb89da921c4ae8295cae1655d3aa554c6b62a25
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.i.div2 x0, x0, x0
+    cv.cplxmul.i.div2 x1, x1, x1
+    cv.cplxmul.i.div2 x2, x2, x2
+    cv.cplxmul.i.div2 x8, x8, x8
+    cv.cplxmul.i.div2 x20, x20, x20
+    cv.cplxmul.i.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e9b9062f17ee6f45bcbb31aaf140a6370b02af76
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div4-fail.s
+#error_output: cv-simd-cplxmul-i-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c3efbe053ebc18002490a68490bd719959c352db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e5ea2fc45fd12928df276a8574b7f75ad2d4c8e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.i.div4 x32, x32, x32
+    cv.cplxmul.i.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..1091785e9511f268cff67ff4ffbf3c8ae98bdf60
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600407b          	cv.cplxmul.i.div4	zero,zero,zero
+   4:	5610c0fb          	cv.cplxmul.i.div4	ra,ra,ra
+   8:	5621417b          	cv.cplxmul.i.div4	sp,sp,sp
+   c:	5684447b          	cv.cplxmul.i.div4	s0,s0,s0
+  10:	574a4a7b          	cv.cplxmul.i.div4	s4,s4,s4
+  14:	57ffcffb          	cv.cplxmul.i.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5d96c06e72d47f17fefa93ceac20da33836c5342
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.i.div4 x0, x0, x0
+    cv.cplxmul.i.div4 x1, x1, x1
+    cv.cplxmul.i.div4 x2, x2, x2
+    cv.cplxmul.i.div4 x8, x8, x8
+    cv.cplxmul.i.div4 x20, x20, x20
+    cv.cplxmul.i.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a5959794dfe0f98efcbd1c810428a6e1e6e75cf6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div8-fail.s
+#error_output: cv-simd-cplxmul-i-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..cc52645bf80bc3d1206d0d91f045730596f017eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..bcd458cd249d37c878699cf6838156c4ad200e0b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.i.div8 x32, x32, x32
+    cv.cplxmul.i.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c81a1dc7c8ec0d800c09523f70e515a9b047a175
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600607b          	cv.cplxmul.i.div8	zero,zero,zero
+   4:	5610e0fb          	cv.cplxmul.i.div8	ra,ra,ra
+   8:	5621617b          	cv.cplxmul.i.div8	sp,sp,sp
+   c:	5684647b          	cv.cplxmul.i.div8	s0,s0,s0
+  10:	574a6a7b          	cv.cplxmul.i.div8	s4,s4,s4
+  14:	57ffeffb          	cv.cplxmul.i.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f01268fb5c0576b8f6936a709661bfb1733ecae1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.i.div8 x0, x0, x0
+    cv.cplxmul.i.div8 x1, x1, x1
+    cv.cplxmul.i.div8 x2, x2, x2
+    cv.cplxmul.i.div8 x8, x8, x8
+    cv.cplxmul.i.div8 x20, x20, x20
+    cv.cplxmul.i.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..5a1f3f4025b0add3173beafac74e85fa2aafbec1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-fail.s
+#error_output: cv-simd-cplxmul-i-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4d63c3d02b5315b4d2d3379467686f3354a6dd75
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..3b1cd653850d99b98123e154f1c5153b8cb349d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.i x32, x32, x32
+    cv.cplxmul.i x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4c346bde03d86857f58b87a536588b09d018e587
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600007b          	cv.cplxmul.i	zero,zero,zero
+   4:	561080fb          	cv.cplxmul.i	ra,ra,ra
+   8:	5621017b          	cv.cplxmul.i	sp,sp,sp
+   c:	5684047b          	cv.cplxmul.i	s0,s0,s0
+  10:	574a0a7b          	cv.cplxmul.i	s4,s4,s4
+  14:	57ff8ffb          	cv.cplxmul.i	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1384fa157b1707302c5bd45549029edbc9d92815
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.i x0, x0, x0
+    cv.cplxmul.i x1, x1, x1
+    cv.cplxmul.i x2, x2, x2
+    cv.cplxmul.i x8, x8, x8
+    cv.cplxmul.i x20, x20, x20
+    cv.cplxmul.i x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..329cfbdf65ed1f199dc5f9bc1f06aa71632e59f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div2-fail.s
+#error_output: cv-simd-cplxmul-r-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0f6c70cbaa197a782ba22be841241ea123ed292a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a88cc6b3c73bcaa248378b348cec3fec348cb17a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.r.div2 x32, x32, x32
+    cv.cplxmul.r.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c8e8e61b55ee7ce8306254af5be3ad7e25c78cb6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400207b          	cv.cplxmul.r.div2	zero,zero,zero
+   4:	5410a0fb          	cv.cplxmul.r.div2	ra,ra,ra
+   8:	5421217b          	cv.cplxmul.r.div2	sp,sp,sp
+   c:	5484247b          	cv.cplxmul.r.div2	s0,s0,s0
+  10:	554a2a7b          	cv.cplxmul.r.div2	s4,s4,s4
+  14:	55ffaffb          	cv.cplxmul.r.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..48d694098cc7a0dc8db14d062afed0bb7ea9837f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.r.div2 x0, x0, x0
+    cv.cplxmul.r.div2 x1, x1, x1
+    cv.cplxmul.r.div2 x2, x2, x2
+    cv.cplxmul.r.div2 x8, x8, x8
+    cv.cplxmul.r.div2 x20, x20, x20
+    cv.cplxmul.r.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e1dd762124de6b589d0136f3692b162cca0f50c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div4-fail.s
+#error_output: cv-simd-cplxmul-r-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3fa875f7a3c8bbc1c0737b9fb9d267a4f7ce3c4b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..1af6d1192abd30d59cd9e16c8abaeac7f9a7f8a1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.r.div4 x32, x32, x32
+    cv.cplxmul.r.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..3f99541f5bdd53dee811eb8e6ce7cb10fbd6bcde
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400407b          	cv.cplxmul.r.div4	zero,zero,zero
+   4:	5410c0fb          	cv.cplxmul.r.div4	ra,ra,ra
+   8:	5421417b          	cv.cplxmul.r.div4	sp,sp,sp
+   c:	5484447b          	cv.cplxmul.r.div4	s0,s0,s0
+  10:	554a4a7b          	cv.cplxmul.r.div4	s4,s4,s4
+  14:	55ffcffb          	cv.cplxmul.r.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5729b88b45d4030b5edcf169c883b9994292527d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.r.div4 x0, x0, x0
+    cv.cplxmul.r.div4 x1, x1, x1
+    cv.cplxmul.r.div4 x2, x2, x2
+    cv.cplxmul.r.div4 x8, x8, x8
+    cv.cplxmul.r.div4 x20, x20, x20
+    cv.cplxmul.r.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..02b11f312285dc9f4f0173e66698fdd5840114fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div8-fail.s
+#error_output: cv-simd-cplxmul-r-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ba8c9752dad7eafed977b712e342cf4b8c5b29ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..47cdfbe15da277c09ffc54a2153b1a160c20464a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.r.div8 x32, x32, x32
+    cv.cplxmul.r.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..cdc13e64fcd03a10c3404c3958380dfe51a7a01b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400607b          	cv.cplxmul.r.div8	zero,zero,zero
+   4:	5410e0fb          	cv.cplxmul.r.div8	ra,ra,ra
+   8:	5421617b          	cv.cplxmul.r.div8	sp,sp,sp
+   c:	5484647b          	cv.cplxmul.r.div8	s0,s0,s0
+  10:	554a6a7b          	cv.cplxmul.r.div8	s4,s4,s4
+  14:	55ffeffb          	cv.cplxmul.r.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9c29967f4af2394a5db14f4f25bc8196037a44e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.r.div8 x0, x0, x0
+    cv.cplxmul.r.div8 x1, x1, x1
+    cv.cplxmul.r.div8 x2, x2, x2
+    cv.cplxmul.r.div8 x8, x8, x8
+    cv.cplxmul.r.div8 x20, x20, x20
+    cv.cplxmul.r.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..ee4480a46e77bcff6c98e1add20ad240c4e8b899
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-fail.s
+#error_output: cv-simd-cplxmul-r-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..f3f3a9cc5429484081004023814c3c79c396917c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..64b3b0d158bf7ea3d9d379bd71a1e745eb9c64ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.cplxmul.r x32, x32, x32
+    cv.cplxmul.r x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d8f8c7ab0d8a83cdc0de0b94ba45ccd3e45eed54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400007b          	cv.cplxmul.r	zero,zero,zero
+   4:	541080fb          	cv.cplxmul.r	ra,ra,ra
+   8:	5421017b          	cv.cplxmul.r	sp,sp,sp
+   c:	5484047b          	cv.cplxmul.r	s0,s0,s0
+  10:	554a0a7b          	cv.cplxmul.r	s4,s4,s4
+  14:	55ff8ffb          	cv.cplxmul.r	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..8f588e7edee90e5145cdcb47c31c64f6fd200990
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.cplxmul.r x0, x0, x0
+    cv.cplxmul.r x1, x1, x1
+    cv.cplxmul.r x2, x2, x2
+    cv.cplxmul.r x8, x8, x8
+    cv.cplxmul.r x20, x20, x20
+    cv.cplxmul.r x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..78a375e025f279514b5832d3046e2cdc0f373195
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-b-fail.s
+#error_output: cv-simd-dotsp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..05e061341487696b8acccaa186dd1122a81b1d92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..233872c9e037221f40d294de44c2555021baa7ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotsp.b x32, x32, x32
+    cv.dotsp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..43fb568fe05b49db83b18a10c86366f9f268367a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000107b          	cv.dotsp.b	zero,zero,zero
+   4:	901090fb          	cv.dotsp.b	ra,ra,ra
+   8:	9021117b          	cv.dotsp.b	sp,sp,sp
+   c:	9084147b          	cv.dotsp.b	s0,s0,s0
+  10:	914a1a7b          	cv.dotsp.b	s4,s4,s4
+  14:	91ff9ffb          	cv.dotsp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e42ccef2344af43dc92db886d49cbaced5c73f9c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotsp.b x0, x0, x0
+    cv.dotsp.b x1, x1, x1
+    cv.dotsp.b x2, x2, x2
+    cv.dotsp.b x8, x8, x8
+    cv.dotsp.b x20, x20, x20
+    cv.dotsp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..cb8ba2656fb69e85a3fe2bc4fbb049c6951bdb40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-h-fail.s
+#error_output: cv-simd-dotsp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9a4969c3e922006d769a597c735dc63cf55443b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..309d96733e47b094218aa978409382da322017fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotsp.h x32, x32, x32
+    cv.dotsp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b6ee73a3f15199ce0593218252e9bc1d25016bfb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000007b          	cv.dotsp.h	zero,zero,zero
+   4:	901080fb          	cv.dotsp.h	ra,ra,ra
+   8:	9021017b          	cv.dotsp.h	sp,sp,sp
+   c:	9084047b          	cv.dotsp.h	s0,s0,s0
+  10:	914a0a7b          	cv.dotsp.h	s4,s4,s4
+  14:	91ff8ffb          	cv.dotsp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b9d49cbbfc564aa61dcd392c432fe4581cdb6dd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotsp.h x0, x0, x0
+    cv.dotsp.h x1, x1, x1
+    cv.dotsp.h x2, x2, x2
+    cv.dotsp.h x8, x8, x8
+    cv.dotsp.h x20, x20, x20
+    cv.dotsp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..cd9ffacc679a8e575242487bb54133dadd34ba63
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-b-fail.s
+#error_output: cv-simd-dotsp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..f08b9016d620e39c9eee6f240907b04f34ba82cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b45e83cfc31bb34d9c3d6e86417139d6539eea33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotsp.sc.b x32, x32, x32
+    cv.dotsp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d318e9030eb30e19d1c009f8fc4f8523f5570445
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000507b          	cv.dotsp.sc.b	zero,zero,zero
+   4:	9010d0fb          	cv.dotsp.sc.b	ra,ra,ra
+   8:	9021517b          	cv.dotsp.sc.b	sp,sp,sp
+   c:	9084547b          	cv.dotsp.sc.b	s0,s0,s0
+  10:	914a5a7b          	cv.dotsp.sc.b	s4,s4,s4
+  14:	91ffdffb          	cv.dotsp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..966a6ca8a8b80f50d9066422d6dde74651e1f560
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotsp.sc.b x0, x0, x0
+    cv.dotsp.sc.b x1, x1, x1
+    cv.dotsp.sc.b x2, x2, x2
+    cv.dotsp.sc.b x8, x8, x8
+    cv.dotsp.sc.b x20, x20, x20
+    cv.dotsp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..6760134f668e08e4b427521db0846b148030d843
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-h-fail.s
+#error_output: cv-simd-dotsp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..16aa43d60bddffecba6233ab5300a9cf21e635b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..935203cae15df6b89c8c64affc57ab6ebf0a4e59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotsp.sc.h x32, x32, x32
+    cv.dotsp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..418ccea634328ac9f21a56ec15f62db259130235
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000407b          	cv.dotsp.sc.h	zero,zero,zero
+   4:	9010c0fb          	cv.dotsp.sc.h	ra,ra,ra
+   8:	9021417b          	cv.dotsp.sc.h	sp,sp,sp
+   c:	9084447b          	cv.dotsp.sc.h	s0,s0,s0
+  10:	914a4a7b          	cv.dotsp.sc.h	s4,s4,s4
+  14:	91ffcffb          	cv.dotsp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..a9e6ccc2cb5447be9a58f723b18b35130b96e038
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotsp.sc.h x0, x0, x0
+    cv.dotsp.sc.h x1, x1, x1
+    cv.dotsp.sc.h x2, x2, x2
+    cv.dotsp.sc.h x8, x8, x8
+    cv.dotsp.sc.h x20, x20, x20
+    cv.dotsp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..57ec9b6093b36b00f84d9f9f08f56c665d7f3fc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-b-fail.s
+#error_output: cv-simd-dotsp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..76fff08f39b41a33e5649930a9f47faef6852dbf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotsp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..475b2207f85498a5c67d3b1ffa34189d35402367
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.dotsp.sci.b x32, x32, 20
+    cv.dotsp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotsp.sci.b x6, x7, -33
+    cv.dotsp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f89184af378931739a83799c310d7f8a7807c49e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	90a0707b          	cv.dotsp.sci.b	zero,zero,20
+   4:	90a0f0fb          	cv.dotsp.sci.b	ra,ra,20
+   8:	90a1717b          	cv.dotsp.sci.b	sp,sp,20
+   c:	90a4747b          	cv.dotsp.sci.b	s0,s0,20
+  10:	90aa7a7b          	cv.dotsp.sci.b	s4,s4,20
+  14:	90affffb          	cv.dotsp.sci.b	t6,t6,20
+  18:	9103f37b          	cv.dotsp.sci.b	t1,t2,-32
+  1c:	9003f37b          	cv.dotsp.sci.b	t1,t2,0
+  20:	92f3f37b          	cv.dotsp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..47bc8405e8f48b89997d09a98d045bc1a3358446
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.dotsp.sci.b x0, x0, 20
+    cv.dotsp.sci.b x1, x1, 20
+    cv.dotsp.sci.b x2, x2, 20
+    cv.dotsp.sci.b x8, x8, 20
+    cv.dotsp.sci.b x20, x20, 20
+    cv.dotsp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotsp.sci.b x6, x7, -32
+    cv.dotsp.sci.b x6, x7, 0
+    cv.dotsp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3aba92e63497d7053ca02e625069411cc31add67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-h-fail.s
+#error_output: cv-simd-dotsp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9410a24e1c945e68323d416df7969856ab8f1003
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotsp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ba4a59e29b42f2d665040ea959de20ccbfd5ffc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.dotsp.sci.h x32, x32, 20
+    cv.dotsp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotsp.sci.h x6, x7, -33
+    cv.dotsp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..330dcdadab0a226ffd520025e63c0d8f8ae67f92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	90a0607b          	cv.dotsp.sci.h	zero,zero,20
+   4:	90a0e0fb          	cv.dotsp.sci.h	ra,ra,20
+   8:	90a1617b          	cv.dotsp.sci.h	sp,sp,20
+   c:	90a4647b          	cv.dotsp.sci.h	s0,s0,20
+  10:	90aa6a7b          	cv.dotsp.sci.h	s4,s4,20
+  14:	90afeffb          	cv.dotsp.sci.h	t6,t6,20
+  18:	9103e37b          	cv.dotsp.sci.h	t1,t2,-32
+  1c:	9003e37b          	cv.dotsp.sci.h	t1,t2,0
+  20:	92f3e37b          	cv.dotsp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9503a70569721e776885807dc729de8b93655364
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.dotsp.sci.h x0, x0, 20
+    cv.dotsp.sci.h x1, x1, 20
+    cv.dotsp.sci.h x2, x2, 20
+    cv.dotsp.sci.h x8, x8, 20
+    cv.dotsp.sci.h x20, x20, 20
+    cv.dotsp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotsp.sci.h x6, x7, -32
+    cv.dotsp.sci.h x6, x7, 0
+    cv.dotsp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a1acd2d00d06fe3b2d89e165b79ff0ae42658bb8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-b-fail.s
+#error_output: cv-simd-dotup-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7a3964aece111c6424e59dcd4d54b5a982c29938
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..be8a84793ab66f38db9f49e21e16cdc32c749ac5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotup.b x32, x32, x32
+    cv.dotup.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..baee7940f2e411c3d439c462e9a42b280148f5f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000107b          	cv.dotup.b	zero,zero,zero
+   4:	801090fb          	cv.dotup.b	ra,ra,ra
+   8:	8021117b          	cv.dotup.b	sp,sp,sp
+   c:	8084147b          	cv.dotup.b	s0,s0,s0
+  10:	814a1a7b          	cv.dotup.b	s4,s4,s4
+  14:	81ff9ffb          	cv.dotup.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..92b94f9a382eac014cf02650d535bc28a57217b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotup.b x0, x0, x0
+    cv.dotup.b x1, x1, x1
+    cv.dotup.b x2, x2, x2
+    cv.dotup.b x8, x8, x8
+    cv.dotup.b x20, x20, x20
+    cv.dotup.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..744f55d56c30445f1212ee13ce2f90b71194f023
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-h-fail.s
+#error_output: cv-simd-dotup-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3bc820e3e8b6d49ba0e228067245b64726fe6c35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7a72d90c6ea97ff45b7c1b1e6053225eb5915c86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotup.h x32, x32, x32
+    cv.dotup.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..44f9c9c7e3c65ff2add36e62621272c9266912ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000007b          	cv.dotup.h	zero,zero,zero
+   4:	801080fb          	cv.dotup.h	ra,ra,ra
+   8:	8021017b          	cv.dotup.h	sp,sp,sp
+   c:	8084047b          	cv.dotup.h	s0,s0,s0
+  10:	814a0a7b          	cv.dotup.h	s4,s4,s4
+  14:	81ff8ffb          	cv.dotup.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c5390d114aaf93a5e595d29d9628051225f58358
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotup.h x0, x0, x0
+    cv.dotup.h x1, x1, x1
+    cv.dotup.h x2, x2, x2
+    cv.dotup.h x8, x8, x8
+    cv.dotup.h x20, x20, x20
+    cv.dotup.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b43265562a797c68af20427302aa586783f73aaf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-b-fail.s
+#error_output: cv-simd-dotup-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..86044aeac47ee6c95a318972c3d49f12cad36bd0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c3265a0f753ba3fb290dc191d6108a6744a14ea7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotup.sc.b x32, x32, x32
+    cv.dotup.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..305d5ec70c413990abd27f3a923692367438151d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000507b          	cv.dotup.sc.b	zero,zero,zero
+   4:	8010d0fb          	cv.dotup.sc.b	ra,ra,ra
+   8:	8021517b          	cv.dotup.sc.b	sp,sp,sp
+   c:	8084547b          	cv.dotup.sc.b	s0,s0,s0
+  10:	814a5a7b          	cv.dotup.sc.b	s4,s4,s4
+  14:	81ffdffb          	cv.dotup.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..126d7e3af2afbeb52f8b1709dbf2be648caaf60a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotup.sc.b x0, x0, x0
+    cv.dotup.sc.b x1, x1, x1
+    cv.dotup.sc.b x2, x2, x2
+    cv.dotup.sc.b x8, x8, x8
+    cv.dotup.sc.b x20, x20, x20
+    cv.dotup.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..5f2978f4bbe62f345b601e6c6961f98a0ce2c4f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-h-fail.s
+#error_output: cv-simd-dotup-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c2264dcdb7c18e1caaddc4d261db01bd8f462a4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..659fe95948270a37e36f2ed383b137eb30768452
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotup.sc.h x32, x32, x32
+    cv.dotup.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..72ce17d933bdb533d2c50803c64ad9be6b7b48a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000407b          	cv.dotup.sc.h	zero,zero,zero
+   4:	8010c0fb          	cv.dotup.sc.h	ra,ra,ra
+   8:	8021417b          	cv.dotup.sc.h	sp,sp,sp
+   c:	8084447b          	cv.dotup.sc.h	s0,s0,s0
+  10:	814a4a7b          	cv.dotup.sc.h	s4,s4,s4
+  14:	81ffcffb          	cv.dotup.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..89ee845f7cb36f8625c7f8eba106aacfeb47394d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotup.sc.h x0, x0, x0
+    cv.dotup.sc.h x1, x1, x1
+    cv.dotup.sc.h x2, x2, x2
+    cv.dotup.sc.h x8, x8, x8
+    cv.dotup.sc.h x20, x20, x20
+    cv.dotup.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1e1d17b7df28e233e90b4203919b849b73654a7a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-b-fail.s
+#error_output: cv-simd-dotup-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..06ab6ad68c9ff9e7359b56226a9421ad0262c718
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotup.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ad04559e35a7460f619702def00746d54cbcbb59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.dotup.sci.b x32, x32, 20
+    cv.dotup.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotup.sci.b x6, x7, -1
+    cv.dotup.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e730b7157e884b07b187ee1e0ed5888edc130ea9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	80a0707b          	cv.dotup.sci.b	zero,zero,20
+   4:	80a0f0fb          	cv.dotup.sci.b	ra,ra,20
+   8:	80a1717b          	cv.dotup.sci.b	sp,sp,20
+   c:	80a4747b          	cv.dotup.sci.b	s0,s0,20
+  10:	80aa7a7b          	cv.dotup.sci.b	s4,s4,20
+  14:	80affffb          	cv.dotup.sci.b	t6,t6,20
+  18:	8003f37b          	cv.dotup.sci.b	t1,t2,0
+  1c:	83f3f37b          	cv.dotup.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ab1611b0ebc37bb19c78e58d9b2b90a65c11dc86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.dotup.sci.b x0, x0, 20
+    cv.dotup.sci.b x1, x1, 20
+    cv.dotup.sci.b x2, x2, 20
+    cv.dotup.sci.b x8, x8, 20
+    cv.dotup.sci.b x20, x20, 20
+    cv.dotup.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotup.sci.b x6, x7, 0
+    cv.dotup.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b2d5431016119317702f3e8462bd1c008f836d91
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-h-fail.s
+#error_output: cv-simd-dotup-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..f62408540dec93366684a0db623b1b3327480864
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotup.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e8d75f41b6de0b040d0c30584c20d4ec8f32ae57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.dotup.sci.h x32, x32, 20
+    cv.dotup.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotup.sci.h x6, x7, -1
+    cv.dotup.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..fed5c6b5b8c8c35f1b50cc2b70f148fa17ad8e31
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	80a0607b          	cv.dotup.sci.h	zero,zero,20
+   4:	80a0e0fb          	cv.dotup.sci.h	ra,ra,20
+   8:	80a1617b          	cv.dotup.sci.h	sp,sp,20
+   c:	80a4647b          	cv.dotup.sci.h	s0,s0,20
+  10:	80aa6a7b          	cv.dotup.sci.h	s4,s4,20
+  14:	80afeffb          	cv.dotup.sci.h	t6,t6,20
+  18:	8003e37b          	cv.dotup.sci.h	t1,t2,0
+  1c:	83f3e37b          	cv.dotup.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..75db073250b2307e785971e4f5040daa881c7d40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.dotup.sci.h x0, x0, 20
+    cv.dotup.sci.h x1, x1, 20
+    cv.dotup.sci.h x2, x2, 20
+    cv.dotup.sci.h x8, x8, 20
+    cv.dotup.sci.h x20, x20, 20
+    cv.dotup.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotup.sci.h x6, x7, 0
+    cv.dotup.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..cefd5542193057648475b187cdb7a3f3660f6fe6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-b-fail.s
+#error_output: cv-simd-dotusp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..da8dcc445894a09d5a9d2312f42b9deeebc46b32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..875e9629d057b7ef5ce2b32fe4670d035542a73e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotusp.b x32, x32, x32
+    cv.dotusp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..adb512c1d6d308b979065cb18007d855474ca70b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800107b          	cv.dotusp.b	zero,zero,zero
+   4:	881090fb          	cv.dotusp.b	ra,ra,ra
+   8:	8821117b          	cv.dotusp.b	sp,sp,sp
+   c:	8884147b          	cv.dotusp.b	s0,s0,s0
+  10:	894a1a7b          	cv.dotusp.b	s4,s4,s4
+  14:	89ff9ffb          	cv.dotusp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b39b8abc5da6f87d838c924d693738e080e6c65e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotusp.b x0, x0, x0
+    cv.dotusp.b x1, x1, x1
+    cv.dotusp.b x2, x2, x2
+    cv.dotusp.b x8, x8, x8
+    cv.dotusp.b x20, x20, x20
+    cv.dotusp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fdede84e736396459d7b1758a65598c3e6cb31f5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-h-fail.s
+#error_output: cv-simd-dotusp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3b025c9b7189f8a3ae3882d46b82978b1c6a3fef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..cf41e79b32eea298fe28a2072c50dca1306e9ad8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotusp.h x32, x32, x32
+    cv.dotusp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4727622b9599e6a588cdb22262d7ce6e585c19fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800007b          	cv.dotusp.h	zero,zero,zero
+   4:	881080fb          	cv.dotusp.h	ra,ra,ra
+   8:	8821017b          	cv.dotusp.h	sp,sp,sp
+   c:	8884047b          	cv.dotusp.h	s0,s0,s0
+  10:	894a0a7b          	cv.dotusp.h	s4,s4,s4
+  14:	89ff8ffb          	cv.dotusp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..8abcb4ea21c4c334390dd5a87e62475e4a61d179
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotusp.h x0, x0, x0
+    cv.dotusp.h x1, x1, x1
+    cv.dotusp.h x2, x2, x2
+    cv.dotusp.h x8, x8, x8
+    cv.dotusp.h x20, x20, x20
+    cv.dotusp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..dc763469da8d2fa5fa080a4a70202fad8b302720
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-b-fail.s
+#error_output: cv-simd-dotusp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c1c7d325c9904408998d162477841ea3537e9e35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a4a1cac98598c7416a836d17604cec91cd4d3301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotusp.sc.b x32, x32, x32
+    cv.dotusp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a8c2408e753f50d506f05492306e7086f87608e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800507b          	cv.dotusp.sc.b	zero,zero,zero
+   4:	8810d0fb          	cv.dotusp.sc.b	ra,ra,ra
+   8:	8821517b          	cv.dotusp.sc.b	sp,sp,sp
+   c:	8884547b          	cv.dotusp.sc.b	s0,s0,s0
+  10:	894a5a7b          	cv.dotusp.sc.b	s4,s4,s4
+  14:	89ffdffb          	cv.dotusp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7b8cc4f2b0391705ef064d9d6b4e560a8469b113
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotusp.sc.b x0, x0, x0
+    cv.dotusp.sc.b x1, x1, x1
+    cv.dotusp.sc.b x2, x2, x2
+    cv.dotusp.sc.b x8, x8, x8
+    cv.dotusp.sc.b x20, x20, x20
+    cv.dotusp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..aa166ddc6e7bb81a403d38feaad537e4f8432f22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-h-fail.s
+#error_output: cv-simd-dotusp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..48e1819aa5362e0d6df2fda52361bcc63d7475fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a69450163b5718cfff28f58e4ad11baf186fc83e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.dotusp.sc.h x32, x32, x32
+    cv.dotusp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a3afc79157e68458d47326f83ac3b9ee9132538d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800407b          	cv.dotusp.sc.h	zero,zero,zero
+   4:	8810c0fb          	cv.dotusp.sc.h	ra,ra,ra
+   8:	8821417b          	cv.dotusp.sc.h	sp,sp,sp
+   c:	8884447b          	cv.dotusp.sc.h	s0,s0,s0
+  10:	894a4a7b          	cv.dotusp.sc.h	s4,s4,s4
+  14:	89ffcffb          	cv.dotusp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c10f72f2fa4d5968b67a7351682d135d4a7e9f1f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.dotusp.sc.h x0, x0, x0
+    cv.dotusp.sc.h x1, x1, x1
+    cv.dotusp.sc.h x2, x2, x2
+    cv.dotusp.sc.h x8, x8, x8
+    cv.dotusp.sc.h x20, x20, x20
+    cv.dotusp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0ea3d54f7c7eca935bcddb2c33f888b1dcd42200
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-b-fail.s
+#error_output: cv-simd-dotusp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..6e3e7bf28deda8f7b530728c36374847265f8a8b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotusp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..14a57c61669ca55451faf3c8b60eabe514833153
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.dotusp.sci.b x32, x32, 20
+    cv.dotusp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotusp.sci.b x6, x7, -33
+    cv.dotusp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e9f956ad38413542de85c4e75d622fe7fb9d9e16
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	88a0707b          	cv.dotusp.sci.b	zero,zero,20
+   4:	88a0f0fb          	cv.dotusp.sci.b	ra,ra,20
+   8:	88a1717b          	cv.dotusp.sci.b	sp,sp,20
+   c:	88a4747b          	cv.dotusp.sci.b	s0,s0,20
+  10:	88aa7a7b          	cv.dotusp.sci.b	s4,s4,20
+  14:	88affffb          	cv.dotusp.sci.b	t6,t6,20
+  18:	8903f37b          	cv.dotusp.sci.b	t1,t2,-32
+  1c:	8803f37b          	cv.dotusp.sci.b	t1,t2,0
+  20:	8af3f37b          	cv.dotusp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9ca11c5d86887da7e6e05f989f421ab89d18076f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.dotusp.sci.b x0, x0, 20
+    cv.dotusp.sci.b x1, x1, 20
+    cv.dotusp.sci.b x2, x2, 20
+    cv.dotusp.sci.b x8, x8, 20
+    cv.dotusp.sci.b x20, x20, 20
+    cv.dotusp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotusp.sci.b x6, x7, -32
+    cv.dotusp.sci.b x6, x7, 0
+    cv.dotusp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..89ed824b8a617d394477ca5f7d17631e595854da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-h-fail.s
+#error_output: cv-simd-dotusp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..99f14c09c125f01c35ab71494c26d19d61e0bb8b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotusp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0075dd1b82269943512aa186c4a612b94d73d03d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.dotusp.sci.h x32, x32, 20
+    cv.dotusp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotusp.sci.h x6, x7, -33
+    cv.dotusp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..cb5e2aeca57b926ee0652a23a9560ae06eb246df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	88a0607b          	cv.dotusp.sci.h	zero,zero,20
+   4:	88a0e0fb          	cv.dotusp.sci.h	ra,ra,20
+   8:	88a1617b          	cv.dotusp.sci.h	sp,sp,20
+   c:	88a4647b          	cv.dotusp.sci.h	s0,s0,20
+  10:	88aa6a7b          	cv.dotusp.sci.h	s4,s4,20
+  14:	88afeffb          	cv.dotusp.sci.h	t6,t6,20
+  18:	8903e37b          	cv.dotusp.sci.h	t1,t2,-32
+  1c:	8803e37b          	cv.dotusp.sci.h	t1,t2,0
+  20:	8af3e37b          	cv.dotusp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..49528dc05e10a46ff25c612ab2c09a7d5a6019d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.dotusp.sci.h x0, x0, 20
+    cv.dotusp.sci.h x1, x1, 20
+    cv.dotusp.sci.h x2, x2, 20
+    cv.dotusp.sci.h x8, x8, 20
+    cv.dotusp.sci.h x20, x20, 20
+    cv.dotusp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotusp.sci.h x6, x7, -32
+    cv.dotusp.sci.h x6, x7, 0
+    cv.dotusp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..dc987eef71c0b3a369db9fa1a3ddd4b2eddbd5b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-b-fail.s
+#error_output: cv-simd-extract-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ac33235412102ff974720fcd3c887656af5041fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extract.b x32,x32,20'
+.*: Error: illegal operands `cv.extract.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..57b900a61da95678130ffd6722cea913f158c97b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.extract.b x32, x32, 20
+    cv.extract.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.extract.b x6, x7, -1
+    cv.extract.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d3839e744c49be05951ae3098dbc1117e7246e25
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b8a0107b          	cv.extract.b	zero,zero,20
+   4:	b8a090fb          	cv.extract.b	ra,ra,20
+   8:	b8a1117b          	cv.extract.b	sp,sp,20
+   c:	b8a4147b          	cv.extract.b	s0,s0,20
+  10:	b8aa1a7b          	cv.extract.b	s4,s4,20
+  14:	b8af9ffb          	cv.extract.b	t6,t6,20
+  18:	b803937b          	cv.extract.b	t1,t2,0
+  1c:	bbf3937b          	cv.extract.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..010f6e4b0e3e213ffca21073bb0f36fca3e8369c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.extract.b x0, x0, 20
+    cv.extract.b x1, x1, 20
+    cv.extract.b x2, x2, 20
+    cv.extract.b x8, x8, 20
+    cv.extract.b x20, x20, 20
+    cv.extract.b x31, x31, 20
+    #Immediate Values Test
+    cv.extract.b x6, x7, 0
+    cv.extract.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b6f94bfb620595d3b315ca4ab33670d01a6c2d82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-h-fail.s
+#error_output: cv-simd-extract-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..da307db9e964c7fad58947771ba22932146c3ac2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extract.h x32,x32,20'
+.*: Error: illegal operands `cv.extract.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..dfb52d13971af87e2727c28b4f24f43b80d0c70b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.extract.h x32, x32, 20
+    cv.extract.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.extract.h x6, x7, -1
+    cv.extract.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a37ed2ca18c2d89bec279fdd41f5f7498dd46743
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b8a0007b          	cv.extract.h	zero,zero,20
+   4:	b8a080fb          	cv.extract.h	ra,ra,20
+   8:	b8a1017b          	cv.extract.h	sp,sp,20
+   c:	b8a4047b          	cv.extract.h	s0,s0,20
+  10:	b8aa0a7b          	cv.extract.h	s4,s4,20
+  14:	b8af8ffb          	cv.extract.h	t6,t6,20
+  18:	b803837b          	cv.extract.h	t1,t2,0
+  1c:	bbf3837b          	cv.extract.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..cd75722149df3c8469e0bafae59512d5a3eb819a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.extract.h x0, x0, 20
+    cv.extract.h x1, x1, 20
+    cv.extract.h x2, x2, 20
+    cv.extract.h x8, x8, 20
+    cv.extract.h x20, x20, 20
+    cv.extract.h x31, x31, 20
+    #Immediate Values Test
+    cv.extract.h x6, x7, 0
+    cv.extract.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a591c64c8d12608e22d7846780d29155de78da8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-b-fail.s
+#error_output: cv-simd-extractu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1dcf1cee6d50202d61476ba1c00ee5e82e63b290
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extractu.b x32,x32,20'
+.*: Error: illegal operands `cv.extractu.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e186805f43e6e3cc32d558a1becbe1bb3dc901c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.extractu.b x32, x32, 20
+    cv.extractu.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.extractu.b x6, x7, -1
+    cv.extractu.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..289544b72d7d8793b7a38d14db0228682cd7fec1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b8a0307b          	cv.extractu.b	zero,zero,20
+   4:	b8a0b0fb          	cv.extractu.b	ra,ra,20
+   8:	b8a1317b          	cv.extractu.b	sp,sp,20
+   c:	b8a4347b          	cv.extractu.b	s0,s0,20
+  10:	b8aa3a7b          	cv.extractu.b	s4,s4,20
+  14:	b8afbffb          	cv.extractu.b	t6,t6,20
+  18:	b803b37b          	cv.extractu.b	t1,t2,0
+  1c:	bbf3b37b          	cv.extractu.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..a2ee7bf981e5a62182342048a5a4f6e556ee0cac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.extractu.b x0, x0, 20
+    cv.extractu.b x1, x1, 20
+    cv.extractu.b x2, x2, 20
+    cv.extractu.b x8, x8, 20
+    cv.extractu.b x20, x20, 20
+    cv.extractu.b x31, x31, 20
+    #Immediate Values Test
+    cv.extractu.b x6, x7, 0
+    cv.extractu.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fb23af44fecf69423c7279f31f245af357f0b345
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-h-fail.s
+#error_output: cv-simd-extractu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..e9b58a7b1e4bdd26a6bed0a41ad65d214ef32ba8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extractu.h x32,x32,20'
+.*: Error: illegal operands `cv.extractu.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7ebe67729fdfaaae240df1e4159280bb9166382c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.extractu.h x32, x32, 20
+    cv.extractu.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.extractu.h x6, x7, -1
+    cv.extractu.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..661b4a0fccff7448a1bc93cd319b03d0c390e210
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b8a0207b          	cv.extractu.h	zero,zero,20
+   4:	b8a0a0fb          	cv.extractu.h	ra,ra,20
+   8:	b8a1217b          	cv.extractu.h	sp,sp,20
+   c:	b8a4247b          	cv.extractu.h	s0,s0,20
+  10:	b8aa2a7b          	cv.extractu.h	s4,s4,20
+  14:	b8afaffb          	cv.extractu.h	t6,t6,20
+  18:	b803a37b          	cv.extractu.h	t1,t2,0
+  1c:	bbf3a37b          	cv.extractu.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e169c664a09276e7fcc0aa31dd2cb8470d2cb343
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.extractu.h x0, x0, 20
+    cv.extractu.h x1, x1, 20
+    cv.extractu.h x2, x2, 20
+    cv.extractu.h x8, x8, 20
+    cv.extractu.h x20, x20, 20
+    cv.extractu.h x31, x31, 20
+    #Immediate Values Test
+    cv.extractu.h x6, x7, 0
+    cv.extractu.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1b367d2a8ee6de05a8ce88b425a8af316364c4a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-b-fail.s
+#error_output: cv-simd-insert-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4c111857301f38afa72064f3afde97f4de80ab98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.insert.b x32,x32,20'
+.*: Error: illegal operands `cv.insert.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..677310e2c27abe7659ff32092e22ff893716b080
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.insert.b x32, x32, 20
+    cv.insert.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.insert.b x6, x7, -1
+    cv.insert.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a4f2bafe2b7c00195b73302d88be892d8c598f05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b8a0507b          	cv.insert.b	zero,zero,20
+   4:	b8a0d0fb          	cv.insert.b	ra,ra,20
+   8:	b8a1517b          	cv.insert.b	sp,sp,20
+   c:	b8a4547b          	cv.insert.b	s0,s0,20
+  10:	b8aa5a7b          	cv.insert.b	s4,s4,20
+  14:	b8afdffb          	cv.insert.b	t6,t6,20
+  18:	b803d37b          	cv.insert.b	t1,t2,0
+  1c:	bbf3d37b          	cv.insert.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b29128d174d785bcf0edd3a547e3f736d044ee6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.insert.b x0, x0, 20
+    cv.insert.b x1, x1, 20
+    cv.insert.b x2, x2, 20
+    cv.insert.b x8, x8, 20
+    cv.insert.b x20, x20, 20
+    cv.insert.b x31, x31, 20
+    #Immediate Values Test
+    cv.insert.b x6, x7, 0
+    cv.insert.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8b7a2f097cd9a0192d06c3b1def0d8782533673c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-h-fail.s
+#error_output: cv-simd-insert-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..85491de6ccb1167ce9cc064e8d0fdb328ad4bb43
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.insert.h x32,x32,20'
+.*: Error: illegal operands `cv.insert.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..89719c7a48df52fcb87cc9fd7597d21377b5c27c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.insert.h x32, x32, 20
+    cv.insert.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.insert.h x6, x7, -1
+    cv.insert.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d81042568fa01312e6f51f740b8cd509c9e942ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b8a0407b          	cv.insert.h	zero,zero,20
+   4:	b8a0c0fb          	cv.insert.h	ra,ra,20
+   8:	b8a1417b          	cv.insert.h	sp,sp,20
+   c:	b8a4447b          	cv.insert.h	s0,s0,20
+  10:	b8aa4a7b          	cv.insert.h	s4,s4,20
+  14:	b8afcffb          	cv.insert.h	t6,t6,20
+  18:	b803c37b          	cv.insert.h	t1,t2,0
+  1c:	bbf3c37b          	cv.insert.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c19829828e2ed537c7802d2153e69cab3f16f1c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.insert.h x0, x0, 20
+    cv.insert.h x1, x1, 20
+    cv.insert.h x2, x2, 20
+    cv.insert.h x8, x8, 20
+    cv.insert.h x20, x20, 20
+    cv.insert.h x31, x31, 20
+    #Immediate Values Test
+    cv.insert.h x6, x7, 0
+    cv.insert.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.d b/gas/testsuite/gas/riscv/cv-simd-march-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..4ae0a97b4cea44a3d391272d8bee8329716b1fe7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-simd-march-fail.s
+#error_output: cv-simd-march-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.l b/gas/testsuite/gas/riscv/cv-simd-march-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..dc9eef29026a25f8cc9f12f886b54cfd053ab3c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.l
@@ -0,0 +1,221 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.add.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.abs.h x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.abs.b x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extract.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extract.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extractu.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extractu.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.insert.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.insert.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei0.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei1.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei2.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei3.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle2.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle2.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.pack x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.pack.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.packhi.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.packlo.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxconj x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.div8 x5,x6,x7', extension `xcvsimd' required
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.s b/gas/testsuite/gas/riscv/cv-simd-march-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a63586918cd81769edafec3188ca1e142fca38ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.s
@@ -0,0 +1,221 @@
+target: 
+    cv.add.h x5, x6, x7
+    cv.add.b x5, x6, x7
+    cv.add.sc.h x5, x6, x7
+    cv.add.sc.b x5, x6, x7
+    cv.add.sci.h x6, x7, 20
+    cv.add.sci.b x6, x7, 20
+    cv.sub.h x5, x6, x7
+    cv.sub.b x5, x6, x7
+    cv.sub.sc.h x5, x6, x7
+    cv.sub.sc.b x5, x6, x7
+    cv.sub.sci.h x6, x7, 20
+    cv.sub.sci.b x6, x7, 20
+    cv.avg.h x5, x6, x7
+    cv.avg.b x5, x6, x7
+    cv.avg.sc.h x5, x6, x7
+    cv.avg.sc.b x5, x6, x7
+    cv.avg.sci.h x6, x7, 20
+    cv.avg.sci.b x6, x7, 20
+    cv.avgu.h x5, x6, x7
+    cv.avgu.b x5, x6, x7
+    cv.avgu.sc.h x5, x6, x7
+    cv.avgu.sc.b x5, x6, x7
+    cv.avgu.sci.h x6, x7, 20
+    cv.avgu.sci.b x6, x7, 20
+    cv.min.h x5, x6, x7
+    cv.min.b x5, x6, x7
+    cv.min.sc.h x5, x6, x7
+    cv.min.sc.b x5, x6, x7
+    cv.min.sci.h x6, x7, 20
+    cv.min.sci.b x6, x7, 20
+    cv.minu.h x5, x6, x7
+    cv.minu.b x5, x6, x7
+    cv.minu.sc.h x5, x6, x7
+    cv.minu.sc.b x5, x6, x7
+    cv.minu.sci.h x6, x7, 20
+    cv.minu.sci.b x6, x7, 20
+    cv.max.h x5, x6, x7
+    cv.max.b x5, x6, x7
+    cv.max.sc.h x5, x6, x7
+    cv.max.sc.b x5, x6, x7
+    cv.max.sci.h x6, x7, 20
+    cv.max.sci.b x6, x7, 20
+    cv.maxu.h x5, x6, x7
+    cv.maxu.b x5, x6, x7
+    cv.maxu.sc.h x5, x6, x7
+    cv.maxu.sc.b x5, x6, x7
+    cv.maxu.sci.h x6, x7, 20
+    cv.maxu.sci.b x6, x7, 20
+    cv.srl.h x5, x6, x7
+    cv.srl.b x5, x6, x7
+    cv.srl.sc.h x5, x6, x7
+    cv.srl.sc.b x5, x6, x7
+    cv.srl.sci.h x6, x7, 20
+    cv.srl.sci.b x6, x7, 20
+    cv.sra.h x5, x6, x7
+    cv.sra.b x5, x6, x7
+    cv.sra.sc.h x5, x6, x7
+    cv.sra.sc.b x5, x6, x7
+    cv.sra.sci.h x6, x7, 20
+    cv.sra.sci.b x6, x7, 20
+    cv.sll.h x5, x6, x7
+    cv.sll.b x5, x6, x7
+    cv.sll.sc.h x5, x6, x7
+    cv.sll.sc.b x5, x6, x7
+    cv.sll.sci.h x6, x7, 20
+    cv.sll.sci.b x6, x7, 20
+    cv.or.h x5, x6, x7
+    cv.or.b x5, x6, x7
+    cv.or.sc.h x5, x6, x7
+    cv.or.sc.b x5, x6, x7
+    cv.or.sci.h x6, x7, 20
+    cv.or.sci.b x6, x7, 20
+    cv.xor.h x5, x6, x7
+    cv.xor.b x5, x6, x7
+    cv.xor.sc.h x5, x6, x7
+    cv.xor.sc.b x5, x6, x7
+    cv.xor.sci.h x6, x7, 20
+    cv.xor.sci.b x6, x7, 20
+    cv.and.h x5, x6, x7
+    cv.and.b x5, x6, x7
+    cv.and.sc.h x5, x6, x7
+    cv.and.sc.b x5, x6, x7
+    cv.and.sci.h x6, x7, 20
+    cv.and.sci.b x6, x7, 20
+    cv.abs.h x6, x7
+    cv.abs.b x6, x7
+    cv.dotup.h x5, x6, x7
+    cv.dotup.b x5, x6, x7
+    cv.dotup.sc.h x5, x6, x7
+    cv.dotup.sc.b x5, x6, x7
+    cv.dotup.sci.h x6, x7, 20
+    cv.dotup.sci.b x6, x7, 20
+    cv.dotusp.h x5, x6, x7
+    cv.dotusp.b x5, x6, x7
+    cv.dotusp.sc.h x5, x6, x7
+    cv.dotusp.sc.b x5, x6, x7
+    cv.dotusp.sci.h x6, x7, 20
+    cv.dotusp.sci.b x6, x7, 20
+    cv.dotsp.h x5, x6, x7
+    cv.dotsp.b x5, x6, x7
+    cv.dotsp.sc.h x5, x6, x7
+    cv.dotsp.sc.b x5, x6, x7
+    cv.dotsp.sci.h x6, x7, 20
+    cv.dotsp.sci.b x6, x7, 20
+    cv.sdotup.h x5, x6, x7
+    cv.sdotup.b x5, x6, x7
+    cv.sdotup.sc.h x5, x6, x7
+    cv.sdotup.sc.b x5, x6, x7
+    cv.sdotup.sci.h x6, x7, 20
+    cv.sdotup.sci.b x6, x7, 20
+    cv.sdotusp.h x5, x6, x7
+    cv.sdotusp.b x5, x6, x7
+    cv.sdotusp.sc.h x5, x6, x7
+    cv.sdotusp.sc.b x5, x6, x7
+    cv.sdotusp.sci.h x6, x7, 20
+    cv.sdotusp.sci.b x6, x7, 20
+    cv.sdotsp.h x5, x6, x7
+    cv.sdotsp.b x5, x6, x7
+    cv.sdotsp.sc.h x5, x6, x7
+    cv.sdotsp.sc.b x5, x6, x7
+    cv.sdotsp.sci.h x6, x7, 20
+    cv.sdotsp.sci.b x6, x7, 20
+    cv.extract.h x6, x7, 20
+    cv.extract.b x6, x7, 20
+    cv.extractu.h x6, x7, 20
+    cv.extractu.b x6, x7, 20
+    cv.insert.h x6, x7, 20
+    cv.insert.b x6, x7, 20
+    cv.shuffle.h x5, x6, x7
+    cv.shuffle.b x5, x6, x7
+    cv.shuffle.sci.h x6, x7, 20
+    cv.shufflei0.sci.b x6, x7, 20
+    cv.shufflei1.sci.b x6, x7, 20
+    cv.shufflei2.sci.b x6, x7, 20
+    cv.shufflei3.sci.b x6, x7, 20
+    cv.shuffle2.h x5, x6, x7
+    cv.shuffle2.b x5, x6, x7
+    cv.pack x5, x6, x7
+    cv.pack.h x5, x6, x7
+    cv.packhi.b x5, x6, x7
+    cv.packlo.b x5, x6, x7
+    cv.cmpeq.h x5, x6, x7
+    cv.cmpeq.b x5, x6, x7
+    cv.cmpeq.sc.h x5, x6, x7
+    cv.cmpeq.sc.b x5, x6, x7
+    cv.cmpeq.sci.h x6, x7, 20
+    cv.cmpeq.sci.b x6, x7, 20
+    cv.cmpne.h x5, x6, x7
+    cv.cmpne.b x5, x6, x7
+    cv.cmpne.sc.h x5, x6, x7
+    cv.cmpne.sc.b x5, x6, x7
+    cv.cmpne.sci.h x6, x7, 20
+    cv.cmpne.sci.b x6, x7, 20
+    cv.cmpgt.h x5, x6, x7
+    cv.cmpgt.b x5, x6, x7
+    cv.cmpgt.sc.h x5, x6, x7
+    cv.cmpgt.sc.b x5, x6, x7
+    cv.cmpgt.sci.h x6, x7, 20
+    cv.cmpgt.sci.b x6, x7, 20
+    cv.cmpge.h x5, x6, x7
+    cv.cmpge.b x5, x6, x7
+    cv.cmpge.sc.h x5, x6, x7
+    cv.cmpge.sc.b x5, x6, x7
+    cv.cmpge.sci.h x6, x7, 20
+    cv.cmpge.sci.b x6, x7, 20
+    cv.cmplt.h x5, x6, x7
+    cv.cmplt.b x5, x6, x7
+    cv.cmplt.sc.h x5, x6, x7
+    cv.cmplt.sc.b x5, x6, x7
+    cv.cmplt.sci.h x6, x7, 20
+    cv.cmplt.sci.b x6, x7, 20
+    cv.cmple.h x5, x6, x7
+    cv.cmple.b x5, x6, x7
+    cv.cmple.sc.h x5, x6, x7
+    cv.cmple.sc.b x5, x6, x7
+    cv.cmple.sci.h x6, x7, 20
+    cv.cmple.sci.b x6, x7, 20
+    cv.cmpgtu.h x5, x6, x7
+    cv.cmpgtu.b x5, x6, x7
+    cv.cmpgtu.sc.h x5, x6, x7
+    cv.cmpgtu.sc.b x5, x6, x7
+    cv.cmpgtu.sci.h x6, x7, 20
+    cv.cmpgtu.sci.b x6, x7, 20
+    cv.cmpgeu.h x5, x6, x7
+    cv.cmpgeu.b x5, x6, x7
+    cv.cmpgeu.sc.h x5, x6, x7
+    cv.cmpgeu.sc.b x5, x6, x7
+    cv.cmpgeu.sci.h x6, x7, 20
+    cv.cmpgeu.sci.b x6, x7, 20
+    cv.cmpltu.h x5, x6, x7
+    cv.cmpltu.b x5, x6, x7
+    cv.cmpltu.sc.h x5, x6, x7
+    cv.cmpltu.sc.b x5, x6, x7
+    cv.cmpltu.sci.h x6, x7, 20
+    cv.cmpltu.sci.b x6, x7, 20
+    cv.cmpleu.h x5, x6, x7
+    cv.cmpleu.b x5, x6, x7
+    cv.cmpleu.sc.h x5, x6, x7
+    cv.cmpleu.sc.b x5, x6, x7
+    cv.cmpleu.sci.h x6, x7, 20
+    cv.cmpleu.sci.b x6, x7, 20
+    cv.cplxmul.r x5, x6, x7
+    cv.cplxmul.i x5, x6, x7
+    cv.cplxmul.r.div2 x5, x6, x7
+    cv.cplxmul.i.div2 x5, x6, x7
+    cv.cplxmul.r.div4 x5, x6, x7
+    cv.cplxmul.i.div4 x5, x6, x7
+    cv.cplxmul.r.div8 x5, x6, x7
+    cv.cplxmul.i.div8 x5, x6, x7
+    cv.cplxconj x6, x7
+    cv.subrotmj x5, x6, x7
+    cv.subrotmj.div2 x5, x6, x7
+    cv.subrotmj.div4 x5, x6, x7
+    cv.subrotmj.div8 x5, x6, x7
+    cv.add.div2 x5, x6, x7
+    cv.add.div4 x5, x6, x7
+    cv.add.div8 x5, x6, x7
+    cv.sub.div2 x5, x6, x7
+    cv.sub.div4 x5, x6, x7
+    cv.sub.div8 x5, x6, x7
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.d b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.d
new file mode 100644
index 0000000000000000000000000000000000000000..05dfa349dde4049d4e8d5f108c359eb83a94ba83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.d
@@ -0,0 +1,230 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-march-xcvsimd.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[  ]+0:[ 	]+007302fb[ 	]+cv.add.h	t0,t1,t2
+[  ]+4:[ 	]+007312fb[ 	]+cv.add.b	t0,t1,t2
+[  ]+8:[ 	]+007342fb[ 	]+cv.add.sc.h	t0,t1,t2
+[  ]+c:[ 	]+007352fb[ 	]+cv.add.sc.b	t0,t1,t2
+[  ]+10:[ 	]+00a3e37b[ 	]+cv.add.sci.h	t1,t2,20
+[  ]+14:[ 	]+00a3f37b[ 	]+cv.add.sci.b	t1,t2,20
+[  ]+18:[ 	]+087302fb[ 	]+cv.sub.h	t0,t1,t2
+[  ]+1c:[ 	]+087312fb[ 	]+cv.sub.b	t0,t1,t2
+[  ]+20:[ 	]+087342fb[ 	]+cv.sub.sc.h	t0,t1,t2
+[  ]+24:[ 	]+087352fb[ 	]+cv.sub.sc.b	t0,t1,t2
+[  ]+28:[ 	]+08a3e37b[ 	]+cv.sub.sci.h	t1,t2,20
+[  ]+2c:[ 	]+08a3f37b[ 	]+cv.sub.sci.b	t1,t2,20
+[  ]+30:[ 	]+107302fb[ 	]+cv.avg.h	t0,t1,t2
+[  ]+34:[ 	]+107312fb[ 	]+cv.avg.b	t0,t1,t2
+[  ]+38:[ 	]+107342fb[ 	]+cv.avg.sc.h	t0,t1,t2
+[  ]+3c:[ 	]+107352fb[ 	]+cv.avg.sc.b	t0,t1,t2
+[  ]+40:[ 	]+10a3e37b[ 	]+cv.avg.sci.h	t1,t2,20
+[  ]+44:[ 	]+10a3f37b[ 	]+cv.avg.sci.b	t1,t2,20
+[  ]+48:[ 	]+187302fb[ 	]+cv.avgu.h	t0,t1,t2
+[  ]+4c:[ 	]+187312fb[ 	]+cv.avgu.b	t0,t1,t2
+[  ]+50:[ 	]+187342fb[ 	]+cv.avgu.sc.h	t0,t1,t2
+[  ]+54:[ 	]+187352fb[ 	]+cv.avgu.sc.b	t0,t1,t2
+[  ]+58:[ 	]+18a3e37b[ 	]+cv.avgu.sci.h	t1,t2,20
+[  ]+5c:[ 	]+18a3f37b[ 	]+cv.avgu.sci.b	t1,t2,20
+[  ]+60:[ 	]+207302fb[ 	]+cv.min.h	t0,t1,t2
+[  ]+64:[ 	]+207312fb[ 	]+cv.min.b	t0,t1,t2
+[  ]+68:[ 	]+207342fb[ 	]+cv.min.sc.h	t0,t1,t2
+[  ]+6c:[ 	]+207352fb[ 	]+cv.min.sc.b	t0,t1,t2
+[  ]+70:[ 	]+20a3e37b[ 	]+cv.min.sci.h	t1,t2,20
+[  ]+74:[ 	]+20a3f37b[ 	]+cv.min.sci.b	t1,t2,20
+[  ]+78:[ 	]+287302fb[ 	]+cv.minu.h	t0,t1,t2
+[  ]+7c:[ 	]+287312fb[ 	]+cv.minu.b	t0,t1,t2
+[  ]+80:[ 	]+287342fb[ 	]+cv.minu.sc.h	t0,t1,t2
+[  ]+84:[ 	]+287352fb[ 	]+cv.minu.sc.b	t0,t1,t2
+[  ]+88:[ 	]+28a3e37b[ 	]+cv.minu.sci.h	t1,t2,20
+[  ]+8c:[ 	]+28a3f37b[ 	]+cv.minu.sci.b	t1,t2,20
+[  ]+90:[ 	]+307302fb[ 	]+cv.max.h	t0,t1,t2
+[  ]+94:[ 	]+307312fb[ 	]+cv.max.b	t0,t1,t2
+[  ]+98:[ 	]+307342fb[ 	]+cv.max.sc.h	t0,t1,t2
+[  ]+9c:[ 	]+307352fb[ 	]+cv.max.sc.b	t0,t1,t2
+[  ]+a0:[ 	]+30a3e37b[ 	]+cv.max.sci.h	t1,t2,20
+[  ]+a4:[ 	]+30a3f37b[ 	]+cv.max.sci.b	t1,t2,20
+[  ]+a8:[ 	]+387302fb[ 	]+cv.maxu.h	t0,t1,t2
+[  ]+ac:[ 	]+387312fb[ 	]+cv.maxu.b	t0,t1,t2
+[  ]+b0:[ 	]+387342fb[ 	]+cv.maxu.sc.h	t0,t1,t2
+[  ]+b4:[ 	]+387352fb[ 	]+cv.maxu.sc.b	t0,t1,t2
+[  ]+b8:[ 	]+38a3e37b[ 	]+cv.maxu.sci.h	t1,t2,20
+[  ]+bc:[ 	]+38a3f37b[ 	]+cv.maxu.sci.b	t1,t2,20
+[  ]+c0:[ 	]+407302fb[ 	]+cv.srl.h	t0,t1,t2
+[  ]+c4:[ 	]+407312fb[ 	]+cv.srl.b	t0,t1,t2
+[  ]+c8:[ 	]+407342fb[ 	]+cv.srl.sc.h	t0,t1,t2
+[  ]+cc:[ 	]+407352fb[ 	]+cv.srl.sc.b	t0,t1,t2
+[  ]+d0:[ 	]+40a3e37b[ 	]+cv.srl.sci.h	t1,t2,20
+[  ]+d4:[ 	]+40a3f37b[ 	]+cv.srl.sci.b	t1,t2,20
+[  ]+d8:[ 	]+487302fb[ 	]+cv.sra.h	t0,t1,t2
+[  ]+dc:[ 	]+487312fb[ 	]+cv.sra.b	t0,t1,t2
+[  ]+e0:[ 	]+487342fb[ 	]+cv.sra.sc.h	t0,t1,t2
+[  ]+e4:[ 	]+487352fb[ 	]+cv.sra.sc.b	t0,t1,t2
+[  ]+e8:[ 	]+48a3e37b[ 	]+cv.sra.sci.h	t1,t2,20
+[  ]+ec:[ 	]+48a3f37b[ 	]+cv.sra.sci.b	t1,t2,20
+[  ]+f0:[ 	]+507302fb[ 	]+cv.sll.h	t0,t1,t2
+[  ]+f4:[ 	]+507312fb[ 	]+cv.sll.b	t0,t1,t2
+[  ]+f8:[ 	]+507342fb[ 	]+cv.sll.sc.h	t0,t1,t2
+[  ]+fc:[ 	]+507352fb[ 	]+cv.sll.sc.b	t0,t1,t2
+[  ]+100:[ 	]+50a3e37b[ 	]+cv.sll.sci.h	t1,t2,20
+[  ]+104:[ 	]+50a3f37b[ 	]+cv.sll.sci.b	t1,t2,20
+[  ]+108:[ 	]+587302fb[ 	]+cv.or.h	t0,t1,t2
+[  ]+10c:[ 	]+587312fb[ 	]+cv.or.b	t0,t1,t2
+[  ]+110:[ 	]+587342fb[ 	]+cv.or.sc.h	t0,t1,t2
+[  ]+114:[ 	]+587352fb[ 	]+cv.or.sc.b	t0,t1,t2
+[  ]+118:[ 	]+58a3e37b[ 	]+cv.or.sci.h	t1,t2,20
+[  ]+11c:[ 	]+58a3f37b[ 	]+cv.or.sci.b	t1,t2,20
+[  ]+120:[ 	]+607302fb[ 	]+cv.xor.h	t0,t1,t2
+[  ]+124:[ 	]+607312fb[ 	]+cv.xor.b	t0,t1,t2
+[  ]+128:[ 	]+607342fb[ 	]+cv.xor.sc.h	t0,t1,t2
+[  ]+12c:[ 	]+607352fb[ 	]+cv.xor.sc.b	t0,t1,t2
+[  ]+130:[ 	]+60a3e37b[ 	]+cv.xor.sci.h	t1,t2,20
+[  ]+134:[ 	]+60a3f37b[ 	]+cv.xor.sci.b	t1,t2,20
+[  ]+138:[ 	]+687302fb[ 	]+cv.and.h	t0,t1,t2
+[  ]+13c:[ 	]+687312fb[ 	]+cv.and.b	t0,t1,t2
+[  ]+140:[ 	]+687342fb[ 	]+cv.and.sc.h	t0,t1,t2
+[  ]+144:[ 	]+687352fb[ 	]+cv.and.sc.b	t0,t1,t2
+[  ]+148:[ 	]+68a3e37b[ 	]+cv.and.sci.h	t1,t2,20
+[  ]+14c:[ 	]+68a3f37b[ 	]+cv.and.sci.b	t1,t2,20
+[  ]+150:[ 	]+7003837b[ 	]+cv.abs.h	t1,t2
+[  ]+154:[ 	]+7003937b[ 	]+cv.abs.b	t1,t2
+[  ]+158:[ 	]+807302fb[ 	]+cv.dotup.h	t0,t1,t2
+[  ]+15c:[ 	]+807312fb[ 	]+cv.dotup.b	t0,t1,t2
+[  ]+160:[ 	]+807342fb[ 	]+cv.dotup.sc.h	t0,t1,t2
+[  ]+164:[ 	]+807352fb[ 	]+cv.dotup.sc.b	t0,t1,t2
+[  ]+168:[ 	]+80a3e37b[ 	]+cv.dotup.sci.h	t1,t2,20
+[  ]+16c:[ 	]+80a3f37b[ 	]+cv.dotup.sci.b	t1,t2,20
+[  ]+170:[ 	]+887302fb[ 	]+cv.dotusp.h	t0,t1,t2
+[  ]+174:[ 	]+887312fb[ 	]+cv.dotusp.b	t0,t1,t2
+[  ]+178:[ 	]+887342fb[ 	]+cv.dotusp.sc.h	t0,t1,t2
+[  ]+17c:[ 	]+887352fb[ 	]+cv.dotusp.sc.b	t0,t1,t2
+[  ]+180:[ 	]+88a3e37b[ 	]+cv.dotusp.sci.h	t1,t2,20
+[  ]+184:[ 	]+88a3f37b[ 	]+cv.dotusp.sci.b	t1,t2,20
+[  ]+188:[ 	]+907302fb[ 	]+cv.dotsp.h	t0,t1,t2
+[  ]+18c:[ 	]+907312fb[ 	]+cv.dotsp.b	t0,t1,t2
+[  ]+190:[ 	]+907342fb[ 	]+cv.dotsp.sc.h	t0,t1,t2
+[  ]+194:[ 	]+907352fb[ 	]+cv.dotsp.sc.b	t0,t1,t2
+[  ]+198:[ 	]+90a3e37b[ 	]+cv.dotsp.sci.h	t1,t2,20
+[  ]+19c:[ 	]+90a3f37b[ 	]+cv.dotsp.sci.b	t1,t2,20
+[  ]+1a0:[ 	]+987302fb[ 	]+cv.sdotup.h	t0,t1,t2
+[  ]+1a4:[ 	]+987312fb[ 	]+cv.sdotup.b	t0,t1,t2
+[  ]+1a8:[ 	]+987342fb[ 	]+cv.sdotup.sc.h	t0,t1,t2
+[  ]+1ac:[ 	]+987352fb[ 	]+cv.sdotup.sc.b	t0,t1,t2
+[  ]+1b0:[ 	]+98a3e37b[ 	]+cv.sdotup.sci.h	t1,t2,20
+[  ]+1b4:[ 	]+98a3f37b[ 	]+cv.sdotup.sci.b	t1,t2,20
+[  ]+1b8:[ 	]+a07302fb[ 	]+cv.sdotusp.h	t0,t1,t2
+[  ]+1bc:[ 	]+a07312fb[ 	]+cv.sdotusp.b	t0,t1,t2
+[  ]+1c0:[ 	]+a07342fb[ 	]+cv.sdotusp.sc.h	t0,t1,t2
+[  ]+1c4:[ 	]+a07352fb[ 	]+cv.sdotusp.sc.b	t0,t1,t2
+[  ]+1c8:[ 	]+a0a3e37b[ 	]+cv.sdotusp.sci.h	t1,t2,20
+[  ]+1cc:[ 	]+a0a3f37b[ 	]+cv.sdotusp.sci.b	t1,t2,20
+[  ]+1d0:[ 	]+a87302fb[ 	]+cv.sdotsp.h	t0,t1,t2
+[  ]+1d4:[ 	]+a87312fb[ 	]+cv.sdotsp.b	t0,t1,t2
+[  ]+1d8:[ 	]+a87342fb[ 	]+cv.sdotsp.sc.h	t0,t1,t2
+[  ]+1dc:[ 	]+a87352fb[ 	]+cv.sdotsp.sc.b	t0,t1,t2
+[  ]+1e0:[ 	]+a8a3e37b[ 	]+cv.sdotsp.sci.h	t1,t2,20
+[  ]+1e4:[ 	]+a8a3f37b[ 	]+cv.sdotsp.sci.b	t1,t2,20
+[  ]+1e8:[ 	]+b8a3837b[ 	]+cv.extract.h	t1,t2,20
+[  ]+1ec:[ 	]+b8a3937b[ 	]+cv.extract.b	t1,t2,20
+[  ]+1f0:[ 	]+b8a3a37b[ 	]+cv.extractu.h	t1,t2,20
+[  ]+1f4:[ 	]+b8a3b37b[ 	]+cv.extractu.b	t1,t2,20
+[  ]+1f8:[ 	]+b8a3c37b[ 	]+cv.insert.h	t1,t2,20
+[  ]+1fc:[ 	]+b8a3d37b[ 	]+cv.insert.b	t1,t2,20
+[  ]+200:[ 	]+c07302fb[ 	]+cv.shuffle.h	t0,t1,t2
+[  ]+204:[ 	]+c07312fb[ 	]+cv.shuffle.b	t0,t1,t2
+[  ]+208:[ 	]+c0a3e37b[ 	]+cv.shuffle.sci.h	t1,t2,20
+[  ]+20c:[ 	]+c0a3f37b[ 	]+cv.shufflei0.sci.b	t1,t2,20
+[  ]+210:[ 	]+c8a3f37b[ 	]+cv.shufflei1.sci.b	t1,t2,20
+[  ]+214:[ 	]+d0a3f37b[ 	]+cv.shufflei2.sci.b	t1,t2,20
+[  ]+218:[ 	]+d8a3f37b[ 	]+cv.shufflei3.sci.b	t1,t2,20
+[  ]+21c:[ 	]+e07302fb[ 	]+cv.shuffle2.h	t0,t1,t2
+[  ]+220:[ 	]+e07312fb[ 	]+cv.shuffle2.b	t0,t1,t2
+[  ]+224:[ 	]+f07302fb[ 	]+cv.pack	t0,t1,t2
+[  ]+228:[ 	]+f27302fb[ 	]+cv.pack.h	t0,t1,t2
+[  ]+22c:[ 	]+fa7312fb[ 	]+cv.packhi.b	t0,t1,t2
+[  ]+230:[ 	]+f87312fb[ 	]+cv.packlo.b	t0,t1,t2
+[  ]+234:[ 	]+047302fb[ 	]+cv.cmpeq.h	t0,t1,t2
+[  ]+238:[ 	]+047312fb[ 	]+cv.cmpeq.b	t0,t1,t2
+[  ]+23c:[ 	]+047342fb[ 	]+cv.cmpeq.sc.h	t0,t1,t2
+[  ]+240:[ 	]+047352fb[ 	]+cv.cmpeq.sc.b	t0,t1,t2
+[  ]+244:[ 	]+04a3e37b[ 	]+cv.cmpeq.sci.h	t1,t2,20
+[  ]+248:[ 	]+04a3f37b[ 	]+cv.cmpeq.sci.b	t1,t2,20
+[  ]+24c:[ 	]+0c7302fb[ 	]+cv.cmpne.h	t0,t1,t2
+[  ]+250:[ 	]+0c7312fb[ 	]+cv.cmpne.b	t0,t1,t2
+[  ]+254:[ 	]+0c7342fb[ 	]+cv.cmpne.sc.h	t0,t1,t2
+[  ]+258:[ 	]+0c7352fb[ 	]+cv.cmpne.sc.b	t0,t1,t2
+[  ]+25c:[ 	]+0ca3e37b[ 	]+cv.cmpne.sci.h	t1,t2,20
+[  ]+260:[ 	]+0ca3f37b[ 	]+cv.cmpne.sci.b	t1,t2,20
+[  ]+264:[ 	]+147302fb[ 	]+cv.cmpgt.h	t0,t1,t2
+[  ]+268:[ 	]+147312fb[ 	]+cv.cmpgt.b	t0,t1,t2
+[  ]+26c:[ 	]+147342fb[ 	]+cv.cmpgt.sc.h	t0,t1,t2
+[  ]+270:[ 	]+147352fb[ 	]+cv.cmpgt.sc.b	t0,t1,t2
+[  ]+274:[ 	]+14a3e37b[ 	]+cv.cmpgt.sci.h	t1,t2,20
+[  ]+278:[ 	]+14a3f37b[ 	]+cv.cmpgt.sci.b	t1,t2,20
+[  ]+27c:[ 	]+1c7302fb[ 	]+cv.cmpge.h	t0,t1,t2
+[  ]+280:[ 	]+1c7312fb[ 	]+cv.cmpge.b	t0,t1,t2
+[  ]+284:[ 	]+1c7342fb[ 	]+cv.cmpge.sc.h	t0,t1,t2
+[  ]+288:[ 	]+1c7352fb[ 	]+cv.cmpge.sc.b	t0,t1,t2
+[  ]+28c:[ 	]+1ca3e37b[ 	]+cv.cmpge.sci.h	t1,t2,20
+[  ]+290:[ 	]+1ca3f37b[ 	]+cv.cmpge.sci.b	t1,t2,20
+[  ]+294:[ 	]+247302fb[ 	]+cv.cmplt.h	t0,t1,t2
+[  ]+298:[ 	]+247312fb[ 	]+cv.cmplt.b	t0,t1,t2
+[  ]+29c:[ 	]+247342fb[ 	]+cv.cmplt.sc.h	t0,t1,t2
+[  ]+2a0:[ 	]+247352fb[ 	]+cv.cmplt.sc.b	t0,t1,t2
+[  ]+2a4:[ 	]+24a3e37b[ 	]+cv.cmplt.sci.h	t1,t2,20
+[  ]+2a8:[ 	]+24a3f37b[ 	]+cv.cmplt.sci.b	t1,t2,20
+[  ]+2ac:[ 	]+2c7302fb[ 	]+cv.cmple.h	t0,t1,t2
+[  ]+2b0:[ 	]+2c7312fb[ 	]+cv.cmple.b	t0,t1,t2
+[  ]+2b4:[ 	]+2c7342fb[ 	]+cv.cmple.sc.h	t0,t1,t2
+[  ]+2b8:[ 	]+2c7352fb[ 	]+cv.cmple.sc.b	t0,t1,t2
+[  ]+2bc:[ 	]+2ca3e37b[ 	]+cv.cmple.sci.h	t1,t2,20
+[  ]+2c0:[ 	]+2ca3f37b[ 	]+cv.cmple.sci.b	t1,t2,20
+[  ]+2c4:[ 	]+347302fb[ 	]+cv.cmpgtu.h	t0,t1,t2
+[  ]+2c8:[ 	]+347312fb[ 	]+cv.cmpgtu.b	t0,t1,t2
+[  ]+2cc:[ 	]+347342fb[ 	]+cv.cmpgtu.sc.h	t0,t1,t2
+[  ]+2d0:[ 	]+347352fb[ 	]+cv.cmpgtu.sc.b	t0,t1,t2
+[  ]+2d4:[ 	]+34a3e37b[ 	]+cv.cmpgtu.sci.h	t1,t2,20
+[  ]+2d8:[ 	]+34a3f37b[ 	]+cv.cmpgtu.sci.b	t1,t2,20
+[  ]+2dc:[ 	]+3c7302fb[ 	]+cv.cmpgeu.h	t0,t1,t2
+[  ]+2e0:[ 	]+3c7312fb[ 	]+cv.cmpgeu.b	t0,t1,t2
+[  ]+2e4:[ 	]+3c7342fb[ 	]+cv.cmpgeu.sc.h	t0,t1,t2
+[  ]+2e8:[ 	]+3c7352fb[ 	]+cv.cmpgeu.sc.b	t0,t1,t2
+[  ]+2ec:[ 	]+3ca3e37b[ 	]+cv.cmpgeu.sci.h	t1,t2,20
+[  ]+2f0:[ 	]+3ca3f37b[ 	]+cv.cmpgeu.sci.b	t1,t2,20
+[  ]+2f4:[ 	]+447302fb[ 	]+cv.cmpltu.h	t0,t1,t2
+[  ]+2f8:[ 	]+447312fb[ 	]+cv.cmpltu.b	t0,t1,t2
+[  ]+2fc:[ 	]+447342fb[ 	]+cv.cmpltu.sc.h	t0,t1,t2
+[  ]+300:[ 	]+447352fb[ 	]+cv.cmpltu.sc.b	t0,t1,t2
+[  ]+304:[ 	]+44a3e37b[ 	]+cv.cmpltu.sci.h	t1,t2,20
+[  ]+308:[ 	]+44a3f37b[ 	]+cv.cmpltu.sci.b	t1,t2,20
+[  ]+30c:[ 	]+4c7302fb[ 	]+cv.cmpleu.h	t0,t1,t2
+[  ]+310:[ 	]+4c7312fb[ 	]+cv.cmpleu.b	t0,t1,t2
+[  ]+314:[ 	]+4c7342fb[ 	]+cv.cmpleu.sc.h	t0,t1,t2
+[  ]+318:[ 	]+4c7352fb[ 	]+cv.cmpleu.sc.b	t0,t1,t2
+[  ]+31c:[ 	]+4ca3e37b[ 	]+cv.cmpleu.sci.h	t1,t2,20
+[  ]+320:[ 	]+4ca3f37b[ 	]+cv.cmpleu.sci.b	t1,t2,20
+[  ]+324:[ 	]+547302fb[ 	]+cv.cplxmul.r	t0,t1,t2
+[  ]+328:[ 	]+567302fb[ 	]+cv.cplxmul.i	t0,t1,t2
+[  ]+32c:[ 	]+547322fb[ 	]+cv.cplxmul.r.div2	t0,t1,t2
+[  ]+330:[ 	]+567322fb[ 	]+cv.cplxmul.i.div2	t0,t1,t2
+[  ]+334:[ 	]+547342fb[ 	]+cv.cplxmul.r.div4	t0,t1,t2
+[  ]+338:[ 	]+567342fb[ 	]+cv.cplxmul.i.div4	t0,t1,t2
+[  ]+33c:[ 	]+547362fb[ 	]+cv.cplxmul.r.div8	t0,t1,t2
+[  ]+340:[ 	]+567362fb[ 	]+cv.cplxmul.i.div8	t0,t1,t2
+[  ]+344:[ 	]+5c03837b[ 	]+cv.cplxconj	t1,t2
+[  ]+348:[ 	]+647302fb[ 	]+cv.subrotmj	t0,t1,t2
+[  ]+34c:[ 	]+647322fb[ 	]+cv.subrotmj.div2	t0,t1,t2
+[  ]+350:[ 	]+647342fb[ 	]+cv.subrotmj.div4	t0,t1,t2
+[  ]+354:[ 	]+647362fb[ 	]+cv.subrotmj.div8	t0,t1,t2
+[  ]+358:[ 	]+6c7322fb[ 	]+cv.add.div2	t0,t1,t2
+[  ]+35c:[ 	]+6c7342fb[ 	]+cv.add.div4	t0,t1,t2
+[  ]+360:[ 	]+6c7362fb[ 	]+cv.add.div8	t0,t1,t2
+[  ]+364:[ 	]+747322fb[ 	]+cv.sub.div2	t0,t1,t2
+[  ]+368:[ 	]+747342fb[ 	]+cv.sub.div4	t0,t1,t2
+[  ]+36c:[ 	]+747362fb[ 	]+cv.sub.div8	t0,t1,t2
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.s b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.s
new file mode 100644
index 0000000000000000000000000000000000000000..a63586918cd81769edafec3188ca1e142fca38ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.s
@@ -0,0 +1,221 @@
+target: 
+    cv.add.h x5, x6, x7
+    cv.add.b x5, x6, x7
+    cv.add.sc.h x5, x6, x7
+    cv.add.sc.b x5, x6, x7
+    cv.add.sci.h x6, x7, 20
+    cv.add.sci.b x6, x7, 20
+    cv.sub.h x5, x6, x7
+    cv.sub.b x5, x6, x7
+    cv.sub.sc.h x5, x6, x7
+    cv.sub.sc.b x5, x6, x7
+    cv.sub.sci.h x6, x7, 20
+    cv.sub.sci.b x6, x7, 20
+    cv.avg.h x5, x6, x7
+    cv.avg.b x5, x6, x7
+    cv.avg.sc.h x5, x6, x7
+    cv.avg.sc.b x5, x6, x7
+    cv.avg.sci.h x6, x7, 20
+    cv.avg.sci.b x6, x7, 20
+    cv.avgu.h x5, x6, x7
+    cv.avgu.b x5, x6, x7
+    cv.avgu.sc.h x5, x6, x7
+    cv.avgu.sc.b x5, x6, x7
+    cv.avgu.sci.h x6, x7, 20
+    cv.avgu.sci.b x6, x7, 20
+    cv.min.h x5, x6, x7
+    cv.min.b x5, x6, x7
+    cv.min.sc.h x5, x6, x7
+    cv.min.sc.b x5, x6, x7
+    cv.min.sci.h x6, x7, 20
+    cv.min.sci.b x6, x7, 20
+    cv.minu.h x5, x6, x7
+    cv.minu.b x5, x6, x7
+    cv.minu.sc.h x5, x6, x7
+    cv.minu.sc.b x5, x6, x7
+    cv.minu.sci.h x6, x7, 20
+    cv.minu.sci.b x6, x7, 20
+    cv.max.h x5, x6, x7
+    cv.max.b x5, x6, x7
+    cv.max.sc.h x5, x6, x7
+    cv.max.sc.b x5, x6, x7
+    cv.max.sci.h x6, x7, 20
+    cv.max.sci.b x6, x7, 20
+    cv.maxu.h x5, x6, x7
+    cv.maxu.b x5, x6, x7
+    cv.maxu.sc.h x5, x6, x7
+    cv.maxu.sc.b x5, x6, x7
+    cv.maxu.sci.h x6, x7, 20
+    cv.maxu.sci.b x6, x7, 20
+    cv.srl.h x5, x6, x7
+    cv.srl.b x5, x6, x7
+    cv.srl.sc.h x5, x6, x7
+    cv.srl.sc.b x5, x6, x7
+    cv.srl.sci.h x6, x7, 20
+    cv.srl.sci.b x6, x7, 20
+    cv.sra.h x5, x6, x7
+    cv.sra.b x5, x6, x7
+    cv.sra.sc.h x5, x6, x7
+    cv.sra.sc.b x5, x6, x7
+    cv.sra.sci.h x6, x7, 20
+    cv.sra.sci.b x6, x7, 20
+    cv.sll.h x5, x6, x7
+    cv.sll.b x5, x6, x7
+    cv.sll.sc.h x5, x6, x7
+    cv.sll.sc.b x5, x6, x7
+    cv.sll.sci.h x6, x7, 20
+    cv.sll.sci.b x6, x7, 20
+    cv.or.h x5, x6, x7
+    cv.or.b x5, x6, x7
+    cv.or.sc.h x5, x6, x7
+    cv.or.sc.b x5, x6, x7
+    cv.or.sci.h x6, x7, 20
+    cv.or.sci.b x6, x7, 20
+    cv.xor.h x5, x6, x7
+    cv.xor.b x5, x6, x7
+    cv.xor.sc.h x5, x6, x7
+    cv.xor.sc.b x5, x6, x7
+    cv.xor.sci.h x6, x7, 20
+    cv.xor.sci.b x6, x7, 20
+    cv.and.h x5, x6, x7
+    cv.and.b x5, x6, x7
+    cv.and.sc.h x5, x6, x7
+    cv.and.sc.b x5, x6, x7
+    cv.and.sci.h x6, x7, 20
+    cv.and.sci.b x6, x7, 20
+    cv.abs.h x6, x7
+    cv.abs.b x6, x7
+    cv.dotup.h x5, x6, x7
+    cv.dotup.b x5, x6, x7
+    cv.dotup.sc.h x5, x6, x7
+    cv.dotup.sc.b x5, x6, x7
+    cv.dotup.sci.h x6, x7, 20
+    cv.dotup.sci.b x6, x7, 20
+    cv.dotusp.h x5, x6, x7
+    cv.dotusp.b x5, x6, x7
+    cv.dotusp.sc.h x5, x6, x7
+    cv.dotusp.sc.b x5, x6, x7
+    cv.dotusp.sci.h x6, x7, 20
+    cv.dotusp.sci.b x6, x7, 20
+    cv.dotsp.h x5, x6, x7
+    cv.dotsp.b x5, x6, x7
+    cv.dotsp.sc.h x5, x6, x7
+    cv.dotsp.sc.b x5, x6, x7
+    cv.dotsp.sci.h x6, x7, 20
+    cv.dotsp.sci.b x6, x7, 20
+    cv.sdotup.h x5, x6, x7
+    cv.sdotup.b x5, x6, x7
+    cv.sdotup.sc.h x5, x6, x7
+    cv.sdotup.sc.b x5, x6, x7
+    cv.sdotup.sci.h x6, x7, 20
+    cv.sdotup.sci.b x6, x7, 20
+    cv.sdotusp.h x5, x6, x7
+    cv.sdotusp.b x5, x6, x7
+    cv.sdotusp.sc.h x5, x6, x7
+    cv.sdotusp.sc.b x5, x6, x7
+    cv.sdotusp.sci.h x6, x7, 20
+    cv.sdotusp.sci.b x6, x7, 20
+    cv.sdotsp.h x5, x6, x7
+    cv.sdotsp.b x5, x6, x7
+    cv.sdotsp.sc.h x5, x6, x7
+    cv.sdotsp.sc.b x5, x6, x7
+    cv.sdotsp.sci.h x6, x7, 20
+    cv.sdotsp.sci.b x6, x7, 20
+    cv.extract.h x6, x7, 20
+    cv.extract.b x6, x7, 20
+    cv.extractu.h x6, x7, 20
+    cv.extractu.b x6, x7, 20
+    cv.insert.h x6, x7, 20
+    cv.insert.b x6, x7, 20
+    cv.shuffle.h x5, x6, x7
+    cv.shuffle.b x5, x6, x7
+    cv.shuffle.sci.h x6, x7, 20
+    cv.shufflei0.sci.b x6, x7, 20
+    cv.shufflei1.sci.b x6, x7, 20
+    cv.shufflei2.sci.b x6, x7, 20
+    cv.shufflei3.sci.b x6, x7, 20
+    cv.shuffle2.h x5, x6, x7
+    cv.shuffle2.b x5, x6, x7
+    cv.pack x5, x6, x7
+    cv.pack.h x5, x6, x7
+    cv.packhi.b x5, x6, x7
+    cv.packlo.b x5, x6, x7
+    cv.cmpeq.h x5, x6, x7
+    cv.cmpeq.b x5, x6, x7
+    cv.cmpeq.sc.h x5, x6, x7
+    cv.cmpeq.sc.b x5, x6, x7
+    cv.cmpeq.sci.h x6, x7, 20
+    cv.cmpeq.sci.b x6, x7, 20
+    cv.cmpne.h x5, x6, x7
+    cv.cmpne.b x5, x6, x7
+    cv.cmpne.sc.h x5, x6, x7
+    cv.cmpne.sc.b x5, x6, x7
+    cv.cmpne.sci.h x6, x7, 20
+    cv.cmpne.sci.b x6, x7, 20
+    cv.cmpgt.h x5, x6, x7
+    cv.cmpgt.b x5, x6, x7
+    cv.cmpgt.sc.h x5, x6, x7
+    cv.cmpgt.sc.b x5, x6, x7
+    cv.cmpgt.sci.h x6, x7, 20
+    cv.cmpgt.sci.b x6, x7, 20
+    cv.cmpge.h x5, x6, x7
+    cv.cmpge.b x5, x6, x7
+    cv.cmpge.sc.h x5, x6, x7
+    cv.cmpge.sc.b x5, x6, x7
+    cv.cmpge.sci.h x6, x7, 20
+    cv.cmpge.sci.b x6, x7, 20
+    cv.cmplt.h x5, x6, x7
+    cv.cmplt.b x5, x6, x7
+    cv.cmplt.sc.h x5, x6, x7
+    cv.cmplt.sc.b x5, x6, x7
+    cv.cmplt.sci.h x6, x7, 20
+    cv.cmplt.sci.b x6, x7, 20
+    cv.cmple.h x5, x6, x7
+    cv.cmple.b x5, x6, x7
+    cv.cmple.sc.h x5, x6, x7
+    cv.cmple.sc.b x5, x6, x7
+    cv.cmple.sci.h x6, x7, 20
+    cv.cmple.sci.b x6, x7, 20
+    cv.cmpgtu.h x5, x6, x7
+    cv.cmpgtu.b x5, x6, x7
+    cv.cmpgtu.sc.h x5, x6, x7
+    cv.cmpgtu.sc.b x5, x6, x7
+    cv.cmpgtu.sci.h x6, x7, 20
+    cv.cmpgtu.sci.b x6, x7, 20
+    cv.cmpgeu.h x5, x6, x7
+    cv.cmpgeu.b x5, x6, x7
+    cv.cmpgeu.sc.h x5, x6, x7
+    cv.cmpgeu.sc.b x5, x6, x7
+    cv.cmpgeu.sci.h x6, x7, 20
+    cv.cmpgeu.sci.b x6, x7, 20
+    cv.cmpltu.h x5, x6, x7
+    cv.cmpltu.b x5, x6, x7
+    cv.cmpltu.sc.h x5, x6, x7
+    cv.cmpltu.sc.b x5, x6, x7
+    cv.cmpltu.sci.h x6, x7, 20
+    cv.cmpltu.sci.b x6, x7, 20
+    cv.cmpleu.h x5, x6, x7
+    cv.cmpleu.b x5, x6, x7
+    cv.cmpleu.sc.h x5, x6, x7
+    cv.cmpleu.sc.b x5, x6, x7
+    cv.cmpleu.sci.h x6, x7, 20
+    cv.cmpleu.sci.b x6, x7, 20
+    cv.cplxmul.r x5, x6, x7
+    cv.cplxmul.i x5, x6, x7
+    cv.cplxmul.r.div2 x5, x6, x7
+    cv.cplxmul.i.div2 x5, x6, x7
+    cv.cplxmul.r.div4 x5, x6, x7
+    cv.cplxmul.i.div4 x5, x6, x7
+    cv.cplxmul.r.div8 x5, x6, x7
+    cv.cplxmul.i.div8 x5, x6, x7
+    cv.cplxconj x6, x7
+    cv.subrotmj x5, x6, x7
+    cv.subrotmj.div2 x5, x6, x7
+    cv.subrotmj.div4 x5, x6, x7
+    cv.subrotmj.div8 x5, x6, x7
+    cv.add.div2 x5, x6, x7
+    cv.add.div4 x5, x6, x7
+    cv.add.div8 x5, x6, x7
+    cv.sub.div2 x5, x6, x7
+    cv.sub.div4 x5, x6, x7
+    cv.sub.div8 x5, x6, x7
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..7adfdf10d878f11c7e32d05dac1c9d24428eb870
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-b-fail.s
+#error_output: cv-simd-max-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ffa9db5ce2eb6c6b1972f8b54b5003413d817d6e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.b x32,x32,x32'
+.*: Error: illegal operands `cv.max.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6e172d02599fc6d1522f745bf01683923eb0ae6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.max.b x32, x32, x32
+    cv.max.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..994a4c89222a46ea70ffc9cbd921d9e739ba5611
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000107b          	cv.max.b	zero,zero,zero
+   4:	301090fb          	cv.max.b	ra,ra,ra
+   8:	3021117b          	cv.max.b	sp,sp,sp
+   c:	3084147b          	cv.max.b	s0,s0,s0
+  10:	314a1a7b          	cv.max.b	s4,s4,s4
+  14:	31ff9ffb          	cv.max.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c3fbaac00363ee14ad7ea7d31389572ad36628f8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.max.b x0, x0, x0
+    cv.max.b x1, x1, x1
+    cv.max.b x2, x2, x2
+    cv.max.b x8, x8, x8
+    cv.max.b x20, x20, x20
+    cv.max.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2902f67e7c2d38c461396cd116baebb90bbc76b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-h-fail.s
+#error_output: cv-simd-max-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..e99ba005a12351f7e65d168a3f0b59e966e18008
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.h x32,x32,x32'
+.*: Error: illegal operands `cv.max.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a8b7670f0e33730bd82c4d3fa68f1326c8418b82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.max.h x32, x32, x32
+    cv.max.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..296f9e597db3754c5774d45651839d92967a4100
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000007b          	cv.max.h	zero,zero,zero
+   4:	301080fb          	cv.max.h	ra,ra,ra
+   8:	3021017b          	cv.max.h	sp,sp,sp
+   c:	3084047b          	cv.max.h	s0,s0,s0
+  10:	314a0a7b          	cv.max.h	s4,s4,s4
+  14:	31ff8ffb          	cv.max.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..db8bdcc94b543b4f1e4baf0b7c4d84e63d855ed9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.max.h x0, x0, x0
+    cv.max.h x1, x1, x1
+    cv.max.h x2, x2, x2
+    cv.max.h x8, x8, x8
+    cv.max.h x20, x20, x20
+    cv.max.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..200aebfe5b86b2cd089dcb058899578471f4bb44
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-b-fail.s
+#error_output: cv-simd-max-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..62bb8033164556fcc4fa8f2f7c432f2600261689
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.max.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9856ce452ad4b8f287cdf2070728757e63fa8b74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.max.sc.b x32, x32, x32
+    cv.max.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f986253741cbf0754369c9cd7f95022c1d086581
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000507b          	cv.max.sc.b	zero,zero,zero
+   4:	3010d0fb          	cv.max.sc.b	ra,ra,ra
+   8:	3021517b          	cv.max.sc.b	sp,sp,sp
+   c:	3084547b          	cv.max.sc.b	s0,s0,s0
+  10:	314a5a7b          	cv.max.sc.b	s4,s4,s4
+  14:	31ffdffb          	cv.max.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..bd6af1624d92b27fe8035e554561d1fed08ea731
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.max.sc.b x0, x0, x0
+    cv.max.sc.b x1, x1, x1
+    cv.max.sc.b x2, x2, x2
+    cv.max.sc.b x8, x8, x8
+    cv.max.sc.b x20, x20, x20
+    cv.max.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..4c79df34eac132667e37b506bc510068a70788cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-h-fail.s
+#error_output: cv-simd-max-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1b60f1d2a9be1423e1b4795c5b05d80d12a879b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.max.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..cb311e985bd0ebb6b59a94e351eebb2518f92c94
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.max.sc.h x32, x32, x32
+    cv.max.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..bfecf4ece4224405c83a9d131391ea5a9e4eb1f8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000407b          	cv.max.sc.h	zero,zero,zero
+   4:	3010c0fb          	cv.max.sc.h	ra,ra,ra
+   8:	3021417b          	cv.max.sc.h	sp,sp,sp
+   c:	3084447b          	cv.max.sc.h	s0,s0,s0
+  10:	314a4a7b          	cv.max.sc.h	s4,s4,s4
+  14:	31ffcffb          	cv.max.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..73e7b4ed3f57c1034b6af133f7180f316a2e4a61
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.max.sc.h x0, x0, x0
+    cv.max.sc.h x1, x1, x1
+    cv.max.sc.h x2, x2, x2
+    cv.max.sc.h x8, x8, x8
+    cv.max.sc.h x20, x20, x20
+    cv.max.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2c1fdd0fae43e2b847bbd25b753d30b0f8ae7c98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-b-fail.s
+#error_output: cv-simd-max-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..27fd4658b42c9dadb4b737a7c2ffffe2a0fc50df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.max.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f6712c3ac94a2467f91ab8a97b7bba74c759375c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.max.sci.b x32, x32, 20
+    cv.max.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.max.sci.b x6, x7, -33
+    cv.max.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..bd6d549cff15619bcf6ba1f16c36b1e877f83835
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	30a0707b          	cv.max.sci.b	zero,zero,20
+   4:	30a0f0fb          	cv.max.sci.b	ra,ra,20
+   8:	30a1717b          	cv.max.sci.b	sp,sp,20
+   c:	30a4747b          	cv.max.sci.b	s0,s0,20
+  10:	30aa7a7b          	cv.max.sci.b	s4,s4,20
+  14:	30affffb          	cv.max.sci.b	t6,t6,20
+  18:	3103f37b          	cv.max.sci.b	t1,t2,-32
+  1c:	3003f37b          	cv.max.sci.b	t1,t2,0
+  20:	32f3f37b          	cv.max.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..10751b5b3eb88f909aa5c854a636604fd0354a3f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.max.sci.b x0, x0, 20
+    cv.max.sci.b x1, x1, 20
+    cv.max.sci.b x2, x2, 20
+    cv.max.sci.b x8, x8, 20
+    cv.max.sci.b x20, x20, 20
+    cv.max.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.max.sci.b x6, x7, -32
+    cv.max.sci.b x6, x7, 0
+    cv.max.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2230bd4ed6d44f475b444aa865290ed27daa2071
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-h-fail.s
+#error_output: cv-simd-max-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..de60c07a756ace245efc50269f4735162633cb42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.max.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..fc8b8dd178f5ba4a3b37cca2cb646eeb213437af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.max.sci.h x32, x32, 20
+    cv.max.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.max.sci.h x6, x7, -33
+    cv.max.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..022f13aedd50c40c589e51a1421f0197b9331c26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	30a0607b          	cv.max.sci.h	zero,zero,20
+   4:	30a0e0fb          	cv.max.sci.h	ra,ra,20
+   8:	30a1617b          	cv.max.sci.h	sp,sp,20
+   c:	30a4647b          	cv.max.sci.h	s0,s0,20
+  10:	30aa6a7b          	cv.max.sci.h	s4,s4,20
+  14:	30afeffb          	cv.max.sci.h	t6,t6,20
+  18:	3103e37b          	cv.max.sci.h	t1,t2,-32
+  1c:	3003e37b          	cv.max.sci.h	t1,t2,0
+  20:	32f3e37b          	cv.max.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f0e4c7b06127441272b4e1c7751eb7af64a2954c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.max.sci.h x0, x0, 20
+    cv.max.sci.h x1, x1, 20
+    cv.max.sci.h x2, x2, 20
+    cv.max.sci.h x8, x8, 20
+    cv.max.sci.h x20, x20, 20
+    cv.max.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.max.sci.h x6, x7, -32
+    cv.max.sci.h x6, x7, 0
+    cv.max.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..ece0eb491ceb7e8c5412b582716953bdbb9a433d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-b-fail.s
+#error_output: cv-simd-maxu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ac57a2f9361207b9b72de5cb8f8cdd065926334e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.b x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..aa05e82b980f78caa7fe1985154068811f17da00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.maxu.b x32, x32, x32
+    cv.maxu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4d7a1e8ac05b0d5439432ff2cb8b697566e66439
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800107b          	cv.maxu.b	zero,zero,zero
+   4:	381090fb          	cv.maxu.b	ra,ra,ra
+   8:	3821117b          	cv.maxu.b	sp,sp,sp
+   c:	3884147b          	cv.maxu.b	s0,s0,s0
+  10:	394a1a7b          	cv.maxu.b	s4,s4,s4
+  14:	39ff9ffb          	cv.maxu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6a87bf969b29ac3770c024dd0d350d432de6fa71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.maxu.b x0, x0, x0
+    cv.maxu.b x1, x1, x1
+    cv.maxu.b x2, x2, x2
+    cv.maxu.b x8, x8, x8
+    cv.maxu.b x20, x20, x20
+    cv.maxu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..60114f2669af1bc332c6ec287285efed20877785
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-h-fail.s
+#error_output: cv-simd-maxu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1d530582eaab6da162dea37007a0917dc24f46c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.h x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f28718085c5ef983d1f25d249a9f1d81ba36b5d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.maxu.h x32, x32, x32
+    cv.maxu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ebc70e756474abac23f5937d63292f2007818662
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800007b          	cv.maxu.h	zero,zero,zero
+   4:	381080fb          	cv.maxu.h	ra,ra,ra
+   8:	3821017b          	cv.maxu.h	sp,sp,sp
+   c:	3884047b          	cv.maxu.h	s0,s0,s0
+  10:	394a0a7b          	cv.maxu.h	s4,s4,s4
+  14:	39ff8ffb          	cv.maxu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ecafc3afd1c451099e41ad8287c9adfeedacb571
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.maxu.h x0, x0, x0
+    cv.maxu.h x1, x1, x1
+    cv.maxu.h x2, x2, x2
+    cv.maxu.h x8, x8, x8
+    cv.maxu.h x20, x20, x20
+    cv.maxu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a1da7306139baa79a16f43c97ec2cf2ee88bc814
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-b-fail.s
+#error_output: cv-simd-maxu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7f1928d30bdf05e542c0cdbd310de83c925477ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..68b8f9e41019a30cf39bbb55c272db8c87711622
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.maxu.sc.b x32, x32, x32
+    cv.maxu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5e18aca58ace63a22bff38b98e409ca3c36a59c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800507b          	cv.maxu.sc.b	zero,zero,zero
+   4:	3810d0fb          	cv.maxu.sc.b	ra,ra,ra
+   8:	3821517b          	cv.maxu.sc.b	sp,sp,sp
+   c:	3884547b          	cv.maxu.sc.b	s0,s0,s0
+  10:	394a5a7b          	cv.maxu.sc.b	s4,s4,s4
+  14:	39ffdffb          	cv.maxu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..37273c1beb44b56da7caad9bb21de74fc60e7c4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.maxu.sc.b x0, x0, x0
+    cv.maxu.sc.b x1, x1, x1
+    cv.maxu.sc.b x2, x2, x2
+    cv.maxu.sc.b x8, x8, x8
+    cv.maxu.sc.b x20, x20, x20
+    cv.maxu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..91c8ef5f879deadb5f40f47e8b9506ade1cb315a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-h-fail.s
+#error_output: cv-simd-maxu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1fc68d464286963083dd1cb7a4d60a1b19442e9b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..1dd73f293cee89d7057eab96ad582b846ebfea2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.maxu.sc.h x32, x32, x32
+    cv.maxu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..451224eea8222ca891ae01f5a370308560c61ac4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800407b          	cv.maxu.sc.h	zero,zero,zero
+   4:	3810c0fb          	cv.maxu.sc.h	ra,ra,ra
+   8:	3821417b          	cv.maxu.sc.h	sp,sp,sp
+   c:	3884447b          	cv.maxu.sc.h	s0,s0,s0
+  10:	394a4a7b          	cv.maxu.sc.h	s4,s4,s4
+  14:	39ffcffb          	cv.maxu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5d1c42c962a65b8a65f69c5f0ecbb38ed56d77dd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.maxu.sc.h x0, x0, x0
+    cv.maxu.sc.h x1, x1, x1
+    cv.maxu.sc.h x2, x2, x2
+    cv.maxu.sc.h x8, x8, x8
+    cv.maxu.sc.h x20, x20, x20
+    cv.maxu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..260b58a43b882ae4c51e9ec9422ac20f944b36dd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-b-fail.s
+#error_output: cv-simd-maxu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c1429c0b23c27ca37005044c67f8e30be772ffbf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.maxu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..7ea3585c8f3ec217c08e9edc62b4818fbeada56a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.maxu.sci.b x32, x32, 20
+    cv.maxu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.maxu.sci.b x6, x7, -1
+    cv.maxu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f7e9be756a1f4a0c978acb174eb5f441680feee3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	38a0707b          	cv.maxu.sci.b	zero,zero,20
+   4:	38a0f0fb          	cv.maxu.sci.b	ra,ra,20
+   8:	38a1717b          	cv.maxu.sci.b	sp,sp,20
+   c:	38a4747b          	cv.maxu.sci.b	s0,s0,20
+  10:	38aa7a7b          	cv.maxu.sci.b	s4,s4,20
+  14:	38affffb          	cv.maxu.sci.b	t6,t6,20
+  18:	3803f37b          	cv.maxu.sci.b	t1,t2,0
+  1c:	3bf3f37b          	cv.maxu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b08e79aa7670e02d081f3a14e49d7a8a644b0505
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.maxu.sci.b x0, x0, 20
+    cv.maxu.sci.b x1, x1, 20
+    cv.maxu.sci.b x2, x2, 20
+    cv.maxu.sci.b x8, x8, 20
+    cv.maxu.sci.b x20, x20, 20
+    cv.maxu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.maxu.sci.b x6, x7, 0
+    cv.maxu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b1841b44de251e8dd520fd9a8ea8cc85d45060fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-h-fail.s
+#error_output: cv-simd-maxu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..444a3b52c41fc7e9bdc05b6bbac163c110e57bec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.maxu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f3a1ceb4fa8f34c2f8cd982a4dbfbcffe55c3da2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.maxu.sci.h x32, x32, 20
+    cv.maxu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.maxu.sci.h x6, x7, -1
+    cv.maxu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..1510bec98f589f51d027cddeddab6831eab2426c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	38a0607b          	cv.maxu.sci.h	zero,zero,20
+   4:	38a0e0fb          	cv.maxu.sci.h	ra,ra,20
+   8:	38a1617b          	cv.maxu.sci.h	sp,sp,20
+   c:	38a4647b          	cv.maxu.sci.h	s0,s0,20
+  10:	38aa6a7b          	cv.maxu.sci.h	s4,s4,20
+  14:	38afeffb          	cv.maxu.sci.h	t6,t6,20
+  18:	3803e37b          	cv.maxu.sci.h	t1,t2,0
+  1c:	3bf3e37b          	cv.maxu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..546da9eb9c1849c0c4a00bbbfb8df820ce184f5a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.maxu.sci.h x0, x0, 20
+    cv.maxu.sci.h x1, x1, 20
+    cv.maxu.sci.h x2, x2, 20
+    cv.maxu.sci.h x8, x8, 20
+    cv.maxu.sci.h x20, x20, 20
+    cv.maxu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.maxu.sci.h x6, x7, 0
+    cv.maxu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8757fdd74bdf19ddb992305197f5f6c76502f9dd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-b-fail.s
+#error_output: cv-simd-min-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3d78d2d91b8e9bef79517156080eff71fb41180b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.b x32,x32,x32'
+.*: Error: illegal operands `cv.min.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0d6ed295eed05c729b904ba9f144c5731dc33819
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.min.b x32, x32, x32
+    cv.min.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..cb238cbc7dd3cc5daa057b4d8d34f25de3f593e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000107b          	cv.min.b	zero,zero,zero
+   4:	201090fb          	cv.min.b	ra,ra,ra
+   8:	2021117b          	cv.min.b	sp,sp,sp
+   c:	2084147b          	cv.min.b	s0,s0,s0
+  10:	214a1a7b          	cv.min.b	s4,s4,s4
+  14:	21ff9ffb          	cv.min.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..40af59781be5660cbda2f36bd4536da0a322faf1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.min.b x0, x0, x0
+    cv.min.b x1, x1, x1
+    cv.min.b x2, x2, x2
+    cv.min.b x8, x8, x8
+    cv.min.b x20, x20, x20
+    cv.min.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fc20e7ebb771e85f8aa4ef25ac35dda1bb0e3246
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-h-fail.s
+#error_output: cv-simd-min-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0f959466de858308caa9e3d72900619af50003d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.h x32,x32,x32'
+.*: Error: illegal operands `cv.min.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2e30e37c7954b7e389c8ebe6fc7bc60bea14bcfb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.min.h x32, x32, x32
+    cv.min.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d3a67463904f1e86f7245e8806c0a081662497c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000007b          	cv.min.h	zero,zero,zero
+   4:	201080fb          	cv.min.h	ra,ra,ra
+   8:	2021017b          	cv.min.h	sp,sp,sp
+   c:	2084047b          	cv.min.h	s0,s0,s0
+  10:	214a0a7b          	cv.min.h	s4,s4,s4
+  14:	21ff8ffb          	cv.min.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f3ab4b20b74b7f2ee19fd2dab2f3d7d10505319d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.min.h x0, x0, x0
+    cv.min.h x1, x1, x1
+    cv.min.h x2, x2, x2
+    cv.min.h x8, x8, x8
+    cv.min.h x20, x20, x20
+    cv.min.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1fc40b59be6a5337d3d7cace6591847a552120b7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-b-fail.s
+#error_output: cv-simd-min-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7f31ec02691612175d5ecf33ba018efa5ff8fbd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.min.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5b7fdcc7aa11bf777a81110f6a8f91a43cda0d37
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.min.sc.b x32, x32, x32
+    cv.min.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..739164a5872e7e51d1d92861c14428b7454ec1e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000507b          	cv.min.sc.b	zero,zero,zero
+   4:	2010d0fb          	cv.min.sc.b	ra,ra,ra
+   8:	2021517b          	cv.min.sc.b	sp,sp,sp
+   c:	2084547b          	cv.min.sc.b	s0,s0,s0
+  10:	214a5a7b          	cv.min.sc.b	s4,s4,s4
+  14:	21ffdffb          	cv.min.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..671b8d32a6bb20be48a324829b6ffc08050ec733
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.min.sc.b x0, x0, x0
+    cv.min.sc.b x1, x1, x1
+    cv.min.sc.b x2, x2, x2
+    cv.min.sc.b x8, x8, x8
+    cv.min.sc.b x20, x20, x20
+    cv.min.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..600b3b9b3ff4daaa32c0cdbf660650ea92177dec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-h-fail.s
+#error_output: cv-simd-min-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..72ce1e76a292d296c9779c3c6653e83e6349b57e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.min.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5b62233762bf520e0002de5737a056f469ed87e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.min.sc.h x32, x32, x32
+    cv.min.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c6361bed1fa29d768d9ea34657f0dea9dbf25eed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000407b          	cv.min.sc.h	zero,zero,zero
+   4:	2010c0fb          	cv.min.sc.h	ra,ra,ra
+   8:	2021417b          	cv.min.sc.h	sp,sp,sp
+   c:	2084447b          	cv.min.sc.h	s0,s0,s0
+  10:	214a4a7b          	cv.min.sc.h	s4,s4,s4
+  14:	21ffcffb          	cv.min.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..19ed53f70add003da3f0a738b99055560f8bdc29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.min.sc.h x0, x0, x0
+    cv.min.sc.h x1, x1, x1
+    cv.min.sc.h x2, x2, x2
+    cv.min.sc.h x8, x8, x8
+    cv.min.sc.h x20, x20, x20
+    cv.min.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..62b171d785679cc59e3669c514f9ba5ab04694ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-b-fail.s
+#error_output: cv-simd-min-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..204cae31c6aa11cbf221abfc6d82fcb581d1fbf7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.min.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6144655cdb0adacc33ba33608906e1b2ba24feb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.min.sci.b x32, x32, 20
+    cv.min.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.min.sci.b x6, x7, -33
+    cv.min.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6c367a193652a19aeb236a08af7dbb5e7ed1ec06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	20a0707b          	cv.min.sci.b	zero,zero,20
+   4:	20a0f0fb          	cv.min.sci.b	ra,ra,20
+   8:	20a1717b          	cv.min.sci.b	sp,sp,20
+   c:	20a4747b          	cv.min.sci.b	s0,s0,20
+  10:	20aa7a7b          	cv.min.sci.b	s4,s4,20
+  14:	20affffb          	cv.min.sci.b	t6,t6,20
+  18:	2103f37b          	cv.min.sci.b	t1,t2,-32
+  1c:	2003f37b          	cv.min.sci.b	t1,t2,0
+  20:	22f3f37b          	cv.min.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..bef55674ef3db36311ef7553fc9daf99c98e16a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.min.sci.b x0, x0, 20
+    cv.min.sci.b x1, x1, 20
+    cv.min.sci.b x2, x2, 20
+    cv.min.sci.b x8, x8, 20
+    cv.min.sci.b x20, x20, 20
+    cv.min.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.min.sci.b x6, x7, -32
+    cv.min.sci.b x6, x7, 0
+    cv.min.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3af7fe1f9122108b3bbce3ccea0cb854b5bbf2f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-h-fail.s
+#error_output: cv-simd-min-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1179f3066630f4dd3ee63cb1a82ea128ee31896a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.min.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..6e911ce5a682390d4730cf551c55b36230b2546a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.min.sci.h x32, x32, 20
+    cv.min.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.min.sci.h x6, x7, -33
+    cv.min.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8d6d6006314d3c6f4b9996562ab7f97c1e67186f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	20a0607b          	cv.min.sci.h	zero,zero,20
+   4:	20a0e0fb          	cv.min.sci.h	ra,ra,20
+   8:	20a1617b          	cv.min.sci.h	sp,sp,20
+   c:	20a4647b          	cv.min.sci.h	s0,s0,20
+  10:	20aa6a7b          	cv.min.sci.h	s4,s4,20
+  14:	20afeffb          	cv.min.sci.h	t6,t6,20
+  18:	2103e37b          	cv.min.sci.h	t1,t2,-32
+  1c:	2003e37b          	cv.min.sci.h	t1,t2,0
+  20:	22f3e37b          	cv.min.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7f134823fabedacd0ce33608ad2d3624f9613683
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.min.sci.h x0, x0, 20
+    cv.min.sci.h x1, x1, 20
+    cv.min.sci.h x2, x2, 20
+    cv.min.sci.h x8, x8, 20
+    cv.min.sci.h x20, x20, 20
+    cv.min.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.min.sci.h x6, x7, -32
+    cv.min.sci.h x6, x7, 0
+    cv.min.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1849d1e58d9f078220e9b9a227cbfade9693875a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-b-fail.s
+#error_output: cv-simd-minu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9971ea8223ece14362a69b1c85db31a7fdf26914
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.b x32,x32,x32'
+.*: Error: illegal operands `cv.minu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c017c91d7c215dac91934d42b4382c7320318b8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.minu.b x32, x32, x32
+    cv.minu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8447639c46700ccdeb755a26cd405f123cc0b814
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800107b          	cv.minu.b	zero,zero,zero
+   4:	281090fb          	cv.minu.b	ra,ra,ra
+   8:	2821117b          	cv.minu.b	sp,sp,sp
+   c:	2884147b          	cv.minu.b	s0,s0,s0
+  10:	294a1a7b          	cv.minu.b	s4,s4,s4
+  14:	29ff9ffb          	cv.minu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1ac118bd7bd20b0226fa8affb6306b0db7b34de4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.minu.b x0, x0, x0
+    cv.minu.b x1, x1, x1
+    cv.minu.b x2, x2, x2
+    cv.minu.b x8, x8, x8
+    cv.minu.b x20, x20, x20
+    cv.minu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f10a6c20d8ed4ea00b46e63e57b5abeea489885c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-h-fail.s
+#error_output: cv-simd-minu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..8916337969a9b5ea947e9ea9184511a3ff13a768
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.h x32,x32,x32'
+.*: Error: illegal operands `cv.minu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..eb1bd42d06ce65af0688bdd6b25225f2193ef559
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.minu.h x32, x32, x32
+    cv.minu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..dd00cb5d9e9daf0f3de382c0a3a8c341ee3b9826
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800007b          	cv.minu.h	zero,zero,zero
+   4:	281080fb          	cv.minu.h	ra,ra,ra
+   8:	2821017b          	cv.minu.h	sp,sp,sp
+   c:	2884047b          	cv.minu.h	s0,s0,s0
+  10:	294a0a7b          	cv.minu.h	s4,s4,s4
+  14:	29ff8ffb          	cv.minu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3c5dbaa63b5b92338de4f208466e45a036af5a94
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.minu.h x0, x0, x0
+    cv.minu.h x1, x1, x1
+    cv.minu.h x2, x2, x2
+    cv.minu.h x8, x8, x8
+    cv.minu.h x20, x20, x20
+    cv.minu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..865ba166c106b25fe13c8325f9210e83c7450b1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-b-fail.s
+#error_output: cv-simd-minu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..de8c2c89c0ed2ab5b687a22810a461428ba39ccb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.minu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..720480b15ed068dd21eae1b2a1d72e39074ff76d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.minu.sc.b x32, x32, x32
+    cv.minu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c3f33bc2649b4fd1451f104befbac49b8a786df5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800507b          	cv.minu.sc.b	zero,zero,zero
+   4:	2810d0fb          	cv.minu.sc.b	ra,ra,ra
+   8:	2821517b          	cv.minu.sc.b	sp,sp,sp
+   c:	2884547b          	cv.minu.sc.b	s0,s0,s0
+  10:	294a5a7b          	cv.minu.sc.b	s4,s4,s4
+  14:	29ffdffb          	cv.minu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3b88a467e2716c5e5fffd003c157de812cee87a9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.minu.sc.b x0, x0, x0
+    cv.minu.sc.b x1, x1, x1
+    cv.minu.sc.b x2, x2, x2
+    cv.minu.sc.b x8, x8, x8
+    cv.minu.sc.b x20, x20, x20
+    cv.minu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..eb2298dc4cb1fe16717f651257132b322fb53f4d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-h-fail.s
+#error_output: cv-simd-minu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9d66f906a9fe923f6ce26f424509791488d46eda
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.minu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5f421663ad7a692ccad3893c041fb0ed2e74f35b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.minu.sc.h x32, x32, x32
+    cv.minu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..517459662aa46f965f35c6a03cf0c62661ce0775
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800407b          	cv.minu.sc.h	zero,zero,zero
+   4:	2810c0fb          	cv.minu.sc.h	ra,ra,ra
+   8:	2821417b          	cv.minu.sc.h	sp,sp,sp
+   c:	2884447b          	cv.minu.sc.h	s0,s0,s0
+  10:	294a4a7b          	cv.minu.sc.h	s4,s4,s4
+  14:	29ffcffb          	cv.minu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9e752f493852b00faf8566545f93da924e5eacef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.minu.sc.h x0, x0, x0
+    cv.minu.sc.h x1, x1, x1
+    cv.minu.sc.h x2, x2, x2
+    cv.minu.sc.h x8, x8, x8
+    cv.minu.sc.h x20, x20, x20
+    cv.minu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..644315337e3801dc5e24d336eac7d92b840e8c3b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-b-fail.s
+#error_output: cv-simd-minu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b4fd02693a256a7d9201989ef9d5cb80dd69fcea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.minu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5fb1900e6ddccde2fec41aac940cdc5cbd89c395
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.minu.sci.b x32, x32, 20
+    cv.minu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.minu.sci.b x6, x7, -1
+    cv.minu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..37bb919f7e0de41be9fb68b13d427a60a56e5cc5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	28a0707b          	cv.minu.sci.b	zero,zero,20
+   4:	28a0f0fb          	cv.minu.sci.b	ra,ra,20
+   8:	28a1717b          	cv.minu.sci.b	sp,sp,20
+   c:	28a4747b          	cv.minu.sci.b	s0,s0,20
+  10:	28aa7a7b          	cv.minu.sci.b	s4,s4,20
+  14:	28affffb          	cv.minu.sci.b	t6,t6,20
+  18:	2803f37b          	cv.minu.sci.b	t1,t2,0
+  1c:	2bf3f37b          	cv.minu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f3268628236e02420e2af2908b9e0ae657a07e79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.minu.sci.b x0, x0, 20
+    cv.minu.sci.b x1, x1, 20
+    cv.minu.sci.b x2, x2, 20
+    cv.minu.sci.b x8, x8, 20
+    cv.minu.sci.b x20, x20, 20
+    cv.minu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.minu.sci.b x6, x7, 0
+    cv.minu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..d3d2c9e63eb30914838fe1c91040ab8b6543b769
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-h-fail.s
+#error_output: cv-simd-minu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0b91dab38882de1f98bcd8b7645d9ba2f0d2d12e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.minu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..35ec6ca4a4831d1c165e17a49b1db8c66a794077
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.minu.sci.h x32, x32, 20
+    cv.minu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.minu.sci.h x6, x7, -1
+    cv.minu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..3676b05182004e5adac60a10804e109291560d22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	28a0607b          	cv.minu.sci.h	zero,zero,20
+   4:	28a0e0fb          	cv.minu.sci.h	ra,ra,20
+   8:	28a1617b          	cv.minu.sci.h	sp,sp,20
+   c:	28a4647b          	cv.minu.sci.h	s0,s0,20
+  10:	28aa6a7b          	cv.minu.sci.h	s4,s4,20
+  14:	28afeffb          	cv.minu.sci.h	t6,t6,20
+  18:	2803e37b          	cv.minu.sci.h	t1,t2,0
+  1c:	2bf3e37b          	cv.minu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f9be2efa8c7c727af11379fdfd50701ed5430bfd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.minu.sci.h x0, x0, 20
+    cv.minu.sci.h x1, x1, 20
+    cv.minu.sci.h x2, x2, 20
+    cv.minu.sci.h x8, x8, 20
+    cv.minu.sci.h x20, x20, 20
+    cv.minu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.minu.sci.h x6, x7, 0
+    cv.minu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..80bd5bfdd85fa2be77986ce81cb83cd8534932a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-b-fail.s
+#error_output: cv-simd-or-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b74c77f5aecab9048f9990fef8c3fa00c047cd90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.b x32,x32,x32'
+.*: Error: illegal operands `cv.or.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..d0d81f550d4107b018dbee6933f1484f1d72ec40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.or.b x32, x32, x32
+    cv.or.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f43c9a3feeb12559f9ec296746213f1dd3a0bee2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800107b          	cv.or.b	zero,zero,zero
+   4:	581090fb          	cv.or.b	ra,ra,ra
+   8:	5821117b          	cv.or.b	sp,sp,sp
+   c:	5884147b          	cv.or.b	s0,s0,s0
+  10:	594a1a7b          	cv.or.b	s4,s4,s4
+  14:	59ff9ffb          	cv.or.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..95155723eb238e97da59edf2cf492acba19d1891
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.or.b x0, x0, x0
+    cv.or.b x1, x1, x1
+    cv.or.b x2, x2, x2
+    cv.or.b x8, x8, x8
+    cv.or.b x20, x20, x20
+    cv.or.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..99835ee84bfc61f4356a39f97086db431c0763a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-h-fail.s
+#error_output: cv-simd-or-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..d0c6c34792ed33a784e71f13c82c68e7cefc4bd1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.h x32,x32,x32'
+.*: Error: illegal operands `cv.or.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b3b72199264719e08064f696b08bc34f391c4746
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.or.h x32, x32, x32
+    cv.or.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..1bf40c7172836ee482d8905f60b2a31e402fa172
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800007b          	cv.or.h	zero,zero,zero
+   4:	581080fb          	cv.or.h	ra,ra,ra
+   8:	5821017b          	cv.or.h	sp,sp,sp
+   c:	5884047b          	cv.or.h	s0,s0,s0
+  10:	594a0a7b          	cv.or.h	s4,s4,s4
+  14:	59ff8ffb          	cv.or.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f53d50254409014a20815315a82978923fb64fd8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.or.h x0, x0, x0
+    cv.or.h x1, x1, x1
+    cv.or.h x2, x2, x2
+    cv.or.h x8, x8, x8
+    cv.or.h x20, x20, x20
+    cv.or.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..346754469821a344fb022ff4632dde5e66d95b2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-b-fail.s
+#error_output: cv-simd-or-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..91efc3051a428be4ef9b4510267f7aa357dedfde
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.or.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..672faf0a6b6c48d6078e1011f0aa0d300bd83838
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.or.sc.b x32, x32, x32
+    cv.or.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..784acbb5da4dd4650cf5ecb87e6b4df271e43df3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800507b          	cv.or.sc.b	zero,zero,zero
+   4:	5810d0fb          	cv.or.sc.b	ra,ra,ra
+   8:	5821517b          	cv.or.sc.b	sp,sp,sp
+   c:	5884547b          	cv.or.sc.b	s0,s0,s0
+  10:	594a5a7b          	cv.or.sc.b	s4,s4,s4
+  14:	59ffdffb          	cv.or.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..69829e57b2120e3df83d5be40959dc38139bacf7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.or.sc.b x0, x0, x0
+    cv.or.sc.b x1, x1, x1
+    cv.or.sc.b x2, x2, x2
+    cv.or.sc.b x8, x8, x8
+    cv.or.sc.b x20, x20, x20
+    cv.or.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..000d37048390367e402bdce5aa10d6e16e00b9ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-h-fail.s
+#error_output: cv-simd-or-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..18e64bd956a6f1596ebb94d911962f005a4cc692
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.or.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b3f8574ba52a871e10bf23ddc822c6f4e8ace05a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.or.sc.h x32, x32, x32
+    cv.or.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5f4f09431a84ac42bf7ef42a4a510bef4e567b83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800407b          	cv.or.sc.h	zero,zero,zero
+   4:	5810c0fb          	cv.or.sc.h	ra,ra,ra
+   8:	5821417b          	cv.or.sc.h	sp,sp,sp
+   c:	5884447b          	cv.or.sc.h	s0,s0,s0
+  10:	594a4a7b          	cv.or.sc.h	s4,s4,s4
+  14:	59ffcffb          	cv.or.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..611d7bbf55d4324fab3ee6025d813ffea41c37da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.or.sc.h x0, x0, x0
+    cv.or.sc.h x1, x1, x1
+    cv.or.sc.h x2, x2, x2
+    cv.or.sc.h x8, x8, x8
+    cv.or.sc.h x20, x20, x20
+    cv.or.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..76eed3c76dff2dbb82e9d29a8470191a6a74653b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-b-fail.s
+#error_output: cv-simd-or-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..475ea370e42878b930414a7693b7695f6b069444
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.or.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..27cc046d5d7063841a5984254c3d3bcdea7db1f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.or.sci.b x32, x32, 20
+    cv.or.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.or.sci.b x6, x7, -33
+    cv.or.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a417f85956a092d2b905a9c29a1c94159d300cfa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	58a0707b          	cv.or.sci.b	zero,zero,20
+   4:	58a0f0fb          	cv.or.sci.b	ra,ra,20
+   8:	58a1717b          	cv.or.sci.b	sp,sp,20
+   c:	58a4747b          	cv.or.sci.b	s0,s0,20
+  10:	58aa7a7b          	cv.or.sci.b	s4,s4,20
+  14:	58affffb          	cv.or.sci.b	t6,t6,20
+  18:	5903f37b          	cv.or.sci.b	t1,t2,-32
+  1c:	5803f37b          	cv.or.sci.b	t1,t2,0
+  20:	5af3f37b          	cv.or.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..36c55cf5e7549c10dcd792b421021f53cb5fe90d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.or.sci.b x0, x0, 20
+    cv.or.sci.b x1, x1, 20
+    cv.or.sci.b x2, x2, 20
+    cv.or.sci.b x8, x8, 20
+    cv.or.sci.b x20, x20, 20
+    cv.or.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.or.sci.b x6, x7, -32
+    cv.or.sci.b x6, x7, 0
+    cv.or.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f6b8d5920ad22141dfa81352b9147126e2b79802
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-h-fail.s
+#error_output: cv-simd-or-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..691d6d4354b9c3ab2c854fccc663990dd2f7f435
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.or.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..178bc1b806999b608d17af26cc275acb6622f335
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.or.sci.h x32, x32, 20
+    cv.or.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.or.sci.h x6, x7, -33
+    cv.or.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5ec05f4c33c46b1e90c4cc92b5cfeef6e2600d4a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	58a0607b          	cv.or.sci.h	zero,zero,20
+   4:	58a0e0fb          	cv.or.sci.h	ra,ra,20
+   8:	58a1617b          	cv.or.sci.h	sp,sp,20
+   c:	58a4647b          	cv.or.sci.h	s0,s0,20
+  10:	58aa6a7b          	cv.or.sci.h	s4,s4,20
+  14:	58afeffb          	cv.or.sci.h	t6,t6,20
+  18:	5903e37b          	cv.or.sci.h	t1,t2,-32
+  1c:	5803e37b          	cv.or.sci.h	t1,t2,0
+  20:	5af3e37b          	cv.or.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1fc6f304a71fcbc1a3f672ddce3f18297c8548e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.or.sci.h x0, x0, 20
+    cv.or.sci.h x1, x1, 20
+    cv.or.sci.h x2, x2, 20
+    cv.or.sci.h x8, x8, 20
+    cv.or.sci.h x20, x20, 20
+    cv.or.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.or.sci.h x6, x7, -32
+    cv.or.sci.h x6, x7, 0
+    cv.or.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-fail.d b/gas/testsuite/gas/riscv/cv-simd-pack-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a2d609657c186a07276b121991512b9850a9c78e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-fail.s
+#error_output: cv-simd-pack-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-fail.l b/gas/testsuite/gas/riscv/cv-simd-pack-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9668f1f40c0c49289ff3da44c9ae093d35b3ebca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.pack x32,x32,x32'
+.*: Error: illegal operands `cv.pack x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-fail.s b/gas/testsuite/gas/riscv/cv-simd-pack-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..caf3ed7e0bcb8953705ca9d61542587f8ad9a98f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.pack x32, x32, x32
+    cv.pack x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..07a3e2f9a210eebab5b58aa2dc4a4443ea7dd500
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-h-fail.s
+#error_output: cv-simd-pack-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..db35aa977f563b81ba844e28f577c562ed96342d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.pack.h x32,x32,x32'
+.*: Error: illegal operands `cv.pack.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..1b360c55e1d3fc79ab6bb7d7a2367568a50231fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.pack.h x32, x32, x32
+    cv.pack.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..89e420c8940434181b0340351d656b4e8dcc80d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	f200007b          	cv.pack.h	zero,zero,zero
+   4:	f21080fb          	cv.pack.h	ra,ra,ra
+   8:	f221017b          	cv.pack.h	sp,sp,sp
+   c:	f284047b          	cv.pack.h	s0,s0,s0
+  10:	f34a0a7b          	cv.pack.h	s4,s4,s4
+  14:	f3ff8ffb          	cv.pack.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5b06ec1f4fad3b9bb039f567d0872b88c000b5b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.pack.h x0, x0, x0
+    cv.pack.h x1, x1, x1
+    cv.pack.h x2, x2, x2
+    cv.pack.h x8, x8, x8
+    cv.pack.h x20, x20, x20
+    cv.pack.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-pass.d b/gas/testsuite/gas/riscv/cv-simd-pack-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e6031015c71c6047adf4bc07dafabf68eb15255f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	f000007b          	cv.pack	zero,zero,zero
+   4:	f01080fb          	cv.pack	ra,ra,ra
+   8:	f021017b          	cv.pack	sp,sp,sp
+   c:	f084047b          	cv.pack	s0,s0,s0
+  10:	f14a0a7b          	cv.pack	s4,s4,s4
+  14:	f1ff8ffb          	cv.pack	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-pass.s b/gas/testsuite/gas/riscv/cv-simd-pack-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..bde466c1507efe8cbc733531e06949588129682d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.pack x0, x0, x0
+    cv.pack x1, x1, x1
+    cv.pack x2, x2, x2
+    cv.pack x8, x8, x8
+    cv.pack x20, x20, x20
+    cv.pack x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..745dac08bc593f2c1f69d08a65836e13a573edbf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packhi-b-fail.s
+#error_output: cv-simd-packhi-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..60cc30ac241e8c429d674dc9ea203d864019e81d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.packhi.b x32,x32,x32'
+.*: Error: illegal operands `cv.packhi.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..43b6fc82d34e12a1e346db95c763175f383f3cf5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.packhi.b x32, x32, x32
+    cv.packhi.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..72a07bba6b5eefb76d63f4a28a8aa8485a5e63f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packhi-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	fa00107b          	cv.packhi.b	zero,zero,zero
+   4:	fa1090fb          	cv.packhi.b	ra,ra,ra
+   8:	fa21117b          	cv.packhi.b	sp,sp,sp
+   c:	fa84147b          	cv.packhi.b	s0,s0,s0
+  10:	fb4a1a7b          	cv.packhi.b	s4,s4,s4
+  14:	fbff9ffb          	cv.packhi.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c3a3eebf6c59325b9ba66329e9db68262e5e84d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.packhi.b x0, x0, x0
+    cv.packhi.b x1, x1, x1
+    cv.packhi.b x2, x2, x2
+    cv.packhi.b x8, x8, x8
+    cv.packhi.b x20, x20, x20
+    cv.packhi.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3fc6ee8c3968635c3301137bd226f082fb81e2ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packlo-b-fail.s
+#error_output: cv-simd-packlo-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1141174e9e705fe562cca6c0747748b186d2861a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.packlo.b x32,x32,x32'
+.*: Error: illegal operands `cv.packlo.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f39d1ec4faf210fb5caaf33811936f90ebea5678
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.packlo.b x32, x32, x32
+    cv.packlo.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..bc63970192d2f4e7d3f503e76a23c80d466aaa97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packlo-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	f800107b          	cv.packlo.b	zero,zero,zero
+   4:	f81090fb          	cv.packlo.b	ra,ra,ra
+   8:	f821117b          	cv.packlo.b	sp,sp,sp
+   c:	f884147b          	cv.packlo.b	s0,s0,s0
+  10:	f94a1a7b          	cv.packlo.b	s4,s4,s4
+  14:	f9ff9ffb          	cv.packlo.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..9d2a067d3f02f41255cb9e9b315a72f71b1b15b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.packlo.b x0, x0, x0
+    cv.packlo.b x1, x1, x1
+    cv.packlo.b x2, x2, x2
+    cv.packlo.b x8, x8, x8
+    cv.packlo.b x20, x20, x20
+    cv.packlo.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..80d14327e2352fb329c84b828e95a26dd5157632
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-b-fail.s
+#error_output: cv-simd-sdotsp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0171aeac5edaab0a0a3e2939eea7fa9de1c773b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2521ee9a886a73845f64d92b3b2d41b45864f484
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotsp.b x32, x32, x32
+    cv.sdotsp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..bc4609ed8cb4fe324d73b755f53a6e19fe328305
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800107b          	cv.sdotsp.b	zero,zero,zero
+   4:	a81090fb          	cv.sdotsp.b	ra,ra,ra
+   8:	a821117b          	cv.sdotsp.b	sp,sp,sp
+   c:	a884147b          	cv.sdotsp.b	s0,s0,s0
+  10:	a94a1a7b          	cv.sdotsp.b	s4,s4,s4
+  14:	a9ff9ffb          	cv.sdotsp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..bf1a7c60eaa352d3cbe830034ff9aea61e0a8f44
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotsp.b x0, x0, x0
+    cv.sdotsp.b x1, x1, x1
+    cv.sdotsp.b x2, x2, x2
+    cv.sdotsp.b x8, x8, x8
+    cv.sdotsp.b x20, x20, x20
+    cv.sdotsp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..821d988cd60072c11ef56a0103c3fee32ca54af3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-h-fail.s
+#error_output: cv-simd-sdotsp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ae9b66816ae6632a216333fc4e185215a6e29bf9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..067436e8dec2acbf06a5d178ac12ec6fe2168811
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotsp.h x32, x32, x32
+    cv.sdotsp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..19d7265febd4a67f6e1627dd100e7fc426131f26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800007b          	cv.sdotsp.h	zero,zero,zero
+   4:	a81080fb          	cv.sdotsp.h	ra,ra,ra
+   8:	a821017b          	cv.sdotsp.h	sp,sp,sp
+   c:	a884047b          	cv.sdotsp.h	s0,s0,s0
+  10:	a94a0a7b          	cv.sdotsp.h	s4,s4,s4
+  14:	a9ff8ffb          	cv.sdotsp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..90efc5b978f43692522e484efb5d6ca074471ba5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotsp.h x0, x0, x0
+    cv.sdotsp.h x1, x1, x1
+    cv.sdotsp.h x2, x2, x2
+    cv.sdotsp.h x8, x8, x8
+    cv.sdotsp.h x20, x20, x20
+    cv.sdotsp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..c47123c226ec286c8ed8d037ef6e776078d90780
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-b-fail.s
+#error_output: cv-simd-sdotsp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..020979b381cfc31c36866f910dd3ece26b3f5385
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5cd494400c0ed4678bd2b02c271fd73e1c231d1c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotsp.sc.b x32, x32, x32
+    cv.sdotsp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8dd43031fdd496f8d0fa859bb4d13f75f7794fa3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800507b          	cv.sdotsp.sc.b	zero,zero,zero
+   4:	a810d0fb          	cv.sdotsp.sc.b	ra,ra,ra
+   8:	a821517b          	cv.sdotsp.sc.b	sp,sp,sp
+   c:	a884547b          	cv.sdotsp.sc.b	s0,s0,s0
+  10:	a94a5a7b          	cv.sdotsp.sc.b	s4,s4,s4
+  14:	a9ffdffb          	cv.sdotsp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..98e6f5acbbc843a4be32d470685b975e816b5504
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotsp.sc.b x0, x0, x0
+    cv.sdotsp.sc.b x1, x1, x1
+    cv.sdotsp.sc.b x2, x2, x2
+    cv.sdotsp.sc.b x8, x8, x8
+    cv.sdotsp.sc.b x20, x20, x20
+    cv.sdotsp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2118706c8d4deeddde2c278a34ee802092cf8b3e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-h-fail.s
+#error_output: cv-simd-sdotsp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..8a24210b195e5f6318069c5cd6912ee8b51985da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..4a73a6e09fc3bf4434021f49f7dfd0e60a343d8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotsp.sc.h x32, x32, x32
+    cv.sdotsp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..2df1134184937272d5b4d461954a019e6ab9a4cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800407b          	cv.sdotsp.sc.h	zero,zero,zero
+   4:	a810c0fb          	cv.sdotsp.sc.h	ra,ra,ra
+   8:	a821417b          	cv.sdotsp.sc.h	sp,sp,sp
+   c:	a884447b          	cv.sdotsp.sc.h	s0,s0,s0
+  10:	a94a4a7b          	cv.sdotsp.sc.h	s4,s4,s4
+  14:	a9ffcffb          	cv.sdotsp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ad3fac3fc2041b8f50a6d4fd4c60c053c562bccc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotsp.sc.h x0, x0, x0
+    cv.sdotsp.sc.h x1, x1, x1
+    cv.sdotsp.sc.h x2, x2, x2
+    cv.sdotsp.sc.h x8, x8, x8
+    cv.sdotsp.sc.h x20, x20, x20
+    cv.sdotsp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..94bcf063687490b01a7fd5410afe78201213ace4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-b-fail.s
+#error_output: cv-simd-sdotsp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..39f53beb9c32a9c1c52293e3079571b659894d31
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sdotsp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b79605e65f0e65149e6a29e983d6cb5912927e6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotsp.sci.b x32, x32, 20
+    cv.sdotsp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotsp.sci.b x6, x7, -33
+    cv.sdotsp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0e51830b652076b17b6978a32d17de34a31539d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a8a0707b          	cv.sdotsp.sci.b	zero,zero,20
+   4:	a8a0f0fb          	cv.sdotsp.sci.b	ra,ra,20
+   8:	a8a1717b          	cv.sdotsp.sci.b	sp,sp,20
+   c:	a8a4747b          	cv.sdotsp.sci.b	s0,s0,20
+  10:	a8aa7a7b          	cv.sdotsp.sci.b	s4,s4,20
+  14:	a8affffb          	cv.sdotsp.sci.b	t6,t6,20
+  18:	a903f37b          	cv.sdotsp.sci.b	t1,t2,-32
+  1c:	a803f37b          	cv.sdotsp.sci.b	t1,t2,0
+  20:	aaf3f37b          	cv.sdotsp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c9aab8e06286f7a367025f8f62b843667b0e4ce0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.sdotsp.sci.b x0, x0, 20
+    cv.sdotsp.sci.b x1, x1, 20
+    cv.sdotsp.sci.b x2, x2, 20
+    cv.sdotsp.sci.b x8, x8, 20
+    cv.sdotsp.sci.b x20, x20, 20
+    cv.sdotsp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sdotsp.sci.b x6, x7, -32
+    cv.sdotsp.sci.b x6, x7, 0
+    cv.sdotsp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..67509879f4c3d3d6075ea0b9ff282290363943cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-h-fail.s
+#error_output: cv-simd-sdotsp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..28dda48691611403fab1f6d824bb660ca47c532e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sdotsp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..eb0788db611e872ce2b737f52487db2035ab5477
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotsp.sci.h x32, x32, 20
+    cv.sdotsp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotsp.sci.h x6, x7, -33
+    cv.sdotsp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6c7cbf53c2d71e2e520cfae94f40826a583e0302
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a8a0607b          	cv.sdotsp.sci.h	zero,zero,20
+   4:	a8a0e0fb          	cv.sdotsp.sci.h	ra,ra,20
+   8:	a8a1617b          	cv.sdotsp.sci.h	sp,sp,20
+   c:	a8a4647b          	cv.sdotsp.sci.h	s0,s0,20
+  10:	a8aa6a7b          	cv.sdotsp.sci.h	s4,s4,20
+  14:	a8afeffb          	cv.sdotsp.sci.h	t6,t6,20
+  18:	a903e37b          	cv.sdotsp.sci.h	t1,t2,-32
+  1c:	a803e37b          	cv.sdotsp.sci.h	t1,t2,0
+  20:	aaf3e37b          	cv.sdotsp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7af38caf00218d60e13926196c9129ab57f62439
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.sdotsp.sci.h x0, x0, 20
+    cv.sdotsp.sci.h x1, x1, 20
+    cv.sdotsp.sci.h x2, x2, 20
+    cv.sdotsp.sci.h x8, x8, 20
+    cv.sdotsp.sci.h x20, x20, 20
+    cv.sdotsp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sdotsp.sci.h x6, x7, -32
+    cv.sdotsp.sci.h x6, x7, 0
+    cv.sdotsp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2a54817d10f6dc857991a6ce1f4ef832020344ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-b-fail.s
+#error_output: cv-simd-sdotup-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0230952e0612049731612d921a12d561fceb5aec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b92684acf7453106af57c7151b1abe416d9f9ee9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotup.b x32, x32, x32
+    cv.sdotup.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a14a4946c93b417719bdebd0abbfbb1a94a65da9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800107b          	cv.sdotup.b	zero,zero,zero
+   4:	981090fb          	cv.sdotup.b	ra,ra,ra
+   8:	9821117b          	cv.sdotup.b	sp,sp,sp
+   c:	9884147b          	cv.sdotup.b	s0,s0,s0
+  10:	994a1a7b          	cv.sdotup.b	s4,s4,s4
+  14:	99ff9ffb          	cv.sdotup.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..eacf6e1293be5192415717415e15b402822cc870
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotup.b x0, x0, x0
+    cv.sdotup.b x1, x1, x1
+    cv.sdotup.b x2, x2, x2
+    cv.sdotup.b x8, x8, x8
+    cv.sdotup.b x20, x20, x20
+    cv.sdotup.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b40273bff97d5fbef3050257cd332aae27d57e6b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-h-fail.s
+#error_output: cv-simd-sdotup-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..cb56228f18c2fe492b5274c4da92625626b85860
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..cff83cba14568ebbe2a8f39b7c43aa21f7325532
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotup.h x32, x32, x32
+    cv.sdotup.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..31b1afe8888f9322ccfbfe2c95a87868b0971997
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800007b          	cv.sdotup.h	zero,zero,zero
+   4:	981080fb          	cv.sdotup.h	ra,ra,ra
+   8:	9821017b          	cv.sdotup.h	sp,sp,sp
+   c:	9884047b          	cv.sdotup.h	s0,s0,s0
+  10:	994a0a7b          	cv.sdotup.h	s4,s4,s4
+  14:	99ff8ffb          	cv.sdotup.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..cacaa1cdcb89649900d98b310a0e5bf179548378
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotup.h x0, x0, x0
+    cv.sdotup.h x1, x1, x1
+    cv.sdotup.h x2, x2, x2
+    cv.sdotup.h x8, x8, x8
+    cv.sdotup.h x20, x20, x20
+    cv.sdotup.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..631daae534309d63705f2b9864d56fe458f65cf1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-b-fail.s
+#error_output: cv-simd-sdotup-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..79ebb6da0ace5801a176c36038a4dfe946f87c34
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2fbae1c01b3790ed7826e6846e05e41af78d0bda
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotup.sc.b x32, x32, x32
+    cv.sdotup.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ac08c73d9a0188cd181aced601f00e8c28019182
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800507b          	cv.sdotup.sc.b	zero,zero,zero
+   4:	9810d0fb          	cv.sdotup.sc.b	ra,ra,ra
+   8:	9821517b          	cv.sdotup.sc.b	sp,sp,sp
+   c:	9884547b          	cv.sdotup.sc.b	s0,s0,s0
+  10:	994a5a7b          	cv.sdotup.sc.b	s4,s4,s4
+  14:	99ffdffb          	cv.sdotup.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3164734bea05d59fe73d431c64381c1c8be49a26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotup.sc.b x0, x0, x0
+    cv.sdotup.sc.b x1, x1, x1
+    cv.sdotup.sc.b x2, x2, x2
+    cv.sdotup.sc.b x8, x8, x8
+    cv.sdotup.sc.b x20, x20, x20
+    cv.sdotup.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a9582cb71b8b22523559993fac8e58d6c9cb67c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-h-fail.s
+#error_output: cv-simd-sdotup-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c770ee8f30dc651dc57bdac193101e5e7cc43801
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9fac8b86bd8abef7c8c3a0a9cc949ac403f1ac6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotup.sc.h x32, x32, x32
+    cv.sdotup.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6514df356a563a3619f9ca3b0412b5d121d876b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800407b          	cv.sdotup.sc.h	zero,zero,zero
+   4:	9810c0fb          	cv.sdotup.sc.h	ra,ra,ra
+   8:	9821417b          	cv.sdotup.sc.h	sp,sp,sp
+   c:	9884447b          	cv.sdotup.sc.h	s0,s0,s0
+  10:	994a4a7b          	cv.sdotup.sc.h	s4,s4,s4
+  14:	99ffcffb          	cv.sdotup.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..605c165e4f53ea991165deba700fad220f79f45f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotup.sc.h x0, x0, x0
+    cv.sdotup.sc.h x1, x1, x1
+    cv.sdotup.sc.h x2, x2, x2
+    cv.sdotup.sc.h x8, x8, x8
+    cv.sdotup.sc.h x20, x20, x20
+    cv.sdotup.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..b546567f5aaf1e1a3b8cbcc365341e05d9758bca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-b-fail.s
+#error_output: cv-simd-sdotup-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..961bb876c3bad311195bca13b9b9e65cd8e202e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sdotup.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..709100668cbcb8651c6b322aa1369af07a91b8be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotup.sci.b x32, x32, 20
+    cv.sdotup.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotup.sci.b x6, x7, -1
+    cv.sdotup.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e5e1d87ef90d457f088b7ba608b676a8beca1922
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	98a0707b          	cv.sdotup.sci.b	zero,zero,20
+   4:	98a0f0fb          	cv.sdotup.sci.b	ra,ra,20
+   8:	98a1717b          	cv.sdotup.sci.b	sp,sp,20
+   c:	98a4747b          	cv.sdotup.sci.b	s0,s0,20
+  10:	98aa7a7b          	cv.sdotup.sci.b	s4,s4,20
+  14:	98affffb          	cv.sdotup.sci.b	t6,t6,20
+  18:	9803f37b          	cv.sdotup.sci.b	t1,t2,0
+  1c:	9bf3f37b          	cv.sdotup.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..afb2f4008e9d26bca1b16e00fb97d198921bc0f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.sdotup.sci.b x0, x0, 20
+    cv.sdotup.sci.b x1, x1, 20
+    cv.sdotup.sci.b x2, x2, 20
+    cv.sdotup.sci.b x8, x8, 20
+    cv.sdotup.sci.b x20, x20, 20
+    cv.sdotup.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sdotup.sci.b x6, x7, 0
+    cv.sdotup.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e215f69ae4814236c753f378b86c5d30e1b1c502
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-h-fail.s
+#error_output: cv-simd-sdotup-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..323e89fe522105de54207528534ad5362a8a08a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sdotup.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..3c243f86183a9e42f9dcf6320cc78bf8b8318ba1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotup.sci.h x32, x32, 20
+    cv.sdotup.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotup.sci.h x6, x7, -1
+    cv.sdotup.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6f82a62dc66a39dbc2cbc3a1ee17245b9b749d5b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	98a0607b          	cv.sdotup.sci.h	zero,zero,20
+   4:	98a0e0fb          	cv.sdotup.sci.h	ra,ra,20
+   8:	98a1617b          	cv.sdotup.sci.h	sp,sp,20
+   c:	98a4647b          	cv.sdotup.sci.h	s0,s0,20
+  10:	98aa6a7b          	cv.sdotup.sci.h	s4,s4,20
+  14:	98afeffb          	cv.sdotup.sci.h	t6,t6,20
+  18:	9803e37b          	cv.sdotup.sci.h	t1,t2,0
+  1c:	9bf3e37b          	cv.sdotup.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..89d9a1fb8f5d5df5bcd30ccf1f69810a4a259dc5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.sdotup.sci.h x0, x0, 20
+    cv.sdotup.sci.h x1, x1, 20
+    cv.sdotup.sci.h x2, x2, 20
+    cv.sdotup.sci.h x8, x8, 20
+    cv.sdotup.sci.h x20, x20, 20
+    cv.sdotup.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sdotup.sci.h x6, x7, 0
+    cv.sdotup.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..071fb82c15a6e8ecb680346cd0f2c4234f4e829d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-b-fail.s
+#error_output: cv-simd-sdotusp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7488a3d54a6fd53148b733fca84db7ecb9f97be8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..be0791d85eb61c2b572452704ae75adb713e2a51
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotusp.b x32, x32, x32
+    cv.sdotusp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4ae36a515a80525ac5f7282d75567f469660f279
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000107b          	cv.sdotusp.b	zero,zero,zero
+   4:	a01090fb          	cv.sdotusp.b	ra,ra,ra
+   8:	a021117b          	cv.sdotusp.b	sp,sp,sp
+   c:	a084147b          	cv.sdotusp.b	s0,s0,s0
+  10:	a14a1a7b          	cv.sdotusp.b	s4,s4,s4
+  14:	a1ff9ffb          	cv.sdotusp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..413c4a2f8aa5d4f23c7d2adeb6aeab7179003b02
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotusp.b x0, x0, x0
+    cv.sdotusp.b x1, x1, x1
+    cv.sdotusp.b x2, x2, x2
+    cv.sdotusp.b x8, x8, x8
+    cv.sdotusp.b x20, x20, x20
+    cv.sdotusp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..d2951d6a703fbd61d2c8e651c4cebd322cfb682a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-h-fail.s
+#error_output: cv-simd-sdotusp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..82883936deaf3aec1e208e187a9d2aa4103123f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..403423840fb80073f6171f6ae12d85cff3774204
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotusp.h x32, x32, x32
+    cv.sdotusp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..47a5bbf8c878383e095d813d0940b9392a3a022d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000007b          	cv.sdotusp.h	zero,zero,zero
+   4:	a01080fb          	cv.sdotusp.h	ra,ra,ra
+   8:	a021017b          	cv.sdotusp.h	sp,sp,sp
+   c:	a084047b          	cv.sdotusp.h	s0,s0,s0
+  10:	a14a0a7b          	cv.sdotusp.h	s4,s4,s4
+  14:	a1ff8ffb          	cv.sdotusp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4a00c3f01af4dad08383312771582346cf3f7d2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotusp.h x0, x0, x0
+    cv.sdotusp.h x1, x1, x1
+    cv.sdotusp.h x2, x2, x2
+    cv.sdotusp.h x8, x8, x8
+    cv.sdotusp.h x20, x20, x20
+    cv.sdotusp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..dc4a9da6b599cca487d681c0b306e2696e1c532f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-b-fail.s
+#error_output: cv-simd-sdotusp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..0224aea1c52ada1f5a84e4ac5e922dc0450de668
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..535fe4c5eac4df5930d6864388f00688918430b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotusp.sc.b x32, x32, x32
+    cv.sdotusp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..9a88454cbc47ac8eae3026c35e1cab52f3759161
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000507b          	cv.sdotusp.sc.b	zero,zero,zero
+   4:	a010d0fb          	cv.sdotusp.sc.b	ra,ra,ra
+   8:	a021517b          	cv.sdotusp.sc.b	sp,sp,sp
+   c:	a084547b          	cv.sdotusp.sc.b	s0,s0,s0
+  10:	a14a5a7b          	cv.sdotusp.sc.b	s4,s4,s4
+  14:	a1ffdffb          	cv.sdotusp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..47d539c44dad37823d54e1bb4204f98b04a11a91
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotusp.sc.b x0, x0, x0
+    cv.sdotusp.sc.b x1, x1, x1
+    cv.sdotusp.sc.b x2, x2, x2
+    cv.sdotusp.sc.b x8, x8, x8
+    cv.sdotusp.sc.b x20, x20, x20
+    cv.sdotusp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1f88d60190da45c3324ccd71ad539fd876245c22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-h-fail.s
+#error_output: cv-simd-sdotusp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..9f55f7dc75ddcac4d2a740aa13e019b17666ea36
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c4f0263f997992e1fbeaf9f2a293e6436b686e8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotusp.sc.h x32, x32, x32
+    cv.sdotusp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d95de77253597bfaac02ef222bcf073499e41a9b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000407b          	cv.sdotusp.sc.h	zero,zero,zero
+   4:	a010c0fb          	cv.sdotusp.sc.h	ra,ra,ra
+   8:	a021417b          	cv.sdotusp.sc.h	sp,sp,sp
+   c:	a084447b          	cv.sdotusp.sc.h	s0,s0,s0
+  10:	a14a4a7b          	cv.sdotusp.sc.h	s4,s4,s4
+  14:	a1ffcffb          	cv.sdotusp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..789edd107285231ce01f567d65809eaa15eb10ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sdotusp.sc.h x0, x0, x0
+    cv.sdotusp.sc.h x1, x1, x1
+    cv.sdotusp.sc.h x2, x2, x2
+    cv.sdotusp.sc.h x8, x8, x8
+    cv.sdotusp.sc.h x20, x20, x20
+    cv.sdotusp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..6fcc866dbffb8ef9b6c2a975b162741b2215a9bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-b-fail.s
+#error_output: cv-simd-sdotusp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..efd927e7658db95b0edddd58b533c1f24adb2321
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sdotusp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..121e86bd1f93bb4e47c4d0f706d58c5e515e9259
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotusp.sci.b x32, x32, 20
+    cv.sdotusp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotusp.sci.b x6, x7, -33
+    cv.sdotusp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..3c8d95ec8687b247d07b544b03de597723ba3385
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a0a0707b          	cv.sdotusp.sci.b	zero,zero,20
+   4:	a0a0f0fb          	cv.sdotusp.sci.b	ra,ra,20
+   8:	a0a1717b          	cv.sdotusp.sci.b	sp,sp,20
+   c:	a0a4747b          	cv.sdotusp.sci.b	s0,s0,20
+  10:	a0aa7a7b          	cv.sdotusp.sci.b	s4,s4,20
+  14:	a0affffb          	cv.sdotusp.sci.b	t6,t6,20
+  18:	a103f37b          	cv.sdotusp.sci.b	t1,t2,-32
+  1c:	a003f37b          	cv.sdotusp.sci.b	t1,t2,0
+  20:	a2f3f37b          	cv.sdotusp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b7be1e357fe56ab597e72f9ef1fb774978e397f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.sdotusp.sci.b x0, x0, 20
+    cv.sdotusp.sci.b x1, x1, 20
+    cv.sdotusp.sci.b x2, x2, 20
+    cv.sdotusp.sci.b x8, x8, 20
+    cv.sdotusp.sci.b x20, x20, 20
+    cv.sdotusp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sdotusp.sci.b x6, x7, -32
+    cv.sdotusp.sci.b x6, x7, 0
+    cv.sdotusp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..36d3ab6950b4ba74486009906e1994b4b9ce9d1c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-h-fail.s
+#error_output: cv-simd-sdotusp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..abc1063c15d4f067ec1c875761a8e40311712a0e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sdotusp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..df2e3e328bdd61cadc71d6a1d3ef22d2d1f20d42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sdotusp.sci.h x32, x32, 20
+    cv.sdotusp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotusp.sci.h x6, x7, -33
+    cv.sdotusp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..7b656986ff92d0c6096d7a4d3f89e5b4bce18b02
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a0a0607b          	cv.sdotusp.sci.h	zero,zero,20
+   4:	a0a0e0fb          	cv.sdotusp.sci.h	ra,ra,20
+   8:	a0a1617b          	cv.sdotusp.sci.h	sp,sp,20
+   c:	a0a4647b          	cv.sdotusp.sci.h	s0,s0,20
+  10:	a0aa6a7b          	cv.sdotusp.sci.h	s4,s4,20
+  14:	a0afeffb          	cv.sdotusp.sci.h	t6,t6,20
+  18:	a103e37b          	cv.sdotusp.sci.h	t1,t2,-32
+  1c:	a003e37b          	cv.sdotusp.sci.h	t1,t2,0
+  20:	a2f3e37b          	cv.sdotusp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..fd6631e1c9fbb7f36c94ff6d8f2483ccec7d28fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.sdotusp.sci.h x0, x0, 20
+    cv.sdotusp.sci.h x1, x1, 20
+    cv.sdotusp.sci.h x2, x2, 20
+    cv.sdotusp.sci.h x8, x8, 20
+    cv.sdotusp.sci.h x20, x20, 20
+    cv.sdotusp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sdotusp.sci.h x6, x7, -32
+    cv.sdotusp.sci.h x6, x7, 0
+    cv.sdotusp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0889cbf48266aaa4ca2c6ddf721af7fa412983f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-b-fail.s
+#error_output: cv-simd-shuffle-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..6ccb07a2a9687074978e961607bda228d57d23ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle.b x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f5a24b2af550db632b9de6578a9d2017395dbe6e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.shuffle.b x32, x32, x32
+    cv.shuffle.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f751a03bef47de34b2aa4c49e0ca7d1cd6b69b0c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c000107b          	cv.shuffle.b	zero,zero,zero
+   4:	c01090fb          	cv.shuffle.b	ra,ra,ra
+   8:	c021117b          	cv.shuffle.b	sp,sp,sp
+   c:	c084147b          	cv.shuffle.b	s0,s0,s0
+  10:	c14a1a7b          	cv.shuffle.b	s4,s4,s4
+  14:	c1ff9ffb          	cv.shuffle.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e908ad5b1e79ff8475e72972447ed3145a69ae39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.shuffle.b x0, x0, x0
+    cv.shuffle.b x1, x1, x1
+    cv.shuffle.b x2, x2, x2
+    cv.shuffle.b x8, x8, x8
+    cv.shuffle.b x20, x20, x20
+    cv.shuffle.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3c1d6268a7d784765cdced75aab1cd22b710fb60
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-h-fail.s
+#error_output: cv-simd-shuffle-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..28004f29675ba9be5cafb57a5f41b69d9f1126c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle.h x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..91a805eb9456d1e89ba6afb41dc823a67aae0bf0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.shuffle.h x32, x32, x32
+    cv.shuffle.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5ae168db9a43bb92e868740202ad6cab426be288
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c000007b          	cv.shuffle.h	zero,zero,zero
+   4:	c01080fb          	cv.shuffle.h	ra,ra,ra
+   8:	c021017b          	cv.shuffle.h	sp,sp,sp
+   c:	c084047b          	cv.shuffle.h	s0,s0,s0
+  10:	c14a0a7b          	cv.shuffle.h	s4,s4,s4
+  14:	c1ff8ffb          	cv.shuffle.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..08afc2bab54c05f8ce6add207cc797c7a27321e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.shuffle.h x0, x0, x0
+    cv.shuffle.h x1, x1, x1
+    cv.shuffle.h x2, x2, x2
+    cv.shuffle.h x8, x8, x8
+    cv.shuffle.h x20, x20, x20
+    cv.shuffle.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..9657e9a994cc805985cbf128d83a94f4be1f7b48
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-sci-h-fail.s
+#error_output: cv-simd-shuffle-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4cb3b46692a474ffb8a2739e4e8a776d592aa655
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.shuffle.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9637bf01145eea6d03c95c870541a49097dffb42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.shuffle.sci.h x32, x32, 20
+    cv.shuffle.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shuffle.sci.h x6, x7, -1
+    cv.shuffle.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..6620e0c6bb4a641aa9739364f11c865ad83aa6a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c0a0607b          	cv.shuffle.sci.h	zero,zero,20
+   4:	c0a0e0fb          	cv.shuffle.sci.h	ra,ra,20
+   8:	c0a1617b          	cv.shuffle.sci.h	sp,sp,20
+   c:	c0a4647b          	cv.shuffle.sci.h	s0,s0,20
+  10:	c0aa6a7b          	cv.shuffle.sci.h	s4,s4,20
+  14:	c0afeffb          	cv.shuffle.sci.h	t6,t6,20
+  18:	c003e37b          	cv.shuffle.sci.h	t1,t2,0
+  1c:	c3f3e37b          	cv.shuffle.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2de957e0046abe549997c9b15d97ef1f1a10296b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.shuffle.sci.h x0, x0, 20
+    cv.shuffle.sci.h x1, x1, 20
+    cv.shuffle.sci.h x2, x2, 20
+    cv.shuffle.sci.h x8, x8, 20
+    cv.shuffle.sci.h x20, x20, 20
+    cv.shuffle.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.shuffle.sci.h x6, x7, 0
+    cv.shuffle.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f714cf9ab2bd09b2e6e25f6f1d7b27cbc85505b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-b-fail.s
+#error_output: cv-simd-shuffle2-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..94e47f7f8c762a11b742ae2ecef29025f4dbbed1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle2.b x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle2.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..23f1a2596973145068d48666fa73177ad2e21e49
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.shuffle2.b x32, x32, x32
+    cv.shuffle2.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..7116c7913a420547495bbbd61dcd33ab6d11df6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	e000107b          	cv.shuffle2.b	zero,zero,zero
+   4:	e01090fb          	cv.shuffle2.b	ra,ra,ra
+   8:	e021117b          	cv.shuffle2.b	sp,sp,sp
+   c:	e084147b          	cv.shuffle2.b	s0,s0,s0
+  10:	e14a1a7b          	cv.shuffle2.b	s4,s4,s4
+  14:	e1ff9ffb          	cv.shuffle2.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e4e58940ccc1020b695066fd2f65d3b439cb99c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.shuffle2.b x0, x0, x0
+    cv.shuffle2.b x1, x1, x1
+    cv.shuffle2.b x2, x2, x2
+    cv.shuffle2.b x8, x8, x8
+    cv.shuffle2.b x20, x20, x20
+    cv.shuffle2.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..e1fba2e4d3d2620f512e7428116ee7c2cce6e93d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-h-fail.s
+#error_output: cv-simd-shuffle2-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..31b69598bbfe83300fa22f22c7278cce468c06d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle2.h x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle2.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..96ba440aa64e23b14dde0dae6089443772cb3e68
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.shuffle2.h x32, x32, x32
+    cv.shuffle2.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..d4af2fd10b4b46c1f40abd3193e8d91d6b3654dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	e000007b          	cv.shuffle2.h	zero,zero,zero
+   4:	e01080fb          	cv.shuffle2.h	ra,ra,ra
+   8:	e021017b          	cv.shuffle2.h	sp,sp,sp
+   c:	e084047b          	cv.shuffle2.h	s0,s0,s0
+  10:	e14a0a7b          	cv.shuffle2.h	s4,s4,s4
+  14:	e1ff8ffb          	cv.shuffle2.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f3a2ba29bf11a0f2684741c0dac9992e7af86354
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.shuffle2.h x0, x0, x0
+    cv.shuffle2.h x1, x1, x1
+    cv.shuffle2.h x2, x2, x2
+    cv.shuffle2.h x8, x8, x8
+    cv.shuffle2.h x20, x20, x20
+    cv.shuffle2.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..40cc07242372d527d96fe1a2839e54803403e73c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei0-sci-b-fail.s
+#error_output: cv-simd-shufflei0-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..64a0bbaee56232ffe3fa19489b6a170ed12a1412
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei0.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei0.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b8f5b8b5324675ee59264fd0d0081759e10853a3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.shufflei0.sci.b x32, x32, 20
+    cv.shufflei0.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei0.sci.b x6, x7, -1
+    cv.shufflei0.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..9bf3b044749e3df8bc69338f7913ef720fb7996a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei0-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c0a0707b          	cv.shufflei0.sci.b	zero,zero,20
+   4:	c0a0f0fb          	cv.shufflei0.sci.b	ra,ra,20
+   8:	c0a1717b          	cv.shufflei0.sci.b	sp,sp,20
+   c:	c0a4747b          	cv.shufflei0.sci.b	s0,s0,20
+  10:	c0aa7a7b          	cv.shufflei0.sci.b	s4,s4,20
+  14:	c0affffb          	cv.shufflei0.sci.b	t6,t6,20
+  18:	c003f37b          	cv.shufflei0.sci.b	t1,t2,0
+  1c:	c3f3f37b          	cv.shufflei0.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e7e4a6c4252b85fb9ffb8ff79251eb4853fb3e5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.shufflei0.sci.b x0, x0, 20
+    cv.shufflei0.sci.b x1, x1, 20
+    cv.shufflei0.sci.b x2, x2, 20
+    cv.shufflei0.sci.b x8, x8, 20
+    cv.shufflei0.sci.b x20, x20, 20
+    cv.shufflei0.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei0.sci.b x6, x7, 0
+    cv.shufflei0.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..4dba182f72cbc82d51253994f6736ecaaeaae64d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei1-sci-b-fail.s
+#error_output: cv-simd-shufflei1-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a77e4235c7806b75fca08dc3c48f7048dadf91fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei1.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei1.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..4b3a4122f0067a046e1c64bfbc6adb20db44188e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.shufflei1.sci.b x32, x32, 20
+    cv.shufflei1.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei1.sci.b x6, x7, -1
+    cv.shufflei1.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..bbc757444005e3fc1831755e1e056c75e5af36f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei1-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c8a0707b          	cv.shufflei1.sci.b	zero,zero,20
+   4:	c8a0f0fb          	cv.shufflei1.sci.b	ra,ra,20
+   8:	c8a1717b          	cv.shufflei1.sci.b	sp,sp,20
+   c:	c8a4747b          	cv.shufflei1.sci.b	s0,s0,20
+  10:	c8aa7a7b          	cv.shufflei1.sci.b	s4,s4,20
+  14:	c8affffb          	cv.shufflei1.sci.b	t6,t6,20
+  18:	c803f37b          	cv.shufflei1.sci.b	t1,t2,0
+  1c:	cbf3f37b          	cv.shufflei1.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..6918bfdb607630fad66615ef9d0d79443fbd2d01
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.shufflei1.sci.b x0, x0, 20
+    cv.shufflei1.sci.b x1, x1, 20
+    cv.shufflei1.sci.b x2, x2, 20
+    cv.shufflei1.sci.b x8, x8, 20
+    cv.shufflei1.sci.b x20, x20, 20
+    cv.shufflei1.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei1.sci.b x6, x7, 0
+    cv.shufflei1.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1113d60d073802d49cd7e17e49aeb21ee53ff8dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei2-sci-b-fail.s
+#error_output: cv-simd-shufflei2-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c136de86700b2073db9543c10a2da8e7fdc52643
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei2.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei2.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ec68ae8f7eb2fe382a23d216face4160ce16d6f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.shufflei2.sci.b x32, x32, 20
+    cv.shufflei2.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei2.sci.b x6, x7, -1
+    cv.shufflei2.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0ec56cfa0ca6d2d1d0b0386af1654f8cbf597301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei2-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	d0a0707b          	cv.shufflei2.sci.b	zero,zero,20
+   4:	d0a0f0fb          	cv.shufflei2.sci.b	ra,ra,20
+   8:	d0a1717b          	cv.shufflei2.sci.b	sp,sp,20
+   c:	d0a4747b          	cv.shufflei2.sci.b	s0,s0,20
+  10:	d0aa7a7b          	cv.shufflei2.sci.b	s4,s4,20
+  14:	d0affffb          	cv.shufflei2.sci.b	t6,t6,20
+  18:	d003f37b          	cv.shufflei2.sci.b	t1,t2,0
+  1c:	d3f3f37b          	cv.shufflei2.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..708ffc7f6c31f42e223e4a503d79177b9cd419b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.shufflei2.sci.b x0, x0, 20
+    cv.shufflei2.sci.b x1, x1, 20
+    cv.shufflei2.sci.b x2, x2, 20
+    cv.shufflei2.sci.b x8, x8, 20
+    cv.shufflei2.sci.b x20, x20, 20
+    cv.shufflei2.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei2.sci.b x6, x7, 0
+    cv.shufflei2.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..eb783f4d8311c1ec778b8c896da96959654ef2d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei3-sci-b-fail.s
+#error_output: cv-simd-shufflei3-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..41cadc70ed615202beb9071a94ca3cd33bd58d2f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei3.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei3.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e0a01cc45f7b78da61d446222369b22e00db6242
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.shufflei3.sci.b x32, x32, 20
+    cv.shufflei3.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei3.sci.b x6, x7, -1
+    cv.shufflei3.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..ef9d3018f34d644dedbfaff4d5feed83a4c94a66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei3-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	d8a0707b          	cv.shufflei3.sci.b	zero,zero,20
+   4:	d8a0f0fb          	cv.shufflei3.sci.b	ra,ra,20
+   8:	d8a1717b          	cv.shufflei3.sci.b	sp,sp,20
+   c:	d8a4747b          	cv.shufflei3.sci.b	s0,s0,20
+  10:	d8aa7a7b          	cv.shufflei3.sci.b	s4,s4,20
+  14:	d8affffb          	cv.shufflei3.sci.b	t6,t6,20
+  18:	d803f37b          	cv.shufflei3.sci.b	t1,t2,0
+  1c:	dbf3f37b          	cv.shufflei3.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..aadc00bfa73a9406ed36ff3ddd6ef0e1a0e2dcb6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.shufflei3.sci.b x0, x0, 20
+    cv.shufflei3.sci.b x1, x1, 20
+    cv.shufflei3.sci.b x2, x2, 20
+    cv.shufflei3.sci.b x8, x8, 20
+    cv.shufflei3.sci.b x20, x20, 20
+    cv.shufflei3.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei3.sci.b x6, x7, 0
+    cv.shufflei3.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..77dec2bbf74fb776668357bb738c605176767c40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-b-fail.s
+#error_output: cv-simd-sll-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..4bf8b2b1f9784739e744b98f3c93a1b16abc6dc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.b x32,x32,x32'
+.*: Error: illegal operands `cv.sll.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c64950c5ef6261afc56d2431813bc3e3c011db6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sll.b x32, x32, x32
+    cv.sll.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0896652ce8d92c07646562074c78f6b2240bbea7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000107b          	cv.sll.b	zero,zero,zero
+   4:	501090fb          	cv.sll.b	ra,ra,ra
+   8:	5021117b          	cv.sll.b	sp,sp,sp
+   c:	5084147b          	cv.sll.b	s0,s0,s0
+  10:	514a1a7b          	cv.sll.b	s4,s4,s4
+  14:	51ff9ffb          	cv.sll.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..929d3c607dc4487980eeffc8069557fe2ec03d87
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sll.b x0, x0, x0
+    cv.sll.b x1, x1, x1
+    cv.sll.b x2, x2, x2
+    cv.sll.b x8, x8, x8
+    cv.sll.b x20, x20, x20
+    cv.sll.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..79f1bfdf4e632d3daf31316d001ed1247fb451d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-h-fail.s
+#error_output: cv-simd-sll-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..3ea79744e4f4d34e165830b5b5fe3d4aa3f2f431
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.h x32,x32,x32'
+.*: Error: illegal operands `cv.sll.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a47ce4c06dd7f3807e4b131922eac51e2f117918
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sll.h x32, x32, x32
+    cv.sll.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c9f21b61afe112aca3f6fbc87552970fd3df11ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000007b          	cv.sll.h	zero,zero,zero
+   4:	501080fb          	cv.sll.h	ra,ra,ra
+   8:	5021017b          	cv.sll.h	sp,sp,sp
+   c:	5084047b          	cv.sll.h	s0,s0,s0
+  10:	514a0a7b          	cv.sll.h	s4,s4,s4
+  14:	51ff8ffb          	cv.sll.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4fa2c8c2b07e87479861432bd93470c6c8792d79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sll.h x0, x0, x0
+    cv.sll.h x1, x1, x1
+    cv.sll.h x2, x2, x2
+    cv.sll.h x8, x8, x8
+    cv.sll.h x20, x20, x20
+    cv.sll.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f03efb96d608b336f16c420b47161530bc1238cd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-b-fail.s
+#error_output: cv-simd-sll-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ce3d6df659af104041b977a3df0f88d59025f326
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sll.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..faeb0c7cd668746b402b0a512e6bfd5699578301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sll.sc.b x32, x32, x32
+    cv.sll.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..0ac1111df9950b0f512e58a868981884214e8f0f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000507b          	cv.sll.sc.b	zero,zero,zero
+   4:	5010d0fb          	cv.sll.sc.b	ra,ra,ra
+   8:	5021517b          	cv.sll.sc.b	sp,sp,sp
+   c:	5084547b          	cv.sll.sc.b	s0,s0,s0
+  10:	514a5a7b          	cv.sll.sc.b	s4,s4,s4
+  14:	51ffdffb          	cv.sll.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e8453d8dfd0682705a4a02090aaf1af2b46a804a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sll.sc.b x0, x0, x0
+    cv.sll.sc.b x1, x1, x1
+    cv.sll.sc.b x2, x2, x2
+    cv.sll.sc.b x8, x8, x8
+    cv.sll.sc.b x20, x20, x20
+    cv.sll.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..734471824899deffcd23ac491935bd6f815f9ea9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-h-fail.s
+#error_output: cv-simd-sll-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..320fa74ec56b3f1a31ad38c0c46e64f0fcedff1f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sll.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..0fa9838b6b6b89a9eb98d5586dd4ebf483cd242a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sll.sc.h x32, x32, x32
+    cv.sll.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..37d4d74cdebe095104bf589b34d32f8ec1bd06ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000407b          	cv.sll.sc.h	zero,zero,zero
+   4:	5010c0fb          	cv.sll.sc.h	ra,ra,ra
+   8:	5021417b          	cv.sll.sc.h	sp,sp,sp
+   c:	5084447b          	cv.sll.sc.h	s0,s0,s0
+  10:	514a4a7b          	cv.sll.sc.h	s4,s4,s4
+  14:	51ffcffb          	cv.sll.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..d496d672b49ac6baa00d816c73fb22783fc47abb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sll.sc.h x0, x0, x0
+    cv.sll.sc.h x1, x1, x1
+    cv.sll.sc.h x2, x2, x2
+    cv.sll.sc.h x8, x8, x8
+    cv.sll.sc.h x20, x20, x20
+    cv.sll.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fe54c3062b09e68bc982d025206817cc39c5f678
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-b-fail.s
+#error_output: cv-simd-sll-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7baf9f5592f8b6294d24202555bc8e48b36dcaef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sll.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b45a756b8276169680811ded35713c41435e3841
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sll.sci.b x32, x32, 20
+    cv.sll.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sll.sci.b x6, x7, -1
+    cv.sll.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..7464db59cdb95ec667c59c590eb1153f6e916db4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	50a0707b          	cv.sll.sci.b	zero,zero,20
+   4:	50a0f0fb          	cv.sll.sci.b	ra,ra,20
+   8:	50a1717b          	cv.sll.sci.b	sp,sp,20
+   c:	50a4747b          	cv.sll.sci.b	s0,s0,20
+  10:	50aa7a7b          	cv.sll.sci.b	s4,s4,20
+  14:	50affffb          	cv.sll.sci.b	t6,t6,20
+  18:	5003f37b          	cv.sll.sci.b	t1,t2,0
+  1c:	53f3f37b          	cv.sll.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e598c701eb95c535fe97899657fc3feabd1c21f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.sll.sci.b x0, x0, 20
+    cv.sll.sci.b x1, x1, 20
+    cv.sll.sci.b x2, x2, 20
+    cv.sll.sci.b x8, x8, 20
+    cv.sll.sci.b x20, x20, 20
+    cv.sll.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sll.sci.b x6, x7, 0
+    cv.sll.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..0bc189f2c89704cef36d57e48a40a1d3795e9002
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-h-fail.s
+#error_output: cv-simd-sll-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..589fb12650468ee76e41fbf7f596fd95720a3748
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sll.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ae7151f61b029cfec84d4ec624603e1cd83a2180
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sll.sci.h x32, x32, 20
+    cv.sll.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sll.sci.h x6, x7, -1
+    cv.sll.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..954ad5d9df1d171328cfbe5748390df8814892e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	50a0607b          	cv.sll.sci.h	zero,zero,20
+   4:	50a0e0fb          	cv.sll.sci.h	ra,ra,20
+   8:	50a1617b          	cv.sll.sci.h	sp,sp,20
+   c:	50a4647b          	cv.sll.sci.h	s0,s0,20
+  10:	50aa6a7b          	cv.sll.sci.h	s4,s4,20
+  14:	50afeffb          	cv.sll.sci.h	t6,t6,20
+  18:	5003e37b          	cv.sll.sci.h	t1,t2,0
+  1c:	53f3e37b          	cv.sll.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..94da70c7d5699280f36df019d4a8a16262c27a66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.sll.sci.h x0, x0, 20
+    cv.sll.sci.h x1, x1, 20
+    cv.sll.sci.h x2, x2, 20
+    cv.sll.sci.h x8, x8, 20
+    cv.sll.sci.h x20, x20, 20
+    cv.sll.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sll.sci.h x6, x7, 0
+    cv.sll.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..43ea15bf717e2385f8ce5ed1b43361ba6bd949ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-b-fail.s
+#error_output: cv-simd-sra-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..e6d5a0945391a8472e05505e719441f2c81899b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.b x32,x32,x32'
+.*: Error: illegal operands `cv.sra.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c09838a04eaa66937c9be868a0e6b11961d8596b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sra.b x32, x32, x32
+    cv.sra.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..76522b8e892d9e51d4c6b4670f696225cb914b05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800107b          	cv.sra.b	zero,zero,zero
+   4:	481090fb          	cv.sra.b	ra,ra,ra
+   8:	4821117b          	cv.sra.b	sp,sp,sp
+   c:	4884147b          	cv.sra.b	s0,s0,s0
+  10:	494a1a7b          	cv.sra.b	s4,s4,s4
+  14:	49ff9ffb          	cv.sra.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..0cef7810d49c8b8a4abfa67d7c2d9bd2c8b7b0d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sra.b x0, x0, x0
+    cv.sra.b x1, x1, x1
+    cv.sra.b x2, x2, x2
+    cv.sra.b x8, x8, x8
+    cv.sra.b x20, x20, x20
+    cv.sra.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..ddda6efdcddb03000c0da22a7f94e8b44fcadbeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-h-fail.s
+#error_output: cv-simd-sra-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ddf7b46acb0638e2a7e9a385d84ba9e076a52fcd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.h x32,x32,x32'
+.*: Error: illegal operands `cv.sra.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..dcbe979c3f613690bb3b479e2e4a2748f14babd1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sra.h x32, x32, x32
+    cv.sra.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b7eab0a980ce3998e66956bd2ad14f970da4ce1f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800007b          	cv.sra.h	zero,zero,zero
+   4:	481080fb          	cv.sra.h	ra,ra,ra
+   8:	4821017b          	cv.sra.h	sp,sp,sp
+   c:	4884047b          	cv.sra.h	s0,s0,s0
+  10:	494a0a7b          	cv.sra.h	s4,s4,s4
+  14:	49ff8ffb          	cv.sra.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5dad74333e8fb477b81359e8ac6fce181680aa7a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sra.h x0, x0, x0
+    cv.sra.h x1, x1, x1
+    cv.sra.h x2, x2, x2
+    cv.sra.h x8, x8, x8
+    cv.sra.h x20, x20, x20
+    cv.sra.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1a26f3fac356cc5f94e4e9f0dd0bdf29e5d2c211
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-b-fail.s
+#error_output: cv-simd-sra-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..72df02d3a2d733e95f030b95304ce7a99e5f60b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sra.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..5ebdbfb141868d8c5e37c43449d0700a8f991920
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sra.sc.b x32, x32, x32
+    cv.sra.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..23bd8eea69ff5e1fe017ae7268da5f37c42308e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800507b          	cv.sra.sc.b	zero,zero,zero
+   4:	4810d0fb          	cv.sra.sc.b	ra,ra,ra
+   8:	4821517b          	cv.sra.sc.b	sp,sp,sp
+   c:	4884547b          	cv.sra.sc.b	s0,s0,s0
+  10:	494a5a7b          	cv.sra.sc.b	s4,s4,s4
+  14:	49ffdffb          	cv.sra.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..3ae2c92ec39f8cbcbb80c4a2fda81e04d3fefb47
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sra.sc.b x0, x0, x0
+    cv.sra.sc.b x1, x1, x1
+    cv.sra.sc.b x2, x2, x2
+    cv.sra.sc.b x8, x8, x8
+    cv.sra.sc.b x20, x20, x20
+    cv.sra.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..7583498c1f41c4c6ad90c3164bddd51474f397e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-h-fail.s
+#error_output: cv-simd-sra-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..68eef5792728f76f47dbff88eb86c73be4b43a93
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sra.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..3f4dc2b58daa0379b9717a0a6fe234135e849856
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sra.sc.h x32, x32, x32
+    cv.sra.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5617de5e462afd04eba134ff120ad7dacb2c3a67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800407b          	cv.sra.sc.h	zero,zero,zero
+   4:	4810c0fb          	cv.sra.sc.h	ra,ra,ra
+   8:	4821417b          	cv.sra.sc.h	sp,sp,sp
+   c:	4884447b          	cv.sra.sc.h	s0,s0,s0
+  10:	494a4a7b          	cv.sra.sc.h	s4,s4,s4
+  14:	49ffcffb          	cv.sra.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..06f73833df389743d6909480fe735b5f2eb5b704
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sra.sc.h x0, x0, x0
+    cv.sra.sc.h x1, x1, x1
+    cv.sra.sc.h x2, x2, x2
+    cv.sra.sc.h x8, x8, x8
+    cv.sra.sc.h x20, x20, x20
+    cv.sra.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..23a5e75ca593e44428083e7d4677d7d5d0f9a787
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-b-fail.s
+#error_output: cv-simd-sra-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a9e80e9898238c0fa11d750d3d8c09a01ca12455
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sra.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..682cf6aa58229de2db28e2a1f14bfbee2574d9b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sra.sci.b x32, x32, 20
+    cv.sra.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sra.sci.b x6, x7, -1
+    cv.sra.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8968bc486af9115ddee630c0324e567780024c48
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	48a0707b          	cv.sra.sci.b	zero,zero,20
+   4:	48a0f0fb          	cv.sra.sci.b	ra,ra,20
+   8:	48a1717b          	cv.sra.sci.b	sp,sp,20
+   c:	48a4747b          	cv.sra.sci.b	s0,s0,20
+  10:	48aa7a7b          	cv.sra.sci.b	s4,s4,20
+  14:	48affffb          	cv.sra.sci.b	t6,t6,20
+  18:	4803f37b          	cv.sra.sci.b	t1,t2,0
+  1c:	4bf3f37b          	cv.sra.sci.b	t1,t2,63
+
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..27e2aae44d5ade421e3c88cdcd07634fd54b0e0f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.sra.sci.b x0, x0, 20
+    cv.sra.sci.b x1, x1, 20
+    cv.sra.sci.b x2, x2, 20
+    cv.sra.sci.b x8, x8, 20
+    cv.sra.sci.b x20, x20, 20
+    cv.sra.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sra.sci.b x6, x7, 0
+    cv.sra.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..de26bbf183c930feff667cda9b7b50663f31a231
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-h-fail.s
+#error_output: cv-simd-sra-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..16b29ba0801be069d506c248f9f58c855ce25676
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sra.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..9f6c6af00f946fad70231b5314e79500125e0d53
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sra.sci.h x32, x32, 20
+    cv.sra.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sra.sci.h x6, x7, -1
+    cv.sra.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..b4223b8c5e1bd634aa186ce5d8132ae8e6e65024
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	48a0607b          	cv.sra.sci.h	zero,zero,20
+   4:	48a0e0fb          	cv.sra.sci.h	ra,ra,20
+   8:	48a1617b          	cv.sra.sci.h	sp,sp,20
+   c:	48a4647b          	cv.sra.sci.h	s0,s0,20
+  10:	48aa6a7b          	cv.sra.sci.h	s4,s4,20
+  14:	48afeffb          	cv.sra.sci.h	t6,t6,20
+  18:	4803e37b          	cv.sra.sci.h	t1,t2,0
+  1c:	4bf3e37b          	cv.sra.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..0a3d27f2dd204cf9745563666d74367eb1ac02f5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.sra.sci.h x0, x0, 20
+    cv.sra.sci.h x1, x1, 20
+    cv.sra.sci.h x2, x2, 20
+    cv.sra.sci.h x8, x8, 20
+    cv.sra.sci.h x20, x20, 20
+    cv.sra.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sra.sci.h x6, x7, 0
+    cv.sra.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a28f67f7d3024df8c51242e7058b09ba48d78701
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-b-fail.s
+#error_output: cv-simd-srl-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..2e8ea987dac242db83a01ccd2687e6346f5e5edf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.b x32,x32,x32'
+.*: Error: illegal operands `cv.srl.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..da928163404e46f583256409c7aec24bd6332c0f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.srl.b x32, x32, x32
+    cv.srl.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e40562f3f6600de590f803e1f1c85c0c6c86cb46
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000107b          	cv.srl.b	zero,zero,zero
+   4:	401090fb          	cv.srl.b	ra,ra,ra
+   8:	4021117b          	cv.srl.b	sp,sp,sp
+   c:	4084147b          	cv.srl.b	s0,s0,s0
+  10:	414a1a7b          	cv.srl.b	s4,s4,s4
+  14:	41ff9ffb          	cv.srl.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..631271055133fa2450208f783fafe7df5f11c99a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.srl.b x0, x0, x0
+    cv.srl.b x1, x1, x1
+    cv.srl.b x2, x2, x2
+    cv.srl.b x8, x8, x8
+    cv.srl.b x20, x20, x20
+    cv.srl.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..932568b5f3e7c5f511cad6f452e161f76be623ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-h-fail.s
+#error_output: cv-simd-srl-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..427b72b521988395336a0316efd3d63159dcea1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.h x32,x32,x32'
+.*: Error: illegal operands `cv.srl.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..56519e489e174a02c516eb45ff459809228f382b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.srl.h x32, x32, x32
+    cv.srl.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..24dde446e7cba6b6166db7fcd97f703edb2ff7e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000007b          	cv.srl.h	zero,zero,zero
+   4:	401080fb          	cv.srl.h	ra,ra,ra
+   8:	4021017b          	cv.srl.h	sp,sp,sp
+   c:	4084047b          	cv.srl.h	s0,s0,s0
+  10:	414a0a7b          	cv.srl.h	s4,s4,s4
+  14:	41ff8ffb          	cv.srl.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c63c5af091dfbb54e251c96c9176afbdc4159a72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.srl.h x0, x0, x0
+    cv.srl.h x1, x1, x1
+    cv.srl.h x2, x2, x2
+    cv.srl.h x8, x8, x8
+    cv.srl.h x20, x20, x20
+    cv.srl.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..84a93573f392ceb2ba51d406e56e94c7afc15985
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-b-fail.s
+#error_output: cv-simd-srl-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..48f43ede7bc568d2ff36d77982d2e947e385e251
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.srl.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a70ef1704a27c36afeccce7564c350ebc3d9d51f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.srl.sc.b x32, x32, x32
+    cv.srl.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..a8e07f3ab86095f162e8f8d42e532c6f8cabf9ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000507b          	cv.srl.sc.b	zero,zero,zero
+   4:	4010d0fb          	cv.srl.sc.b	ra,ra,ra
+   8:	4021517b          	cv.srl.sc.b	sp,sp,sp
+   c:	4084547b          	cv.srl.sc.b	s0,s0,s0
+  10:	414a5a7b          	cv.srl.sc.b	s4,s4,s4
+  14:	41ffdffb          	cv.srl.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..b104a06f2844917c1f4d986ccfbc475260c5dea3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.srl.sc.b x0, x0, x0
+    cv.srl.sc.b x1, x1, x1
+    cv.srl.sc.b x2, x2, x2
+    cv.srl.sc.b x8, x8, x8
+    cv.srl.sc.b x20, x20, x20
+    cv.srl.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..d7477a206e46ac2684ecb36b59d2121e51203e96
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-h-fail.s
+#error_output: cv-simd-srl-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..721754b3854a70635eb350316b6c523b63a8a2b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.srl.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..95ef1a18e2da87bcf56ce8d9e8c82a8c881df314
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.srl.sc.h x32, x32, x32
+    cv.srl.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..4b986e2a8730df8ad8812a999357218370bb29a8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000407b          	cv.srl.sc.h	zero,zero,zero
+   4:	4010c0fb          	cv.srl.sc.h	ra,ra,ra
+   8:	4021417b          	cv.srl.sc.h	sp,sp,sp
+   c:	4084447b          	cv.srl.sc.h	s0,s0,s0
+  10:	414a4a7b          	cv.srl.sc.h	s4,s4,s4
+  14:	41ffcffb          	cv.srl.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..e961105803bed71421aed7fc83c8a56e224377eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.srl.sc.h x0, x0, x0
+    cv.srl.sc.h x1, x1, x1
+    cv.srl.sc.h x2, x2, x2
+    cv.srl.sc.h x8, x8, x8
+    cv.srl.sc.h x20, x20, x20
+    cv.srl.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f1189136da3a82e2ca02957de2ee0bed5cbf1870
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-b-fail.s
+#error_output: cv-simd-srl-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..5955423a03d7f55ede01be8e6c42c2ef131e8849
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.srl.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..4aef88d32c388d7239b9722150ea781ef2effa4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.srl.sci.b x32, x32, 20
+    cv.srl.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.srl.sci.b x6, x7, -1
+    cv.srl.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c5f5088bcd1c68c5498cb2ac0ad50f55d46d5c64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	40a0707b          	cv.srl.sci.b	zero,zero,20
+   4:	40a0f0fb          	cv.srl.sci.b	ra,ra,20
+   8:	40a1717b          	cv.srl.sci.b	sp,sp,20
+   c:	40a4747b          	cv.srl.sci.b	s0,s0,20
+  10:	40aa7a7b          	cv.srl.sci.b	s4,s4,20
+  14:	40affffb          	cv.srl.sci.b	t6,t6,20
+  18:	4003f37b          	cv.srl.sci.b	t1,t2,0
+  1c:	43f3f37b          	cv.srl.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..f36d6af1a7e70ef0b1582c12e350a0616d4f6487
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.srl.sci.b x0, x0, 20
+    cv.srl.sci.b x1, x1, 20
+    cv.srl.sci.b x2, x2, 20
+    cv.srl.sci.b x8, x8, 20
+    cv.srl.sci.b x20, x20, 20
+    cv.srl.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.srl.sci.b x6, x7, 0
+    cv.srl.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..fbbeae20041c4fd0969cd99c48a3be3174e16b37
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-h-fail.s
+#error_output: cv-simd-srl-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..240a460c9268067ed42573d5e4e7871459159b7f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.srl.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..8aaedf6c4b6dfc0e3a07ecd4f02c531969119094
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.srl.sci.h x32, x32, 20
+    cv.srl.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.srl.sci.h x6, x7, -1
+    cv.srl.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..05fd13a703511622af6940a22d8b128e9eb2dec6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	40a0607b          	cv.srl.sci.h	zero,zero,20
+   4:	40a0e0fb          	cv.srl.sci.h	ra,ra,20
+   8:	40a1617b          	cv.srl.sci.h	sp,sp,20
+   c:	40a4647b          	cv.srl.sci.h	s0,s0,20
+  10:	40aa6a7b          	cv.srl.sci.h	s4,s4,20
+  14:	40afeffb          	cv.srl.sci.h	t6,t6,20
+  18:	4003e37b          	cv.srl.sci.h	t1,t2,0
+  1c:	43f3e37b          	cv.srl.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..267eff3a78c3f6c0527a5075d201f74e88042f00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s
@@ -0,0 +1,11 @@
+target: 
+    #Register Tests
+    cv.srl.sci.h x0, x0, 20
+    cv.srl.sci.h x1, x1, 20
+    cv.srl.sci.h x2, x2, 20
+    cv.srl.sci.h x8, x8, 20
+    cv.srl.sci.h x20, x20, 20
+    cv.srl.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.srl.sci.h x6, x7, 0
+    cv.srl.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..8b07b42ae3a96325fa5bfe50d2cc47c5a120e0c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-b-fail.s
+#error_output: cv-simd-sub-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..02dc7c9c35c46e8117416fedd03b9591c1e3b088
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.b x32,x32,x32'
+.*: Error: illegal operands `cv.sub.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..ca21cbf80a4879d2a513616819b66cf7ba6d2abc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.b x32, x32, x32
+    cv.sub.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..705955d82c65cae27a09a2ea6b1a4a9af29d7a09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800107b          	cv.sub.b	zero,zero,zero
+   4:	081090fb          	cv.sub.b	ra,ra,ra
+   8:	0821117b          	cv.sub.b	sp,sp,sp
+   c:	0884147b          	cv.sub.b	s0,s0,s0
+  10:	094a1a7b          	cv.sub.b	s4,s4,s4
+  14:	09ff9ffb          	cv.sub.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..99f9c1ef13bde94cd91c8c0320d423e53b1b1f67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.b x0, x0, x0
+    cv.sub.b x1, x1, x1
+    cv.sub.b x2, x2, x2
+    cv.sub.b x8, x8, x8
+    cv.sub.b x20, x20, x20
+    cv.sub.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..ce6f41cea9b2b114ac73734d9b6b9a4595221267
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div2-fail.s
+#error_output: cv-simd-sub-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..7776bd5850fb89e542588d3efcffb773d5ad3c96
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.sub.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e1c33a6fd21484e19a9b6cd06b6b909c0e1dc8b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.div2 x32, x32, x32
+    cv.sub.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..fb7c2dc1a57596b23ff8356f65631516a92c5a15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7400207b          	cv.sub.div2	zero,zero,zero
+   4:	7410a0fb          	cv.sub.div2	ra,ra,ra
+   8:	7421217b          	cv.sub.div2	sp,sp,sp
+   c:	7484247b          	cv.sub.div2	s0,s0,s0
+  10:	754a2a7b          	cv.sub.div2	s4,s4,s4
+  14:	75ffaffb          	cv.sub.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7ca4507d27dd14d5e65fdf3975b33cea0dd1d20f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.div2 x0, x0, x0
+    cv.sub.div2 x1, x1, x1
+    cv.sub.div2 x2, x2, x2
+    cv.sub.div2 x8, x8, x8
+    cv.sub.div2 x20, x20, x20
+    cv.sub.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a1cd49b8bdf0b01bac235bc28a4d6f76099d58db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div4-fail.s
+#error_output: cv-simd-sub-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..886d6783979b1766fd3143bc5b098902f3c563d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.sub.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..8e7a639f9a8b0a46350892411bdd9f77f0b50367
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.div4 x32, x32, x32
+    cv.sub.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..8b182daac1d0830002f65219ef33991fd57aada5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7400407b          	cv.sub.div4	zero,zero,zero
+   4:	7410c0fb          	cv.sub.div4	ra,ra,ra
+   8:	7421417b          	cv.sub.div4	sp,sp,sp
+   c:	7484447b          	cv.sub.div4	s0,s0,s0
+  10:	754a4a7b          	cv.sub.div4	s4,s4,s4
+  14:	75ffcffb          	cv.sub.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..8e6ad0c8a6471ff7a1d2147793c423c86b54e485
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.div4 x0, x0, x0
+    cv.sub.div4 x1, x1, x1
+    cv.sub.div4 x2, x2, x2
+    cv.sub.div4 x8, x8, x8
+    cv.sub.div4 x20, x20, x20
+    cv.sub.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..a7e4b1a16795747c10242e53ce4ff59249d831d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div8-fail.s
+#error_output: cv-simd-sub-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..c6141b1dc69198c8be4eed8f28568995ce187b9d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.sub.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..f642daefd3aa27240151a04edf60b0ff3c91537c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.div8 x32, x32, x32
+    cv.sub.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..f0ce2ce92f0e357a32867fe5f84b01dfd422d61b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7400607b          	cv.sub.div8	zero,zero,zero
+   4:	7410e0fb          	cv.sub.div8	ra,ra,ra
+   8:	7421617b          	cv.sub.div8	sp,sp,sp
+   c:	7484647b          	cv.sub.div8	s0,s0,s0
+  10:	754a6a7b          	cv.sub.div8	s4,s4,s4
+  14:	75ffeffb          	cv.sub.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..1d38695d203d04b17fb688cb730c794443d6b749
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.div8 x0, x0, x0
+    cv.sub.div8 x1, x1, x1
+    cv.sub.div8 x2, x2, x2
+    cv.sub.div8 x8, x8, x8
+    cv.sub.div8 x20, x20, x20
+    cv.sub.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2fd004df55ede57eddb7b1a4c37c68483fc02245
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-h-fail.s
+#error_output: cv-simd-sub-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..36728c3b84b872c1b013bc588e2dc044115877e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.h x32,x32,x32'
+.*: Error: illegal operands `cv.sub.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..63a218290f0f22da3ab0450566fcc368dbb39e71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.h x32, x32, x32
+    cv.sub.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..697f6eef4c44103a4092a8f322e747e90fd61840
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800007b          	cv.sub.h	zero,zero,zero
+   4:	081080fb          	cv.sub.h	ra,ra,ra
+   8:	0821017b          	cv.sub.h	sp,sp,sp
+   c:	0884047b          	cv.sub.h	s0,s0,s0
+  10:	094a0a7b          	cv.sub.h	s4,s4,s4
+  14:	09ff8ffb          	cv.sub.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..61fc9f949a0513dcd13eb814ec0b7d52fec155aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.h x0, x0, x0
+    cv.sub.h x1, x1, x1
+    cv.sub.h x2, x2, x2
+    cv.sub.h x8, x8, x8
+    cv.sub.h x20, x20, x20
+    cv.sub.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..d993b5c20f76c48220ea4b1bdbb84ee858789140
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-b-fail.s
+#error_output: cv-simd-sub-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..785f3c7c3be99d65bd7dfd3d51a767e35e07856f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sub.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..83942ae229003a1ba4bf588a77e59092e04474e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.sc.b x32, x32, x32
+    cv.sub.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..3092dca0b2b2cd11de190dd94c519870ed12f332
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800507b          	cv.sub.sc.b	zero,zero,zero
+   4:	0810d0fb          	cv.sub.sc.b	ra,ra,ra
+   8:	0821517b          	cv.sub.sc.b	sp,sp,sp
+   c:	0884547b          	cv.sub.sc.b	s0,s0,s0
+  10:	094a5a7b          	cv.sub.sc.b	s4,s4,s4
+  14:	09ffdffb          	cv.sub.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..2d0170cdfef670529e45915472c36b939f3a33fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.sc.b x0, x0, x0
+    cv.sub.sc.b x1, x1, x1
+    cv.sub.sc.b x2, x2, x2
+    cv.sub.sc.b x8, x8, x8
+    cv.sub.sc.b x20, x20, x20
+    cv.sub.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..027adeb69150a9c50da7bc831d30dc510add8dc4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-h-fail.s
+#error_output: cv-simd-sub-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..5d5c6b67ac2a41dd9bc5d75d6b68fee1a820b39e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sub.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..cc48b52fa2ce57c13da5cd9299bc24d53816816f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.sc.h x32, x32, x32
+    cv.sub.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..29c0fbf7d8a72aa54aee0cccd84ae56387939922
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800407b          	cv.sub.sc.h	zero,zero,zero
+   4:	0810c0fb          	cv.sub.sc.h	ra,ra,ra
+   8:	0821417b          	cv.sub.sc.h	sp,sp,sp
+   c:	0884447b          	cv.sub.sc.h	s0,s0,s0
+  10:	094a4a7b          	cv.sub.sc.h	s4,s4,s4
+  14:	09ffcffb          	cv.sub.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..5608febce85ea92569dbde87910ccebd2d7ce1e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.sub.sc.h x0, x0, x0
+    cv.sub.sc.h x1, x1, x1
+    cv.sub.sc.h x2, x2, x2
+    cv.sub.sc.h x8, x8, x8
+    cv.sub.sc.h x20, x20, x20
+    cv.sub.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..9b1f5367c54c14e18b738e13013b613d2a639a2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-b-fail.s
+#error_output: cv-simd-sub-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..d45c4089d7c7839c798d1f65c9a68b4c592d872e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sub.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..efacb4d76ffe8d0db3b2595c61da21e2b7d75447
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.sci.b x32, x32, 20
+    cv.sub.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sub.sci.b x6, x7, -33
+    cv.sub.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..7de24649a440727d4db2c547a8b26df8ea642e2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	08a0707b          	cv.sub.sci.b	zero,zero,20
+   4:	08a0f0fb          	cv.sub.sci.b	ra,ra,20
+   8:	08a1717b          	cv.sub.sci.b	sp,sp,20
+   c:	08a4747b          	cv.sub.sci.b	s0,s0,20
+  10:	08aa7a7b          	cv.sub.sci.b	s4,s4,20
+  14:	08affffb          	cv.sub.sci.b	t6,t6,20
+  18:	0903f37b          	cv.sub.sci.b	t1,t2,-32
+  1c:	0803f37b          	cv.sub.sci.b	t1,t2,0
+  20:	0af3f37b          	cv.sub.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ef41450b53f4f88a5cdaf8e5a9a082442b3194f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.sub.sci.b x0, x0, 20
+    cv.sub.sci.b x1, x1, 20
+    cv.sub.sci.b x2, x2, 20
+    cv.sub.sci.b x8, x8, 20
+    cv.sub.sci.b x20, x20, 20
+    cv.sub.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sub.sci.b x6, x7, -32
+    cv.sub.sci.b x6, x7, 0
+    cv.sub.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..f9703b9271f1ddc1d5cc4b010355ac1b4cbae9ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-h-fail.s
+#error_output: cv-simd-sub-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..ff9425a443586273c6bfb9a68d17e667c1b982e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sub.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..bdd60606d7af0cbe848980bc956b6bcf72e20def
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.sub.sci.h x32, x32, 20
+    cv.sub.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sub.sci.h x6, x7, -33
+    cv.sub.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..36ed84a7392ddd2deaa951d69d929d4fac1a2684
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	08a0607b          	cv.sub.sci.h	zero,zero,20
+   4:	08a0e0fb          	cv.sub.sci.h	ra,ra,20
+   8:	08a1617b          	cv.sub.sci.h	sp,sp,20
+   c:	08a4647b          	cv.sub.sci.h	s0,s0,20
+  10:	08aa6a7b          	cv.sub.sci.h	s4,s4,20
+  14:	08afeffb          	cv.sub.sci.h	t6,t6,20
+  18:	0903e37b          	cv.sub.sci.h	t1,t2,-32
+  1c:	0803e37b          	cv.sub.sci.h	t1,t2,0
+  20:	0af3e37b          	cv.sub.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..7b74356abc7172912e8a285fafa7b730f1e7d968
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.sub.sci.h x0, x0, 20
+    cv.sub.sci.h x1, x1, 20
+    cv.sub.sci.h x2, x2, 20
+    cv.sub.sci.h x8, x8, 20
+    cv.sub.sci.h x20, x20, 20
+    cv.sub.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sub.sci.h x6, x7, -32
+    cv.sub.sci.h x6, x7, 0
+    cv.sub.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..101d8a33c99711f9a5506d31762b28826a07dec6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div2-fail.s
+#error_output: cv-simd-subrotmj-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..324fe88cfc7f9210b0b76545bef68024147abbb6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..b8a95a56588b2c0b03ecebe01f36a0d485970e8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.subrotmj.div2 x32, x32, x32
+    cv.subrotmj.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..2c65227723f0bd462cc4e4449c1f1b9446a5bc5a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400207b          	cv.subrotmj.div2	zero,zero,zero
+   4:	6410a0fb          	cv.subrotmj.div2	ra,ra,ra
+   8:	6421217b          	cv.subrotmj.div2	sp,sp,sp
+   c:	6484247b          	cv.subrotmj.div2	s0,s0,s0
+  10:	654a2a7b          	cv.subrotmj.div2	s4,s4,s4
+  14:	65ffaffb          	cv.subrotmj.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..809fc2d0cbb40802d67d24cfce0ed3eccec64d1b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.subrotmj.div2 x0, x0, x0
+    cv.subrotmj.div2 x1, x1, x1
+    cv.subrotmj.div2 x2, x2, x2
+    cv.subrotmj.div2 x8, x8, x8
+    cv.subrotmj.div2 x20, x20, x20
+    cv.subrotmj.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..6eb69c0754fb3391007d5c6be0386ea8f44a51b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div4-fail.s
+#error_output: cv-simd-subrotmj-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..73b9e0eea133ad8d6832b6923d8e952d8656b7a3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..e9620aad3fd385234e99895753716fe500ef7a36
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.subrotmj.div4 x32, x32, x32
+    cv.subrotmj.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..65084e82258d718556b83647e3a3bdd1678fe32a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400407b          	cv.subrotmj.div4	zero,zero,zero
+   4:	6410c0fb          	cv.subrotmj.div4	ra,ra,ra
+   8:	6421417b          	cv.subrotmj.div4	sp,sp,sp
+   c:	6484447b          	cv.subrotmj.div4	s0,s0,s0
+  10:	654a4a7b          	cv.subrotmj.div4	s4,s4,s4
+  14:	65ffcffb          	cv.subrotmj.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..a6272be9b73e565ae9f1c8c3ab4c31d27e283995
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.subrotmj.div4 x0, x0, x0
+    cv.subrotmj.div4 x1, x1, x1
+    cv.subrotmj.div4 x2, x2, x2
+    cv.subrotmj.div4 x8, x8, x8
+    cv.subrotmj.div4 x20, x20, x20
+    cv.subrotmj.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..3102640f8069529593137f0fb3dff90fecbcbcbc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div8-fail.s
+#error_output: cv-simd-subrotmj-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..558de39886db934953f7e31013f030ea94d34c83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..4b3b54dd45ccd5bfc621160221b7891bb81ef4d5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.subrotmj.div8 x32, x32, x32
+    cv.subrotmj.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..29560b68dac62433ed8a75037ddebf3b8223ccf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400607b          	cv.subrotmj.div8	zero,zero,zero
+   4:	6410e0fb          	cv.subrotmj.div8	ra,ra,ra
+   8:	6421617b          	cv.subrotmj.div8	sp,sp,sp
+   c:	6484647b          	cv.subrotmj.div8	s0,s0,s0
+  10:	654a6a7b          	cv.subrotmj.div8	s4,s4,s4
+  14:	65ffeffb          	cv.subrotmj.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..4dbabd5df19ec9e64d7894954358e7bc4f0120cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.subrotmj.div8 x0, x0, x0
+    cv.subrotmj.div8 x1, x1, x1
+    cv.subrotmj.div8 x2, x2, x2
+    cv.subrotmj.div8 x8, x8, x8
+    cv.subrotmj.div8 x20, x20, x20
+    cv.subrotmj.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..21ace4da2d8ea6dba5f6966b789e72e33b38e59b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-fail.s
+#error_output: cv-simd-subrotmj-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..1e7f31b122159ab15424accf23a8d2bf9dd94e6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2b05cfcbb4837f87ac1ffbe6a435b8d2c3053b00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.subrotmj x32, x32, x32
+    cv.subrotmj x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c6843343b7eea6ea88ca141386b5eb785973727a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400007b          	cv.subrotmj	zero,zero,zero
+   4:	641080fb          	cv.subrotmj	ra,ra,ra
+   8:	6421017b          	cv.subrotmj	sp,sp,sp
+   c:	6484047b          	cv.subrotmj	s0,s0,s0
+  10:	654a0a7b          	cv.subrotmj	s4,s4,s4
+  14:	65ff8ffb          	cv.subrotmj	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..838f4d3e677c496fbe1dbe4e592266cbc8060289
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.subrotmj x0, x0, x0
+    cv.subrotmj x1, x1, x1
+    cv.subrotmj x2, x2, x2
+    cv.subrotmj x8, x8, x8
+    cv.subrotmj x20, x20, x20
+    cv.subrotmj x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..13adc9f213635e5d724effdc0f4a5cb79d9f0603
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-b-fail.s
+#error_output: cv-simd-xor-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..85aba380181fd76010b06f12a063cacaf7cebfd1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.b x32,x32,x32'
+.*: Error: illegal operands `cv.xor.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c159d6895a9fbaf7d9c2244a302e02e112c0bb7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.xor.b x32, x32, x32
+    cv.xor.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..c5aed6ec9d69e73cf67957ab0eb18f64680ce5a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000107b          	cv.xor.b	zero,zero,zero
+   4:	601090fb          	cv.xor.b	ra,ra,ra
+   8:	6021117b          	cv.xor.b	sp,sp,sp
+   c:	6084147b          	cv.xor.b	s0,s0,s0
+  10:	614a1a7b          	cv.xor.b	s4,s4,s4
+  14:	61ff9ffb          	cv.xor.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..8300bbe3d50315bbaba86cc2f2bc28bd42812f80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.xor.b x0, x0, x0
+    cv.xor.b x1, x1, x1
+    cv.xor.b x2, x2, x2
+    cv.xor.b x8, x8, x8
+    cv.xor.b x20, x20, x20
+    cv.xor.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..2d5d8f2da798edc6f3c885c6d0ba8f4769cedcf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-h-fail.s
+#error_output: cv-simd-xor-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..e17ec8a240d2b3be031920b3211575ad9cf535cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.h x32,x32,x32'
+.*: Error: illegal operands `cv.xor.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..67f8d5c6ba0943c7c9caf5f5cf9eadb032d0756d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.xor.h x32, x32, x32
+    cv.xor.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..377c5f4257e3c4d40e9d9384192ca2de4b838aea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000007b          	cv.xor.h	zero,zero,zero
+   4:	601080fb          	cv.xor.h	ra,ra,ra
+   8:	6021017b          	cv.xor.h	sp,sp,sp
+   c:	6084047b          	cv.xor.h	s0,s0,s0
+  10:	614a0a7b          	cv.xor.h	s4,s4,s4
+  14:	61ff8ffb          	cv.xor.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ac68ef1167d11aab305f1b6b55e1435822b6db1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.xor.h x0, x0, x0
+    cv.xor.h x1, x1, x1
+    cv.xor.h x2, x2, x2
+    cv.xor.h x8, x8, x8
+    cv.xor.h x20, x20, x20
+    cv.xor.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..5467367f223628f7ba0a11476937bbde08ecc006
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-b-fail.s
+#error_output: cv-simd-xor-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..91a289855899a6b51d67773890a78596eaa5acd4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.xor.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..a6bcb1bcb78d2dc8dc1a85d297c826876eb1fa90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.xor.sc.b x32, x32, x32
+    cv.xor.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..12e6917f2b17d02bfaa17b2146afc21c4479b0bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000507b          	cv.xor.sc.b	zero,zero,zero
+   4:	6010d0fb          	cv.xor.sc.b	ra,ra,ra
+   8:	6021517b          	cv.xor.sc.b	sp,sp,sp
+   c:	6084547b          	cv.xor.sc.b	s0,s0,s0
+  10:	614a5a7b          	cv.xor.sc.b	s4,s4,s4
+  14:	61ffdffb          	cv.xor.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ebda07f7c41d30fd3339ac085065bebe0dc228c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.xor.sc.b x0, x0, x0
+    cv.xor.sc.b x1, x1, x1
+    cv.xor.sc.b x2, x2, x2
+    cv.xor.sc.b x8, x8, x8
+    cv.xor.sc.b x20, x20, x20
+    cv.xor.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..7712206da4ffe539f9033d2607e1a2dbf1303515
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-h-fail.s
+#error_output: cv-simd-xor-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..b2417b49029ff9f03de2710155aa8bdf5e711bf3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.xor.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..26905c966b5e72597865fa518a6a7aa6ef9f6c5a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
@@ -0,0 +1,4 @@
+target: 
+    #Boundary Register Tests
+    cv.xor.sc.h x32, x32, x32
+    cv.xor.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..5dc5fd83e2cea48b84213b6c68b3f2ea4b6f1863
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000407b          	cv.xor.sc.h	zero,zero,zero
+   4:	6010c0fb          	cv.xor.sc.h	ra,ra,ra
+   8:	6021417b          	cv.xor.sc.h	sp,sp,sp
+   c:	6084447b          	cv.xor.sc.h	s0,s0,s0
+  10:	614a4a7b          	cv.xor.sc.h	s4,s4,s4
+  14:	61ffcffb          	cv.xor.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..ee2f8c9b6a8b53cf90a182ec795ab3e99f308cff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
@@ -0,0 +1,8 @@
+target: 
+    #Register Tests
+    cv.xor.sc.h x0, x0, x0
+    cv.xor.sc.h x1, x1, x1
+    cv.xor.sc.h x2, x2, x2
+    cv.xor.sc.h x8, x8, x8
+    cv.xor.sc.h x20, x20, x20
+    cv.xor.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..52dcc30c7efc57c72c1c4d08f21a7a777523f8ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-b-fail.s
+#error_output: cv-simd-xor-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..64e90bac715254781d22f2694ca791ac457986f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.xor.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..2b1ad6a16db6d83fd1619d5d9c71f85b70f91b06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.xor.sci.b x32, x32, 20
+    cv.xor.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.xor.sci.b x6, x7, -33
+    cv.xor.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e1eab657bfb678cca8af05e971b37452ba5a5059
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	60a0707b          	cv.xor.sci.b	zero,zero,20
+   4:	60a0f0fb          	cv.xor.sci.b	ra,ra,20
+   8:	60a1717b          	cv.xor.sci.b	sp,sp,20
+   c:	60a4747b          	cv.xor.sci.b	s0,s0,20
+  10:	60aa7a7b          	cv.xor.sci.b	s4,s4,20
+  14:	60affffb          	cv.xor.sci.b	t6,t6,20
+  18:	6103f37b          	cv.xor.sci.b	t1,t2,-32
+  1c:	6003f37b          	cv.xor.sci.b	t1,t2,0
+  20:	62f3f37b          	cv.xor.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..c46e1738dfc5afd917f5d2349e18956f56717e8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.xor.sci.b x0, x0, 20
+    cv.xor.sci.b x1, x1, 20
+    cv.xor.sci.b x2, x2, 20
+    cv.xor.sci.b x8, x8, 20
+    cv.xor.sci.b x20, x20, 20
+    cv.xor.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.xor.sci.b x6, x7, -32
+    cv.xor.sci.b x6, x7, 0
+    cv.xor.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
new file mode 100644
index 0000000000000000000000000000000000000000..1572fc54ec36da5ebbe7913bb8d29ee44f007cb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-h-fail.s
+#error_output: cv-simd-xor-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
new file mode 100644
index 0000000000000000000000000000000000000000..a41246578585fefd98ee8e896893599275bb9e88
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.xor.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
new file mode 100644
index 0000000000000000000000000000000000000000..c100f21df04f1615ec8a9a72cef9c50cadc70072
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
@@ -0,0 +1,7 @@
+target: 
+    #Boundary Register Tests
+    cv.xor.sci.h x32, x32, 20
+    cv.xor.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.xor.sci.h x6, x7, -33
+    cv.xor.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
new file mode 100644
index 0000000000000000000000000000000000000000..e84c597abc0244876a2e5ede6267062a2edb3e99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	60a0607b          	cv.xor.sci.h	zero,zero,20
+   4:	60a0e0fb          	cv.xor.sci.h	ra,ra,20
+   8:	60a1617b          	cv.xor.sci.h	sp,sp,20
+   c:	60a4647b          	cv.xor.sci.h	s0,s0,20
+  10:	60aa6a7b          	cv.xor.sci.h	s4,s4,20
+  14:	60afeffb          	cv.xor.sci.h	t6,t6,20
+  18:	6103e37b          	cv.xor.sci.h	t1,t2,-32
+  1c:	6003e37b          	cv.xor.sci.h	t1,t2,0
+  20:	62f3e37b          	cv.xor.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s
new file mode 100644
index 0000000000000000000000000000000000000000..016147ad4badbf8656f761ec20834d98894a2079
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s
@@ -0,0 +1,12 @@
+target: 
+    #Register Tests
+    cv.xor.sci.h x0, x0, 20
+    cv.xor.sci.h x1, x1, 20
+    cv.xor.sci.h x2, x2, 20
+    cv.xor.sci.h x8, x8, 20
+    cv.xor.sci.h x20, x20, 20
+    cv.xor.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.xor.sci.h x6, x7, -32
+    cv.xor.sci.h x6, x7, 0
+    cv.xor.sci.h x6, x7, 31
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index bdce5b7d3db902c1dd39c80c4dea4bfe97ed5e73..fc23caa75e7f271c7d7e8e3461d93e58a17e1e7e 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2525,6 +2525,449 @@
 #define MATCH_CV_COUNTI 0x442b
 #define MATCH_CV_SETUP  0x472b
 #define MATCH_CV_SETUPI 0x462b
+/* Vendor-specific (CORE-V) Xcvsimd instructions. */
+#define MATCH_CV_ADD_H             0x7b
+#define MATCH_CV_ADD_B             0x107b
+#define MATCH_CV_ADD_SC_H          0x407b
+#define MATCH_CV_ADD_SC_B          0x507b
+#define MATCH_CV_ADD_SCI_H         0x607b
+#define MATCH_CV_ADD_SCI_B         0x707b
+#define MATCH_CV_SUB_H             0x800007b
+#define MATCH_CV_SUB_B             0x800107b
+#define MATCH_CV_SUB_SC_H          0x800407b
+#define MATCH_CV_SUB_SC_B          0x800507b
+#define MATCH_CV_SUB_SCI_H         0x800607b
+#define MATCH_CV_SUB_SCI_B         0x800707b
+#define MATCH_CV_AVG_H             0x1000007b
+#define MATCH_CV_AVG_B             0x1000107b
+#define MATCH_CV_AVG_SC_H          0x1000407b
+#define MATCH_CV_AVG_SC_B          0x1000507b
+#define MATCH_CV_AVG_SCI_H         0x1000607b
+#define MATCH_CV_AVG_SCI_B         0x1000707b
+#define MATCH_CV_AVGU_H            0x1800007b
+#define MATCH_CV_AVGU_B            0x1800107b
+#define MATCH_CV_AVGU_SC_H         0x1800407b
+#define MATCH_CV_AVGU_SC_B         0x1800507b
+#define MATCH_CV_AVGU_SCI_H        0x1800607b
+#define MATCH_CV_AVGU_SCI_B        0x1800707b
+#define MATCH_CV_MIN_H             0x2000007b
+#define MATCH_CV_MIN_B             0x2000107b
+#define MATCH_CV_MIN_SC_H          0x2000407b
+#define MATCH_CV_MIN_SC_B          0x2000507b
+#define MATCH_CV_MIN_SCI_H         0x2000607b
+#define MATCH_CV_MIN_SCI_B         0x2000707b
+#define MATCH_CV_MINU_H            0x2800007b
+#define MATCH_CV_MINU_B            0x2800107b
+#define MATCH_CV_MINU_SC_H         0x2800407b
+#define MATCH_CV_MINU_SC_B         0x2800507b
+#define MATCH_CV_MINU_SCI_H        0x2800607b
+#define MATCH_CV_MINU_SCI_B        0x2800707b
+#define MATCH_CV_MAX_H             0x3000007b
+#define MATCH_CV_MAX_B             0x3000107b
+#define MATCH_CV_MAX_SC_H          0x3000407b
+#define MATCH_CV_MAX_SC_B          0x3000507b
+#define MATCH_CV_MAX_SCI_H         0x3000607b
+#define MATCH_CV_MAX_SCI_B         0x3000707b
+#define MATCH_CV_MAXU_H            0x3800007b
+#define MATCH_CV_MAXU_B            0x3800107b
+#define MATCH_CV_MAXU_SC_H         0x3800407b
+#define MATCH_CV_MAXU_SC_B         0x3800507b
+#define MATCH_CV_MAXU_SCI_H        0x3800607b
+#define MATCH_CV_MAXU_SCI_B        0x3800707b
+#define MATCH_CV_SRL_H             0x4000007b
+#define MATCH_CV_SRL_B             0x4000107b
+#define MATCH_CV_SRL_SC_H          0x4000407b
+#define MATCH_CV_SRL_SC_B          0x4000507b
+#define MATCH_CV_SRL_SCI_H         0x4000607b
+#define MATCH_CV_SRL_SCI_B         0x4000707b
+#define MATCH_CV_SRA_H             0x4800007b
+#define MATCH_CV_SRA_B             0x4800107b
+#define MATCH_CV_SRA_SC_H          0x4800407b
+#define MATCH_CV_SRA_SC_B          0x4800507b
+#define MATCH_CV_SRA_SCI_H         0x4800607b
+#define MATCH_CV_SRA_SCI_B         0x4800707b
+#define MATCH_CV_SLL_H             0x5000007b
+#define MATCH_CV_SLL_B             0x5000107b
+#define MATCH_CV_SLL_SC_H          0x5000407b
+#define MATCH_CV_SLL_SC_B          0x5000507b
+#define MATCH_CV_SLL_SCI_H         0x5000607b
+#define MATCH_CV_SLL_SCI_B         0x5000707b
+#define MATCH_CV_OR_H              0x5800007b
+#define MATCH_CV_OR_B              0x5800107b
+#define MATCH_CV_OR_SC_H           0x5800407b
+#define MATCH_CV_OR_SC_B           0x5800507b
+#define MATCH_CV_OR_SCI_H          0x5800607b
+#define MATCH_CV_OR_SCI_B          0x5800707b
+#define MATCH_CV_XOR_H             0x6000007b
+#define MATCH_CV_XOR_B             0x6000107b
+#define MATCH_CV_XOR_SC_H          0x6000407b
+#define MATCH_CV_XOR_SC_B          0x6000507b
+#define MATCH_CV_XOR_SCI_H         0x6000607b
+#define MATCH_CV_XOR_SCI_B         0x6000707b
+#define MATCH_CV_AND_H             0x6800007b
+#define MATCH_CV_AND_B             0x6800107b
+#define MATCH_CV_AND_SC_H          0x6800407b
+#define MATCH_CV_AND_SC_B          0x6800507b
+#define MATCH_CV_AND_SCI_H         0x6800607b
+#define MATCH_CV_AND_SCI_B         0x6800707b
+#define MATCH_CV_ABS_H             0x7000007b
+#define MATCH_CV_ABS_B             0x7000107b
+#define MATCH_CV_DOTUP_H           0x8000007b
+#define MATCH_CV_DOTUP_B           0x8000107b
+#define MATCH_CV_DOTUP_SC_H        0x8000407b
+#define MATCH_CV_DOTUP_SC_B        0x8000507b
+#define MATCH_CV_DOTUP_SCI_H       0x8000607b
+#define MATCH_CV_DOTUP_SCI_B       0x8000707b
+#define MATCH_CV_DOTUSP_H          0x8800007b
+#define MATCH_CV_DOTUSP_B          0x8800107b
+#define MATCH_CV_DOTUSP_SC_H       0x8800407b
+#define MATCH_CV_DOTUSP_SC_B       0x8800507b
+#define MATCH_CV_DOTUSP_SCI_H      0x8800607b
+#define MATCH_CV_DOTUSP_SCI_B      0x8800707b
+#define MATCH_CV_DOTSP_H           0x9000007b
+#define MATCH_CV_DOTSP_B           0x9000107b
+#define MATCH_CV_DOTSP_SC_H        0x9000407b
+#define MATCH_CV_DOTSP_SC_B        0x9000507b
+#define MATCH_CV_DOTSP_SCI_H       0x9000607b
+#define MATCH_CV_DOTSP_SCI_B       0x9000707b
+#define MATCH_CV_SDOTUP_H          0x9800007b
+#define MATCH_CV_SDOTUP_B          0x9800107b
+#define MATCH_CV_SDOTUP_SC_H       0x9800407b
+#define MATCH_CV_SDOTUP_SC_B       0x9800507b
+#define MATCH_CV_SDOTUP_SCI_H      0x9800607b
+#define MATCH_CV_SDOTUP_SCI_B      0x9800707b
+#define MATCH_CV_SDOTUSP_H         0xa000007b
+#define MATCH_CV_SDOTUSP_B         0xa000107b
+#define MATCH_CV_SDOTUSP_SC_H      0xa000407b
+#define MATCH_CV_SDOTUSP_SC_B      0xa000507b
+#define MATCH_CV_SDOTUSP_SCI_H     0xa000607b
+#define MATCH_CV_SDOTUSP_SCI_B     0xa000707b
+#define MATCH_CV_SDOTSP_H          0xa800007b
+#define MATCH_CV_SDOTSP_B          0xa800107b
+#define MATCH_CV_SDOTSP_SC_H       0xa800407b
+#define MATCH_CV_SDOTSP_SC_B       0xa800507b
+#define MATCH_CV_SDOTSP_SCI_H      0xa800607b
+#define MATCH_CV_SDOTSP_SCI_B      0xa800707b
+#define MATCH_CV_EXTRACT_H         0xb800007b
+#define MATCH_CV_EXTRACT_B         0xb800107b
+#define MATCH_CV_EXTRACTU_H        0xb800207b
+#define MATCH_CV_EXTRACTU_B        0xb800307b
+#define MATCH_CV_INSERT_H          0xb800407b
+#define MATCH_CV_INSERT_B          0xb800507b
+#define MATCH_CV_SHUFFLE_H         0xc000007b
+#define MATCH_CV_SHUFFLE_B         0xc000107b
+#define MATCH_CV_SHUFFLE_SCI_H     0xc000607b
+#define MATCH_CV_SHUFFLEI0_SCI_B   0xc000707b
+#define MATCH_CV_SHUFFLEI1_SCI_B   0xc800707b
+#define MATCH_CV_SHUFFLEI2_SCI_B   0xd000707b
+#define MATCH_CV_SHUFFLEI3_SCI_B   0xd800707b
+#define MATCH_CV_SHUFFLE2_H        0xe000007b
+#define MATCH_CV_SHUFFLE2_B        0xe000107b
+#define MATCH_CV_PACK              0xf000007b
+#define MATCH_CV_PACK_H            0xf200007b
+#define MATCH_CV_PACKHI_B          0xfa00107b
+#define MATCH_CV_PACKLO_B          0xf800107b
+#define MATCH_CV_CMPEQ_H           0x400007b
+#define MATCH_CV_CMPEQ_B           0x400107b
+#define MATCH_CV_CMPEQ_SC_H        0x400407b
+#define MATCH_CV_CMPEQ_SC_B        0x400507b
+#define MATCH_CV_CMPEQ_SCI_H       0x400607b
+#define MATCH_CV_CMPEQ_SCI_B       0x400707b
+#define MATCH_CV_CMPNE_H           0xc00007b
+#define MATCH_CV_CMPNE_B           0xc00107b
+#define MATCH_CV_CMPNE_SC_H        0xc00407b
+#define MATCH_CV_CMPNE_SC_B        0xc00507b
+#define MATCH_CV_CMPNE_SCI_H       0xc00607b
+#define MATCH_CV_CMPNE_SCI_B       0xc00707b
+#define MATCH_CV_CMPGT_H           0x1400007b
+#define MATCH_CV_CMPGT_B           0x1400107b
+#define MATCH_CV_CMPGT_SC_H        0x1400407b
+#define MATCH_CV_CMPGT_SC_B        0x1400507b
+#define MATCH_CV_CMPGT_SCI_H       0x1400607b
+#define MATCH_CV_CMPGT_SCI_B       0x1400707b
+#define MATCH_CV_CMPGE_H           0x1c00007b
+#define MATCH_CV_CMPGE_B           0x1c00107b
+#define MATCH_CV_CMPGE_SC_H        0x1c00407b
+#define MATCH_CV_CMPGE_SC_B        0x1c00507b
+#define MATCH_CV_CMPGE_SCI_H       0x1c00607b
+#define MATCH_CV_CMPGE_SCI_B       0x1c00707b
+#define MATCH_CV_CMPLT_H           0x2400007b
+#define MATCH_CV_CMPLT_B           0x2400107b
+#define MATCH_CV_CMPLT_SC_H        0x2400407b
+#define MATCH_CV_CMPLT_SC_B        0x2400507b
+#define MATCH_CV_CMPLT_SCI_H       0x2400607b
+#define MATCH_CV_CMPLT_SCI_B       0x2400707b
+#define MATCH_CV_CMPLE_H           0x2c00007b
+#define MATCH_CV_CMPLE_B           0x2c00107b
+#define MATCH_CV_CMPLE_SC_H        0x2c00407b
+#define MATCH_CV_CMPLE_SC_B        0x2c00507b
+#define MATCH_CV_CMPLE_SCI_H       0x2c00607b
+#define MATCH_CV_CMPLE_SCI_B       0x2c00707b
+#define MATCH_CV_CMPGTU_H          0x3400007b
+#define MATCH_CV_CMPGTU_B          0x3400107b
+#define MATCH_CV_CMPGTU_SC_H       0x3400407b
+#define MATCH_CV_CMPGTU_SC_B       0x3400507b
+#define MATCH_CV_CMPGTU_SCI_H      0x3400607b
+#define MATCH_CV_CMPGTU_SCI_B      0x3400707b
+#define MATCH_CV_CMPGEU_H          0x3c00007b
+#define MATCH_CV_CMPGEU_B          0x3c00107b
+#define MATCH_CV_CMPGEU_SC_H       0x3c00407b
+#define MATCH_CV_CMPGEU_SC_B       0x3c00507b
+#define MATCH_CV_CMPGEU_SCI_H      0x3c00607b
+#define MATCH_CV_CMPGEU_SCI_B      0x3c00707b
+#define MATCH_CV_CMPLTU_H          0x4400007b
+#define MATCH_CV_CMPLTU_B          0x4400107b
+#define MATCH_CV_CMPLTU_SC_H       0x4400407b
+#define MATCH_CV_CMPLTU_SC_B       0x4400507b
+#define MATCH_CV_CMPLTU_SCI_H      0x4400607b
+#define MATCH_CV_CMPLTU_SCI_B      0x4400707b
+#define MATCH_CV_CMPLEU_H          0x4c00007b
+#define MATCH_CV_CMPLEU_B          0x4c00107b
+#define MATCH_CV_CMPLEU_SC_H       0x4c00407b
+#define MATCH_CV_CMPLEU_SC_B       0x4c00507b
+#define MATCH_CV_CMPLEU_SCI_H      0x4c00607b
+#define MATCH_CV_CMPLEU_SCI_B      0x4c00707b
+#define MATCH_CV_CPLXMUL_R         0x5400007b
+#define MATCH_CV_CPLXMUL_I         0x5600007b
+#define MATCH_CV_CPLXMUL_R_DIV2    0x5400207b
+#define MATCH_CV_CPLXMUL_I_DIV2    0x5600207b
+#define MATCH_CV_CPLXMUL_R_DIV4    0x5400407b
+#define MATCH_CV_CPLXMUL_I_DIV4    0x5600407b
+#define MATCH_CV_CPLXMUL_R_DIV8    0x5400607b
+#define MATCH_CV_CPLXMUL_I_DIV8    0x5600607b
+#define MATCH_CV_CPLXCONJ          0x5c00007b
+#define MATCH_CV_SUBROTMJ          0x6400007b
+#define MATCH_CV_SUBROTMJ_DIV2     0x6400207b
+#define MATCH_CV_SUBROTMJ_DIV4     0x6400407b
+#define MATCH_CV_SUBROTMJ_DIV8     0x6400607b
+#define MATCH_CV_ADD_DIV2          0x6c00207b
+#define MATCH_CV_ADD_DIV4          0x6c00407b
+#define MATCH_CV_ADD_DIV8          0x6c00607b
+#define MATCH_CV_SUB_DIV2          0x7400207b
+#define MATCH_CV_SUB_DIV4          0x7400407b
+#define MATCH_CV_SUB_DIV8          0x7400607b
+#define MASK_CV_ADD_H              0xfe00707f
+#define MASK_CV_ADD_B              0xfe00707f
+#define MASK_CV_ADD_SC_H           0xfe00707f
+#define MASK_CV_ADD_SC_B           0xfe00707f
+#define MASK_CV_ADD_SCI_H          0xfc00707f
+#define MASK_CV_ADD_SCI_B          0xfc00707f
+#define MASK_CV_SUB_H              0xfe00707f
+#define MASK_CV_SUB_B              0xfe00707f
+#define MASK_CV_SUB_SC_H           0xfe00707f
+#define MASK_CV_SUB_SC_B           0xfe00707f
+#define MASK_CV_SUB_SCI_H          0xfc00707f
+#define MASK_CV_SUB_SCI_B          0xfc00707f
+#define MASK_CV_AVG_H              0xfe00707f
+#define MASK_CV_AVG_B              0xfe00707f
+#define MASK_CV_AVG_SC_H           0xfe00707f
+#define MASK_CV_AVG_SC_B           0xfe00707f
+#define MASK_CV_AVG_SCI_H          0xfc00707f
+#define MASK_CV_AVG_SCI_B          0xfc00707f
+#define MASK_CV_AVGU_H             0xfe00707f
+#define MASK_CV_AVGU_B             0xfe00707f
+#define MASK_CV_AVGU_SC_H          0xfe00707f
+#define MASK_CV_AVGU_SC_B          0xfe00707f
+#define MASK_CV_AVGU_SCI_H         0xfc00707f
+#define MASK_CV_AVGU_SCI_B         0xfc00707f
+#define MASK_CV_MIN_H              0xfe00707f
+#define MASK_CV_MIN_B              0xfe00707f
+#define MASK_CV_MIN_SC_H           0xfe00707f
+#define MASK_CV_MIN_SC_B           0xfe00707f
+#define MASK_CV_MIN_SCI_H          0xfc00707f
+#define MASK_CV_MIN_SCI_B          0xfc00707f
+#define MASK_CV_MINU_H             0xfe00707f
+#define MASK_CV_MINU_B             0xfe00707f
+#define MASK_CV_MINU_SC_H          0xfe00707f
+#define MASK_CV_MINU_SC_B          0xfe00707f
+#define MASK_CV_MINU_SCI_H         0xfc00707f
+#define MASK_CV_MINU_SCI_B         0xfc00707f
+#define MASK_CV_MAX_H              0xfe00707f
+#define MASK_CV_MAX_B              0xfe00707f
+#define MASK_CV_MAX_SC_H           0xfe00707f
+#define MASK_CV_MAX_SC_B           0xfe00707f
+#define MASK_CV_MAX_SCI_H          0xfc00707f
+#define MASK_CV_MAX_SCI_B          0xfc00707f
+#define MASK_CV_MAXU_H             0xfe00707f
+#define MASK_CV_MAXU_B             0xfe00707f
+#define MASK_CV_MAXU_SC_H          0xfe00707f
+#define MASK_CV_MAXU_SC_B          0xfe00707f
+#define MASK_CV_MAXU_SCI_H         0xfc00707f
+#define MASK_CV_MAXU_SCI_B         0xfc00707f
+#define MASK_CV_SRL_H              0xfe00707f
+#define MASK_CV_SRL_B              0xfe00707f
+#define MASK_CV_SRL_SC_H           0xfe00707f
+#define MASK_CV_SRL_SC_B           0xfe00707f
+#define MASK_CV_SRL_SCI_H          0xfc00707f
+#define MASK_CV_SRL_SCI_B          0xfc00707f
+#define MASK_CV_SRA_H              0xfe00707f
+#define MASK_CV_SRA_B              0xfe00707f
+#define MASK_CV_SRA_SC_H           0xfe00707f
+#define MASK_CV_SRA_SC_B           0xfe00707f
+#define MASK_CV_SRA_SCI_H          0xfc00707f
+#define MASK_CV_SRA_SCI_B          0xfc00707f
+#define MASK_CV_SLL_H              0xfe00707f
+#define MASK_CV_SLL_B              0xfe00707f
+#define MASK_CV_SLL_SC_H           0xfe00707f
+#define MASK_CV_SLL_SC_B           0xfe00707f
+#define MASK_CV_SLL_SCI_H          0xfc00707f
+#define MASK_CV_SLL_SCI_B          0xfc00707f
+#define MASK_CV_OR_H               0xfe00707f
+#define MASK_CV_OR_B               0xfe00707f
+#define MASK_CV_OR_SC_H            0xfe00707f
+#define MASK_CV_OR_SC_B            0xfe00707f
+#define MASK_CV_OR_SCI_H           0xfc00707f
+#define MASK_CV_OR_SCI_B           0xfc00707f
+#define MASK_CV_XOR_H              0xfe00707f
+#define MASK_CV_XOR_B              0xfe00707f
+#define MASK_CV_XOR_SC_H           0xfe00707f
+#define MASK_CV_XOR_SC_B           0xfe00707f
+#define MASK_CV_XOR_SCI_H          0xfc00707f
+#define MASK_CV_XOR_SCI_B          0xfc00707f
+#define MASK_CV_AND_H              0xfe00707f
+#define MASK_CV_AND_B              0xfe00707f
+#define MASK_CV_AND_SC_H           0xfe00707f
+#define MASK_CV_AND_SC_B           0xfe00707f
+#define MASK_CV_AND_SCI_H          0xfc00707f
+#define MASK_CV_AND_SCI_B          0xfc00707f
+#define MASK_CV_ABS_H              0xfff0707f
+#define MASK_CV_ABS_B              0xfff0707f
+#define MASK_CV_DOTUP_H            0xfe00707f
+#define MASK_CV_DOTUP_B            0xfe00707f
+#define MASK_CV_DOTUP_SC_H         0xfe00707f
+#define MASK_CV_DOTUP_SC_B         0xfe00707f
+#define MASK_CV_DOTUP_SCI_H        0xfc00707f
+#define MASK_CV_DOTUP_SCI_B        0xfc00707f
+#define MASK_CV_DOTUSP_H           0xfe00707f
+#define MASK_CV_DOTUSP_B           0xfe00707f
+#define MASK_CV_DOTUSP_SC_H        0xfe00707f
+#define MASK_CV_DOTUSP_SC_B        0xfe00707f
+#define MASK_CV_DOTUSP_SCI_H       0xfc00707f
+#define MASK_CV_DOTUSP_SCI_B       0xfc00707f
+#define MASK_CV_DOTSP_H            0xfe00707f
+#define MASK_CV_DOTSP_B            0xfe00707f
+#define MASK_CV_DOTSP_SC_H         0xfe00707f
+#define MASK_CV_DOTSP_SC_B         0xfe00707f
+#define MASK_CV_DOTSP_SCI_H        0xfc00707f
+#define MASK_CV_DOTSP_SCI_B        0xfc00707f
+#define MASK_CV_SDOTUP_H           0xfe00707f
+#define MASK_CV_SDOTUP_B           0xfe00707f
+#define MASK_CV_SDOTUP_SC_H        0xfe00707f
+#define MASK_CV_SDOTUP_SC_B        0xfe00707f
+#define MASK_CV_SDOTUP_SCI_H       0xfc00707f
+#define MASK_CV_SDOTUP_SCI_B       0xfc00707f
+#define MASK_CV_SDOTUSP_H          0xfe00707f
+#define MASK_CV_SDOTUSP_B          0xfe00707f
+#define MASK_CV_SDOTUSP_SC_H       0xfe00707f
+#define MASK_CV_SDOTUSP_SC_B       0xfe00707f
+#define MASK_CV_SDOTUSP_SCI_H      0xfc00707f
+#define MASK_CV_SDOTUSP_SCI_B      0xfc00707f
+#define MASK_CV_SDOTSP_H           0xfe00707f
+#define MASK_CV_SDOTSP_B           0xfe00707f
+#define MASK_CV_SDOTSP_SC_H        0xfe00707f
+#define MASK_CV_SDOTSP_SC_B        0xfe00707f
+#define MASK_CV_SDOTSP_SCI_H       0xfc00707f
+#define MASK_CV_SDOTSP_SCI_B       0xfc00707f
+#define MASK_CV_EXTRACT_H          0xfc00707f
+#define MASK_CV_EXTRACT_B          0xfc00707f
+#define MASK_CV_EXTRACTU_H         0xfc00707f
+#define MASK_CV_EXTRACTU_B         0xfc00707f
+#define MASK_CV_INSERT_H           0xfc00707f
+#define MASK_CV_INSERT_B           0xfc00707f
+#define MASK_CV_SHUFFLE_H          0xfe00707f
+#define MASK_CV_SHUFFLE_B          0xfe00707f
+#define MASK_CV_SHUFFLE_SCI_H      0xfc00707f
+#define MASK_CV_SHUFFLEI0_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLEI1_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLEI2_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLEI3_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLE2_H         0xfe00707f
+#define MASK_CV_SHUFFLE2_B         0xfe00707f
+#define MASK_CV_PACK               0xfe00707f
+#define MASK_CV_PACK_H             0xfe00707f
+#define MASK_CV_PACKHI_B           0xfe00707f
+#define MASK_CV_PACKLO_B           0xfe00707f
+#define MASK_CV_CMPEQ_H            0xfe00707f
+#define MASK_CV_CMPEQ_B            0xfe00707f
+#define MASK_CV_CMPEQ_SC_H         0xfe00707f
+#define MASK_CV_CMPEQ_SC_B         0xfe00707f
+#define MASK_CV_CMPEQ_SCI_H        0xfc00707f
+#define MASK_CV_CMPEQ_SCI_B        0xfc00707f
+#define MASK_CV_CMPNE_H            0xfe00707f
+#define MASK_CV_CMPNE_B            0xfe00707f
+#define MASK_CV_CMPNE_SC_H         0xfe00707f
+#define MASK_CV_CMPNE_SC_B         0xfe00707f
+#define MASK_CV_CMPNE_SCI_H        0xfc00707f
+#define MASK_CV_CMPNE_SCI_B        0xfc00707f
+#define MASK_CV_CMPGT_H            0xfe00707f
+#define MASK_CV_CMPGT_B            0xfe00707f
+#define MASK_CV_CMPGT_SC_H         0xfe00707f
+#define MASK_CV_CMPGT_SC_B         0xfe00707f
+#define MASK_CV_CMPGT_SCI_H        0xfc00707f
+#define MASK_CV_CMPGT_SCI_B        0xfc00707f
+#define MASK_CV_CMPGE_H            0xfe00707f
+#define MASK_CV_CMPGE_B            0xfe00707f
+#define MASK_CV_CMPGE_SC_H         0xfe00707f
+#define MASK_CV_CMPGE_SC_B         0xfe00707f
+#define MASK_CV_CMPGE_SCI_H        0xfc00707f
+#define MASK_CV_CMPGE_SCI_B        0xfc00707f
+#define MASK_CV_CMPLT_H            0xfe00707f
+#define MASK_CV_CMPLT_B            0xfe00707f
+#define MASK_CV_CMPLT_SC_H         0xfe00707f
+#define MASK_CV_CMPLT_SC_B         0xfe00707f
+#define MASK_CV_CMPLT_SCI_H        0xfc00707f
+#define MASK_CV_CMPLT_SCI_B        0xfc00707f
+#define MASK_CV_CMPLE_H            0xfe00707f
+#define MASK_CV_CMPLE_B            0xfe00707f
+#define MASK_CV_CMPLE_SC_H         0xfe00707f
+#define MASK_CV_CMPLE_SC_B         0xfe00707f
+#define MASK_CV_CMPLE_SCI_H        0xfc00707f
+#define MASK_CV_CMPLE_SCI_B        0xfc00707f
+#define MASK_CV_CMPGTU_H           0xfe00707f
+#define MASK_CV_CMPGTU_B           0xfe00707f
+#define MASK_CV_CMPGTU_SC_H        0xfe00707f
+#define MASK_CV_CMPGTU_SC_B        0xfe00707f
+#define MASK_CV_CMPGTU_SCI_H       0xfc00707f
+#define MASK_CV_CMPGTU_SCI_B       0xfc00707f
+#define MASK_CV_CMPGEU_H           0xfe00707f
+#define MASK_CV_CMPGEU_B           0xfe00707f
+#define MASK_CV_CMPGEU_SC_H        0xfe00707f
+#define MASK_CV_CMPGEU_SC_B        0xfe00707f
+#define MASK_CV_CMPGEU_SCI_H       0xfc00707f
+#define MASK_CV_CMPGEU_SC_B        0xfe00707f
+#define MASK_CV_CMPGEU_SCI_H       0xfc00707f
+#define MASK_CV_CMPGEU_SCI_B       0xfc00707f
+#define MASK_CV_CMPLTU_H           0xfe00707f
+#define MASK_CV_CMPLTU_B           0xfe00707f
+#define MASK_CV_CMPLTU_SC_H        0xfe00707f
+#define MASK_CV_CMPLTU_SC_B        0xfe00707f
+#define MASK_CV_CMPLTU_SCI_H       0xfc00707f
+#define MASK_CV_CMPLTU_SCI_B       0xfc00707f
+#define MASK_CV_CMPLEU_H           0xfe00707f
+#define MASK_CV_CMPLEU_B           0xfe00707f
+#define MASK_CV_CMPLEU_SC_H        0xfe00707f
+#define MASK_CV_CMPLEU_SC_B        0xfe00707f
+#define MASK_CV_CMPLEU_SCI_H       0xfc00707f
+#define MASK_CV_CMPLEU_SCI_B       0xfc00707f
+#define MASK_CV_CPLXMUL_R          0xfe00707f
+#define MASK_CV_CPLXMUL_I          0xfe00707f
+#define MASK_CV_CPLXMUL_R_DIV2     0xfe00707f
+#define MASK_CV_CPLXMUL_I_DIV2     0xfe00707f
+#define MASK_CV_CPLXMUL_R_DIV4     0xfe00707f
+#define MASK_CV_CPLXMUL_I_DIV4     0xfe00707f
+#define MASK_CV_CPLXMUL_R_DIV8     0xfe00707f
+#define MASK_CV_CPLXMUL_I_DIV8     0xfe00707f
+#define MASK_CV_CPLXCONJ           0xfff0707f
+#define MASK_CV_SUBROTMJ           0xfe00707f
+#define MASK_CV_SUBROTMJ_DIV2      0xfe00707f
+#define MASK_CV_SUBROTMJ_DIV4      0xfe00707f
+#define MASK_CV_SUBROTMJ_DIV8      0xfe00707f
+#define MASK_CV_ADD_DIV2           0xfe00707f
+#define MASK_CV_ADD_DIV4           0xfe00707f
+#define MASK_CV_ADD_DIV8           0xfe00707f
+#define MASK_CV_SUB_DIV2           0xfe00707f
+#define MASK_CV_SUB_DIV4           0xfe00707f
+#define MASK_CV_SUB_DIV8           0xfe00707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index ec5b17db5f2c7b3514f62e7da590f988c84f8828..1a9f343090b98d987d6ba07ee41fb31849ee58cd 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -128,6 +128,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 7, 1))
 #define EXTRACT_CV_HWLP_UIMM12(x) \
   (RV_X(x, 20, 12))
+#define EXTRACT_CV_SIMD_IMM6(x) \
+  ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
+#define EXTRACT_CV_SIMD_UIMM6(x) \
+  ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -190,6 +194,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 5) << 15)
 #define ENCODE_CV_HWLP_LN(x) \
   (RV_X(x, 0, 1) << 7)
+#define ENCODE_CV_UIMM5(x) \
+  (RV_X(x, 0, 5) << 20)
+#define ENCODE_CV_SIMD_IMM6(x) \
+  ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
+#define ENCODE_CV_SIMD_UIMM6(x) \
+  ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -513,6 +523,7 @@ enum riscv_insn_class
   INSN_CLASS_XCVBI,
   INSN_CLASS_XCVMEM,
   INSN_CLASS_XCVHWLP,
+  INSN_CLASS_XCVSIMD,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 3ac7c7a2abecb49dadc1d54e10b371781cd88a2f..e6e1e2e2b89ac1bb327d564c4bc7a92e56556500 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -487,6 +487,24 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      (*info->print_address_func) (info->target, info);
 	      break;
 	    }
+	  else if (oparg[1] == '4')
+	    {
+	      print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_BI_IMM5 (l)));
+	      ++oparg;
+	      break;
+	    }
+	   else if (oparg[1] == '5')
+	    {
+	      print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_SIMD_IMM6 (l)));
+	      ++oparg;
+	      break;
+	    }
+	   else if (oparg[1] == '8')
+	    {
+	      print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_SIMD_UIMM6 (l)));
+	      ++oparg;
+	      break;
+	    }
 	/* Fall through.  */
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 74450f6f8c7111299926b1bbfb41987b3106c73d..24775a070572be8e42cc1bdea48cad01c076c5c7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2250,6 +2250,228 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cv.setup",  0, INSN_CLASS_XCVHWLP, "di,s,b1",  MATCH_CV_SETUP,  MASK_CV_SETUP,  match_opcode, 0},
 {"cv.setupi", 0, INSN_CLASS_XCVHWLP, "di,ji,b2", MATCH_CV_SETUPI, MASK_CV_SETUPI, match_opcode, 0},
 
+/* Vendor-specific (CORE-V) Xcvsimd Instructions */
+{"cv.add.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_H, MASK_CV_ADD_H, match_opcode, 0},
+{"cv.add.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_B, MASK_CV_ADD_B, match_opcode, 0},
+{"cv.add.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_SC_H, MASK_CV_ADD_SC_H, match_opcode, 0},
+{"cv.add.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_SC_B, MASK_CV_ADD_SC_B, match_opcode, 0},
+{"cv.add.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_ADD_SCI_H, MASK_CV_ADD_SCI_H, match_opcode, 0},
+{"cv.add.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_ADD_SCI_B, MASK_CV_ADD_SCI_B, match_opcode, 0},
+{"cv.sub.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_H, MASK_CV_SUB_H, match_opcode, 0},
+{"cv.sub.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_B, MASK_CV_SUB_B, match_opcode, 0},
+{"cv.sub.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_SC_H, MASK_CV_SUB_SC_H, match_opcode, 0},
+{"cv.sub.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_SC_B, MASK_CV_SUB_SC_B, match_opcode, 0},
+{"cv.sub.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SUB_SCI_H, MASK_CV_SUB_SCI_H, match_opcode, 0},
+{"cv.sub.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SUB_SCI_B, MASK_CV_SUB_SCI_B, match_opcode, 0},
+{"cv.avg.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_H, MASK_CV_AVG_H, match_opcode, 0},
+{"cv.avg.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_B, MASK_CV_AVG_B, match_opcode, 0},
+{"cv.avg.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_SC_H, MASK_CV_AVG_SC_H, match_opcode, 0},
+{"cv.avg.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_SC_B, MASK_CV_AVG_SC_B, match_opcode, 0},
+{"cv.avg.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AVG_SCI_H, MASK_CV_AVG_SCI_H, match_opcode, 0},
+{"cv.avg.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AVG_SCI_B, MASK_CV_AVG_SCI_B, match_opcode, 0},
+{"cv.avgu.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_H, MASK_CV_AVGU_H, match_opcode, 0},
+{"cv.avgu.b",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_B, MASK_CV_AVGU_B, match_opcode, 0},
+{"cv.avgu.sc.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_SC_H, MASK_CV_AVGU_SC_H, match_opcode, 0},
+{"cv.avgu.sc.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_SC_B, MASK_CV_AVGU_SC_B, match_opcode, 0},
+{"cv.avgu.sci.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_AVGU_SCI_H, MASK_CV_AVGU_SCI_H, match_opcode, 0},
+{"cv.avgu.sci.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_AVGU_SCI_B, MASK_CV_AVGU_SCI_B, match_opcode, 0},
+{"cv.min.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_H, MASK_CV_MIN_H, match_opcode, 0},
+{"cv.min.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_B, MASK_CV_MIN_B, match_opcode, 0},
+{"cv.min.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_SC_H, MASK_CV_MIN_SC_H, match_opcode, 0},
+{"cv.min.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_SC_B, MASK_CV_MIN_SC_B, match_opcode, 0},
+{"cv.min.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MIN_SCI_H, MASK_CV_MIN_SCI_H, match_opcode, 0},
+{"cv.min.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MIN_SCI_B, MASK_CV_MIN_SCI_B, match_opcode, 0},
+{"cv.minu.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_H, MASK_CV_MINU_H, match_opcode, 0},
+{"cv.minu.b",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_B, MASK_CV_MINU_B, match_opcode, 0},
+{"cv.minu.sc.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_SC_H, MASK_CV_MINU_SC_H, match_opcode, 0},
+{"cv.minu.sc.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_SC_B, MASK_CV_MINU_SC_B, match_opcode, 0},
+{"cv.minu.sci.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MINU_SCI_H, MASK_CV_MINU_SCI_H, match_opcode, 0},
+{"cv.minu.sci.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MINU_SCI_B, MASK_CV_MINU_SCI_B, match_opcode, 0},
+{"cv.max.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_H, MASK_CV_MAX_H, match_opcode, 0},
+{"cv.max.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_B, MASK_CV_MAX_B, match_opcode, 0},
+{"cv.max.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_SC_H, MASK_CV_MAX_SC_H, match_opcode, 0},
+{"cv.max.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_SC_B, MASK_CV_MAX_SC_B, match_opcode, 0},
+{"cv.max.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MAX_SCI_H, MASK_CV_MAX_SCI_H, match_opcode, 0},
+{"cv.max.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MAX_SCI_B, MASK_CV_MAX_SCI_B, match_opcode, 0},
+{"cv.maxu.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_H, MASK_CV_MAXU_H, match_opcode, 0},
+{"cv.maxu.b",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_B, MASK_CV_MAXU_B, match_opcode, 0},
+{"cv.maxu.sc.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_SC_H, MASK_CV_MAXU_SC_H, match_opcode, 0},
+{"cv.maxu.sc.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_SC_B, MASK_CV_MAXU_SC_B, match_opcode, 0},
+{"cv.maxu.sci.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MAXU_SCI_H, MASK_CV_MAXU_SCI_H, match_opcode, 0},
+{"cv.maxu.sci.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MAXU_SCI_B, MASK_CV_MAXU_SCI_B, match_opcode, 0},
+{"cv.srl.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_H, MASK_CV_SRL_H, match_opcode, 0},
+{"cv.srl.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_B, MASK_CV_SRL_B, match_opcode, 0},
+{"cv.srl.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_SC_H, MASK_CV_SRL_SC_H, match_opcode, 0},
+{"cv.srl.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_SC_B, MASK_CV_SRL_SC_B, match_opcode, 0},
+{"cv.srl.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SRL_SCI_H, MASK_CV_SRL_SCI_H, match_opcode, 0},
+{"cv.srl.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SRL_SCI_B, MASK_CV_SRL_SCI_B, match_opcode, 0},
+{"cv.sra.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_H, MASK_CV_SRA_H, match_opcode, 0},
+{"cv.sra.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_B, MASK_CV_SRA_B, match_opcode, 0},
+{"cv.sra.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_SC_H, MASK_CV_SRA_SC_H, match_opcode, 0},
+{"cv.sra.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_SC_B, MASK_CV_SRA_SC_B, match_opcode, 0},
+{"cv.sra.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SRA_SCI_H, MASK_CV_SRA_SCI_H, match_opcode, 0},
+{"cv.sra.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SRA_SCI_B, MASK_CV_SRA_SCI_B, match_opcode, 0},
+{"cv.sll.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_H, MASK_CV_SLL_H, match_opcode, 0},
+{"cv.sll.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_B, MASK_CV_SLL_B, match_opcode, 0},
+{"cv.sll.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_SC_H, MASK_CV_SLL_SC_H, match_opcode, 0},
+{"cv.sll.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_SC_B, MASK_CV_SLL_SC_B, match_opcode, 0},
+{"cv.sll.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SLL_SCI_H, MASK_CV_SLL_SCI_H, match_opcode, 0},
+{"cv.sll.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SLL_SCI_B, MASK_CV_SLL_SCI_B, match_opcode, 0},
+{"cv.or.h",               0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_H, MASK_CV_OR_H, match_opcode, 0},
+{"cv.or.b",               0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_B, MASK_CV_OR_B, match_opcode, 0},
+{"cv.or.sc.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_SC_H, MASK_CV_OR_SC_H, match_opcode, 0},
+{"cv.or.sc.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_SC_B, MASK_CV_OR_SC_B, match_opcode, 0},
+{"cv.or.sci.h",           0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_OR_SCI_H, MASK_CV_OR_SCI_H, match_opcode, 0},
+{"cv.or.sci.b",           0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_OR_SCI_B, MASK_CV_OR_SCI_B, match_opcode, 0},
+{"cv.xor.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_H, MASK_CV_XOR_H, match_opcode, 0},
+{"cv.xor.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_B, MASK_CV_XOR_B, match_opcode, 0},
+{"cv.xor.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_SC_H, MASK_CV_XOR_SC_H, match_opcode, 0},
+{"cv.xor.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_SC_B, MASK_CV_XOR_SC_B, match_opcode, 0},
+{"cv.xor.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_XOR_SCI_H, MASK_CV_XOR_SCI_H, match_opcode, 0},
+{"cv.xor.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_XOR_SCI_B, MASK_CV_XOR_SCI_B, match_opcode, 0},
+{"cv.and.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_H, MASK_CV_AND_H, match_opcode, 0},
+{"cv.and.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_B, MASK_CV_AND_B, match_opcode, 0},
+{"cv.and.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_SC_H, MASK_CV_AND_SC_H, match_opcode, 0},
+{"cv.and.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_SC_B, MASK_CV_AND_SC_B, match_opcode, 0},
+{"cv.and.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AND_SCI_H, MASK_CV_AND_SCI_H, match_opcode, 0},
+{"cv.and.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AND_SCI_B, MASK_CV_AND_SCI_B, match_opcode, 0},
+{"cv.abs.h",              0, INSN_CLASS_XCVSIMD, "d,s",   MATCH_CV_ABS_H, MASK_CV_ABS_H, match_opcode, 0},
+{"cv.abs.b",              0, INSN_CLASS_XCVSIMD, "d,s",   MATCH_CV_ABS_B, MASK_CV_ABS_B, match_opcode, 0},
+{"cv.dotup.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_H, MASK_CV_DOTUP_H, match_opcode, 0},
+{"cv.dotup.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_B, MASK_CV_DOTUP_B, match_opcode, 0},
+{"cv.dotup.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_SC_H, MASK_CV_DOTUP_SC_H, match_opcode, 0},
+{"cv.dotup.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_SC_B, MASK_CV_DOTUP_SC_B, match_opcode, 0},
+{"cv.dotup.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_DOTUP_SCI_H, MASK_CV_DOTUP_SCI_H, match_opcode, 0},
+{"cv.dotup.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_DOTUP_SCI_B, MASK_CV_DOTUP_SCI_B, match_opcode, 0},
+{"cv.dotusp.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_H, MASK_CV_DOTUSP_H, match_opcode, 0},
+{"cv.dotusp.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_B, MASK_CV_DOTUSP_B, match_opcode, 0},
+{"cv.dotusp.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_SC_H, MASK_CV_DOTUSP_SC_H, match_opcode, 0},
+{"cv.dotusp.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_SC_B, MASK_CV_DOTUSP_SC_B, match_opcode, 0},
+{"cv.dotusp.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTUSP_SCI_H, MASK_CV_DOTUSP_SCI_H, match_opcode, 0},
+{"cv.dotusp.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTUSP_SCI_B, MASK_CV_DOTUSP_SCI_B, match_opcode, 0},
+{"cv.dotsp.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_H, MASK_CV_DOTSP_H, match_opcode, 0},
+{"cv.dotsp.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_B, MASK_CV_DOTSP_B, match_opcode, 0},
+{"cv.dotsp.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_SC_H, MASK_CV_DOTSP_SC_H, match_opcode, 0},
+{"cv.dotsp.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_SC_B, MASK_CV_DOTSP_SC_B, match_opcode, 0},
+{"cv.dotsp.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTSP_SCI_H, MASK_CV_DOTSP_SCI_H, match_opcode, 0},
+{"cv.dotsp.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTSP_SCI_B, MASK_CV_DOTSP_SCI_B, match_opcode, 0},
+{"cv.sdotup.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_H, MASK_CV_SDOTUP_H, match_opcode, 0},
+{"cv.sdotup.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_B, MASK_CV_SDOTUP_B, match_opcode, 0},
+{"cv.sdotup.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_SC_H, MASK_CV_SDOTUP_SC_H, match_opcode, 0},
+{"cv.sdotup.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_SC_B, MASK_CV_SDOTUP_SC_B, match_opcode, 0},
+{"cv.sdotup.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SDOTUP_SCI_H, MASK_CV_SDOTUP_SCI_H, match_opcode, 0},
+{"cv.sdotup.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SDOTUP_SCI_B, MASK_CV_SDOTUP_SCI_B, match_opcode, 0},
+{"cv.sdotusp.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_H, MASK_CV_SDOTUSP_H, match_opcode, 0},
+{"cv.sdotusp.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_B, MASK_CV_SDOTUSP_B, match_opcode, 0},
+{"cv.sdotusp.sc.h",       0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_SC_H, MASK_CV_SDOTUSP_SC_H, match_opcode, 0},
+{"cv.sdotusp.sc.b",       0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_SC_B, MASK_CV_SDOTUSP_SC_B, match_opcode, 0},
+{"cv.sdotusp.sci.h",      0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTUSP_SCI_H, MASK_CV_SDOTUSP_SCI_H, match_opcode, 0},
+{"cv.sdotusp.sci.b",      0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTUSP_SCI_B, MASK_CV_SDOTUSP_SCI_B, match_opcode, 0},
+{"cv.sdotsp.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_H, MASK_CV_SDOTSP_H, match_opcode, 0},
+{"cv.sdotsp.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_B, MASK_CV_SDOTSP_B, match_opcode, 0},
+{"cv.sdotsp.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_SC_H, MASK_CV_SDOTSP_SC_H, match_opcode, 0},
+{"cv.sdotsp.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_SC_B, MASK_CV_SDOTSP_SC_B, match_opcode, 0},
+{"cv.sdotsp.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTSP_SCI_H, MASK_CV_SDOTSP_SCI_H, match_opcode, 0},
+{"cv.sdotsp.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTSP_SCI_B, MASK_CV_SDOTSP_SCI_B, match_opcode, 0},
+{"cv.extract.h",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_EXTRACT_H, MASK_CV_EXTRACT_H, match_opcode, 0},
+{"cv.extract.b",          0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_EXTRACT_B, MASK_CV_EXTRACT_B, match_opcode, 0},
+{"cv.extractu.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_EXTRACTU_H, MASK_CV_EXTRACTU_H, match_opcode, 0},
+{"cv.extractu.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_EXTRACTU_B, MASK_CV_EXTRACTU_B, match_opcode, 0},
+{"cv.insert.h",           0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_INSERT_H, MASK_CV_INSERT_H, match_opcode, 0},
+{"cv.insert.b",           0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_INSERT_B, MASK_CV_INSERT_B, match_opcode, 0},
+{"cv.shuffle.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE_H, MASK_CV_SHUFFLE_H, match_opcode, 0},
+{"cv.shuffle.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE_B, MASK_CV_SHUFFLE_B, match_opcode, 0},
+{"cv.shuffle.sci.h",      0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLE_SCI_H, MASK_CV_SHUFFLE_SCI_H, match_opcode, 0},
+{"cv.shufflei0.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI0_SCI_B, MASK_CV_SHUFFLEI0_SCI_B, match_opcode, 0},
+{"cv.shufflei1.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI1_SCI_B, MASK_CV_SHUFFLEI1_SCI_B, match_opcode, 0},
+{"cv.shufflei2.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI2_SCI_B, MASK_CV_SHUFFLEI2_SCI_B, match_opcode, 0},
+{"cv.shufflei3.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI3_SCI_B, MASK_CV_SHUFFLEI3_SCI_B, match_opcode, 0},
+{"cv.shuffle2.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE2_H, MASK_CV_SHUFFLE2_H, match_opcode, 0},
+{"cv.shuffle2.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE2_B, MASK_CV_SHUFFLE2_B, match_opcode, 0},
+{"cv.pack",               0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACK, MASK_CV_PACK, match_opcode, 0},
+{"cv.pack.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACK_H, MASK_CV_PACK_H, match_opcode, 0},
+{"cv.packhi.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACKHI_B, MASK_CV_PACKHI_B, match_opcode, 0},
+{"cv.packlo.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACKLO_B, MASK_CV_PACKLO_B, match_opcode, 0},
+{"cv.cmpeq.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_H, MASK_CV_CMPEQ_H, match_opcode, 0},
+{"cv.cmpeq.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_B, MASK_CV_CMPEQ_B, match_opcode, 0},
+{"cv.cmpeq.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_SC_H, MASK_CV_CMPEQ_SC_H, match_opcode, 0},
+{"cv.cmpeq.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_SC_B, MASK_CV_CMPEQ_SC_B, match_opcode, 0},
+{"cv.cmpeq.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPEQ_SCI_H, MASK_CV_CMPEQ_SCI_H, match_opcode, 0},
+{"cv.cmpeq.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPEQ_SCI_B, MASK_CV_CMPEQ_SCI_B, match_opcode, 0},
+{"cv.cmpne.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_H, MASK_CV_CMPNE_H, match_opcode, 0},
+{"cv.cmpne.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_B, MASK_CV_CMPNE_B, match_opcode, 0},
+{"cv.cmpne.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_SC_H, MASK_CV_CMPNE_SC_H, match_opcode, 0},
+{"cv.cmpne.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_SC_B, MASK_CV_CMPNE_SC_B, match_opcode, 0},
+{"cv.cmpne.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPNE_SCI_H, MASK_CV_CMPNE_SCI_H, match_opcode, 0},
+{"cv.cmpne.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPNE_SCI_B, MASK_CV_CMPNE_SCI_B, match_opcode, 0},
+{"cv.cmpgt.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_H, MASK_CV_CMPGT_H, match_opcode, 0},
+{"cv.cmpgt.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_B, MASK_CV_CMPGT_B, match_opcode, 0},
+{"cv.cmpgt.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_SC_H, MASK_CV_CMPGT_SC_H, match_opcode, 0},
+{"cv.cmpgt.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_SC_B, MASK_CV_CMPGT_SC_B, match_opcode, 0},
+{"cv.cmpgt.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGT_SCI_H, MASK_CV_CMPGT_SCI_H, match_opcode, 0},
+{"cv.cmpgt.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGT_SCI_B, MASK_CV_CMPGT_SCI_B, match_opcode, 0},
+{"cv.cmpge.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_H, MASK_CV_CMPGE_H, match_opcode, 0},
+{"cv.cmpge.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_B, MASK_CV_CMPGE_B, match_opcode, 0},
+{"cv.cmpge.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_SC_H, MASK_CV_CMPGE_SC_H, match_opcode, 0},
+{"cv.cmpge.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_SC_B, MASK_CV_CMPGE_SC_B, match_opcode, 0},
+{"cv.cmpge.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGE_SCI_H, MASK_CV_CMPGE_SCI_H, match_opcode, 0},
+{"cv.cmpge.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGE_SCI_B, MASK_CV_CMPGE_SCI_B, match_opcode, 0},
+{"cv.cmplt.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_H, MASK_CV_CMPLT_H, match_opcode, 0},
+{"cv.cmplt.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_B, MASK_CV_CMPLT_B, match_opcode, 0},
+{"cv.cmplt.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_SC_H, MASK_CV_CMPLT_SC_H, match_opcode, 0},
+{"cv.cmplt.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_SC_B, MASK_CV_CMPLT_SC_B, match_opcode, 0},
+{"cv.cmplt.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLT_SCI_H, MASK_CV_CMPLT_SCI_H, match_opcode, 0},
+{"cv.cmplt.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLT_SCI_B, MASK_CV_CMPLT_SCI_B, match_opcode, 0},
+{"cv.cmple.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_H, MASK_CV_CMPLE_H, match_opcode, 0},
+{"cv.cmple.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_B, MASK_CV_CMPLE_B, match_opcode, 0},
+{"cv.cmple.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_SC_H, MASK_CV_CMPLE_SC_H, match_opcode, 0},
+{"cv.cmple.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_SC_B, MASK_CV_CMPLE_SC_B, match_opcode, 0},
+{"cv.cmple.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLE_SCI_H, MASK_CV_CMPLE_SCI_H, match_opcode, 0},
+{"cv.cmple.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLE_SCI_B, MASK_CV_CMPLE_SCI_B, match_opcode, 0},
+{"cv.cmpgtu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_H, MASK_CV_CMPGTU_H, match_opcode, 0},
+{"cv.cmpgtu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_B, MASK_CV_CMPGTU_B, match_opcode, 0},
+{"cv.cmpgtu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_SC_H, MASK_CV_CMPGTU_SC_H, match_opcode, 0},
+{"cv.cmpgtu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_SC_B, MASK_CV_CMPGTU_SC_B, match_opcode, 0},
+{"cv.cmpgtu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGTU_SCI_H, MASK_CV_CMPGTU_SCI_H, match_opcode, 0},
+{"cv.cmpgtu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGTU_SCI_B, MASK_CV_CMPGTU_SCI_B, match_opcode, 0},
+{"cv.cmpgeu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_H, MASK_CV_CMPGEU_H, match_opcode, 0},
+{"cv.cmpgeu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_B, MASK_CV_CMPGEU_B, match_opcode, 0},
+{"cv.cmpgeu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_SC_H, MASK_CV_CMPGEU_SC_H, match_opcode, 0},
+{"cv.cmpgeu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_SC_B, MASK_CV_CMPGEU_SC_B, match_opcode, 0},
+{"cv.cmpgeu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGEU_SCI_H, MASK_CV_CMPGEU_SCI_H, match_opcode, 0},
+{"cv.cmpgeu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGEU_SCI_B, MASK_CV_CMPGEU_SCI_B, match_opcode, 0},
+{"cv.cmpltu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_H, MASK_CV_CMPLTU_H, match_opcode, 0},
+{"cv.cmpltu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_B, MASK_CV_CMPLTU_B, match_opcode, 0},
+{"cv.cmpltu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_SC_H, MASK_CV_CMPLTU_SC_H, match_opcode, 0},
+{"cv.cmpltu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_SC_B, MASK_CV_CMPLTU_SC_B, match_opcode, 0},
+{"cv.cmpltu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLTU_SCI_H, MASK_CV_CMPLTU_SCI_H, match_opcode, 0},
+{"cv.cmpltu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLTU_SCI_B, MASK_CV_CMPLTU_SCI_B, match_opcode, 0},
+{"cv.cmpleu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_H, MASK_CV_CMPLEU_H, match_opcode, 0},
+{"cv.cmpleu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_B, MASK_CV_CMPLEU_B, match_opcode, 0},
+{"cv.cmpleu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_SC_H, MASK_CV_CMPLEU_SC_H, match_opcode, 0},
+{"cv.cmpleu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_SC_B, MASK_CV_CMPLEU_SC_B, match_opcode, 0},
+{"cv.cmpleu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLEU_SCI_H, MASK_CV_CMPLEU_SCI_H, match_opcode, 0},
+{"cv.cmpleu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLEU_SCI_B, MASK_CV_CMPLEU_SCI_B, match_opcode, 0},
+{"cv.cplxmul.r",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R, MASK_CV_CPLXMUL_R, match_opcode, 0},
+{"cv.cplxmul.i",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I, MASK_CV_CPLXMUL_I, match_opcode, 0},
+{"cv.cplxmul.r.div2",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R_DIV2, MASK_CV_CPLXMUL_R_DIV2, match_opcode, 0},
+{"cv.cplxmul.i.div2",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I_DIV2, MASK_CV_CPLXMUL_I_DIV2, match_opcode, 0},
+{"cv.cplxmul.r.div4",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R_DIV4, MASK_CV_CPLXMUL_R_DIV4, match_opcode, 0},
+{"cv.cplxmul.i.div4",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I_DIV4, MASK_CV_CPLXMUL_I_DIV4, match_opcode, 0},
+{"cv.cplxmul.r.div8",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R_DIV8, MASK_CV_CPLXMUL_R_DIV8, match_opcode, 0},
+{"cv.cplxmul.i.div8",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I_DIV8, MASK_CV_CPLXMUL_I_DIV8, match_opcode, 0},
+{"cv.cplxconj",           0, INSN_CLASS_XCVSIMD, "d,s",   MATCH_CV_CPLXCONJ, MASK_CV_CPLXCONJ, match_opcode, 0},
+{"cv.subrotmj",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ, MASK_CV_SUBROTMJ, match_opcode, 0},
+{"cv.subrotmj.div2",      0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ_DIV2, MASK_CV_SUBROTMJ_DIV2, match_opcode, 0},
+{"cv.subrotmj.div4",      0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ_DIV4, MASK_CV_SUBROTMJ_DIV4, match_opcode, 0},
+{"cv.subrotmj.div8",      0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ_DIV8, MASK_CV_SUBROTMJ_DIV8, match_opcode, 0},
+{"cv.add.div2",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_DIV2, MASK_CV_ADD_DIV2, match_opcode, 0},
+{"cv.add.div4",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_DIV4, MASK_CV_ADD_DIV4, match_opcode, 0},
+{"cv.add.div8",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_DIV8, MASK_CV_ADD_DIV8, match_opcode, 0},
+{"cv.sub.div2",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_DIV2, MASK_CV_SUB_DIV2, match_opcode, 0},
+{"cv.sub.div4",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_DIV4, MASK_CV_SUB_DIV4, match_opcode, 0},
+{"cv.sub.div8",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_DIV8, MASK_CV_SUB_DIV8, match_opcode, 0},
+
 
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},